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[PR #63] int4_tensorwise: W4A4 layout (+ConvRot) with fused CUDA kernels #118
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Comfy-Org/comfy-kitchen#118
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📋 Pull Request Information
Original PR: https://github.com/Comfy-Org/comfy-kitchen/pull/63
Author: @HK416-TYPED
Created: 7/6/2026
Status: 🔄 Open
Base:
main← Head:feat/int4-tensorwise-convrot📝 Commits (9)
83d4566feat: int4_tensorwise W4A4 (+ConvRot) eager reference and layout5d800c2cuda: fused int4_tensorwise activation quantize + s4 MMA dispatchba6ab49cuda: rank-one accumulation fast path for the int4_tensorwise GEMM1c77543cuda: widen the rank-one GEMM M-tile (kMUnroll 1 -> 4)005cf9acuda: int4 rank-one tuning sweep + same-activation quantize memo32349eccuda: ldmatrix fragment loads + 48B smem row stride for the rank-one GEMM1ef96a5style: lowercase GEMM dim locals in int4_linear (ruff N806)3e94fd4review: keep int4 GEMM scales in the out_dtype lane; raise MIN_SM to 8.0be4a39eeager: warn once when int4_tensorwise runs the slow reference path on CUDA📊 Changes
11 files changed (+1823 additions, -27 deletions)
View changed files
📝
comfy_kitchen/backends/cuda/CMakeLists.txt(+1 -0)📝
comfy_kitchen/backends/cuda/__init__.py(+127 -4)📝
comfy_kitchen/backends/cuda/dlpack_bindings.cpp(+47 -1)➕
comfy_kitchen/backends/cuda/ops/int4_tensorwise.cu(+315 -0)📝
comfy_kitchen/backends/cuda/ops/scaled_mm_svdquant_w4a4.cu(+171 -22)📝
comfy_kitchen/backends/cuda/ops/svdquant_utils.cuh(+12 -0)📝
comfy_kitchen/backends/eager/__init__.py(+72 -0)📝
comfy_kitchen/backends/eager/quantization.py(+363 -0)📝
comfy_kitchen/tensor/__init__.py(+3 -0)➕
comfy_kitchen/tensor/int4.py(+296 -0)➕
tests/test_int4_tensorwise.py(+416 -0)📄 Description
Adds
TensorWiseINT4Layout— a 4-bit downward extension of int8_tensorwise. Weights are packed signed int4 pairs (low-nibble-first,[N, K/2]int8 container) with fp32[N, 1]per-row scales; activations are rotated + quantized to int4 dynamically inside the kernel.Eager:
quantize_int4_rowwise/quantize_int4_convrot_weight/int4_linearreference path, exact pack/unpack roundtrip, works on CPU.CUDA (SM >= 8.0 for the MMA path, layout MIN_SM (7,5)):
cp.async+mma.m16n8k64.s4with carried int32 accumulators (|acc| <= 49·K << 2^31) — no in-loop CUDA-core dequantldmatrix.x4/x2fragment loads over a 48-byte-stride smem layout (bank-conflict-free); both operands share the ldmatrix k-permutation so the dot product is unchanged_versionguarded, inference-mode safe)Per-layer, L4 (SM 8.9, native int4 tensor cores), M=4608, vs the compiled int8 path:
E2E Qwen-Image-Edit-2511 mixed checkpoint (80% int4 / 20% int8 layers, 20 steps, 1024², L4, same session): 4.22 s/it vs 4.29 s/it for full int8, at 75% of the file size (14.9 GB vs 20 GB, bf16 is 40 GB). Krea-2 Turbo/Raw: 1.33×/1.22× vs bf16. Published checkpoints for testing:
To test them, use ComfyUI from the companion loader branch: HK416-TYPED/ComfyUI
feat/int4-tensorwise-loaderwith this branch🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.