[PR #24] [MERGED] Add Intel XPU support to Triton backend #86

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opened 2026-10-26 22:20:15 +00:00 by bsakaguchi · 0 comments

bsakaguchi commented

2026-10-26 22:20:15 +00:00

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📋 Pull Request Information

Original PR: https://github.com/Comfy-Org/comfy-kitchen/pull/24
Author: @maxious
Created: 1/17/2026
Status: ✅ Merged
Merged: 1/21/2026
Merged by: @comfyanonymous

Base: main ← Head: intel-xpu-triton

📝 Commits (1)

200d677 Add Intel XPU support to Triton backend

📊 Changes

1 file changed (+11 additions, -8 deletions)

View changed files

📝 comfy_kitchen/backends/triton/__init__.py (+11 -8)

📄 Description

This PR adds Intel XPU (Arc/Data Center GPU) support to the Triton backend.

Changes

Add 'xpu' to supported devices in Triton backend constraints
Detect XPU availability alongside CUDA in backend registration
Triton kernels (FP8, RoPE) now work on Intel Arc/Data Center GPUs

NVFP4 operations still require CUDA (PTX assembly) and will fall back to eager mode on XPU.

Benchmarks

Tested on Intel Arc Pro B60 (PyTorch 2.11.0.dev+xpu):

Operation	Size	Time	Throughput
FP8 Quantize	256x256	0.022ms	2.9 GE/s
FP8 Quantize	1024x1024	0.022ms	48.3 GE/s
FP8 Quantize	4096x4096	0.215ms	78.1 GE/s
FP8 Dequantize	256x256	0.021ms	3.1 GE/s
FP8 Dequantize	1024x1024	0.022ms	48.5 GE/s
FP8 Dequantize	4096x4096	0.147ms	113.9 GE/s
RoPE	B=1,H=8,S=128,D=64	0.024ms	2.7 GE/s
RoPE	B=2,H=32,S=1024,D=128	0.351ms	23.9 GE/s
RoPE	B=4,H=32,S=2048,D=128	0.841ms	39.9 GE/s

_{🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.}

## 📋 Pull Request Information **Original PR:** https://github.com/Comfy-Org/comfy-kitchen/pull/24 **Author:** [@maxious](https://github.com/maxious) **Created:** 1/17/2026 **Status:** ✅ Merged **Merged:** 1/21/2026 **Merged by:** [@comfyanonymous](https://github.com/comfyanonymous) **Base:** `main` ← **Head:** `intel-xpu-triton` --- ### 📝 Commits (1) - [`200d677`](https://github.com/Comfy-Org/comfy-kitchen/commit/200d6778076ab9f34f9508292b31216049ee80b6) Add Intel XPU support to Triton backend ### 📊 Changes **1 file changed** (+11 additions, -8 deletions) <details> <summary>View changed files</summary> 📝 `comfy_kitchen/backends/triton/__init__.py` (+11 -8) </details> ### 📄 Description This PR adds Intel XPU (Arc/Data Center GPU) support to the Triton backend. ## Changes - Add 'xpu' to supported devices in Triton backend constraints - Detect XPU availability alongside CUDA in backend registration - Triton kernels (FP8, RoPE) now work on Intel Arc/Data Center GPUs NVFP4 operations still require CUDA (PTX assembly) and will fall back to eager mode on XPU. ## Benchmarks Tested on Intel Arc Pro B60 (PyTorch 2.11.0.dev+xpu): | Operation | Size | Time | Throughput | |-----------|------|------|------------| | FP8 Quantize | 256x256 | 0.022ms | 2.9 GE/s | | FP8 Quantize | 1024x1024 | 0.022ms | 48.3 GE/s | | FP8 Quantize | 4096x4096 | 0.215ms | 78.1 GE/s | | FP8 Dequantize | 256x256 | 0.021ms | 3.1 GE/s | | FP8 Dequantize | 1024x1024 | 0.022ms | 48.5 GE/s | | FP8 Dequantize | 4096x4096 | 0.147ms | 113.9 GE/s | | RoPE | B=1,H=8,S=128,D=64 | 0.024ms | 2.7 GE/s | | RoPE | B=2,H=32,S=1024,D=128 | 0.351ms | 23.9 GE/s | | RoPE | B=4,H=32,S=2048,D=128 | 0.841ms | 39.9 GE/s | --- <sub>🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.</sub>

bsakaguchi

2026-10-26 22:20:15 +00:00