mirror of
https://github.com/NVIDIA/nvbench.git
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5d70492714
- /W4 on MSVC - -Wall -Wextra + others on gcc/clang - New NVBench_ENABLE_WERROR option to toggle "warnings as errors" - Mark the nlohmann_json library as IMPORTED to switch to system includes - Rename nvbench_main -> nvbench.main to follow target name conventions - Explicitly suppress some cudafe warnings when compiling templates in nlohmann_json headers. - Explicitly suppress some warnings from Thrust headers. - Various fixes for warnings exposed by new flags. - Disable CUPTI on CTK < 11.3 (See #52).
84 lines
3.0 KiB
Plaintext
84 lines
3.0 KiB
Plaintext
/*
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* Copyright 2021 NVIDIA Corporation
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*
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* Licensed under the Apache License, Version 2.0 with the LLVM exception
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* (the "License"); you may not use this file except in compliance with
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* the License.
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*
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* You may obtain a copy of the License at
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*
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* http://llvm.org/foundation/relicensing/LICENSE.txt
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <nvbench/range.cuh>
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#include "test_asserts.cuh"
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void test_basic()
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{
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ASSERT((nvbench::range(0, 6) ==
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std::vector<nvbench::int64_t>{0, 1, 2, 3, 4, 5, 6}));
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ASSERT((nvbench::range(0, 6, 1) ==
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std::vector<nvbench::int64_t>{0, 1, 2, 3, 4, 5, 6}));
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ASSERT(
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(nvbench::range(0, 6, 2) == std::vector<nvbench::int64_t>{0, 2, 4, 6}));
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ASSERT((nvbench::range(0, 6, 3) == std::vector<nvbench::int64_t>{0, 3, 6}));
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ASSERT((nvbench::range(0, 6, 4) == std::vector<nvbench::int64_t>{0, 4}));
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ASSERT((nvbench::range(0, 6, 5) == std::vector<nvbench::int64_t>{0, 5}));
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ASSERT((nvbench::range(0, 6, 7) == std::vector<nvbench::int64_t>{0}));
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}
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void test_result_type()
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{
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// All ints should turn into int64 by default:
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ASSERT((std::is_same_v<decltype(nvbench::range(0ll, 1ll)),
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std::vector<nvbench::int64_t>>));
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ASSERT((std::is_same_v<decltype(nvbench::range(0, 1)),
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std::vector<nvbench::int64_t>>));
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ASSERT((std::is_same_v<decltype(nvbench::range(0u, 1u)),
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std::vector<nvbench::int64_t>>));
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// All floats should turn into float64 by default:
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ASSERT((std::is_same_v<decltype(nvbench::range(0., 1.)),
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std::vector<nvbench::float64_t>>));
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ASSERT((std::is_same_v<decltype(nvbench::range(0.f, 1.f)),
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std::vector<nvbench::float64_t>>));
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// Other types may be explicitly specified:
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ASSERT((std::is_same_v<decltype(nvbench::range<nvbench::float32_t,
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nvbench::float32_t>(0.f, 1.f)),
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std::vector<nvbench::float32_t>>));
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ASSERT((std::is_same_v<
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decltype(nvbench::range<nvbench::int32_t, nvbench::int32_t>(0, 1)),
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std::vector<nvbench::int32_t>>));
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}
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void test_fp_tolerance()
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{
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// Make sure that the range is padded a bit for floats to prevent rounding
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// errors from skipping `end`. This test will trigger failures without
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// the padding.
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const nvbench::float32_t start = 0.1f;
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const nvbench::float32_t stride = 1e-4f;
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for (std::size_t size = 1; size < 1024; ++size)
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{
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const nvbench::float32_t end =
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start + stride * static_cast<nvbench::float32_t>(size - 1);
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ASSERT_MSG(nvbench::range(start, end, stride).size() == size,
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"size={}", size);
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}
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}
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int main()
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{
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test_basic();
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test_result_type();
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test_fp_tolerance();
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}
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