/*
 * SPDX-FileCopyrightText: Copyright (c) 2023-25 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#pragma once

#include <nvtypes.h>

//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file:      ctrl/ctrl2080/ctrl2080bif.finn
//

#include "nvcfg_sdk.h"
#include "ctrl/ctrl2080/ctrl2080base.h"

/* NV20_SUBDEVICE_XX bif control commands and parameters
 * This control command is intended for handling APIs that GET/SET information
 * related to PCIe.
 */

typedef enum NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG {
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_INVALID = 0,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_DEVICE_CTRL_STATUS = 1,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_LINK_CTRL_STATUS = 2,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_DEVICE_CTRL_STATUS_2 = 3,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_LINK_CAP = 4,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_L1_PM_SUBSTATES_CTRL1 = 5,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_STATUS = 6,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_STATUS = 7,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_STATUS = 8,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_MASK = 9,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_MASK = 10,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_MASK = 11,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_SEVERITY = 12,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_SEVERITY = 13,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_SEVERITY = 14,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TLP_ENCRYPTION_STATUS = 15,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_LINK_STREAM_ENABLED = 16,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_SELECTIVE_STREAM_ENABLED = 17,
    NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_FLOW_THROUGH_STREAM_ENABLED = 18,
} NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG;

#define NV2080_CTRL_CMD_BIF_DATA_PARAMS_MAX 32

#define NV2080_CTRL_CMD_BIF_GET_DATA        (0x20803b01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIF_INTERFACE_ID << 8) | NV2080_CTRL_BIF_GET_DATA_PARAMS_MESSAGE_ID" */

#define NV2080_CTRL_BIF_GET_DATA_PARAMS_MESSAGE_ID (0x1U)

typedef struct NV2080_CTRL_BIF_GET_DATA_PARAMS {
    NvU32 featureId;
    NvU32 paramId[NV2080_CTRL_CMD_BIF_DATA_PARAMS_MAX];
    NvU32 paramVal[NV2080_CTRL_CMD_BIF_DATA_PARAMS_MAX];
    NvU32 flags;
    NvU32 paramSize;
} NV2080_CTRL_BIF_GET_DATA_PARAMS;

typedef enum NV2080_CTRL_BIF_FEATURE_ID {
    NV2080_CTRL_BIF_FEATURE_ID_INVALID = 0,
    NV2080_CTRL_BIF_FEATURE_ID_CONFIG_REG = 1,

} NV2080_CTRL_BIF_FEATURE_ID;



/* _ctrl2080bif_h_ */
