/*
 * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the Software),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef __ls10_dev_pri_masterstation_ip_h__
#define __ls10_dev_pri_masterstation_ip_h__
/* This file is autogenerated.  Do not edit */
#define NV_PPRIV_MASTER_RING_COMMAND                                           0x0000004c /* RW-4R */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD                                              5:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING_RESET_VAL_0                      0x01 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD_RESET_VAL_1                          0x00 /* RWB-V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD                                      0x00 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING                                  0x01 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT                               0x02 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS                          0x03 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_AND_START_RING                    0x04 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_TAG_ENUMERATE_AND_START_RING             0x05 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP                    9:6 /* RWBVF */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL                0x0 /* RWB-V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_GPC                0x1 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_FBP                0x2 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_SYS                0x3 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_L2                 0x4 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_SYSB               0x5 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_ALL         0x8 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_GPC         0x9 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_FBP         0xa /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_SYS         0xb /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_L2          0xc /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_SYSB        0xd /* RW--V */
#define NV_PPRIV_MASTER_RING_START_RESULTS                                     0x00000050 /* R--4R */
#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY                               0:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS                          0x1 /* R---V */
#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_FAIL                          0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0                                 0x00000058 /* R--4R */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_FBP                  31:16 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_FBP_V               0x0000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYS                    8:8 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYS_V                  0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYSB                   9:9 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYSB_V                 0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_START_CONN_FAULT                  0:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_START_CONN_FAULT_V                0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DISCONNECT_FAULT                       1:1 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DISCONNECT_FAULT_V                     0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_OVERFLOW_FAULT                         2:2 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_OVERFLOW_FAULT_V                       0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_ENUMERATION_FAULT                 3:3 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_ENUMERATION_FAULT_V               0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GPC_RS_MAP_CONFIG_FAULT                4:4 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GPC_RS_MAP_CONFIG_FAULT_V              0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DEBUG_INTR_FAULT                       5:5 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DEBUG_INTR_FAULT_V                     0x0 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1                                 0x0000005c /* R--4R */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1_GBL_WRITE_ERROR_GPC                   31:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1_GBL_WRITE_ERROR_GPC_V           0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER                                             0x000003ff:0x00000000 /* RW--D */
#define NV_PPRIV_MASTER_CG1                                                    0x000000a8 /* RW-4R */
#define NV_PPRIV_MASTER_CG1_SLCG                                                      0:0 /* RWBVF */
#define NV_PPRIV_MASTER_CG1_SLCG__PROD                                                0x0 /* RW--V */
#define NV_PPRIV_MASTER_CG1_SLCG_ENABLED                                              0x0 /* RW--V */
#define NV_PPRIV_MASTER_CG1_SLCG_DISABLED                                             0x1 /* RWB-V */
#endif // __ls10_dev_pri_masterstation_ip_h__
