/*
 * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 */

#ifndef _GPU_ECC_H_
#define _GPU_ECC_H_

typedef struct ECC_INFO
{
    NvU32  address;
    NvU32  addressExt;
    NvU32  locationId;     // Holds GPC#, Partition#, etc. depending on unit
    NvU32  subLocationId;  // Holds TPC#, sub-partition#, slice#, etc. depending on unit
    NvU64  corTotCnt;
    NvU64  corUniCnt;
    NvU64  uncTotCnt;
    NvU64  uncUniCnt;
    NvBool bCorError;
    NvBool bCorTotOverflow;
    NvBool bCorUniOverflow;
    NvBool bUncError;
    NvBool bUncTotOverflow;
    NvBool bUncUniOverflow;
    NvBool bPermanentCorError;
} ECC_INFO;

typedef struct ECC_COUNTERS
{
    NvU64 corCntTotCached;
    NvU64 corCntTotVolatile;
    NvU64 corCntUniCached;
    NvU64 corCntUniVolatile;
    NvU64 uncCntTotCached;
    NvU64 uncCntUniCached;
    NvU32 corTotOverflowCount;
    NvU32 corUniOverflowCount;
    NvU32 uncTotOverflowCount;
    NvU32 uncUniOverflowCount;
} ECC_COUNTERS;

#endif // _GPU_ECC_H
