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This commit is contained in:
Bernhard Stoeckner
2025-09-10 16:52:44 +02:00
parent e0566f7913
commit 0bf68f06cc
47 changed files with 1077 additions and 708 deletions
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6
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -260,6 +260,12 @@ namespace DisplayPort
// Flag to check if the system is UEFI.
bool bIsUefiSystem;
//
// Flag to ensure we take into account that
// Displayport++ supports HDMI as well.
//
bool bHDMIOnDPPlusPlus;
bool bSkipResetLinkStateDuringPlug;
// Flag to check if LT should be skipped.

3
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -110,6 +110,8 @@
#define NV_DP_REGKEY_SKIP_SETTING_LINK_STATE_DURING_UNPLUG "DP_SKIP_SETTING_LINK_STATE_DURING_UNPLUG"
// This regkey ensures DPLib takes into account Displayport++ supports HDMI.
#define NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS "HDMI_ON_DP_PLUS_PLUS"
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -154,6 +156,7 @@ struct DP_REGKEY_DATABASE
bool bEnableLowerBppCheckForDsc;
bool bSkipSettingLinkStateDuringUnplug;
bool bEnableDevId;
bool bHDMIOnDPPlusPlus;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;

10
src/common/displayport/src/dp_configcaps2x.cpp
View File

@@ -151,6 +151,16 @@ void DPCDHALImpl2x::parseAndReadCaps()
DPCDHALImpl::parseAndReadCaps();
// reset DP tunneling UHBR caps
caps2x.dpInTunnelingCaps.bUHBR_10GSupported = NV_FALSE;
caps2x.dpInTunnelingCaps.bUHBR_13_5GSupported = NV_FALSE;
caps2x.dpInTunnelingCaps.bUHBR_20GSupported = NV_FALSE;
// reset CableCaps
caps2x.cableCaps.bUHBR_10GSupported = NV_TRUE;
caps2x.cableCaps.bUHBR_13_5GSupported = NV_TRUE;
caps2x.cableCaps.bUHBR_20GSupported = NV_TRUE;
// 02206h
if (AuxRetry::ack == bus.read(NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING, &buffer[0], 1))
{

12
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -199,6 +199,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bEnableLowerBppCheckForDsc = dpRegkeyDatabase.bEnableLowerBppCheckForDsc;
this->bSkipSettingLinkStateDuringUnplug = dpRegkeyDatabase.bSkipSettingLinkStateDuringUnplug;
this->bEnableDevId = dpRegkeyDatabase.bEnableDevId;
this->bHDMIOnDPPlusPlus = dpRegkeyDatabase.bHDMIOnDPPlusPlus;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -412,7 +413,16 @@ void ConnectorImpl::processNewDevice(const DiscoveryManager::Device & device,
{
case DISPLAY_PORT:
case DISPLAY_PORT_PLUSPLUS: // DP port that supports DP and TMDS
connector = connectorDisplayPort;
if (bHDMIOnDPPlusPlus &&
existingDev &&
existingDev->connectorType == connectorHDMI)
{
connector = connectorHDMI;
}
else
{
connector = connectorDisplayPort;
}
break;
case ANALOG_VGA:

3
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -108,7 +108,8 @@ const struct
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_LOWER_BPP_CHECK_FOR_DSC, &dpRegkeyDatabase.bEnableLowerBppCheckForDsc, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_SETTING_LINK_STATE_DURING_UNPLUG, &dpRegkeyDatabase.bSkipSettingLinkStateDuringUnplug, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS, &dpRegkeyDatabase.bHDMIOnDPPlusPlus, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

16
src/common/inc/nvBldVer.h
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@@ -43,18 +43,18 @@
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r570_00-540"
#define NV_BUILD_CHANGELIST_NUM (36324750)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r570_00-575"
#define NV_BUILD_CHANGELIST_NUM (36467544)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r570/r570_00-540"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36324750)
#define NV_BUILD_NAME "rel/gpu_drv/r570/r570_00-575"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36467544)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r570_00-536"
#define NV_BUILD_CHANGELIST_NUM (36324750)
#define NV_BUILD_BRANCH_VERSION "r570_00-569"
#define NV_BUILD_CHANGELIST_NUM (36467544)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "573.65"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36324750)
#define NV_BUILD_NAME "573.73"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36467544)
#define NV_BUILD_BRANCH_BASE_VERSION R570
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "570.181"
#define NV_VERSION_STRING "570.190"
#else

21
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h
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@@ -724,4 +724,25 @@ typedef struct NV208F_CTRL_FB_CONVERT_CHANNEL_PARAMS {
#define NV208F_CTRL_FB_CHANNEL_CONVERSION_TYPE_LOGICAL_TO_PHYSICAL (0x00000000U)
#define NV208F_CTRL_FB_CHANNEL_CONVERSION_TYPE_PHYSICAL_TO_LOGICAL (0x00000001U)
/*
* NV208F_CTRL_CMD_FB_SET_ROW_REMAP_FAILURE_FLAG
*
* This command sets the status of row remap failure flag to the passed value.
*
* value
* The value to set for row remap failure flag
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV208F_CTRL_CMD_FB_SET_ROW_REMAP_FAILURE_FLAG (0x208f051cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_SET_ROW_REMAP_FAILURE_FLAG_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_FB_SET_ROW_REMAP_FAILURE_FLAG_PARAMS_MESSAGE_ID (0x1cU)
typedef struct NV208F_CTRL_FB_SET_ROW_REMAP_FAILURE_FLAG_PARAMS {
NvBool value;
} NV208F_CTRL_FB_SET_ROW_REMAP_FAILURE_FLAG_PARAMS;
/* _ctrl208ffb_h_ */

64
src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c
View File

@@ -1505,25 +1505,25 @@ NvBool isLibosPreserveLogBufferFull(LIBOS_LOG_DECODE *pLogDecode, NvU32 gpuInsta
{
NvU64 i = (NvU32)(pLogDecode->numLogBuffers);
NvU32 tag = LIBOS_LOG_NVLOG_BUFFER_TAG(pLogDecode->sourceName, i * 2);
NVLOG_BUFFER_HANDLE handle = 0;
NV_STATUS status = nvlogGetBufferHandleFromTag(tag, &handle);
if (status != NV_OK)
//
// Cannot use nvlogGetBufferHandleFromTag here since in multi GPU case,
// we can have multiple buffers with exact same tag, only differentiable
// from gpuInstance
//
for (i = 0; i < NVLOG_MAX_BUFFERS; i++)
{
return NV_FALSE;
}
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[handle];
if (pNvLogBuffer == NULL)
{
return NV_FALSE;
}
if (FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance &&
(pNvLogBuffer->pos >= pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
{
return NV_TRUE;
if (NvLogLogger.pBuffers[i] != NULL)
{
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[i];
if ((pNvLogBuffer->tag == tag) &&
(DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance) &&
FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
(pNvLogBuffer->pos >= pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
{
return NV_TRUE;
}
}
}
return NV_FALSE;
@@ -1531,19 +1531,27 @@ NvBool isLibosPreserveLogBufferFull(LIBOS_LOG_DECODE *pLogDecode, NvU32 gpuInsta
static NvBool findPreservedNvlogBuffer(NvU32 tag, NvU32 gpuInstance, NVLOG_BUFFER_HANDLE *pHandle)
{
NVLOG_BUFFER_HANDLE handle = 0;
NV_STATUS status = nvlogGetBufferHandleFromTag(tag, &handle);
NvU64 i;
if (status != NV_OK)
return NV_FALSE;
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[handle];
if (FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance &&
(pNvLogBuffer->pos < pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
//
// Cannot use nvlogGetBufferHandleFromTag here since in multi GPU case,
// we can have multiple buffers with exact same tag, only differentiable
// from gpuInstance
//
for (i = 0; i < NVLOG_MAX_BUFFERS; i++)
{
*pHandle = handle;
return NV_TRUE;
if (NvLogLogger.pBuffers[i] != NULL)
{
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[i];
if ((pNvLogBuffer->tag == tag) &&
(DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance) &&
FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
(pNvLogBuffer->pos < pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
{
*pHandle = i;
return NV_TRUE;
}
}
}
return NV_FALSE;

2
src/nvidia/arch/nvalloc/unix/include/osapi.h
View File

@@ -176,6 +176,8 @@ void RmUpdateGc6ConsoleRefCount (nv_state_t *, NvBool);
NvBool rm_get_uefi_console_status (nv_state_t *);
NvU64 rm_get_uefi_console_size (nv_state_t *, NvU64 *);
void rm_check_s0ix_regkey_and_platform_support(void);
RM_API *RmUnixRmApiPrologue (nv_state_t *, THREAD_STATE_NODE *, NvU32 module);
void RmUnixRmApiEpilogue (nv_state_t *, THREAD_STATE_NODE *);

10
src/nvidia/arch/nvalloc/unix/src/dynamic-power.c
View File

@@ -747,6 +747,16 @@ rmReadAndParseDynamicPowerRegkey
}
#undef NV_PMC_BOOT_42_CHIP_ID_GA102
void rm_check_s0ix_regkey_and_platform_support(void)
{
OBJSYS *pSys = SYS_GET_INSTANCE();
NvU32 data;
NvBool status = ((nv_platform_supports_s0ix()) &&
((osReadRegistryDword(NULL, NV_REG_ENABLE_S0IX_POWER_MANAGEMENT, &data) == NV_OK) && (data == 1)));
pSys->setProperty(pSys, PDB_PROP_SYS_SUPPORTS_S0IX, status);
}
/*!
* @brief Initialize state related to dynamic power management.
* Called once per GPU during driver initialization.

2
src/nvidia/arch/nvalloc/unix/src/osinit.c
View File

@@ -272,6 +272,8 @@ NV_STATUS osRmInitRm(void)
return status;
}
rm_check_s0ix_regkey_and_platform_support();
// Setup any ThreadState defaults
threadStateInitSetupFlags(THREAD_STATE_SETUP_FLAGS_ENABLED |
THREAD_STATE_SETUP_FLAGS_TIMEOUT_ENABLED |

14
src/nvidia/generated/g_engines_pb.c
View File

@@ -368,6 +368,18 @@ const PRB_FIELD_DESC prb_fields_nvdebug_eng_kgsp_rpcinfo[] = {
PRB_MAYBE_FIELD_NAME("data1")
PRB_MAYBE_FIELD_DEFAULT(0)
},
{
6,
{
PRB_OPTIONAL,
PRB_UINT32,
0,
},
0,
0,
PRB_MAYBE_FIELD_NAME("sequence")
PRB_MAYBE_FIELD_DEFAULT(0)
},
};
// Message descriptors
@@ -403,7 +415,7 @@ const PRB_MSG_DESC prb_messages_nvdebug_eng[] = {
PRB_MAYBE_MESSAGE_NAME("NvDebug.Eng.Mc.PciBarInfo")
},
{
5,
6,
prb_fields_nvdebug_eng_kgsp_rpcinfo,
PRB_MAYBE_MESSAGE_NAME("NvDebug.Eng.KGsp.RpcInfo")
},

10
src/nvidia/generated/g_engines_pb.h
View File

@@ -21,10 +21,10 @@ extern const PRB_MSG_DESC prb_messages_nvdebug_eng[];
#define NVDEBUG_ENG_MC_LEN 66
#define NVDEBUG_ENG_GPU_LEN 62
#define NVDEBUG_ENG_NVD_LEN 30
#define NVDEBUG_ENG_KGSP_LEN 88
#define NVDEBUG_ENG_KGSP_LEN 100
#define NVDEBUG_ENG_MC_RMDATA_LEN 6
#define NVDEBUG_ENG_MC_PCIBARINFO_LEN 22
#define NVDEBUG_ENG_KGSP_RPCINFO_LEN 40
#define NVDEBUG_ENG_KGSP_RPCINFO_LEN 46
extern const PRB_FIELD_DESC prb_fields_nvdebug_eng_mc[];
@@ -85,8 +85,8 @@ extern const PRB_FIELD_DESC prb_fields_nvdebug_eng_kgsp[];
#define NVDEBUG_ENG_KGSP_EVENT_HISTORY (&prb_fields_nvdebug_eng_kgsp[1])
// 'KGsp' field lengths
#define NVDEBUG_ENG_KGSP_RPC_HISTORY_LEN 43
#define NVDEBUG_ENG_KGSP_EVENT_HISTORY_LEN 43
#define NVDEBUG_ENG_KGSP_RPC_HISTORY_LEN 49
#define NVDEBUG_ENG_KGSP_EVENT_HISTORY_LEN 49
extern const PRB_FIELD_DESC prb_fields_nvdebug_eng_mc_rmdata[];
@@ -114,6 +114,7 @@ extern const PRB_FIELD_DESC prb_fields_nvdebug_eng_kgsp_rpcinfo[];
#define NVDEBUG_ENG_KGSP_RPCINFO_TS_END (&prb_fields_nvdebug_eng_kgsp_rpcinfo[2])
#define NVDEBUG_ENG_KGSP_RPCINFO_DATA0 (&prb_fields_nvdebug_eng_kgsp_rpcinfo[3])
#define NVDEBUG_ENG_KGSP_RPCINFO_DATA1 (&prb_fields_nvdebug_eng_kgsp_rpcinfo[4])
#define NVDEBUG_ENG_KGSP_RPCINFO_SEQUENCE (&prb_fields_nvdebug_eng_kgsp_rpcinfo[5])
// 'RpcInfo' field lengths
#define NVDEBUG_ENG_KGSP_RPCINFO_FUNCTION_LEN 5
@@ -121,6 +122,7 @@ extern const PRB_FIELD_DESC prb_fields_nvdebug_eng_kgsp_rpcinfo[];
#define NVDEBUG_ENG_KGSP_RPCINFO_TS_END_LEN 10
#define NVDEBUG_ENG_KGSP_RPCINFO_DATA0_LEN 5
#define NVDEBUG_ENG_KGSP_RPCINFO_DATA1_LEN 5
#define NVDEBUG_ENG_KGSP_RPCINFO_SEQUENCE_LEN 5
extern const PRB_SERVICE_DESC prb_services_nvdebug_eng[];

10
src/nvidia/generated/g_intr_nvoc.h
View File

@@ -1054,23 +1054,23 @@ static inline NV_STATUS intrRestoreIntrRegValue(OBJGPU *pGpu, struct Intr *pIntr
#define intrRestoreIntrRegValue_HAL(pGpu, pIntr, arg3, arg4, arg5) intrRestoreIntrRegValue(pGpu, pIntr, arg3, arg4, arg5)
static inline NV_STATUS intrTriggerCpuDoorbellForVF_46f6a7(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) {
static inline NV_STATUS intrTriggerCpuDoorbellForVF_46f6a7(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid, NvBool bRearmIntr) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS intrTriggerCpuDoorbellForVF_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid);
NV_STATUS intrTriggerCpuDoorbellForVF_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid, NvBool bRearmIntr);
#ifdef __nvoc_intr_h_disabled
static inline NV_STATUS intrTriggerCpuDoorbellForVF(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) {
static inline NV_STATUS intrTriggerCpuDoorbellForVF(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid, NvBool bRearmIntr) {
NV_ASSERT_FAILED_PRECOMP("Intr was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else //__nvoc_intr_h_disabled
#define intrTriggerCpuDoorbellForVF(pGpu, pIntr, gfid) intrTriggerCpuDoorbellForVF_46f6a7(pGpu, pIntr, gfid)
#define intrTriggerCpuDoorbellForVF(pGpu, pIntr, gfid, bRearmIntr) intrTriggerCpuDoorbellForVF_46f6a7(pGpu, pIntr, gfid, bRearmIntr)
#endif //__nvoc_intr_h_disabled
#define intrTriggerCpuDoorbellForVF_HAL(pGpu, pIntr, gfid) intrTriggerCpuDoorbellForVF(pGpu, pIntr, gfid)
#define intrTriggerCpuDoorbellForVF_HAL(pGpu, pIntr, gfid, bRearmIntr) intrTriggerCpuDoorbellForVF(pGpu, pIntr, gfid, bRearmIntr)
void intrRetriggerTopLevel_TU102(OBJGPU *pGpu, struct Intr *pIntr);

25
src/nvidia/generated/g_kernel_bif_nvoc.c
View File

@@ -895,18 +895,25 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner *
pThis->__kbifCacheMnocSupport__ = &kbifCacheMnocSupport_b3696a;
}
// kbifCacheVFInfo -- halified (3 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xc0000000UL) )) /* ChipHal: GB100 | GB102 */
// kbifCacheVFInfo -- halified (4 hals) body
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
{
pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_GB100;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
{
pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_TU102;
pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_b3696a;
}
else
{
pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_GH100;
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xc0000000UL) )) /* ChipHal: GB100 | GB102 */
{
pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_GB100;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
{
pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_TU102;
}
else
{
pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_GH100;
}
}
// kbifRestoreBar0 -- halified (3 hals) body
@@ -1113,7 +1120,7 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner *
{
pThis->__kbifDoSecondaryBusHotReset__ = &kbifDoSecondaryBusHotReset_GH100;
}
} // End __nvoc_init_funcTable_KernelBif_1 with approximately 159 basic block(s).
} // End __nvoc_init_funcTable_KernelBif_1 with approximately 160 basic block(s).
// Initialize vtable(s) for 75 virtual method(s).

6
src/nvidia/generated/g_kernel_bif_nvoc.h
View File

@@ -225,7 +225,7 @@ struct KernelBif {
void (*__kbifCacheFlrSupport__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (3 hals) body
void (*__kbifCache64bBar0Support__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (4 hals) body
void (*__kbifCacheMnocSupport__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (2 hals) body
void (*__kbifCacheVFInfo__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (3 hals) body
void (*__kbifCacheVFInfo__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (4 hals) body
void (*__kbifRestoreBar0__)(struct OBJGPU *, struct KernelBif * /*this*/, void *, NvU32 *); // halified (3 hals) body
NvBool (*__kbifAnyBarsAreValid__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (2 hals) body
NV_STATUS (*__kbifRestoreBarsAndCommand__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (3 hals) body
@@ -1302,6 +1302,10 @@ static inline void kbifCacheMnocSupport_b3696a(struct OBJGPU *pGpu, struct Kerne
void kbifCacheMnocSupport_GB100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif);
static inline void kbifCacheVFInfo_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) {
return;
}
void kbifCacheVFInfo_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif);
void kbifCacheVFInfo_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif);

7
src/nvidia/generated/g_nv_name_released.h
View File

@@ -5416,6 +5416,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2941, 0x21ca, 0x10de, "NVIDIA GB200" },
{ 0x2B85, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090" },
{ 0x2B87, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 D" },
{ 0x2B8C, 0x530c, 0x17aa, "NVIDIA GeForce RTX 5090 D v2" },
{ 0x2BB1, 0x204b, 0x1028, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
{ 0x2BB1, 0x204b, 0x103c, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
{ 0x2BB1, 0x204b, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
@@ -5436,6 +5437,9 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2C31, 0x2051, 0x103c, "NVIDIA RTX PRO 4500 Blackwell" },
{ 0x2C31, 0x2051, 0x10de, "NVIDIA RTX PRO 4500 Blackwell" },
{ 0x2C31, 0x2051, 0x17aa, "NVIDIA RTX PRO 4500 Blackwell" },
{ 0x2C33, 0x2053, 0x1028, "NVIDIA RTX PRO 4000 Blackwell SFF Edition" },
{ 0x2C33, 0x2053, 0x103c, "NVIDIA RTX PRO 4000 Blackwell SFF Edition" },
{ 0x2C33, 0x2053, 0x17aa, "NVIDIA RTX PRO 4000 Blackwell SFF Edition" },
{ 0x2C34, 0x2052, 0x1028, "NVIDIA RTX PRO 4000 Blackwell" },
{ 0x2C34, 0x2052, 0x103c, "NVIDIA RTX PRO 4000 Blackwell" },
{ 0x2C34, 0x2052, 0x10de, "NVIDIA RTX PRO 4000 Blackwell" },
@@ -5448,6 +5452,9 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2D05, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060" },
{ 0x2D18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D19, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },
{ 0x2D30, 0x2054, 0x1028, "NVIDIA RTX PRO 2000 Blackwell" },
{ 0x2D30, 0x2054, 0x103c, "NVIDIA RTX PRO 2000 Blackwell" },
{ 0x2D30, 0x2054, 0x17aa, "NVIDIA RTX PRO 2000 Blackwell" },
{ 0x2D39, 0x0000, 0x0000, "NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU" },
{ 0x2D58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },

8
src/nvidia/generated/g_nvdebug_pb.h
View File

@@ -42,8 +42,8 @@ extern const PRB_MSG_DESC prb_messages_nvdebug[];
// Message maximum lengths
// Does not include repeated fields, strings and byte arrays.
#define NVDEBUG_SYSTEMINFO_LEN 354
#define NVDEBUG_GPUINFO_LEN 262
#define NVDEBUG_NVDUMP_LEN 1613
#define NVDEBUG_GPUINFO_LEN 274
#define NVDEBUG_NVDUMP_LEN 1625
#define NVDEBUG_SYSTEMINFO_NORTHBRIDGEINFO_LEN 12
#define NVDEBUG_SYSTEMINFO_SOCINFO_LEN 12
#define NVDEBUG_SYSTEMINFO_CPUINFO_LEN 24
@@ -101,7 +101,7 @@ extern const PRB_FIELD_DESC prb_fields_nvdebug_gpuinfo[];
#define NVDEBUG_GPUINFO_ENG_GPU_LEN 65
#define NVDEBUG_GPUINFO_ENG_MC_LEN 69
#define NVDEBUG_GPUINFO_ENG_NVD_LEN 33
#define NVDEBUG_GPUINFO_ENG_KGSP_LEN 91
#define NVDEBUG_GPUINFO_ENG_KGSP_LEN 103
extern const PRB_FIELD_DESC prb_fields_nvdebug_nvdump[];
@@ -115,7 +115,7 @@ extern const PRB_FIELD_DESC prb_fields_nvdebug_nvdump[];
// 'NvDump' field lengths
#define NVDEBUG_NVDUMP_SYSTEM_INFO_LEN 357
#define NVDEBUG_NVDUMP_DCL_MSG_LEN 619
#define NVDEBUG_NVDUMP_GPU_INFO_LEN 265
#define NVDEBUG_NVDUMP_GPU_INFO_LEN 277
#define NVDEBUG_NVDUMP_EXCEPTION_ADDRESS_LEN 10
#define NVDEBUG_NVDUMP_SYSTEM_INFO_GSPRM_LEN 357

12
src/nvidia/generated/g_rpc_hal.h
View File

@@ -16,8 +16,8 @@
typedef NV_STATUS RpcConstruct(POBJGPU, POBJRPC);
typedef void RpcDestroy(POBJGPU, POBJRPC);
typedef NV_STATUS RpcSendMessage(POBJGPU, POBJRPC);
typedef NV_STATUS RpcRecvPoll(POBJGPU, POBJRPC, NvU32);
typedef NV_STATUS RpcSendMessage(POBJGPU, POBJRPC, NvU32 *);
typedef NV_STATUS RpcRecvPoll(POBJGPU, POBJRPC, NvU32, NvU32);
//
@@ -42,10 +42,10 @@ typedef struct RPC_OBJ_IFACES {
(_pRpc)->obj.__rpcConstruct__(_pGpu, _pRpc)
#define rpcDestroy(_pGpu, _pRpc) \
(_pRpc)->obj.__rpcDestroy__(_pGpu, _pRpc)
#define rpcSendMessage(_pGpu, _pRpc) \
(_pRpc)->obj.__rpcSendMessage__(_pGpu, _pRpc)
#define rpcRecvPoll(_pGpu, _pRpc, _arg0) \
(_pRpc)->obj.__rpcRecvPoll__(_pGpu, _pRpc, _arg0)
#define rpcSendMessage(_pGpu, _pRpc, _pArg0) \
(_pRpc)->obj.__rpcSendMessage__(_pGpu, _pRpc, _pArg0)
#define rpcRecvPoll(_pGpu, _pRpc, _arg0, _arg1) \
(_pRpc)->obj.__rpcRecvPoll__(_pGpu, _pRpc, _arg0, _arg1)
//

1
src/nvidia/generated/g_system_nvoc.c
View File

@@ -103,6 +103,7 @@ void __nvoc_init_dataField_OBJSYS(OBJSYS *pThis) {
pThis->clientListDeferredFreeLimit = 0;
pThis->setProperty(pThis, PDB_PROP_SYS_RECOVERY_REBOOT_REQUIRED, NV_FALSE);
pThis->setProperty(pThis, PDB_PROP_SYS_SUPPORTS_S0IX, (0));
}
NV_STATUS __nvoc_ctor_Object(Object* );

5
src/nvidia/generated/g_system_nvoc.h
View File

@@ -418,7 +418,7 @@ struct OBJSYS {
struct OBJTRACEABLE *__nvoc_pbase_OBJTRACEABLE; // traceable super
struct OBJSYS *__nvoc_pbase_OBJSYS; // sys
// 34 PDB properties
// 35 PDB properties
NvBool PDB_PROP_SYS_SBIOS_NVIF_POWERMIZER_LIMIT;
NvBool PDB_PROP_SYS_MXM_THERMAL_CONTROL_PRESENT;
NvBool PDB_PROP_SYS_POWER_BATTERY;
@@ -453,6 +453,7 @@ struct OBJSYS {
NvBool PDB_PROP_SYS_ENABLE_FORCE_SHARED_LOCK;
NvBool PDB_PROP_SYS_DESTRUCTING;
NvBool PDB_PROP_SYS_RECOVERY_REBOOT_REQUIRED;
NvBool PDB_PROP_SYS_SUPPORTS_S0IX;
// Data members
NvU32 apiLockMask;
@@ -547,6 +548,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJSYS;
#define PDB_PROP_SYS_VALIDATE_CLIENT_HANDLE_STRICT_BASE_NAME PDB_PROP_SYS_VALIDATE_CLIENT_HANDLE_STRICT
#define PDB_PROP_SYS_DESTRUCTING_BASE_CAST
#define PDB_PROP_SYS_DESTRUCTING_BASE_NAME PDB_PROP_SYS_DESTRUCTING
#define PDB_PROP_SYS_SUPPORTS_S0IX_BASE_CAST
#define PDB_PROP_SYS_SUPPORTS_S0IX_BASE_NAME PDB_PROP_SYS_SUPPORTS_S0IX
#define PDB_PROP_SYS_VALIDATE_KERNEL_BUFFERS_BASE_CAST
#define PDB_PROP_SYS_VALIDATE_KERNEL_BUFFERS_BASE_NAME PDB_PROP_SYS_VALIDATE_KERNEL_BUFFERS
#define PDB_PROP_SYS_PRIMARY_VBIOS_STATE_SAVED_BASE_CAST

1
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
View File

@@ -218,6 +218,7 @@ typedef struct GspSystemInfo
NvBool bRouteDispIntrsToCPU;
NvU64 hostPageSize;
NvBool bGspNocatEnabled;
NvBool bS0ixSupport;
NvU16 virtualConfigBits;
} GspSystemInfo;

4
src/nvidia/inc/kernel/gpu/rpc/objrpc.h
View File

@@ -58,6 +58,7 @@ TYPEDEF_BITVECTOR(MC_ENGINE_BITVECTOR);
typedef struct RpcHistoryEntry
{
NvU32 function;
NvU32 sequence;
NvU64 data[2];
NvU64 ts_start;
NvU64 ts_end;
@@ -89,6 +90,9 @@ struct OBJRPC{
NvU32 rpcHistoryCurrent;
RpcHistoryEntry rpcEventHistory[RPC_HISTORY_DEPTH];
NvU32 rpcEventHistoryCurrent;
/* sequence number for RPC */
NvU32 sequence;
NvU32 timeoutCount;
NvBool bQuietPrints;

70
src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c
View File

@@ -129,9 +129,9 @@ static void _kgspFreeRpcInfrastructure(OBJGPU *, KernelGsp *);
static NV_STATUS _kgspConstructRpcObject(OBJGPU *, KernelGsp *, MESSAGE_QUEUE_INFO *, OBJRPC **);
static NV_STATUS _kgspRpcSendMessage(OBJGPU *, OBJRPC *);
static NV_STATUS _kgspRpcRecvPoll(OBJGPU *, OBJRPC *, NvU32);
static NV_STATUS _kgspRpcDrainEvents(OBJGPU *, KernelGsp *, NvU32, KernelGspRpcEventHandlerContext);
static NV_STATUS _kgspRpcSendMessage(OBJGPU *, OBJRPC *, NvU32 *);
static NV_STATUS _kgspRpcRecvPoll(OBJGPU *, OBJRPC *, NvU32, NvU32);
static NV_STATUS _kgspRpcDrainEvents(OBJGPU *, KernelGsp *, NvU32, NvU32, KernelGspRpcEventHandlerContext);
static void _kgspRpcIncrementTimeoutCountAndRateLimitPrints(OBJGPU *, OBJRPC *);
static NV_STATUS _kgspAllocSimAccessBuffer(OBJGPU *pGpu, KernelGsp *pKernelGsp);
@@ -312,12 +312,14 @@ _kgspAddRpcHistoryEntry
)
{
NvU32 func = RPC_HDR->function;
NvU32 sequence = RPC_HDR->sequence;
NvU32 entry;
entry = *pCurrent = (*pCurrent + 1) % RPC_HISTORY_DEPTH;
portMemSet(&pHistory[entry], 0, sizeof(pHistory[0]));
pHistory[entry].function = func;
pHistory[entry].sequence = sequence;
pHistory[entry].ts_start = osGetTimestamp();
_kgspGetActiveRpcDebugData(pRpc, func,
@@ -367,7 +369,8 @@ static NV_STATUS
_kgspRpcSendMessage
(
OBJGPU *pGpu,
OBJRPC *pRpc
OBJRPC *pRpc,
NvU32 *pSequence
)
{
NV_STATUS nvStatus;
@@ -376,6 +379,11 @@ _kgspRpcSendMessage
NV_ASSERT(rmGpuGroupLockIsOwner(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &gpuMaskUnused));
if (pSequence)
vgpu_rpc_message_header_v->sequence = *pSequence = pRpc->sequence++;
else
vgpu_rpc_message_header_v->sequence = 0;
NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, _kgspRpcSanityCheck(pGpu, pKernelGsp, pRpc));
nvStatus = GspMsgQueueSendCommand(pRpc->pMessageQueueInfo, pGpu);
@@ -1582,8 +1590,8 @@ _kgspProcessRpcEvent
// eventually comes in as an unexpected event. The error handling
// for the timeout should have already happened.
//
NV_PRINTF(LEVEL_ERROR, "Unexpected RPC event from GPU%d: 0x%x (%s)\n",
gpuGetInstance(pGpu), event, _getRpcName(event));
NV_PRINTF(LEVEL_ERROR, "Unexpected RPC event from GPU%d: 0x%x (%s), sequence: %u\n",
gpuGetInstance(pGpu), event, _getRpcName(event), pMsgHdr->sequence);
break;
}
@@ -1718,6 +1726,7 @@ _kgspRpcDrainOneEvent
OBJGPU *pGpu,
OBJRPC *pRpc,
NvU32 expectedFunc,
NvU32 expectedSequence,
KernelGspRpcEventHandlerContext rpcHandlerContext
)
{
@@ -1734,8 +1743,11 @@ _kgspRpcDrainOneEvent
{
rpc_message_header_v *pMsgHdr = RPC_HDR;
if (pMsgHdr->function == expectedFunc)
if (pMsgHdr->function == expectedFunc &&
pMsgHdr->sequence == expectedSequence)
{
return NV_WARN_MORE_PROCESSING_REQUIRED;
}
_kgspProcessRpcEvent(pGpu, pRpc, rpcHandlerContext);
}
@@ -1768,6 +1780,7 @@ _kgspRpcDrainEvents
OBJGPU *pGpu,
KernelGsp *pKernelGsp,
NvU32 expectedFunc,
NvU32 expectedSequence,
KernelGspRpcEventHandlerContext rpcHandlerContext
)
{
@@ -1776,7 +1789,7 @@ _kgspRpcDrainEvents
while (nvStatus == NV_OK)
{
nvStatus = _kgspRpcDrainOneEvent(pGpu, pRpc, expectedFunc, rpcHandlerContext);
nvStatus = _kgspRpcDrainOneEvent(pGpu, pRpc, expectedFunc, expectedSequence, rpcHandlerContext);
kgspDumpGspLogs(pKernelGsp, NV_FALSE);
}
@@ -1871,11 +1884,12 @@ _kgspLogRpcHistoryEntry
duration = _tsDiffToDuration(duration, &durationUnitsChar);
NV_ERROR_LOG_DATA(pGpu, errorNum,
" %c%-4d %-4d %-21.21s 0x%016llx 0x%016llx 0x%016llx 0x%016llx %6llu%cs %c\n",
" %c%-4d %-4d %-21.21s %10u 0x%016llx 0x%016llx 0x%016llx 0x%016llx %6llu%cs %c\n",
((historyIndex == 0) ? ' ' : '-'),
historyIndex,
pEntry->function,
_getRpcName(pEntry->function),
pEntry->sequence,
pEntry->data[0],
pEntry->data[1],
pEntry->ts_start,
@@ -1886,11 +1900,12 @@ _kgspLogRpcHistoryEntry
else
{
NV_ERROR_LOG_DATA(pGpu, errorNum,
" %c%-4d %-4d %-21.21s 0x%016llx 0x%016llx 0x%016llx 0x%016llx %c\n",
" %c%-4d %-4d %-21.21s %10u 0x%016llx 0x%016llx 0x%016llx 0x%016llx %c\n",
((historyIndex == 0) ? ' ' : '-'),
historyIndex,
pEntry->function,
_getRpcName(pEntry->function),
pEntry->sequence,
pEntry->data[0],
pEntry->data[1],
pEntry->ts_start,
@@ -1918,16 +1933,16 @@ kgspLogRpcDebugInfo
_kgspGetActiveRpcDebugData(pRpc, pMsgHdr->function,
&activeData[0], &activeData[1]);
NV_ERROR_LOG_DATA(pGpu, errorNum,
"GPU%d GSP RPC buffer contains function %d (%s) and data 0x%016llx 0x%016llx.\n",
"GPU%d GSP RPC buffer contains function %d (%s) sequence %u and data 0x%016llx 0x%016llx.\n",
gpuGetInstance(pGpu),
pMsgHdr->function, _getRpcName(pMsgHdr->function),
pMsgHdr->function, _getRpcName(pMsgHdr->function), pMsgHdr->sequence,
activeData[0], activeData[1]);
NV_ERROR_LOG_DATA(pGpu, errorNum,
"GPU%d RPC history (CPU -> GSP):\n",
gpuGetInstance(pGpu));
NV_ERROR_LOG_DATA(pGpu, errorNum,
" entry function data0 data1 ts_start ts_end duration actively_polling\n");
" entry function sequence data0 data1 ts_start ts_end duration actively_polling\n");
for (historyIndex = 0; historyIndex < rpcEntriesToLog; historyIndex++)
{
historyEntry = (pRpc->rpcHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH;
@@ -1939,7 +1954,7 @@ kgspLogRpcDebugInfo
"GPU%d RPC event history (CPU <- GSP):\n",
gpuGetInstance(pGpu));
NV_ERROR_LOG_DATA(pGpu, errorNum,
" entry function data0 data1 ts_start ts_end duration during_incomplete_rpc\n");
" entry function sequence data0 data1 ts_start ts_end duration during_incomplete_rpc\n");
for (historyIndex = 0; historyIndex < rpcEntriesToLog; historyIndex++)
{
historyEntry = (pRpc->rpcEventHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH;
@@ -1958,7 +1973,8 @@ _kgspLogXid119
(
OBJGPU *pGpu,
OBJRPC *pRpc,
NvU32 expectedFunc
NvU32 expectedFunc,
NvU32 expectedSequence
)
{
RpcHistoryEntry *pHistoryEntry = &pRpc->rpcHistory[pRpc->rpcHistoryCurrent];
@@ -1980,11 +1996,12 @@ _kgspLogXid119
duration = _tsDiffToDuration(ts_end - pHistoryEntry->ts_start, &durationUnitsChar);
NV_ERROR_LOG(pGpu, GSP_RPC_TIMEOUT,
"Timeout after %llus of waiting for RPC response from GPU%d GSP! Expected function %d (%s) (0x%llx 0x%llx).",
"Timeout after %llus of waiting for RPC response from GPU%d GSP! Expected function %d (%s) sequence %u (0x%llx 0x%llx).",
(durationUnitsChar == 'm' ? duration / 1000 : duration),
gpuGetInstance(pGpu),
expectedFunc,
_getRpcName(expectedFunc),
expectedSequence,
pHistoryEntry->data[0],
pHistoryEntry->data[1]);
@@ -2013,7 +2030,8 @@ _kgspLogRpcSanityCheckFailure
OBJGPU *pGpu,
OBJRPC *pRpc,
NvU32 rpcStatus,
NvU32 expectedFunc
NvU32 expectedFunc,
NvU32 expectedSequence
)
{
RpcHistoryEntry *pHistoryEntry = &pRpc->rpcHistory[pRpc->rpcHistoryCurrent];
@@ -2021,11 +2039,12 @@ _kgspLogRpcSanityCheckFailure
NV_ASSERT(expectedFunc == pHistoryEntry->function);
NV_PRINTF(LEVEL_ERROR,
"GPU%d sanity check failed 0x%x waiting for RPC response from GSP. Expected function %d (%s) (0x%llx 0x%llx).\n",
"GPU%d sanity check failed 0x%x waiting for RPC response from GSP. Expected function %d (%s) sequence %u (0x%llx 0x%llx).\n",
gpuGetInstance(pGpu),
rpcStatus,
expectedFunc,
_getRpcName(expectedFunc),
expectedSequence,
pHistoryEntry->data[0],
pHistoryEntry->data[1]);
@@ -2072,7 +2091,8 @@ _kgspRpcRecvPoll
(
OBJGPU *pGpu,
OBJRPC *pRpc,
NvU32 expectedFunc
NvU32 expectedFunc,
NvU32 expectedSequence
)
{
KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu);
@@ -2165,7 +2185,7 @@ _kgspRpcRecvPoll
//
timeoutStatus = gpuCheckTimeout(pGpu, &timeout);
rpcStatus = _kgspRpcDrainEvents(pGpu, pKernelGsp, expectedFunc, rpcHandlerContext);
rpcStatus = _kgspRpcDrainEvents(pGpu, pKernelGsp, expectedFunc, expectedSequence, rpcHandlerContext);
switch (rpcStatus) {
case NV_WARN_MORE_PROCESSING_REQUIRED:
@@ -2191,7 +2211,7 @@ _kgspRpcRecvPoll
{
if (!pRpc->bQuietPrints)
{
_kgspLogRpcSanityCheckFailure(pGpu, pRpc, rpcStatus, expectedFunc);
_kgspLogRpcSanityCheckFailure(pGpu, pRpc, rpcStatus, expectedFunc, expectedSequence);
pRpc->bQuietPrints = NV_TRUE;
}
goto done;
@@ -2205,7 +2225,7 @@ _kgspRpcRecvPoll
if (!pRpc->bQuietPrints)
{
_kgspLogXid119(pGpu, pRpc, expectedFunc);
_kgspLogXid119(pGpu, pRpc, expectedFunc, expectedSequence);
}
goto done;
@@ -4744,7 +4764,7 @@ kgspRpcRecvEvents_IMPL
// If we do the assert will fail on NV_WARN_MORE_PROCESSING_REQUIRED,
// in addition to general error codes.
//
NV_ASSERT_OK(_kgspRpcDrainEvents(pGpu, pKernelGsp, NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS, KGSP_RPC_EVENT_HANDLER_CONTEXT_INTERRUPT));
NV_ASSERT_OK(_kgspRpcDrainEvents(pGpu, pKernelGsp, NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS, 0, KGSP_RPC_EVENT_HANDLER_CONTEXT_INTERRUPT));
}
/*!
@@ -4766,7 +4786,7 @@ kgspWaitForRmInitDone_IMPL
threadStateResetTimeout(pGpu);
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
rpcRecvPoll(pGpu, pRpc, NV_VGPU_MSG_EVENT_GSP_INIT_DONE));
rpcRecvPoll(pGpu, pRpc, NV_VGPU_MSG_EVENT_GSP_INIT_DONE, 0));
//
// Now check if RPC really succeeded (NV_VGPU_MSG_RESULT_* are defined to
@@ -5256,6 +5276,7 @@ static NV_STATUS _kgspDumpEngineFunc
prbEncNestedStart(pPrbEnc, NVDEBUG_ENG_KGSP_RPC_HISTORY));
prbEncAddUInt32(pPrbEnc, NVDEBUG_ENG_KGSP_RPCINFO_FUNCTION, entry->function);
prbEncAddUInt32(pPrbEnc, NVDEBUG_ENG_KGSP_RPCINFO_SEQUENCE, entry->sequence);
prbEncAddUInt64(pPrbEnc, NVDEBUG_ENG_KGSP_RPCINFO_TS_START, entry->ts_start);
prbEncAddUInt64(pPrbEnc, NVDEBUG_ENG_KGSP_RPCINFO_TS_END, entry->ts_end);
prbEncAddUInt32(pPrbEnc, NVDEBUG_ENG_KGSP_RPCINFO_DATA0, entry->data[0]);
@@ -5276,6 +5297,7 @@ static NV_STATUS _kgspDumpEngineFunc
prbEncNestedStart(pPrbEnc, NVDEBUG_ENG_KGSP_EVENT_HISTORY));
prbEncAddUInt32(pPrbEnc, NVDEBUG_ENG_KGSP_RPCINFO_FUNCTION, entry->function);
prbEncAddUInt32(pPrbEnc, NVDEBUG_ENG_KGSP_RPCINFO_SEQUENCE, entry->sequence);
prbEncAddUInt64(pPrbEnc, NVDEBUG_ENG_KGSP_RPCINFO_TS_START, entry->ts_start);
prbEncAddUInt64(pPrbEnc, NVDEBUG_ENG_KGSP_RPCINFO_TS_END, entry->ts_end);
prbEncAddUInt32(pPrbEnc, NVDEBUG_ENG_KGSP_RPCINFO_DATA0, entry->data[0]);

25
src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c
View File

@@ -49,6 +49,7 @@
#include "vgpu/rpc.h"
#include "vgpu/vgpu_events.h"
#include "nvdevid.h"
//
// statics
@@ -1412,15 +1413,37 @@ memmgrGetRsvdSizeForSr_GM107
MemoryManager *pMemoryManager
)
{
//
// Temporary WAR to override WDDM S/R buffer for specific skus
// Bug 5327051
//
static const NvU16 gb20x_devid[] = { 0x2B8C };
NvU32 pciDeviceID = DRF_VAL(_PCI, _DEVID, _DEVICE, pGpu->idInfo.PCIDeviceID);
NvBool overrideFbsrRsvdBufferSize = NV_FALSE;
for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(gb20x_devid); i++)
{
if (pciDeviceID == gb20x_devid[i])
{
overrideFbsrRsvdBufferSize = NV_TRUE;
break;
}
}
if (((pMemoryManager->Ram.fbTotalMemSizeMb >> 10) >= 31) || IS_GSP_CLIENT(pGpu))
{
//
// We need to reserve more memory for S/R if
// 1. FB size is > 32GB Bug Id: 2468357
// 1. FB size is >= 31GB Bug Id: 2468357
// 2. Or GSP is enabled Bug Id: 4312881
//
return 512 * 1024 * 1024;
}
else if (overrideFbsrRsvdBufferSize)
{
// Bug 5327051: WAR to override WDDM S/R buffer for specific skus
return 300 * 1024 * 1024;
}
else
{
return 256 * 1024 * 1024;

2
src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c
View File

@@ -306,8 +306,6 @@ memdescCreate
// (4k >> 12 = 1). This modification helps us to avoid overflow of variable
// allocSize, in case caller of this function passes highest value of NvU64.
//
// If allocSize is passed as 0, PageCount should be returned as 0.
//
if (allocSize == 0)
{
PageCount = 0;

2
src/nvidia/src/kernel/mem_mgr/standard_mem.c
View File

@@ -57,7 +57,7 @@ NV_STATUS stdmemValidateParams
return NV_ERR_INVALID_ARGUMENT;
}
//
//
// These flags don't do anything in this path. No mapping on alloc and
// kernel map is controlled by TYPE
//

2
src/nvidia/src/kernel/rmapi/nv_gpu_ops.c
View File

@@ -7694,7 +7694,7 @@ static NV_STATUS dupMemory(struct gpuDevice *device,
// particular doesn't create IOMMU mappings required for the mapped GPU
// to access the memory. That's a problem if the mapped GPU is different
// from the GPU that the allocation was created under. Add them
// explicitly here and remove them when the memory is freed in n
// explicitly here and remove them when the memory is freed in
// nvGpuOpsFreeDupedHandle(). Notably memdescMapIommu() refcounts the
// mappings so it's ok to call it if the mappings are already there.
//

3
src/nvidia/src/kernel/rmapi/rpc_common.c
View File

@@ -88,7 +88,8 @@ OBJRPC *initRpcObject(OBJGPU *pGpu)
pRpc->timeoutCount = 0;
pRpc->bQuietPrints = NV_FALSE;
// VIRTUALIZATION is disabled on DCE. Only run the below code on VGPU and GSP.
pRpc->sequence = 0;
// VIRTUALIZATION is disabled on DCE. Only run the below code on VGPU and GSP.
rpcSetIpVersion(pGpu, pRpc,
RPC_VERSION_FROM_VGX_VERSION(VGX_MAJOR_VERSION_NUMBER,
VGX_MINOR_VERSION_NUMBER));

82
src/nvidia/src/kernel/vgpu/rpc.c
View File

@@ -120,8 +120,8 @@ static NvU64 startTimeInNs, endTimeInNs, elapsedTimeInNs;
static NV_STATUS updateHostVgpuFbUsage(OBJGPU *pGpu, NvHandle hClient, NvHandle hDevice,
NvHandle hSubdevice);
static NV_STATUS _rpcSendMessage_VGPUGSP(OBJGPU *pGpu, OBJRPC *pRPC);
static NV_STATUS _rpcRecvPoll_VGPUGSP(OBJGPU *pGpu, OBJRPC *pRPC, NvU32 expectedFunc);
static NV_STATUS _rpcSendMessage_VGPUGSP(OBJGPU *pGpu, OBJRPC *pRPC, NvU32 *pSequence);
static NV_STATUS _rpcRecvPoll_VGPUGSP(OBJGPU *pGpu, OBJRPC *pRPC, NvU32 expectedFunc, NvU32 expectedSequence);
void setGuestEccStatus(OBJGPU *pGpu);
typedef NV_STATUS dma_control_copy_params_to_rpc_buffer_v(NvU32 cmd, void *Params, void *params_in);
@@ -1386,6 +1386,9 @@ NV_STATUS vgpuGspSetupBuffers(OBJGPU *pGpu)
return NV_ERR_NOT_SUPPORTED;
}
// Modifying the DMA address size to the value supported by the hardware
osDmaSetAddressSize(pGpu->pOsGpuInfo, gpuGetPhysAddrWidth_HAL(pGpu, ADDR_SYSMEM));
rpcSendMessage_FNPTR(pVGpu->pRpc) = _rpcSendMessage_VGPUGSP;
rpcRecvPoll_FNPTR(pVGpu->pRpc) = _rpcRecvPoll_VGPUGSP;
@@ -1665,28 +1668,29 @@ NV_STATUS freeRpcInfrastructure_VGPU(OBJGPU *pGpu)
return rmStatus;
}
NV_STATUS rpcSendMessage_IMPL(OBJGPU *pGpu, OBJRPC *pRpc)
NV_STATUS rpcSendMessage_IMPL(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 *pSequence)
{
NV_PRINTF(LEVEL_ERROR, "virtual function not implemented.\n");
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS rpcRecvPoll_IMPL(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 expectedFunc)
NV_STATUS rpcRecvPoll_IMPL(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 expectedFunc, NvU32 expectedSequence)
{
NV_PRINTF(LEVEL_ERROR, "virtual function not implemented.\n");
return NV_ERR_NOT_SUPPORTED;
}
static NV_STATUS _rpcSendMessage_VGPUGSP(OBJGPU *pGpu, OBJRPC *pRpc)
static NV_STATUS _rpcSendMessage_VGPUGSP(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 *pSequence)
{
OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu);
vgpu_rpc_message_header_v->sequence = pVGpu->sequence_base++;
NV_ASSERT(pSequence != NULL);
vgpu_rpc_message_header_v->sequence = *pSequence = pVGpu->sequence_base++;
return _vgpuGspSendRpcRequest(pGpu, pRpc);
}
static NV_STATUS _rpcRecvPoll_VGPUGSP(OBJGPU *pGpu, OBJRPC *pRPC, NvU32 expectedFunc)
static NV_STATUS _rpcRecvPoll_VGPUGSP(OBJGPU *pGpu, OBJRPC *pRPC, NvU32 expectedFunc, NvU32 expectedSequence)
{
return _vgpuGspWaitForResponse(pGpu);
}
@@ -1722,6 +1726,15 @@ static NV_STATUS _issueRpcAndWait(OBJGPU *pGpu, OBJRPC *pRpc)
pNewEntry->rpcData.rpcDataTag = vgpu_rpc_message_header_v->function;
switch (vgpu_rpc_message_header_v->function)
{
case NV_VGPU_MSG_FUNCTION_RM_API_CONTROL:
pNewEntry->rpcData.rpcExtraData = rpc_message->rm_api_control_v.params.cmd;
break;
default:
break;
}
rpcProfilerEntryCount++;
osGetPerformanceCounter(&pNewEntry->rpcData.startTimeInNs);
@@ -1729,13 +1742,14 @@ static NV_STATUS _issueRpcAndWait(OBJGPU *pGpu, OBJRPC *pRpc)
// For HCC, cache expectedFunc value before encrypting.
NvU32 expectedFunc = vgpu_rpc_message_header_v->function;
NvU32 expectedSequence = 0;
status = rpcSendMessage(pGpu, pRpc);
status = rpcSendMessage(pGpu, pRpc, &expectedSequence);
if (status != NV_OK)
{
NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR,
"rpcSendMessage failed with status 0x%08x for fn %d!\n",
status, vgpu_rpc_message_header_v->function);
"rpcSendMessage failed with status 0x%08x for fn %d sequence %d!\n",
status, expectedFunc, expectedSequence);
//
// It has been observed that returning NV_ERR_BUSY_RETRY in a bad state (RPC
// buffers full and not being serviced) can make things worse, i.e. turn RPC
@@ -1746,20 +1760,20 @@ static NV_STATUS _issueRpcAndWait(OBJGPU *pGpu, OBJRPC *pRpc)
}
// Use cached expectedFunc here because vgpu_rpc_message_header_v is encrypted for HCC.
status = rpcRecvPoll(pGpu, pRpc, expectedFunc);
status = rpcRecvPoll(pGpu, pRpc, expectedFunc, expectedSequence);
if (status != NV_OK)
{
if (status == NV_ERR_TIMEOUT)
{
NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR,
"rpcRecvPoll timedout for fn %d!\n",
vgpu_rpc_message_header_v->function);
"rpcRecvPoll timedout for fn %d sequence %u!\n",
expectedFunc, expectedSequence);
}
else
{
NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR,
"rpcRecvPoll failed with status 0x%08x for fn %d!\n",
status, vgpu_rpc_message_header_v->function);
"rpcRecvPoll failed with status 0x%08x for fn %d sequence %u!\n",
status, expectedFunc, expectedSequence);
}
return status;
}
@@ -1793,10 +1807,10 @@ static NV_STATUS _issueRpcAsync(OBJGPU *pGpu, OBJRPC *pRpc)
// should not be called in broadcast mode
NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE);
status = rpcSendMessage(pGpu, pRpc);
status = rpcSendMessage(pGpu, pRpc, NULL);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "rpcSendMessage failed with status 0x%08x for fn %d!\n",
NV_PRINTF(LEVEL_ERROR, "rpcSendMessage async failed with status 0x%08x for fn %d!\n",
status, vgpu_rpc_message_header_v->function);
NV_ASSERT(0);
//
@@ -1824,6 +1838,8 @@ static NV_STATUS _issueRpcLarge
NvU8 *pBuf8 = (NvU8 *)pBuffer;
NV_STATUS nvStatus = NV_OK;
NvU32 expectedFunc = vgpu_rpc_message_header_v->function;
NvU32 firstSequence = pRpc->sequence;
NvU32 lastSequence, waitSequence;
NvU32 entryLength;
NvU32 remainingSize = bufSize;
NvU32 recordCount = 0;
@@ -1840,7 +1856,7 @@ static NV_STATUS _issueRpcLarge
// Set the correct length for this queue entry.
vgpu_rpc_message_header_v->length = entryLength;
nvStatus = rpcSendMessage(pGpu, pRpc);
nvStatus = rpcSendMessage(pGpu, pRpc, &firstSequence);
if (nvStatus != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "rpcSendMessage failed with status 0x%08x for fn %d!\n",
@@ -1876,7 +1892,7 @@ static NV_STATUS _issueRpcLarge
vgpu_rpc_message_header_v->length = entryLength + sizeof(rpc_message_header_v);
vgpu_rpc_message_header_v->function = NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD;
nvStatus = rpcSendMessage(pGpu, pRpc);
nvStatus = rpcSendMessage(pGpu, pRpc, &lastSequence);
if (nvStatus != NV_OK)
{
NV_PRINTF(LEVEL_ERROR,
@@ -1897,6 +1913,8 @@ static NV_STATUS _issueRpcLarge
recordCount++;
}
NV_ASSERT(lastSequence == (firstSequence + recordCount));
if (!bWait)
{
// In case of Async RPC, we are done here.
@@ -1904,18 +1922,20 @@ static NV_STATUS _issueRpcLarge
}
// Always receive at least one..
nvStatus = rpcRecvPoll(pGpu, pRpc, expectedFunc);
waitSequence = firstSequence;
nvStatus = rpcRecvPoll(pGpu, pRpc, expectedFunc, waitSequence);
if (nvStatus != NV_OK)
{
if (nvStatus == NV_ERR_TIMEOUT)
{
NV_PRINTF(LEVEL_ERROR, "rpcRecvPoll timedout for fn %d!\n",
vgpu_rpc_message_header_v->function);
NV_PRINTF(LEVEL_ERROR, "rpcRecvPoll timedout for fn %d sequence %d!\n",
expectedFunc, waitSequence);
}
else
{
NV_PRINTF(LEVEL_ERROR, "rpcRecvPoll failed with status 0x%08x for fn %d!\n",
nvStatus, vgpu_rpc_message_header_v->function);
NV_PRINTF(LEVEL_ERROR, "rpcRecvPoll failed with status 0x%08x for fn %d sequence %d!\n",
nvStatus, expectedFunc, waitSequence);
}
NV_ASSERT(0);
return nvStatus;
@@ -1931,26 +1951,27 @@ static NV_STATUS _issueRpcLarge
remainingSize -= entryLength;
pBuf8 += entryLength;
waitSequence++;
// For bidirectional transfer messages, need to receive all other frames as well
if (bBidirectional && (recordCount > 0))
{
while (remainingSize > 0)
{
nvStatus = rpcRecvPoll(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD);
nvStatus = rpcRecvPoll(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD, waitSequence);
if (nvStatus != NV_OK)
{
if (nvStatus == NV_ERR_TIMEOUT)
{
NV_PRINTF(LEVEL_ERROR,
"rpcRecvPoll timedout for fn %d continuation record (remainingSize=0x%x)!\n",
vgpu_rpc_message_header_v->function, remainingSize);
"rpcRecvPoll timedout for fn %d sequence %d continuation record (remainingSize=0x%x)!\n",
expectedFunc, waitSequence, remainingSize);
}
else
{
NV_PRINTF(LEVEL_ERROR,
"rpcRecvPoll failed with status 0x%08x for fn %d continuation record! (remainingSize=0x%x)\n",
nvStatus, vgpu_rpc_message_header_v->function, remainingSize);
"rpcRecvPoll failed with status 0x%08x for fn %d sequence %d continuation record! (remainingSize=0x%x)\n",
nvStatus, expectedFunc, waitSequence, remainingSize);
}
NV_ASSERT(0);
return nvStatus;
@@ -1968,9 +1989,11 @@ static NV_STATUS _issueRpcLarge
remainingSize -= entryLength;
pBuf8 += entryLength;
recordCount--;
waitSequence++;
}
vgpu_rpc_message_header_v->function = expectedFunc;
NV_ASSERT(recordCount == 0);
NV_ASSERT(waitSequence - 1 == lastSequence);
}
// Now check if RPC really succeeded
@@ -9577,6 +9600,7 @@ NV_STATUS rpcGspSetSystemInfo_v17_00
rpcInfo->bIsPrimary = pGpu->getProperty(pGpu, PDB_PROP_GPU_PRIMARY_DEVICE);
rpcInfo->bS0ixSupport = pSys->getProperty(pSys, PDB_PROP_SYS_SUPPORTS_S0IX);
#if defined(NV_UNIX) && !RMCFG_FEATURE_MODS_FEATURES
rpcInfo->isGridBuild = os_is_grid_supported();
#endif