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This commit is contained in:
Bernhard Stoeckner
2025-02-27 17:32:23 +01:00
parent 81fe4fb417
commit 129479b1b7
141 changed files with 102245 additions and 100070 deletions
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19
src/common/displayport/inc/dp_configcaps.h
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@@ -567,8 +567,10 @@ namespace DisplayPort
virtual AuxRetry::status notifySDPErrDetectionCapability() = 0;
virtual bool isDp2xChannelCodingCapable() = 0;
virtual void setIgnoreCableIdCaps(bool bIgnore) = 0;
virtual void overrideCableIdCap(LinkRate linkRate, bool bEnable) = 0;
virtual void initialize() = 0;
virtual AuxRetry::status setMainLinkChannelCoding(MainLinkChannelCoding channelCoding) = 0;
virtual void setConnectorTypeC(bool bTypeC) = 0;
virtual ~DPCDHAL() {}
};
@@ -1483,23 +1485,16 @@ namespace DisplayPort
bool clearDpTunnelingEstimatedBwStatus();
bool clearDpTunnelingBwAllocationCapStatus();
virtual AuxRetry::status notifySDPErrDetectionCapability()
{
return AuxRetry::ack;
}
virtual bool isDp2xChannelCodingCapable()
{
return false;
}
virtual void setIgnoreCableIdCaps(bool bIgnore)
{
return;
}
virtual AuxRetry::status notifySDPErrDetectionCapability() { return AuxRetry::ack; }
virtual bool isDp2xChannelCodingCapable() { return false; }
virtual void setIgnoreCableIdCaps(bool bIgnore) { return; }
virtual void overrideCableIdCap(LinkRate linkRate, bool bEnable) { return; }
// implement this function if DPCDHALImpl needs updated state between hotunplug/plug
virtual void initialize(){};
virtual AuxRetry::status setMainLinkChannelCoding(MainLinkChannelCoding channelCoding){ return AuxRetry::ack; }
virtual MainLinkChannelCoding getMainLinkChannelCoding() { return ChannelCoding8B10B; }
virtual void setConnectorTypeC(bool bTypeC) {};
};
}

22
src/common/displayport/inc/dp_configcaps2x.h
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@@ -104,14 +104,17 @@ namespace DisplayPort
virtual AuxRetry::status setMainLinkChannelCoding(MainLinkChannelCoding channelCoding);
virtual MainLinkChannelCoding getMainLinkChannelCoding();
void performCableIdHandshake();
virtual void setGpuDPSupportedVersions(NvU32 _gpuDPSupportedVersions);
virtual bool isDp2xChannelCodingCapable();
virtual void parseAndReadCaps();
virtual LinkRate getMaxLinkRate();
virtual NvU32 getUHBRSupported();
virtual void setIgnoreCableIdCaps(bool bIgnore){ bIgnoreCableIdCaps = bIgnore; }
void performCableIdHandshake();
void performCableIdHandshakeForTypeC();
void parseAndSetCableId(NvU8 cableId);
virtual void setGpuDPSupportedVersions(NvU32 _gpuDPSupportedVersions);
virtual bool isDp2xChannelCodingCapable();
virtual void parseAndReadCaps();
virtual LinkRate getMaxLinkRate();
virtual NvU32 getUHBRSupported();
virtual void setIgnoreCableIdCaps(bool bIgnore){ bIgnoreCableIdCaps = bIgnore; }
virtual void overrideCableIdCap(LinkRate linkRate, bool bEnable);
virtual bool parseTestRequestPhy();
virtual bool parseTestRequestTraining(NvU8 * buffer);
// DPCD offset 2230 - 2250
@@ -123,13 +126,16 @@ namespace DisplayPort
// class fields that need re-initialization
bool bIgnoreCableIdCaps;
bool bConnectorIsTypeC;
virtual void initialize()
{
setIgnoreCableIdCaps(false);
}
DPCDHALImpl2x(AuxBus * bus, Timer * timer) : DPCDHALImpl(bus, timer), bIgnoreCableIdCaps(false)
virtual void setConnectorTypeC(bool bTypeC);
DPCDHALImpl2x(AuxBus * bus, Timer * timer) : DPCDHALImpl(bus, timer), bIgnoreCableIdCaps(false), bConnectorIsTypeC(false)
{
dpMemZero(&caps2x, sizeof(caps2x));
dpMemZero(&interrupts2x, sizeof(interrupts2x));

8
src/common/displayport/inc/dp_connectorimpl.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -329,6 +329,12 @@ namespace DisplayPort
// On eDP, do not cache the source OUI if it reads 0. See bug 4793112
bool bSkipZeroOuiCache;
bool bDisable5019537Fix;
bool bForceHeadShutdownFromRegkey;
bool bForceHeadShutdownPerMonitor;
//
// Dual SST Partner connector object pointer
ConnectorImpl *pCoupledConnector;

8
src/common/displayport/inc/dp_deviceimpl.h
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@@ -79,9 +79,10 @@ namespace DisplayPort
{
struct _Enum_Path
{
unsigned availableStreams, total, free;
unsigned availableStreams, total, free, dfpLinkAvailable;
bool bPathFECCapable;
bool dataValid; // Is the cache valid?
bool availablePbnUpdated;
} enum_path;
struct Compound_Query_State
@@ -110,6 +111,7 @@ namespace DisplayPort
void resetCacheInferredLink();
LinkConfiguration * inferLeafLink(unsigned * totalLinkSlots);
void inferPathConstraints();
DeviceImpl * parent; // Upstream parent device
@@ -503,8 +505,8 @@ namespace DisplayPort
unsigned getDscMaxSliceWidth();
unsigned getDscDecoderColorDepthSupportMask();
void setDscDecompressionDevice(bool bDscCapBasedOnParent);
virtual bool getDeviceSpecificData(NvU8 *oui, NvU8 *deviceIdString,
NvU8 *hwRevision, NvU8 *swMajorRevision,
virtual bool getDeviceSpecificData(NvU8 *oui, NvU8 *deviceIdString,
NvU8 *hwRevision, NvU8 *swMajorRevision,
NvU8 *swMinorRevision);
virtual bool setModeList(DisplayPort::DpModesetParams *pModeList, unsigned numModes);

3
src/common/displayport/inc/dp_edid.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2010-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -167,6 +167,7 @@ namespace DisplayPort
bool useLegacyAddress;
bool bIgnoreDscCap; // Ignore DSC even if sink reports DSC capability
bool bDisableDownspread;
bool bForceHeadShutdown;
bool bSkipCableIdCheck;
bool bAllocateManualTimeslots;
}_WARFlags;

7
src/common/displayport/inc/dp_evoadapter.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -425,10 +425,7 @@ namespace DisplayPort
bool freeDisplayId(NvU32 displayId);
virtual bool queryAndUpdateDfpParams();
virtual bool queryGPUCapability();
virtual void updateFallbackMap(NvU32 maxLaneCount, LinkRate maxLinkRate, NvU32 sinkUhbrCaps = 0)
{
return;
}
bool getEdpPowerData(bool *panelPowerOn, bool *dpcdPowerStateD0);
virtual bool vrrRunEnablementStage(unsigned stage, NvU32 *status);

15
src/common/displayport/inc/dp_evoadapter2x.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -107,6 +107,8 @@ namespace DisplayPort
bool bSupportUHBR2_70; // Support UHBR2.7 for internal testing.
bool bSupportUHBR5_00; // Support UHBR5.0 for internal testing.
bool bConnectorIsUSBTypeC;
// Start time of DP2.x LT Channel Eqaulization phase.
NvU64 channelEqualizationStartTimeUs;
@@ -124,7 +126,7 @@ namespace DisplayPort
// and with correct channel encoding.
// Return false if not.
//
bool isSupportedDPLinkConfig(LinkConfiguration &link);
virtual bool isSupportedDPLinkConfig(LinkConfiguration &link);
// Before link training start, reset DPRX link and make sure it's ready.
bool resetDPRXLink(DP2XResetParam param);
@@ -144,7 +146,8 @@ namespace DisplayPort
virtual bool clearFlushMode(FlushModePhase phase, NvU32 attachFailedHeadMask = 0, NvU32 headIndex = 0);
virtual bool isRgFlushSequenceUsed() {return bUseRgFlushSequence;}
void applyDP2xRegkeyOverrides();
virtual NvU32 headToStream(NvU32 head, bool bSidebandMessageSupported, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
virtual NvU32 headToStream(NvU32 head, bool bSidebandMessageSupported,
DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
// Link Rate will return the value with 10M convention!
virtual void getLinkConfig(unsigned &laneCount, NvU64 & linkRate);
@@ -170,6 +173,12 @@ namespace DisplayPort
virtual bool getDp2xLaneData(NvU32 *numLanes, NvU32 *data);
virtual bool setDp2xLaneData(NvU32 numLanes, NvU32 *data);
virtual bool physicalLayerSetDP2xTestPattern(DP2xPatternInfo *patternInfo);
virtual bool isConnectorUSBTypeC()
{
return bConnectorIsUSBTypeC;
}
virtual void invalidateLinkRatesInFallbackTable(const LinkRate linkRate);
};
}

16
src/common/displayport/inc/dp_mainlink.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -280,16 +280,14 @@ namespace DisplayPort
virtual bool queryGPUCapability() {return false;}
virtual bool queryAndUpdateDfpParams() = 0;
virtual void updateFallbackMap(NvU32 maxLaneCount, LinkRate maxLinkRate, NvU32 sinkUhbrCaps = 0) { return; }
virtual bool isConnectorUSBTypeC() { return false; }
virtual void invalidateLinkRatesInFallbackTable(const LinkRate linkRate) { return; }
virtual bool setFlushMode(FlushModePhase phase) { return false; }
virtual bool clearFlushMode(FlushModePhase phase, NvU32 attachFailedHeadMask = 0, NvU32 headIndex = 0) { return false; }
virtual bool getDp2xLaneData(NvU32 *numLanes, NvU32 *data)
{
return false;
}
virtual bool setDp2xLaneData(NvU32 numLanes, NvU32 *data)
{
return false;
}
virtual bool getDp2xLaneData(NvU32 *numLanes, NvU32 *data) { return false; }
virtual bool setDp2xLaneData(NvU32 numLanes, NvU32 *data) { return false; }
virtual bool isSupportedDPLinkConfig(LinkConfiguration &link) {return false; };
virtual bool getEdpPowerData(bool *panelPowerOn, bool *bDPCDPowerStateD0) = 0;
virtual bool vrrRunEnablementStage(unsigned stage, NvU32 *status) = 0;

1
src/common/displayport/inc/dp_messagecodings.h
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@@ -278,6 +278,7 @@ namespace DisplayPort
bool bFECCapability;
unsigned TotalPBN;
unsigned FreePBN;
unsigned DFPLinkAvailablePBN;
} reply;
EnumPathResMessage(const Address & target, unsigned port, bool point);
};

18
src/common/displayport/inc/dp_regkeydatabase.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -85,18 +85,21 @@
#define NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_2_7G NVBIT(1)
#define NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_5_0G NVBIT(2)
#define NV_DP2X_IGNORE_CABLE_ID_CAPS "DP2X_IGNORE_CABLE_ID_CAPS"
//
// Bug 4388987 : This regkey will disable reading PCON caps for MST.
//
#define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED "DP_BUG_4388987_WAR"
#define NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION "DP_DISABLE_TUNNEL_BW_ALLOCATION"
#define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED "DP_BUG_4388987_WAR"
#define NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION "DP_DISABLE_TUNNEL_BW_ALLOCATION"
// Bug 4793112 : On eDP panel, do not cache source OUI if it reads zero
#define NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE "DP_SKIP_ZERO_OUI_CACHE"
#define NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE "DP_SKIP_ZERO_OUI_CACHE"
#define NV_DP_REGKEY_DISABLE_FIX_FOR_5019537 "DP_DISABLE_5019537_FIX"
// Bug 5088957 : Force head shutdown in DpLib
#define NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN "DP_WAR_5088957"
//
// Data Base used to store all the regkey values.
@@ -136,9 +139,10 @@ struct DP_REGKEY_DATABASE
bool bForceDisableTunnelBwAllocation;
bool bDownspreadDisabled;
bool bSkipZeroOuiCache;
bool bDisable5019537Fix;
bool bForceHeadShutdown;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;
#endif //INCLUDED_DP_REGKEYDATABASE_H

154
src/common/displayport/src/dp_configcaps2x.cpp
View File

@@ -35,47 +35,110 @@
using namespace DisplayPort;
void DPCDHALImpl2x::performCableIdHandshake()
void DPCDHALImpl2x::parseAndSetCableId(NvU8 cableId)
{
NvU8 byte = 0;
caps2x.cableCaps.bUHBR_10GSupported = true;
if (AuxRetry::ack ==
bus.read(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX, &byte, sizeof byte))
caps2x.cableCaps.bUHBR_20GSupported =
FLD_TEST_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _UHBR20_10_CAPABILITY, _10_AND_20_GBPS_SUPPORTED, cableId);
caps2x.cableCaps.bUHBR_13_5GSupported =
FLD_TEST_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _13_5_GBPS_SUPPORTED, _YES, cableId);
switch (DRF_VAL(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _CABLE_TYPE, cableId))
{
caps2x.cableCaps.bUHBR_10GSupported =
FLD_TEST_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _UHBR20_10_CAPABILITY, _10_0_GBPS_SUPPORTED, byte) ||
FLD_TEST_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _UHBR20_10_CAPABILITY, _10_AND_20_GBPS_SUPPORTED, byte);
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_CABLE_TYPE_UNKNOWN:
caps2x.cableCaps.cableType = CableTypeUnknown;
break;
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_PASSIVE:
caps2x.cableCaps.cableType = CableTypePassive;
break;
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_LRD:
caps2x.cableCaps.cableType = CableTypeLRD;
break;
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_ACTIVE_RETIMER:
caps2x.cableCaps.cableType = CableTypeActiveReTimer;
break;
default:
DP_PRINTF(DP_ERROR, "Unknown cable type\n");
break;
}
}
caps2x.cableCaps.bUHBR_20GSupported =
FLD_TEST_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _UHBR20_10_CAPABILITY, _10_AND_20_GBPS_SUPPORTED, byte);
void DPCDHALImpl2x::performCableIdHandshakeForTypeC()
{
NvU8 txCableCaps = 0;
NvU8 rxCableCaps = 0;
caps2x.cableCaps.bUHBR_13_5GSupported =
FLD_TEST_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _13_5_GBPS_SUPPORTED, _YES, byte);
switch (DRF_VAL(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _CABLE_TYPE, byte))
{
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_CABLE_TYPE_UNKNOWN:
caps2x.cableCaps.cableType = CableTypeUnknown;
break;
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_PASSIVE:
caps2x.cableCaps.cableType = CableTypePassive;
break;
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_LRD:
caps2x.cableCaps.cableType = CableTypeLRD;
break;
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_ACTIVE_RETIMER:
caps2x.cableCaps.cableType = CableTypeActiveReTimer;
break;
default:
DP_PRINTF(DP_ERROR, "Unknown cable type\n");
break;
}
// Write sink caps to NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX first.
if (caps2x.bUHBR_20GSupported)
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _UHBR20_10_CAPABILITY,
_10_AND_20_GBPS_SUPPORTED, txCableCaps);
}
else
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _UHBR20_10_CAPABILITY,
_10_0_GBPS_SUPPORTED, txCableCaps);
}
if (caps2x.bUHBR_13_5GSupported)
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _13_5_GBPS_SUPPORTED,
_YES, txCableCaps);
}
if (byte == 0)
// Set cable type based on if any LTTPR is detected.
if (!bLttprSupported || (this->caps.phyRepeaterCount == 0))
{
caps2x.cableCaps.bUHBR_10GSupported = true;
return;
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _CABLE_TYPE,
_PASSIVE, txCableCaps);
}
else
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _CABLE_TYPE,
_ACTIVE_RETIMER, txCableCaps);
}
if (AuxRetry::ack != bus.write(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX, &txCableCaps,
sizeof txCableCaps))
{
DP_PRINTF(DP_WARNING, "Failed to write NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX");
}
// Check Cable ID from DPRX
if (AuxRetry::ack !=
bus.read(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX, &rxCableCaps, sizeof rxCableCaps))
{
DP_PRINTF(DP_WARNING, "Failed to read NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX for updated results");
}
parseAndSetCableId(rxCableCaps);
// If no matches, reflect that to the DPRX
if (txCableCaps != rxCableCaps)
{
if (AuxRetry::ack !=
bus.write(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX, &rxCableCaps, sizeof rxCableCaps))
{
DP_PRINTF(DP_WARNING, "Failed to update NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX -> %02x", rxCableCaps);
}
}
}
void DPCDHALImpl2x::performCableIdHandshake()
{
NvU8 rxCableCaps = 0;
if (this->bConnectorIsTypeC)
{
return performCableIdHandshakeForTypeC();
}
// Read Cable ID from DPRX
if (AuxRetry::ack ==
bus.read(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX, &rxCableCaps, sizeof rxCableCaps))
{
parseAndSetCableId(rxCableCaps);
}
}
@@ -183,7 +246,7 @@ void DPCDHALImpl2x::parseAndReadCaps()
}
}
if (!bIgnoreCableIdCaps)
if (caps2x.bDP2xChannelCodingSupported && !bIgnoreCableIdCaps)
{
performCableIdHandshake();
}
@@ -231,6 +294,11 @@ void DPCDHALImpl2x::setGpuDPSupportedVersions(NvU32 _gpuDPSupportedVersions)
return DPCDHALImpl::setGpuDPSupportedVersions(_gpuDPSupportedVersions);
}
void DPCDHALImpl2x::setConnectorTypeC(bool bTypeC)
{
this->bConnectorIsTypeC = bTypeC;
}
AuxRetry::status DPCDHALImpl2x::notifySDPErrDetectionCapability()
{
NvU8 config = 0;
@@ -379,6 +447,24 @@ NvU32 DPCDHALImpl2x::getUHBRSupported()
return uhbrCaps;
}
void DPCDHALImpl2x::overrideCableIdCap(LinkRate linkRate, bool bEnable)
{
switch (linkRate)
{
case dp2LinkRate_20_0Gbps:
caps2x.cableCaps.bUHBR_20GSupported = bEnable;
break;
case dp2LinkRate_13_5Gbps:
caps2x.cableCaps.bUHBR_13_5GSupported = bEnable;
break;
case dp2LinkRate_10_0Gbps:
caps2x.cableCaps.bUHBR_10GSupported = bEnable;
break;
default:
DP_PRINTF(DP_ERROR, "DPHAL> Invalid link rate (%d) to override.", linkRate);
}
}
bool DPCDHALImpl2x::parseTestRequestPhy()
{
NvU8 buffer[2] = {0};

124
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -147,6 +147,7 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co
this->applyRegkeyOverrides(dpRegkeyDatabase);
hal->applyRegkeyOverrides(dpRegkeyDatabase);
hal->setConnectorTypeC(main->isConnectorUSBTypeC());
highestAssessedLC = initMaxLinkConfig();
}
@@ -182,6 +183,8 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
}
this->bForceDisableTunnelBwAllocation = dpRegkeyDatabase.bForceDisableTunnelBwAllocation;
this->bSkipZeroOuiCache = dpRegkeyDatabase.bSkipZeroOuiCache;
this->bDisable5019537Fix = dpRegkeyDatabase.bDisable5019537Fix;
this->bForceHeadShutdownFromRegkey = dpRegkeyDatabase.bForceHeadShutdown;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -2655,10 +2658,16 @@ bool ConnectorImpl::isHeadShutDownNeeded(Group * target, // Group
unsigned headIndex,
ModesetInfo modesetInfo)
{
if (bForceHeadShutdownFromRegkey || bForceHeadShutdownPerMonitor)
{
return true;
}
if (linkUseMultistream())
{
return true;
}
if (activeGroups.isEmpty())
{
return false;
@@ -4399,9 +4408,18 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType)
}
}
//
// Find the active group(s)
GroupImpl * groupAttached = 0;
if (!this->bDisable5019537Fix)
{
for (ListElement * e = activeGroups.begin(); e != activeGroups.end(); e = e->next)
{
DP_ASSERT(bIsUefiSystem || linkUseMultistream() || (!groupAttached && "Multiple attached heads"));
groupAttached = (GroupImpl * )e;
}
}
// Disconnect heads
//
bool bIsFlushModeEnabled = enableFlush();
if (bIsFlushModeEnabled)
@@ -4442,6 +4460,15 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType)
timer->sleep(40);
} while (retryCount++ < WAR_MAX_REASSESS_ATTEMPT);
if (!activeLinkConfig.isValid() && !(this->bDisable5019537Fix))
{
if (groupAttached && groupAttached->lastModesetInfo.pixelClockHz != 0)
{
// If there is no active link, force LT to max before disable flush
lConfig = _maxLinkConfig;
train(lConfig, true);
}
}
disableFlush();
}
@@ -4898,9 +4925,9 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
bool bTwoHeadOneOrLinkRetrain = false; // force link re-train if any attached
// groups are in 2Head1OR mode.
// Power off the link if no stream are active
if (isNoActiveStreamAndPowerdown())
{
DP_PRINTF(DP_INFO, "Power off the link because no stream are active");
return true;
}
@@ -5059,7 +5086,7 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
bSkipLt = false;
}
if (groupAttached && groupAttached->isHeadAttached())
if ((groupAttached && groupAttached->isHeadAttached()) || !(this->bDisable5019537Fix))
{
// Enter flush mode/detach head before LT
if (!bSkipLt)
@@ -5077,7 +5104,7 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
if (!bLinkTrainingSuccessful && bSkipLt)
{
bSkipLt = false;
if (groupAttached && groupAttached->isHeadAttached())
if ((groupAttached && groupAttached->isHeadAttached()) || !(this->bDisable5019537Fix))
{
if (!(bEnteredFlushMode = this->enableFlush()))
return false;
@@ -5087,36 +5114,37 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
if (!bLinkTrainingSuccessful)
{
LinkConfiguration maxLinkConfig = getMaxLinkConfig();
//
// If optimized link config fails, try max link config with fallback.
if (!train(maxLinkConfig, false))
// Note: It's possible some link rates are dynamically invalidated
// during failed link training. That means we can't assume
// maxLinkConfig is always greater than the lowestSelected
// link configuration.
//
train(maxLinkConfig, false);
//
// Note here that fallback might happen while attempting LT to max link config.
// activeLinkConfig will be set to that passing config.
//
if (!willLinkSupportModeSST(activeLinkConfig, groupAttached->lastModesetInfo))
{
//
// Note here that if highest link config fails and a lower
// link config passes, link training will be returned as
// failure but activeLinkConfig will be set to that passing config.
// If none of the link configs pass LT or a fall back link config passed LT
// but cannot support the mode, then we will force the optimized link config
// on the link and mark LT as fail.
//
if (!willLinkSupportModeSST(activeLinkConfig, groupAttached->lastModesetInfo))
{
//
// If none of the link configs pass LT or a fall back link config passed LT
// but cannot support the mode, then we will force the optimized link config
// on the link and mark LT as fail.
//
train(lowestSelected, true);
bLinkTrainingSuccessful = false;
}
else
{
//
// If a fallback link config pass LT and can support
// the mode, mark LT as pass.
//
bLinkTrainingSuccessful = true;
}
// Force LT really should not fail!
DP_ASSERT(train(lowestSelected, true));
bLinkTrainingSuccessful = false;
}
else
{
// If LT passes at max link config, mark LT as pass.
//
// If a fallback link config pass LT and can support
// the mode, mark LT as pass.
//
bLinkTrainingSuccessful = true;
}
}
@@ -5798,10 +5826,15 @@ bool ConnectorImpl::enableFlush()
return false;
//
// Enabling flush mode shuts down the link, so the next link training
// call must not skip programming the hardware. Otherwise, EVO will
// hang if the head is still active when flush mode is disabled.
// Enabling flush mode shuts down the link:
// 1. reset activeLinkConfig to indicate the link is now lost.
// 2. The next link training call must not skip programming the hardware.
// Otherwise, EVO will hang if the head is still active when flush mode is disabled.
//
if (!this->bDisable5019537Fix)
{
activeLinkConfig = LinkConfiguration();
}
bSkipLt = false;
sortActiveGroups(false);
@@ -6826,6 +6859,10 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
{
preferredLinkConfig.multistream = false;
}
if (AuxRetry::ack != hal->setMessagingEnable(false, true))
{
DP_PRINTF(DP_WARNING, "DP> Failed to clear messaging for singlestream panel");
}
// We will report a dongle as new device with videoSink flag as false.
if (hal->getSinkCount() == 0)
@@ -7273,6 +7310,28 @@ void ConnectorImpl::notifyShortPulse()
//save the previous highest assessed LC
LinkConfiguration previousAssessedLC = highestAssessedLC;
if (main->isConnectorUSBTypeC() &&
activeLinkConfig.bIs128b132bChannelCoding &&
activeLinkConfig.peakRate > dp2LinkRate_10_0Gbps)
{
if (activeLinkConfig.isValid() && enableFlush())
{
train(activeLinkConfig, true);
disableFlush();
}
main->invalidateLinkRatesInFallbackTable(activeLinkConfig.peakRate);
hal->overrideCableIdCap(activeLinkConfig.peakRate, false);
highestAssessedLC = getMaxLinkConfig();
DeviceImpl * dev = findDeviceInList(Address());
if (dev)
{
sink->bandwidthChangeNotification(dev, false);
}
return;
}
if (activeLinkConfig.isValid() && enableFlush())
{
LinkConfiguration originalActiveLinkConfig = activeLinkConfig;
@@ -8150,6 +8209,7 @@ void ConnectorImpl::configInit()
allocatedDpTunnelBw = 0;
allocatedDpTunnelBwShadow = 0;
bDP2XPreferNonDSCForLowPClk = false;
bForceHeadShutdownPerMonitor = false;
}
bool ConnectorImpl::dpUpdateDscStream(Group *target, NvU32 dscBpp)

79
src/common/displayport/src/dp_connectorimpl2x.cpp
View File

@@ -72,6 +72,9 @@ bool ConnectorImpl2x::willLinkSupportModeSST
const DscParams *pDscParams
)
{
LinkConfiguration lc = linkConfig;
if (!main->isSupportedDPLinkConfig(lc))
return false;
// no headIndex (default 0) for mode enumeration.
return willLinkSupportMode(linkConfig, modesetInfo, 0, NULL, pDscParams);
}
@@ -464,33 +467,55 @@ bool ConnectorImpl2x::compoundQueryAttachMSTGeneric(Group * target,
return false;
}
for(Device * d = target->enumDevices(0); d; d = target->enumDevices(d))
if (!hal->isDp2xChannelCodingCapable())
{
DeviceImpl * i = (DeviceImpl *)d;
// Allocate bandwidth for the entire path to the root
// NOTE: Above we're already handle the local link
DeviceImpl * tail = i;
while (tail && tail->getParent())
for(Device * d = target->enumDevices(0); d; d = target->enumDevices(d))
{
// Have we already accounted for this stream?
DeviceImpl * i = (DeviceImpl *)d;
// Allocate bandwidth for the entire path to the root
// NOTE: Above we're already handle the local link
DeviceImpl * tail = i;
while (tail && tail->getParent())
{
// Have we already accounted for this stream?
if (!(tail->bandwidth.compound_query_state.bandwidthAllocatedForIndex & (1 << compoundQueryCount)))
{
tail->bandwidth.compound_query_state.bandwidthAllocatedForIndex |= (1 << compoundQueryCount);
LinkConfiguration * linkConfig = tail->inferLeafLink(NULL);
tail->bandwidth.compound_query_state.timeslots_used_by_query += linkConfig->slotsForPBN(base_pbn);
if (tail->bandwidth.compound_query_state.timeslots_used_by_query >
tail->bandwidth.compound_query_state.totalTimeSlots)
{
compoundQueryResult = false;
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH)
}
}
tail = (DeviceImpl*)tail->getParent();
}
}
}
else
{
for(Device * d = target->enumDevices(0); d; d = target->enumDevices(d))
{
DeviceImpl * tail = (DeviceImpl *)d;
if (!(tail->bandwidth.compound_query_state.bandwidthAllocatedForIndex & (1 << compoundQueryCount)))
{
tail->bandwidth.compound_query_state.bandwidthAllocatedForIndex |= (1 << compoundQueryCount);
tail->inferPathConstraints();
LinkConfiguration * linkConfig = tail->inferLeafLink(NULL);
tail->bandwidth.compound_query_state.timeslots_used_by_query += linkConfig->slotsForPBN(base_pbn);
if (tail->bandwidth.compound_query_state.timeslots_used_by_query >
tail->bandwidth.compound_query_state.totalTimeSlots)
if (slots_pbn > DP_MIN(tail->bandwidth.enum_path.total, tail->bandwidth.enum_path.dfpLinkAvailable))
{
compoundQueryResult = false;
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH)
}
}
tail = (DeviceImpl*)tail->getParent();
}
}
return compoundQueryResult;
}
@@ -1063,7 +1088,6 @@ void ConnectorImpl2x::beforeDeleteStream(GroupImpl * group, bool forFlushMode)
// Delete the stream
hal->payloadTableClearACT();
hal->payloadAllocate(group->streamIndex, group->timeslot.begin, 0);
main->triggerACT();
}
}
@@ -1079,7 +1103,7 @@ void ConnectorImpl2x::afterDeleteStream(GroupImpl * group)
return ConnectorImpl::afterDeleteStream(group);
DP_ASSERT(!group->isTimeslotAllocated());
main->triggerACT();
if (group->isHeadAttached() && group->bWaitForDeAllocACT)
{
if (!hal->payloadWaitForACTReceived())
@@ -1110,6 +1134,13 @@ bool ConnectorImpl2x::train(const LinkConfiguration &lConfig, bool force, LinkTr
freeSlots = maximumSlots;
firstFreeSlot = 0;
}
// Invalidate the UHBR if the connector is a USB-C to DP/USB-C.
if (!trainResult && main->isConnectorUSBTypeC() &&
lConfig.bIs128b132bChannelCoding && lConfig.peakRate > dp2LinkRate_10_0Gbps)
{
hal->overrideCableIdCap(lConfig.peakRate, false);
}
return trainResult;
}
@@ -1303,6 +1334,7 @@ bool ConnectorImpl2x::enableFlush()
// call must not skip programming the hardware. Otherwise, EVO will
// hang if the head is still active when flush mode is disabled.
//
bSkipLt = false;
sortActiveGroups(false);
@@ -1335,6 +1367,12 @@ bool ConnectorImpl2x::enableFlush()
return false;
}
// Reset activeLinkConfig to indicate the link is now lost
if (!this->bDisable5019537Fix)
{
activeLinkConfig = LinkConfiguration();
}
return true;
}
@@ -1666,5 +1704,14 @@ void ConnectorImpl2x::handleEdidWARs(Edid & edid, DiscoveryManager::Device & dev
bDP2XPreferNonDSCForLowPClk = true;
}
}
if (edid.WARFlags.bForceHeadShutdown)
{
// SST mode
if (device.address.size() <= 1)
{
bForceHeadShutdownPerMonitor = true;
}
}
}

50
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -1401,6 +1401,56 @@ LinkConfiguration * DeviceImpl::inferLeafLink(unsigned * totalLinkSlots)
return &bandwidth.lastHopLinkConfig;
}
void DeviceImpl::inferPathConstraints()
{
if (!bandwidth.enum_path.availablePbnUpdated)
{
if (plugged)
{
NakData nack;
for (unsigned retries = 0; retries < 7; retries++)
{
// Marking the EPR as a path message in 2x
EnumPathResMessage epr(getTopologyAddress().parent(), getTopologyAddress().tail(), false);
bool sendStatus = connector->messageManager->send(&epr, nack);
if (!sendStatus)
{
if (nack.reason == NakDefer || nack.reason == NakTimeout)
continue;
bandwidth.enum_path.total = 0;
bandwidth.enum_path.free = 0;
bandwidth.enum_path.availableStreams = 0;
bandwidth.enum_path.dfpLinkAvailable = 0;
break;
}
else
{
bandwidth.enum_path.total = epr.reply.TotalPBN;
bandwidth.enum_path.free = epr.reply.FreePBN;
bandwidth.enum_path.bPathFECCapable = epr.reply.bFECCapability;
bandwidth.enum_path.availableStreams = epr.reply.availableStreams;
// Include the new DFP available PBN only for 2x
bandwidth.enum_path.dfpLinkAvailable = epr.reply.DFPLinkAvailablePBN;
break;
}
}
}
else
{
bandwidth.enum_path.total = bandwidth.enum_path.free = bandwidth.enum_path.dfpLinkAvailable = 0;
}
bandwidth.enum_path.dataValid = true;
bandwidth.enum_path.availablePbnUpdated = true;
bandwidth.lastHopLinkConfig = LinkConfiguration(DP_MIN(bandwidth.enum_path.total, bandwidth.enum_path.dfpLinkAvailable));
// Update FEC support of the device after EPR
this->getFECSupport();
}
return;
}
bool DeviceImpl::isActive()
{
DP_ASSERT(!activeGroup || activeGroup->isHeadAttached());

6
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -102,7 +102,9 @@ const struct
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION, &dpRegkeyDatabase.bForceDisableTunnelBwAllocation, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_DOWNSPREAD, &dpRegkeyDatabase.bDownspreadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_FIX_FOR_5019537, &dpRegkeyDatabase.bDisable5019537Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

66
src/common/displayport/src/dp_evoadapter2x.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES.
* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES.
* All rights reserved.
* SPDX-License-Identifier: MIT
*
@@ -180,7 +180,8 @@ bool EvoMainLink2x::queryAndUpdateDfpParams()
if (!EvoMainLink::queryAndUpdateDfpParams())
return false;
dfpUhbrCaps = dfpParams.UHBRSupportedByDfp;
dfpUhbrCaps = dfpParams.UHBRSupportedByDfp;
bConnectorIsUSBTypeC = FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS, _TYPE_C_TO_DP_CONNECTOR, _TRUE, dfpParams.flags);
return true;
}
@@ -197,7 +198,7 @@ bool EvoMainLink2x::queryAndUpdateDfpParams()
* into this function.
*
* Output: EvoMainLink2x::fallbackMandateTable is updated for each entry to indicate
* is a specific link configuration is supported.
* if a specific link configuration is supported.
*
*/
void EvoMainLink2x::updateFallbackMap
@@ -260,6 +261,32 @@ void EvoMainLink2x::updateFallbackMap
}
}
/*!
* @brief Invalidate all entries with specific link rate in fallbackMandateTable based on request.
*
* @param[in] linkRate The link rate to be removed.
*
* Caller of this function has to complete the capabilities probing before calling
* into this function.
*
* Output: EvoMainLink2x::fallbackMandateTable is updated for each entry to indicate
* if a specific link configuration is supported.
*/
void EvoMainLink2x::invalidateLinkRatesInFallbackTable(const LinkRate linkRate)
{
NvU32 idx;
for (idx = 0U; idx < NV_DP2X_VALID_LINK_CONFIGURATION_COUNT; idx++)
{
if (fallbackMandateTable[idx].linkRate == linkRate)
{
fallbackMandateTable[idx].bSupported = NV_FALSE;
if (fallbackMandateTable[idx].laneCount == 1)
return;
}
}
}
/*!
* @brief Update fallbackMandateTable based on the capabilities of GPU, Sink and CableId.
*
@@ -412,11 +439,13 @@ bool EvoMainLink2x::train(const LinkConfiguration & link, bool force,
LinkConfiguration requestRmLC = link;
//
// Check if LinkConfiguration passed in is supported by the system
if (!isSupportedDPLinkConfig(requestRmLC))
// Skip the capability check if client forces the link training.
//
if (!force && !isSupportedDPLinkConfig(requestRmLC))
{
DP_PRINTF(DP_ERROR, "DP2xEVO> EvoMainLink2x::train(): client requested link "
"is not a supported link configuration!");
DP_PRINTF(DP_ERROR, "DP2xEVO> client requested link is not a supported link configuration!");
return false;
}
@@ -444,7 +473,7 @@ bool EvoMainLink2x::train(const LinkConfiguration & link, bool force,
{
if (!resetDPRXLink(resetParam))
{
DP_PRINTF(DP_ERROR, "DP2xEVO> EvoMainLink2x::train(): Reset DP link before LT failed.");
DP_PRINTF(DP_ERROR, "DP2xEVO> Reset DP link before LT failed.");
return false;
}
}
@@ -479,7 +508,7 @@ bool EvoMainLink2x::train(const LinkConfiguration & link, bool force,
if (FLD_TEST_DRF(0073_CTRL, _DP2X_ERR, _LINK_STATUS, _DISCONNECTED, ltRmParams.err))
{
DP_PRINTF(DP_ERROR, "DP2xEVO> EvoMainLink2x::train(): Link Disconnected - stop LT / Fallback.");
DP_PRINTF(DP_ERROR, "DP2xEVO> Link Disconnected - stop LT / Fallback.");
// Do not fallback if link is disconnected.
bFallback = false;
}
@@ -490,13 +519,23 @@ bool EvoMainLink2x::train(const LinkConfiguration & link, bool force,
}
else
{
if (this->isConnectorUSBTypeC() &&
requestRmLC.bIs128b132bChannelCoding &&
requestRmLC.peakRate > dp2LinkRate_10_0Gbps)
{
//
// Invalidate the link rate from fallback table if the connector type is USB-C to DP.
// Source will not retry the same link rate if fallback LT fails again.
//
invalidateLinkRatesInFallbackTable(requestRmLC.peakRate);
}
//
// Get next available link configuration based on DP2.1 spec, Table 3-31
// Break here if next link configuration is not available.
//
if (!this->getFallbackForDP2xLinkTraining(&requestRmLC))
{
// No link configuration available for fallback.
DP_PRINTF(DP_ERROR, "DP2xEVO> No link configuration available for fallback");
bFallback = false;
}
@@ -509,12 +548,12 @@ bool EvoMainLink2x::train(const LinkConfiguration & link, bool force,
bChannelCodingChanged = (requestRmLC.bIs128b132bChannelCoding != bCur128b132bChannelCoding);
if (bChannelCodingChanged)
{
DP_PRINTF(DP_NOTICE, "DP2xEVO> EvoMainLink2x::train(): Fallback - Reset DP link before LT.");
DP_PRINTF(DP_NOTICE, "DP2xEVO> Fallback - Reset DP link before LT.");
// Reset link due to changing the channel coding during LT
resetParam.reason = DP2X_ResetLinkForFallback;
if (!resetDPRXLink(resetParam))
{
DP_PRINTF(DP_ERROR, "DP2xEVO> EvoMainLink2x::train(): Reset DP link for fallback failed.");
DP_PRINTF(DP_ERROR, "DP2xEVO> Reset DP link for fallback failed.");
return false;
}
}
@@ -907,11 +946,6 @@ bool EvoMainLink2x::getFallbackForDP2xLinkTraining(LinkConfiguration *link)
for (linkIdx = 0; linkIdx < NV_DP2X_VALID_LINK_CONFIGURATION_COUNT; linkIdx++)
{
if (!(fallbackMandateTable[linkIdx].bSupported))
{
continue;
}
if ((link->lanes == fallbackMandateTable[linkIdx].laneCount) &&
(link->peakRate == fallbackMandateTable[linkIdx].linkRate) &&
(link->bIs128b132bChannelCoding == (bool)fallbackMandateTable[linkIdx].bUseDP2xChannelCoding))

11
src/common/displayport/src/dp_messagecodings.cpp
View File

@@ -227,11 +227,12 @@ EnumPathResMessage::EnumPathResMessage(const Address & target, unsigned port, bo
ParseResponseStatus EnumPathResMessage::parseResponseAck(EncodedMessage * message, BitStreamReader * reader)
{
reply.portNumber = reader->readOrDefault(4 /*Port_Number*/, 0xF);
reply.availableStreams = reader->readOrDefault(3 /*Available_Streams*/, 0);
reply.bFECCapability = (reader->readOrDefault(1 /*FEC*/, 0x0) == 1) ? true : false;
reply.TotalPBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF);
reply.FreePBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF);
reply.portNumber = reader->readOrDefault(4 /*Port_Number*/, 0xF);
reply.availableStreams = reader->readOrDefault(3 /*Available_Streams*/, 0);
reply.bFECCapability = (reader->readOrDefault(1 /*FEC*/, 0x0) == 1) ? true : false;
reply.TotalPBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF);
reply.FreePBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF);
reply.DFPLinkAvailablePBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF);
if (this->getSinkPort() != reply.portNumber)
return ParseResponseWrong;

11
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -604,6 +604,15 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
this->WARFlags.bSkipCableIdCheck = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Panel does not expose cable capability. Ignoring it. Bug 4968411");
}
else if(ProductID == 0x24b5 || ProductID == 0x32f2)
{
//
// Asus ROG PG248QP (0x24b5) Bug 5100062
// Asus ROG PG32UCDM (0x32f2) Bug 5088957
//
this->WARFlags.bForceHeadShutdown = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Force head shutdown.");
}
break;
// Samsung

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r571_57
#define NV_BUILD_BRANCH r572_46
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r571_57
#define NV_PUBLIC_BRANCH r572_46
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r571_57-276"
#define NV_BUILD_CHANGELIST_NUM (35438409)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r572_46-342"
#define NV_BUILD_CHANGELIST_NUM (35593155)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r570/r571_57-276"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35438409)
#define NV_BUILD_NAME "rel/gpu_drv/r570/r572_46-342"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35593155)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r571_57-35"
#define NV_BUILD_CHANGELIST_NUM (35438409)
#define NV_BUILD_BRANCH_VERSION "r572_46-6"
#define NV_BUILD_CHANGELIST_NUM (35593155)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "572.13"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35438409)
#define NV_BUILD_NAME "572.60"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35593155)
#define NV_BUILD_BRANCH_BASE_VERSION R570
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "570.86.16"
#define NV_VERSION_STRING "570.124.04"
#else

30
src/common/inc/swref/published/ampere/ga10b/dev_ram.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga10b_dev_ram_h__
#define __ga10b_dev_ram_h__
#define NV_RAMIN_ENGINE_CTXSW_FW_MAGIC_VALUE (131*32+31):(131*32+0) /* RWXUF */
#define NV_RAMIN_ENGINE_CTXSW_FW_MAGIC_VALUE_V 0xcafeca11 /* RW--V */
#endif // __ga10b_dev_ram_h__

55
src/common/nvswitch/kernel/ls10/multicast_ls10.c
View File

@@ -33,10 +33,10 @@ static const NVSWITCH_COLUMN_PORT_OFFSET_LS10 nvswitch_portmap_ls10[NVSWITCH_NUM
{ 0, 0 }, { 0, 1 }, { 0, 2 }, { 0, 3 },
{ 0, 4 }, { 0, 5 }, { 0, 6 }, { 0, 7 },
{ 0, 8 }, { 0, 9 }, { 0, 10 },
// ports 11 - 16
// ports 11 - 15
{ 2, 0 }, { 2, 3 }, { 2, 4 }, { 2, 5 },
{ 2, 8 },
//ports 16 - 26
// ports 16 - 26
{ 4, 10 }, { 4, 9 }, { 4, 8 }, { 4, 7 },
{ 4, 6 }, { 4, 5 }, { 4, 4 }, { 4, 3 },
{ 4, 2 }, { 4, 1 }, { 4, 0 },
@@ -297,18 +297,27 @@ _is_primary_replica
// Set the round flags to indicate the size of each multicast round.
// See IAS section "6.12. Consistent MC Semantics" for more info.
//
static void
_nvswitch_mc_set_round_flags
(
// Make sure rounds have following properties:
// - no more than 11 rounds
// - no more than 3 directives per round
// - no duplicate TCP# within same round
//
static NvlStatus
_nvswitch_mc_set_round_flags(
nvswitch_device *device,
NVSWITCH_TCP_DIRECTIVE_LS10 *port_list,
NvU32 port_list_size
)
NvU32 port_list_size)
{
NvU32 cur_portlist_pos, round_size, round_start, round_end;
NVSWITCH_TCP_DIRECTIVE_LS10 *cur_dir, *next_dir;
NvU32 round_tcp_mask = 0;
NvU32 round_count = 0;
if ((port_list == NULL) || (port_list_size == 0))
return;
{
NVSWITCH_PRINT(device, ERROR, "%s: called with empty port list?\n",
__FUNCTION__);
return -NVL_BAD_ARGS;
}
round_start = 0;
round_end = 0;
@@ -329,12 +338,16 @@ _nvswitch_mc_set_round_flags
// set the round size in the first directive
cur_dir = &port_list[round_start];
cur_dir->roundSize = (NvU8)round_size;
round_count++;
}
else
{
// if next tcp is less than or equal to the current, then current is end of round
round_tcp_mask |= (1 << cur_dir->tcp);
// if next tcp is tcp that is already in current round, then current directive is end of round
// if its third directive in current round, end round regardless of tcp assignments
next_dir = &port_list[cur_portlist_pos + 1];
if (next_dir->tcp <= cur_dir->tcp)
if ((round_end - round_start == 2) || ((round_tcp_mask & (1 << next_dir->tcp)) != 0))
{
cur_dir->continueRound = NV_FALSE;
@@ -347,9 +360,21 @@ _nvswitch_mc_set_round_flags
// advance round_start
round_start = cur_portlist_pos + 1;
round_tcp_mask = 0;
round_count++;
}
}
}
if (round_count > 11)
{
NVSWITCH_PRINT(device, ERROR, "%s: Round count exceeds 11: %d\n",
__FUNCTION__, round_count);
return -NVL_BAD_ARGS;
}
return NVL_SUCCESS;
}
//
@@ -359,8 +384,8 @@ _nvswitch_mc_set_round_flags
static void
_nvswitch_mc_set_port_flags
(
NVSWITCH_TCP_DIRECTIVE_LS10 *port_list,
NvU32 port_list_size
NVSWITCH_TCP_DIRECTIVE_LS10 *port_list,
NvU32 port_list_size
)
{
NvU32 cur_portlist_pos;
@@ -766,7 +791,9 @@ nvswitch_mc_build_mcp_list_ls10
NVSWITCH_PRINT(device, INFO, "%s: entries used after building portlist: %d\n",
__FUNCTION__, dir_entries_used_sg);
#endif
_nvswitch_mc_set_round_flags(tmp_mcp_list, dir_entries_used_sg);
ret = _nvswitch_mc_set_round_flags(device, tmp_mcp_list, dir_entries_used_sg);
if (ret != NVL_SUCCESS)
return ret;
_nvswitch_mc_set_port_flags(tmp_mcp_list, dir_entries_used_sg);

7
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -86,6 +86,8 @@
* NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE
* This specifies whether the displayId is capable of sending
* YCBCR444 color format out from the board.
* NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR
* This specifies whether the displayId is a DP connector routed to an USB-TYPE-C port.
* NV0073_CTRL_DFP_FLAGS_DP_LINK_BANDWIDTH
* This specifies max link rate supported by the displayId, if the DFP is
* display port.
@@ -161,6 +163,9 @@ typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS {
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR 13:13
#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U)

7
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -449,6 +449,7 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS {
#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_USB_C 0x00000071U
#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_DSI 0x00000072U
#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_STEREO_3PIN_DIN 0x00000073U
#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_USB_C_UHBR 0x00000074U
#define NV0073_CTRL_SPECIFIC_CONNECTOR_DATA_TYPE_UNKNOWN 0xFFFFFFFFU
/* defines for the platform field */
@@ -1994,9 +1995,9 @@ typedef struct NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS {
/*
* NV0073_CTRL_CMD_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM
* NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM
* These commands retrieve and set the brightness level and Local Tone Mapping (LTM) settings for
* These commands retrieve and set the brightness level and Local Tone Mapping (LTM) settings for
* the specified display.
*
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be

9
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -5252,4 +5252,13 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20800aabU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS
*
* Request from CPU-RM to proccess supressed errors during boot on GSP
* This command accepts no parameters.
*/
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS (0x20800b01U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | 0x1" */
/* ctrl2080internal_h */

2
src/common/sdk/nvidia/inc/g_finn_rm_api.h
View File

@@ -380,6 +380,8 @@ typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PMGR;
#define FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID (0x20800aU)
typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_INTERNAL;
#define FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID (0x20800bU)
typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_INTERNAL_2;
#define FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID (0x208028U)
typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_LPWR;

48
src/common/shared/inc/g_vgpu_chip_flags.h
View File

@@ -675,6 +675,22 @@ ENTRY(0x2329, 0x2034, 0x10de, "NVIDIA H20-48C"),
ENTRY(0x2329, 0x2035, 0x10de, "NVIDIA H20-96C"),
ENTRY(0x2329, 0x2047, 0x10de, "NVIDIA H20-8C"),
ENTRY(0x2329, 0x2048, 0x10de, "NVIDIA H20-32C"),
ENTRY(0x232C, 0x2108, 0x10de, "NVIDIA H20X-1-18CME"),
ENTRY(0x232C, 0x2109, 0x10de, "NVIDIA H20X-1-18C"),
ENTRY(0x232C, 0x210A, 0x10de, "NVIDIA H20X-1-35C"),
ENTRY(0x232C, 0x210B, 0x10de, "NVIDIA H20X-2-35C"),
ENTRY(0x232C, 0x210C, 0x10de, "NVIDIA H20X-3-71C"),
ENTRY(0x232C, 0x210D, 0x10de, "NVIDIA H20X-4-71C"),
ENTRY(0x232C, 0x210E, 0x10de, "NVIDIA H20X-7-141C"),
ENTRY(0x232C, 0x210F, 0x10de, "NVIDIA H20X-4C"),
ENTRY(0x232C, 0x2110, 0x10de, "NVIDIA H20X-7C"),
ENTRY(0x232C, 0x2111, 0x10de, "NVIDIA H20X-8C"),
ENTRY(0x232C, 0x2112, 0x10de, "NVIDIA H20X-14C"),
ENTRY(0x232C, 0x2113, 0x10de, "NVIDIA H20X-17C"),
ENTRY(0x232C, 0x2114, 0x10de, "NVIDIA H20X-28C"),
ENTRY(0x232C, 0x2115, 0x10de, "NVIDIA H20X-35C"),
ENTRY(0x232C, 0x2116, 0x10de, "NVIDIA H20X-70C"),
ENTRY(0x232C, 0x2117, 0x10de, "NVIDIA H20X-141C"),
ENTRY(0x2330, 0x187A, 0x10de, "NVIDIA H100XM-1-10CME"),
ENTRY(0x2330, 0x187B, 0x10de, "NVIDIA H100XM-1-10C"),
ENTRY(0x2330, 0x187C, 0x10de, "NVIDIA H100XM-1-20C"),
@@ -705,13 +721,13 @@ ENTRY(0x2331, 0x16DE, 0x10de, "NVIDIA H100-80C"),
ENTRY(0x2331, 0x1798, 0x10de, "NVIDIA H100-5C"),
ENTRY(0x2331, 0x17F0, 0x10de, "NVIDIA H100-1-10CME"),
ENTRY(0x2331, 0x1844, 0x10de, "NVIDIA H100-1-20C"),
ENTRY(0x2335, 0x206E, 0x10de, "NVIDIA H200X-1-17CME"),
ENTRY(0x2335, 0x206F, 0x10de, "NVIDIA H200X-1-17C"),
ENTRY(0x2335, 0x206E, 0x10de, "NVIDIA H200X-1-18CME"),
ENTRY(0x2335, 0x206F, 0x10de, "NVIDIA H200X-1-18C"),
ENTRY(0x2335, 0x2070, 0x10de, "NVIDIA H200X-1-35C"),
ENTRY(0x2335, 0x2071, 0x10de, "NVIDIA H200X-2-35C"),
ENTRY(0x2335, 0x2072, 0x10de, "NVIDIA H200X-3-70C"),
ENTRY(0x2335, 0x2073, 0x10de, "NVIDIA H200X-4-70C"),
ENTRY(0x2335, 0x2074, 0x10de, "NVIDIA H200X-7-140C"),
ENTRY(0x2335, 0x2072, 0x10de, "NVIDIA H200X-3-71C"),
ENTRY(0x2335, 0x2073, 0x10de, "NVIDIA H200X-4-71C"),
ENTRY(0x2335, 0x2074, 0x10de, "NVIDIA H200X-7-141C"),
ENTRY(0x2335, 0x2075, 0x10de, "NVIDIA H200X-4C"),
ENTRY(0x2335, 0x2076, 0x10de, "NVIDIA H200X-7C"),
ENTRY(0x2335, 0x2077, 0x10de, "NVIDIA H200X-8C"),
@@ -720,7 +736,7 @@ ENTRY(0x2335, 0x2079, 0x10de, "NVIDIA H200X-17C"),
ENTRY(0x2335, 0x207A, 0x10de, "NVIDIA H200X-28C"),
ENTRY(0x2335, 0x207B, 0x10de, "NVIDIA H200X-35C"),
ENTRY(0x2335, 0x207E, 0x10de, "NVIDIA H200X-70C"),
ENTRY(0x2335, 0x207F, 0x10de, "NVIDIA H200X-140C"),
ENTRY(0x2335, 0x207F, 0x10de, "NVIDIA H200X-141C"),
ENTRY(0x2337, 0x18F2, 0x10de, "NVIDIA H100XS-1-8CME"),
ENTRY(0x2337, 0x18F3, 0x10de, "NVIDIA H100XS-1-8C"),
ENTRY(0x2337, 0x18F4, 0x10de, "NVIDIA H100XS-1-16C"),
@@ -761,13 +777,13 @@ ENTRY(0x233A, 0x186B, 0x10de, "NVIDIA H800L-15C"),
ENTRY(0x233A, 0x186C, 0x10de, "NVIDIA H800L-23C"),
ENTRY(0x233A, 0x186D, 0x10de, "NVIDIA H800L-47C"),
ENTRY(0x233A, 0x186E, 0x10de, "NVIDIA H800L-94C"),
ENTRY(0x233B, 0x2081, 0x10de, "NVIDIA H200-1-17CME"),
ENTRY(0x233B, 0x2082, 0x10de, "NVIDIA H200-1-17C"),
ENTRY(0x233B, 0x2081, 0x10de, "NVIDIA H200-1-18CME"),
ENTRY(0x233B, 0x2082, 0x10de, "NVIDIA H200-1-18C"),
ENTRY(0x233B, 0x2083, 0x10de, "NVIDIA H200-1-35C"),
ENTRY(0x233B, 0x2084, 0x10de, "NVIDIA H200-2-35C"),
ENTRY(0x233B, 0x2085, 0x10de, "NVIDIA H200-3-70C"),
ENTRY(0x233B, 0x2086, 0x10de, "NVIDIA H200-4-70C"),
ENTRY(0x233B, 0x2087, 0x10de, "NVIDIA H200-7-140C"),
ENTRY(0x233B, 0x2085, 0x10de, "NVIDIA H200-3-71C"),
ENTRY(0x233B, 0x2086, 0x10de, "NVIDIA H200-4-71C"),
ENTRY(0x233B, 0x2087, 0x10de, "NVIDIA H200-7-141C"),
ENTRY(0x233B, 0x2088, 0x10de, "NVIDIA H200-4C"),
ENTRY(0x233B, 0x2089, 0x10de, "NVIDIA H200-7C"),
ENTRY(0x233B, 0x208A, 0x10de, "NVIDIA H200-8C"),
@@ -776,7 +792,7 @@ ENTRY(0x233B, 0x208C, 0x10de, "NVIDIA H200-17C"),
ENTRY(0x233B, 0x208D, 0x10de, "NVIDIA H200-28C"),
ENTRY(0x233B, 0x208E, 0x10de, "NVIDIA H200-35C"),
ENTRY(0x233B, 0x208F, 0x10de, "NVIDIA H200-70C"),
ENTRY(0x233B, 0x2090, 0x10de, "NVIDIA H200-140C"),
ENTRY(0x233B, 0x2090, 0x10de, "NVIDIA H200-141C"),
ENTRY(0x2342, 0x18C2, 0x10de, "NVIDIA GH200-1-12CME"),
ENTRY(0x2342, 0x18C3, 0x10de, "NVIDIA GH200-1-12C"),
ENTRY(0x2342, 0x18C4, 0x10de, "NVIDIA GH200-1-24C"),
@@ -1146,6 +1162,14 @@ ENTRY(0x27B8, 0x174A, 0x10de, "NVIDIA L4-6C"),
ENTRY(0x27B8, 0x174B, 0x10de, "NVIDIA L4-8C"),
ENTRY(0x27B8, 0x174C, 0x10de, "NVIDIA L4-12C"),
ENTRY(0x27B8, 0x174D, 0x10de, "NVIDIA L4-24C"),
ENTRY(0x2941, 0x20CB, 0x10de, "NVIDIA GB200-1-24CME"),
ENTRY(0x2941, 0x20CC, 0x10de, "NVIDIA GB200-1-24C"),
ENTRY(0x2941, 0x20CD, 0x10de, "NVIDIA GB200-1-47C"),
ENTRY(0x2941, 0x20CE, 0x10de, "NVIDIA GB200-2-47C"),
ENTRY(0x2941, 0x20CF, 0x10de, "NVIDIA GB200-3-95C"),
ENTRY(0x2941, 0x20D0, 0x10de, "NVIDIA GB200-4-95C"),
ENTRY(0x2941, 0x20D1, 0x10de, "NVIDIA GB200-7-189C"),
ENTRY(0x2941, 0x20D2, 0x10de, "NVIDIA GB200-189C"),
};
#endif /* _G_VGPU_CHIP_FLAGS_H_ */

36
src/common/shared/inc/g_vgpu_resman_specific.h
View File

@@ -19,10 +19,12 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
{ 0x20FD, 0x17F8, 0x20F5, 0x0 },
{ 0x2324, 0x17A8, 0x2324, 0x17A6 },
{ 0x2329, 0x198C, 0x2329, 0x198B },
{ 0x232C, 0x2064, 0x232C, 0x2063 },
{ 0x2330, 0x16C0, 0x2330, 0x16C1 },
{ 0x2336, 0x16C2, 0x2330, 0x16C1 },
{ 0x2335, 0x18BF, 0x2335, 0x18BE },
{ 0x26BA, 0x1990, 0x26BA, 0x1957 },
{ 0x2941, 0x2046, 0x2941, 0x2045 },
};
for (NvU32 i = 0; i < (sizeof(vgpu_aliases) / sizeof(struct vgpu_alias_details)); ++i) {
@@ -145,6 +147,13 @@ static const struct {
{0x232910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1401}, // NVIDIA H20-3-48C
{0x232910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1402}, // NVIDIA H20-4-48C
{0x232910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1403}, // NVIDIA H20-7-96C
{0x232C10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1480}, // NVIDIA H20X-1-18CME
{0x232C10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1481}, // NVIDIA H20X-1-18C
{0x232C10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1482}, // NVIDIA H20X-1-35C
{0x232C10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1483}, // NVIDIA H20X-2-35C
{0x232C10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1484}, // NVIDIA H20X-3-71C
{0x232C10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1485}, // NVIDIA H20X-4-71C
{0x232C10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1486}, // NVIDIA H20X-7-141C
{0x233010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1130}, // NVIDIA H100XM-1-10CME
{0x233610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1130}, // NVIDIA H100XM-1-10CME
{0x233010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1131}, // NVIDIA H100XM-1-10C
@@ -166,13 +175,13 @@ static const struct {
{0x233110DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 825}, // NVIDIA H100-7-80C
{0x233110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 993}, // NVIDIA H100-1-10CME
{0x233110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1059}, // NVIDIA H100-1-20C
{0x233510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1413}, // NVIDIA H200X-1-17CME
{0x233510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1414}, // NVIDIA H200X-1-17C
{0x233510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1413}, // NVIDIA H200X-1-18CME
{0x233510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1414}, // NVIDIA H200X-1-18C
{0x233510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1415}, // NVIDIA H200X-1-35C
{0x233510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1416}, // NVIDIA H200X-2-35C
{0x233510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1417}, // NVIDIA H200X-3-70C
{0x233510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1418}, // NVIDIA H200X-4-70C
{0x233510DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1419}, // NVIDIA H200X-7-140C
{0x233510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1417}, // NVIDIA H200X-3-71C
{0x233510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1418}, // NVIDIA H200X-4-71C
{0x233510DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1419}, // NVIDIA H200X-7-141C
{0x233710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1305}, // NVIDIA H100XS-1-8CME
{0x233710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1306}, // NVIDIA H100XS-1-8C
{0x233710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1307}, // NVIDIA H100XS-1-16C
@@ -194,13 +203,13 @@ static const struct {
{0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1079}, // NVIDIA H800L-3-47C
{0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1080}, // NVIDIA H800L-4-47C
{0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1081}, // NVIDIA H800L-7-94C
{0x233B10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1429}, // NVIDIA H200-1-17CME
{0x233B10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1430}, // NVIDIA H200-1-17C
{0x233B10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1429}, // NVIDIA H200-1-18CME
{0x233B10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1430}, // NVIDIA H200-1-18C
{0x233B10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1431}, // NVIDIA H200-1-35C
{0x233B10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1432}, // NVIDIA H200-2-35C
{0x233B10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1433}, // NVIDIA H200-3-70C
{0x233B10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1434}, // NVIDIA H200-4-70C
{0x233B10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1435}, // NVIDIA H200-7-140C
{0x233B10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1433}, // NVIDIA H200-3-71C
{0x233B10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1434}, // NVIDIA H200-4-71C
{0x233B10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1435}, // NVIDIA H200-7-141C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1196}, // NVIDIA GH200-1-12CME
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1197}, // NVIDIA GH200-1-12C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1198}, // NVIDIA GH200-1-24C
@@ -215,6 +224,13 @@ static const struct {
{0x234810DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1454}, // NVIDIA GH200L-3-72C
{0x234810DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1455}, // NVIDIA GH200L-4-72C
{0x234810DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1456}, // NVIDIA GH200L-7-144C
{0x294110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1445}, // NVIDIA GB200-1-24CME
{0x294110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1446}, // NVIDIA GB200-1-24C
{0x294110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1458}, // NVIDIA GB200-1-47C
{0x294110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1447}, // NVIDIA GB200-2-47C
{0x294110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1459}, // NVIDIA GB200-3-95C
{0x294110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1448}, // NVIDIA GB200-4-95C
{0x294110DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1460}, // NVIDIA GB200-7-189C
};
#endif // GENERATE_vgpuSmcTypeIdMappings