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This commit is contained in:
Bernhard Stoeckner
2025-02-27 17:32:23 +01:00
parent 81fe4fb417
commit 129479b1b7
141 changed files with 102245 additions and 100070 deletions
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14
src/nvidia/inc/kernel/core/printf.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2001-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -38,6 +38,9 @@ extern "C" {
#include "utils/nvprintf.h"
#include "nvlog/nvlog.h"
// TODO Bug 5078337: Move these away from kernel/core
#include "kernel/diagnostics/xid_context.h"
#define DBG_FILE_LINE_FUNCTION NV_FILE_STR, __LINE__, NV_FUNCTION_STR
/**
@@ -235,6 +238,10 @@ void nvDbgDumpBufferBytes(void *pBuffer, NvU32 length);
#define DBG_VAL_PTR(p)
#endif
//
// TODO Bug 5078337: Move these away from kernel/core and rename to indicate
// that they emit XIDs
//
#define NV_ERROR_LOG(pGpu, num, fmt, ...) \
nvErrorLog_va((void*)pGpu, num, fmt, ##__VA_ARGS__); \
NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, \
@@ -245,10 +252,9 @@ void nvDbgDumpBufferBytes(void *pBuffer, NvU32 length);
NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, \
NV_PRINTF_ADD_PREFIX(fmt), ##__VA_ARGS__)
void nvErrorLog(void *pVoid, NvU32 num, const char *pFormat, va_list arglist);
void nvErrorLog(void *pVoid, XidContext context, const char *pFormat, va_list arglist);
void nvErrorLog_va(void * pGpu, NvU32 num, const char * pFormat, ...);
void nvErrorLog2(void *pVoid, NvU32 num, NvBool oobLogging, const char *pFormat, va_list arglist);
void nvErrorLog2_va(void * pGpu, NvU32 num, NvBool oobLogging, const char * pFormat, ...);
void nvErrorLog2_va(void * pGpu, XidContext context, NvBool oobLogging, const char * pFormat, ...);
#ifdef __cplusplus
}

8
src/nvidia/inc/kernel/core/thread_state.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -156,6 +156,11 @@ typedef struct THREAD_STATE_DB
//
#define TIMEOUT_WDDM_POWER_TRANSITION_INTERVAL_MS 9800
//
// Thread state timeout for DPC or ISR handling
//
#define TIMEOUT_DPC_ISR_INTERVAL_MS 500
//
// Thread State flags used for threadStateInitSetupFlags
//
@@ -213,6 +218,7 @@ NV_STATUS threadStateResetTimeout(OBJGPU *pGpu);
void threadStateLogTimeout(OBJGPU *pGpu, NvU64 funcAddr, NvU32 lineNum);
void threadStateYieldCpuIfNecessary(OBJGPU *pGpu, NvBool bQuiet);
void threadStateSetTimeoutOverride(THREAD_STATE_NODE *, NvU64);
void threadStateSetTimeoutSingleOverride(THREAD_STATE_NODE *, NvU64);
NV_STATUS threadStateEnqueueCallbackOnFree(THREAD_STATE_NODE *pThreadNode,
THREAD_STATE_FREE_CALLBACK *pCallback);

64
src/nvidia/inc/kernel/diagnostics/xid_context.h Normal file
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@@ -0,0 +1,64 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef XID_CONTEXT_H
#define XID_CONTEXT_H 1
#include "nvtypes.h"
//!
//! Root cause information to print in specific cases.
//!
//! Some Xid strings must be kept "stable", so this information is
//! only printed in certain cases where we can break the stability, or where
//! that particular Xid string was not stable.
//!
//! It will always be okay to pass an all zero struct { 0 }
//!
typedef struct
{
//!
//! If nonzero, print this as a root cause of the current
//! ROBUST_CHANNEL_PREEMPTIVE_REMOVAL
//!
NvU32 preemptiveRemovalPreviousXid;
} RcRootCause;
//!
//! Xid and context information about an Xid passed to KernelRM.
//!
//! This is NOT stable. The Xid printing mechanism must take care that Xid
//! strings which must remain stable continue to do so even some information
//! changes here.
//!
typedef struct
{
//! Xid number.
NvU32 xid;
//! Additional root cause information valid only for certain Xids.
RcRootCause rootCause;
} XidContext;
#endif // XID_CONTEXT_H

3
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -216,6 +216,7 @@ typedef struct GspSystemInfo
NvBool bEnableDynamicGranularityPageArrays;
NvBool bClockBoostSupported;
NvBool bRouteDispIntrsToCPU;
NvU64 hostPageSize;
} GspSystemInfo;

282
src/nvidia/inc/kernel/vgpu/rm_plugin_shared_code.h
View File

@@ -1502,6 +1502,36 @@ return_t deserialize_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14(NVB0CC_
return SUCCESS_T;
}
static
return_t deserialize_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v29_0B(NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v29_0B *src = (void*)(buffer);
NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *dest = pParams;
if (src && dest)
{
#ifdef COPY_INPUT_PARAMETERS
dest->bytesConsumed = src->bytesConsumed;
dest->bUpdateAvailableBytes = src->bUpdateAvailableBytes;
dest->bWait = src->bWait;
dest->bReturnPut = src->bReturnPut;
dest->pmaChannelIdx = src->pmaChannelIdx;
#endif
#ifdef COPY_OUTPUT_PARAMETERS
dest->bytesAvailable = src->bytesAvailable;
dest->putPtr = src->putPtr;
dest->bOverflowStatus = src->bOverflowStatus;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t deserialize_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07(NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *pParams,
NvU8 *buffer,
@@ -2875,6 +2905,64 @@ return_t deserialize_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_SET_HS
return SUCCESS_T;
}
return_t deserialize_NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07(NVB0CC_CTRL_RESERVE_HES_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07 *src = (void*)(buffer);
NVB0CC_CTRL_RESERVE_HES_PARAMS *dest = pParams;
if (src && dest)
{
#ifdef COPY_INPUT_PARAMETERS
dest->type = src->type;
dest->reserveParams.cwd.ctxsw = src->reserveParams.cwd.ctxsw;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
return_t deserialize_NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07(NVB0CC_CTRL_RELEASE_HES_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07 *src = (void*)(buffer);
NVB0CC_CTRL_RELEASE_HES_PARAMS *dest = pParams;
if (src && dest)
{
#ifdef COPY_INPUT_PARAMETERS
dest->type = src->type;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
return_t deserialize_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07(NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07 *src = (void*)(buffer);
NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS *dest = pParams;
if (src && dest)
{
#ifdef COPY_INPUT_PARAMETERS
dest->ctxsw = src->ctxsw;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
#ifndef UMED_BUILD
return_t deserialize_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07(NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS *pParams,
NvU8 *buffer,
@@ -4341,6 +4429,36 @@ return_t serialize_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14(NVB0CC_CT
return SUCCESS_T;
}
static
return_t serialize_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v29_0B(NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v29_0B *dest = (void*)(buffer);
NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *src = pParams;
if (src && dest)
{
#ifdef COPY_INPUT_PARAMETERS
dest->bytesConsumed = src->bytesConsumed;
dest->bUpdateAvailableBytes = src->bUpdateAvailableBytes;
dest->bWait = src->bWait;
dest->bReturnPut = src->bReturnPut;
dest->pmaChannelIdx = src->pmaChannelIdx;
#endif
#ifdef COPY_OUTPUT_PARAMETERS
dest->bytesAvailable = src->bytesAvailable;
dest->putPtr = src->putPtr;
dest->bOverflowStatus = src->bOverflowStatus;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t serialize_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07(NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *pParams,
NvU8 *buffer,
@@ -5711,6 +5829,61 @@ return_t serialize_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_SET_HS_C
return SUCCESS_T;
}
return_t serialize_NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07(NVB0CC_CTRL_RESERVE_HES_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07 *dest = (void*)(buffer);
NVB0CC_CTRL_RESERVE_HES_PARAMS *src = pParams;
if (src && dest)
{
#ifdef COPY_INPUT_PARAMETERS
dest->type = src->type;
dest->reserveParams.cwd.ctxsw = src->reserveParams.cwd.ctxsw;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
return_t serialize_NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07(NVB0CC_CTRL_RELEASE_HES_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07 *dest = (void*)(buffer);
NVB0CC_CTRL_RELEASE_HES_PARAMS *src = pParams;
if (src && dest)
{
#ifdef COPY_INPUT_PARAMETERS
dest->type = src->type;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
return_t serialize_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07(NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07 *dest = (void*)(buffer);
NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS *src = pParams;
if (src && dest)
{
#ifdef COPY_INPUT_PARAMETERS
dest->ctxsw = src->ctxsw;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
#ifndef UMED_BUILD
return_t serialize_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07(NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS *pParams,
NvU8 *buffer,
@@ -6017,6 +6190,115 @@ return_t deserialize_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02(NV20
return SUCCESS_T;
}
static
return_t serialize_NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL_v29_0A(NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL *src = pParams;
NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL_v29_0A *dest = (void*)(buffer);
if (src && dest && (src->poolInfosCount <= NVB0CC_CREDIT_POOL_MAX_COUNT_v29_0A))
{
NvU32 i;
dest->poolInfosCount = src->poolInfosCount;
for (i = 0; i < dest->poolInfosCount; ++i)
{
dest->poolInfos[i].numCredits = src->poolInfos[i].numCredits;
dest->poolInfos[i].poolIndex = src->poolInfos[i].poolIndex;
dest->poolInfos[i].chipletType = src->poolInfos[i].chipletType;
}
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t deserialize_NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL_v29_0A(NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL_v29_0A *src = (void*)(buffer);
NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL *dest = pParams;
if (src && dest && (src->poolInfosCount <= NVB0CC_CREDIT_POOL_MAX_COUNT_v29_0A))
{
NvU32 i;
dest->poolInfosCount = src->poolInfosCount;
for (i = 0; i < dest->poolInfosCount; ++i)
{
dest->poolInfos[i].numCredits = src->poolInfos[i].numCredits;
dest->poolInfos[i].poolIndex = src->poolInfos[i].poolIndex;
dest->poolInfos[i].chipletType = src->poolInfos[i].chipletType;
}
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t serialize_NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS_v29_0A(NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS *src = pParams;
NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS_v29_0A *dest = (void*)(buffer);
NvU16 i;
if (src && dest && (src->numQueries <= NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08))
{
dest->numQueries = src->numQueries;
dest->statusInfo.status = src->statusInfo.status;
dest->statusInfo.entryIndex = src->statusInfo.entryIndex;
for (i = 0; i < dest->numQueries; ++i)
{
dest->queries[i].chipletType = src->queries[i].chipletType;
dest->queries[i].chipletIndex = src->queries[i].chipletIndex;
dest->queries[i].poolIndex = src->queries[i].poolIndex;
}
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t deserialize_NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS_v29_0A(NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS_v29_0A *src = (void*)(buffer);
NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS *dest = pParams;
NvU16 i;
if (src && dest && (src->numQueries <= NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08))
{
dest->numQueries = src->numQueries;
dest->statusInfo.status = src->statusInfo.status;
dest->statusInfo.entryIndex = src->statusInfo.entryIndex;
for (i = 0; i < dest->numQueries; ++i)
{
dest->queries[i].chipletType = src->queries[i].chipletType;
dest->queries[i].chipletIndex = src->queries[i].chipletIndex;
dest->queries[i].poolIndex = src->queries[i].poolIndex;
}
}
else
return FAILURE_T;
return SUCCESS_T;
}
#endif
#ifdef BUILD_COMMON_RPCS

5
src/nvidia/inc/kernel/vgpu/rpc_global_enums.h
View File

@@ -230,7 +230,10 @@ enum {
X(RM, CTRL_RELEASE_HES, 220)
X(RM, CTRL_RESERVE_CCU_PROF, 221)
X(RM, CTRL_RELEASE_CCU_PROF, 222)
X(RM, NUM_FUNCTIONS, 223)
X(RM, RESERVED, 223)
X(RM, CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL, 224)
X(RM, CTRL_CMD_GET_HS_CREDITS_MAPPING, 225)
X(RM, NUM_FUNCTIONS, 226)
#ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H
};
# undef X

3
src/nvidia/inc/kernel/vgpu/sdk-structures.h
View File

@@ -148,6 +148,7 @@ typedef struct vmiopd_SM_info {
#define NV2080_CTRL_MAX_PCES_v21_0A 32
#define NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A 2
#define NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE_v26_05 1024
#define NVB0CC_CREDIT_POOL_MAX_COUNT_v29_0A 30
// Host USM type
#define NV_VGPU_CONFIG_USM_TYPE_DEFAULT 0x00000000 /* R-XVF */
@@ -508,5 +509,7 @@ ct_assert(NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT_v1A_07 == NV9096_CTRL_ZBC_CLEAR
ct_assert(NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05 == NVC637_CTRL_MAX_EXEC_PARTITIONS);
ct_assert(NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11 == NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE);
ct_assert(NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX_v27_01 == NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX);
ct_assert(NVB0CC_CREDIT_POOL_MAX_COUNT_v29_0A == NVB0CC_CREDIT_POOL_MAX_COUNT);
ct_assert(NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08 == NVB0CC_MAX_CREDIT_INFO_ENTRIES);
#endif /*_RPC_SDK_STRUCTURES_H_*/

7
src/nvidia/inc/kernel/vgpu/vgpu_version.h
View File

@@ -31,7 +31,7 @@
#define RPC_VERSION_FROM_VGX_VERSION(major, minor) (DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \
DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor))
#define VGX_MAJOR_VERSION_NUMBER 0x29
#define VGX_MINOR_VERSION_NUMBER 0x09
#define VGX_MINOR_VERSION_NUMBER 0x0B
#define VGX_MAJOR_VERSION_NUMBER_VGPU_12_0 0x1A
#define VGX_MINOR_VERSION_NUMBER_VGPU_12_0 0x18
@@ -39,6 +39,7 @@
#define VGX_MINOR_VERSION_NUMBER_VGPU_13_0 0x0A
#define VGX_MAJOR_VERSION_NUMBER_VGPU_16_0 0x23
#define VGX_MAJOR_VERSION_NUMBER_VGPU_17_0 0x25
#define VGX_MAJOR_VERSION_NUMBER_VGPU_18_0 0x29
#define VGX_MAJOR_VERSION_WITH_FB_COPY_LARGE_BLOCKSZ_SUPPORT 0x28
@@ -53,7 +54,7 @@
* 2. This is the first break in migration compatibility after a release.
*/
#define NV_VGPU_GRIDSW_INTERNAL_TO_EXTERNAL_VERSION_MAPPING \
{{0x29, 0x00}, {0x29, 0x09}, {0x18, 0x01}}, \
{{0x29, 0x00}, {0x29, 0x0B}, {0x18, 0x01}}, \
{{0x28, 0x00}, {0x28, 0x09}, {0x17, 0x01}}, \
{{0x27, 0x00}, {0x27, 0x06}, {0x16, 0x01}}, \
{{0x26, 0x00}, {0x26, 0x05}, {0x15, 0x01}}, \
@@ -111,7 +112,7 @@
/* WARNING: Should be updated with each vGPU release, if minimum supported
* version change on the host.
*/
#define NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x7
#define NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x12
#define NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1
#endif // __vgpu_vgpu_version_h__