mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-04 07:10:19 +00:00
535.98
This commit is contained in:
Bernhard Stoeckner
@@ -86,6 +86,14 @@
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#include <linux/ioport.h>
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#if defined(NV_LINUX_CC_PLATFORM_H_PRESENT)
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#include <linux/cc_platform.h>
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#endif
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#if defined(NV_ASM_CPUFEATURE_H_PRESENT)
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#include <asm/cpufeature.h>
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#endif
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#include "conftest/patches.h"
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#define RM_THRESHOLD_TOTAL_IRQ_COUNT 100000
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@@ -139,8 +147,6 @@ struct semaphore nv_linux_devices_lock;
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static NvTristate nv_chipset_is_io_coherent = NV_TRISTATE_INDETERMINATE;
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NvU64 nv_shared_gpa_boundary = 0;
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// True if all the successfully probed devices support ATS
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// Assigned at device probe (module init) time
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NvBool nv_ats_supported = NVCPU_IS_PPC64LE
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@@ -234,77 +240,23 @@ struct dev_pm_ops nv_pm_ops = {
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*** STATIC functions
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***/
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#if defined(NVCPU_X86_64)
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#define NV_AMD_SEV_BIT BIT(1)
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#define NV_GENMASK_ULL(h, l) \
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(((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
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static
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void get_shared_gpa_boundary(
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void nv_detect_conf_compute_platform(
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void
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)
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{
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NvU32 priv_high = cpuid_ebx(0x40000003);
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if (priv_high & BIT(22))
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#if defined(NV_CC_PLATFORM_PRESENT)
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os_cc_enabled = cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT);
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#if defined(X86_FEATURE_TDX_GUEST)
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if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST))
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{
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NvU32 isolation_config_b = cpuid_ebx(0x4000000C);
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nv_shared_gpa_boundary = ((NvU64)1) << ((isolation_config_b & NV_GENMASK_ULL(11, 6)) >> 6);
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os_cc_tdx_enabled = NV_TRUE;
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}
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}
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static
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NvBool nv_is_sev_supported(
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void
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)
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{
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unsigned int eax, ebx, ecx, edx;
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/* Check for the SME/SEV support leaf */
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eax = 0x80000000;
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ecx = 0;
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native_cpuid(&eax, &ebx, &ecx, &edx);
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if (eax < 0x8000001f)
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return NV_FALSE;
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/* By design, a VM using vTOM doesn't see the SEV setting */
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get_shared_gpa_boundary();
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if (nv_shared_gpa_boundary != 0)
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return NV_TRUE;
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eax = 0x8000001f;
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ecx = 0;
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native_cpuid(&eax, &ebx, &ecx, &edx);
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/* Check whether SEV is supported */
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if (!(eax & NV_AMD_SEV_BIT))
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return NV_FALSE;
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return NV_TRUE;
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}
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#endif
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static
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void nv_sev_init(
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void
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)
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{
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#if defined(MSR_AMD64_SEV) && defined(NVCPU_X86_64)
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NvU32 lo_val, hi_val;
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if (!nv_is_sev_supported())
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return;
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rdmsr(MSR_AMD64_SEV, lo_val, hi_val);
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os_sev_status = lo_val;
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#if defined(MSR_AMD64_SEV_ENABLED)
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os_sev_enabled = (os_sev_status & MSR_AMD64_SEV_ENABLED);
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#endif
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/* By design, a VM using vTOM doesn't see the SEV setting */
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if (nv_shared_gpa_boundary != 0)
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os_sev_enabled = NV_TRUE;
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#else
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os_cc_enabled = NV_FALSE;
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os_cc_tdx_enabled = NV_FALSE;
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#endif
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}
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@@ -710,7 +662,7 @@ nv_module_init(nv_stack_t **sp)
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}
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nv_init_rsync_info();
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nv_sev_init();
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nv_detect_conf_compute_platform();
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if (!rm_init_rm(*sp))
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{
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@@ -4570,19 +4522,19 @@ NvU64 NV_API_CALL nv_get_dma_start_address(
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* as the starting address for all DMA mappings.
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*/
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saved_dma_mask = pci_dev->dma_mask;
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if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64)) != 0)
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if (dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(64)) != 0)
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{
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goto done;
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}
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dma_addr = pci_map_single(pci_dev, NULL, 1, DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(pci_dev, dma_addr))
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dma_addr = dma_map_single(&pci_dev->dev, NULL, 1, DMA_BIDIRECTIONAL);
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if (dma_mapping_error(&pci_dev->dev, dma_addr))
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{
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pci_set_dma_mask(pci_dev, saved_dma_mask);
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dma_set_mask(&pci_dev->dev, saved_dma_mask);
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goto done;
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}
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pci_unmap_single(pci_dev, dma_addr, 1, DMA_BIDIRECTIONAL);
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dma_unmap_single(&pci_dev->dev, dma_addr, 1, DMA_BIDIRECTIONAL);
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/*
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* From IBM: "For IODA2, native DMA bypass or KVM TCE-based implementation
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@@ -4614,7 +4566,7 @@ NvU64 NV_API_CALL nv_get_dma_start_address(
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*/
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nv_printf(NV_DBG_WARNINGS,
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"NVRM: DMA window limited by platform\n");
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pci_set_dma_mask(pci_dev, saved_dma_mask);
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dma_set_mask(&pci_dev->dev, saved_dma_mask);
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goto done;
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}
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else if ((dma_addr & saved_dma_mask) != 0)
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@@ -4633,7 +4585,7 @@ NvU64 NV_API_CALL nv_get_dma_start_address(
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*/
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nv_printf(NV_DBG_WARNINGS,
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"NVRM: DMA window limited by memory size\n");
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pci_set_dma_mask(pci_dev, saved_dma_mask);
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dma_set_mask(&pci_dev->dev, saved_dma_mask);
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goto done;
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}
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}
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@@ -209,7 +209,7 @@ NV_STATUS nvUvmInterfaceSessionCreate(uvmGpuSessionHandle *session,
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memset(platformInfo, 0, sizeof(*platformInfo));
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platformInfo->atsSupported = nv_ats_supported;
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platformInfo->sevEnabled = os_sev_enabled;
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platformInfo->sevEnabled = os_cc_enabled;
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status = rm_gpu_ops_create_session(sp, (gpuSessionHandle *)session);
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@@ -120,6 +120,9 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_memory_array_uc
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_pages_array_uc
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioremap_cache
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioremap_wc
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioremap_driver_hardened
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioremap_driver_hardened_wc
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioremap_cache_shared
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_get_domain_bus_and_slot
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_num_physpages
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += pde_data
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@@ -156,8 +159,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_real_ts64
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += full_name_hash
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_enable_atomic_ops_to_root
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += vga_tryget
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += pgprot_decrypted
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += cc_mkdec
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += cc_platform_has
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += seq_read_iter
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += unsafe_follow_pfn
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NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_get
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@@ -263,4 +265,4 @@ NV_CONFTEST_GENERIC_COMPILE_TESTS += vfio_pci_core_available
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NV_CONFTEST_GENERIC_COMPILE_TESTS += mdev_available
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NV_CONFTEST_GENERIC_COMPILE_TESTS += cmd_uphy_display_port_init
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NV_CONFTEST_GENERIC_COMPILE_TESTS += cmd_uphy_display_port_off
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NV_CONFTEST_GENERIC_COMPILE_TESTS += memory_failure_mf_sw_simulated_defined
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NV_CONFTEST_GENERIC_COMPILE_TESTS += memory_failure_mf_sw_simulated_defined
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@@ -41,8 +41,8 @@ extern nv_kthread_q_t nv_kthread_q;
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NvU32 os_page_size = PAGE_SIZE;
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NvU64 os_page_mask = NV_PAGE_MASK;
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NvU8 os_page_shift = PAGE_SHIFT;
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NvU32 os_sev_status = 0;
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NvBool os_sev_enabled = 0;
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NvBool os_cc_enabled = 0;
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NvBool os_cc_tdx_enabled = 0;
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#if defined(CONFIG_DMA_SHARED_BUFFER)
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NvBool os_dma_buf_enabled = NV_TRUE;
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