mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-01 14:09:47 +00:00
535.98
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@@ -36,25 +36,25 @@
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// and then checked back in. You cannot make changes to these sections without
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// corresponding changes to the buildmeister script
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#ifndef NV_BUILD_BRANCH
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#define NV_BUILD_BRANCH r536_62
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#define NV_BUILD_BRANCH r535_00
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#endif
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#ifndef NV_PUBLIC_BRANCH
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#define NV_PUBLIC_BRANCH r536_62
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#define NV_PUBLIC_BRANCH r535_00
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#endif
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#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
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#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r536_62-219"
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#define NV_BUILD_CHANGELIST_NUM (33114094)
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#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r535_00-239"
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#define NV_BUILD_CHANGELIST_NUM (33134228)
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#define NV_BUILD_TYPE "Official"
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#define NV_BUILD_NAME "rel/gpu_drv/r535/r536_62-219"
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33114094)
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#define NV_BUILD_NAME "rel/gpu_drv/r535/r535_00-239"
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33134228)
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#else /* Windows builds */
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#define NV_BUILD_BRANCH_VERSION "r536_62-3"
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#define NV_BUILD_CHANGELIST_NUM (33061144)
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#define NV_BUILD_BRANCH_VERSION "r535_00-254"
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#define NV_BUILD_CHANGELIST_NUM (33134228)
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#define NV_BUILD_TYPE "Official"
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#define NV_BUILD_NAME "536.67"
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33061144)
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#define NV_BUILD_NAME "536.92"
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33134228)
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#define NV_BUILD_BRANCH_BASE_VERSION R535
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#endif
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// End buildmeister python edited section
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@@ -4,7 +4,7 @@
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#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
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(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
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#define NV_VERSION_STRING "535.86.10"
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#define NV_VERSION_STRING "535.98"
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#else
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@@ -43,7 +43,7 @@
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* This structure represents vGPU host device KERNEL object allocation parameters.
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* dbdf -> domain (31:16), bus (15:8), device (7:3), function (2:0)
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* gfid -> Used only when SRIOV is enabled otherwise set to 0.
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* swizzId [IN/OUT] -> Used only when MIG mode is enabled otherwise set
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* swizzId [IN] -> Used only when MIG mode is enabled otherwise set
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* to NV2080_CTRL_GPU_PARTITION_ID_INVALID.
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* numChannels -> Used only when SRIOV is enabled. Must be a power of 2.
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* bDisableDefaultSmcExecPartRestore - If set to true, SMC default execution partition
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@@ -837,6 +837,7 @@ typedef struct NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS {
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#define NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 0x05U
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#define NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 0x06U
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#define NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 0x07U
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#define NV2080_CTRL_NVLINK_UNIT_MINION 0x08U
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/*
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* NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES
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@@ -105,6 +105,7 @@
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#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE 0
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#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV 1
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#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX 2
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#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE 0
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#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM 1
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@@ -15,6 +15,7 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
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{ 0x20B5, 0x1642, 0x20B5, 0x1533 },
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{ 0x20B8, 0x1581, 0x20B5, 0x1533 },
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{ 0x20B9, 0x157F, 0x20B7, 0x1532 },
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{ 0x2330, 0x16C0, 0x2330, 0x16C1 },
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};
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for (NvU32 i = 0; i < (sizeof(vgpu_aliases) / sizeof(struct vgpu_alias_details)); ++i) {
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@@ -28,3 +29,5 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
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return;
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}
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#endif //__VGPU_ALIAS_PGPU_LIST__
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