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https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-10 10:09:58 +00:00
535.98
This commit is contained in:
@@ -1394,6 +1394,12 @@ typedef struct _NVHwModeTimingsEvo {
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NVHwModeViewPortEvo viewPort;
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} NVHwModeTimingsEvo;
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static inline NvBool nvIsAdaptiveSyncDpyVrrType(enum NvKmsDpyVRRType type)
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{
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return ((type == NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED) ||
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(type == NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED));
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}
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static inline NvU64 nvEvoFrametimeUsFromTimings(const NVHwModeTimingsEvo *pTimings)
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{
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NvU64 pixelsPerFrame = pTimings->rasterSize.x * pTimings->rasterSize.y;
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@@ -232,6 +232,10 @@ static void SetDPMSATiming(const NVDispEvoRec *pDispEvo,
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NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS *msaParams,
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const NVHwModeTimingsEvo *pTimings)
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{
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NV0073_CTRL_DP_MSA_PROPERTIES_MASK *featureMask = &msaParams->featureMask;
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NV0073_CTRL_DP_MSA_PROPERTIES_VALUES *featureValues =
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&msaParams->featureValues;
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nvkms_memset(msaParams, 0, sizeof(*msaParams));
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/*
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@@ -244,12 +248,16 @@ static void SetDPMSATiming(const NVDispEvoRec *pDispEvo,
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msaParams->subDeviceInstance = pDispEvo->displayOwner;
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msaParams->displayId = displayId;
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if ((pTimings->yuv420Mode == NV_YUV420_MODE_SW) && displayId != 0) {
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NV0073_CTRL_DP_MSA_PROPERTIES_MASK *featureMask = &msaParams->featureMask;
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NV0073_CTRL_DP_MSA_PROPERTIES_VALUES *featureValues = &msaParams->featureValues;
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if ((displayId == 0x0) ||
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((pTimings->yuv420Mode != NV_YUV420_MODE_SW) &&
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!nvIsAdaptiveSyncDpyVrrType(pTimings->vrr.type))) {
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return;
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}
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msaParams->bEnableMSA = 1;
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msaParams->bCacheMsaOverrideForNextModeset = 1;
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msaParams->bEnableMSA = 1;
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msaParams->bCacheMsaOverrideForNextModeset = 1;
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if (pTimings->yuv420Mode == NV_YUV420_MODE_SW) {
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featureMask->bRasterTotalHorizontal = true;
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featureMask->bActiveStartHorizontal = true;
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featureMask->bSurfaceTotalHorizontal = true;
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@@ -259,6 +267,15 @@ static void SetDPMSATiming(const NVDispEvoRec *pDispEvo,
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featureValues->surfaceTotalHorizontal = 2 * nvEvoVisibleWidth(pTimings);
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featureValues->syncWidthHorizontal = 2 * (pTimings->rasterSyncEnd.x + 1);
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}
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/*
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* In case of Adaptive-Sync VRR, override VTotal field of MSA (Main Stream
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* Attributes) to workaround bug 4164132.
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*/
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if (nvIsAdaptiveSyncDpyVrrType(pTimings->vrr.type)) {
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featureMask->bRasterTotalVertical = true;
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featureValues->rasterTotalVertical = pTimings->rasterSize.y;
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}
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}
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static void InitDpModesetParams(
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@@ -2117,7 +2117,10 @@ IsProposedModeSetStateOneApiHeadIncompatible(
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&pDispEvo->apiHeadState[apiHead];
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const NVDpyEvoRec *pDpyEvo =
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nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo);
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const NvBool bCurrent2Heads1Or =
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(nvPopCount32(pApiHeadState->hwHeadsMask) > 1);
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const NvBool bProposed2Heads1Or =
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(nvPopCount32(pProposedApiHead->hwHeadsMask) > 1);
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nvAssert(pDpyEvo != NULL);
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/*
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@@ -2127,11 +2130,22 @@ IsProposedModeSetStateOneApiHeadIncompatible(
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*
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* Consider this api-head incompatible if there is change in the api-head
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* to hardware-head(s) mapping.
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*
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* Mark api-head incompatible if its current or proposed modeset state is
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* using 2Heads1OR configuration:
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* Even if there is no change in the hardware heads or modetimings, it is
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* not possible to do modeset on the active 2Heads1OR api-head without
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* shutting it down first. The modeset code path is ready to handle the
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* glitchless 2Heads1OR modeset, for example NV0073_CTRL_CMD_DFP_ASSIGN_SOR
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* does not handles the assignment of secondary SORs if display is already
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* active and returns incorrect information which leads to segfault in
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* NVKMS.
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*/
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if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo) ||
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((pProposedApiHead->hwHeadsMask != 0x0) &&
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(pProposedApiHead->hwHeadsMask != pApiHeadState->hwHeadsMask))) {
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(pProposedApiHead->hwHeadsMask != pApiHeadState->hwHeadsMask)) ||
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bCurrent2Heads1Or || bProposed2Heads1Or) {
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return TRUE;
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}
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@@ -183,13 +183,6 @@ static NvBool DpyIsGsync(const NVDpyEvoRec *pDpyEvo)
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return pDpyEvo->vrr.type == NVKMS_DPY_VRR_TYPE_GSYNC;
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}
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static NvBool IsAdaptiveSyncDpyVrrType(enum NvKmsDpyVRRType type)
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{
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return ((type == NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED) ||
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(type == NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED));
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}
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static NvBool AnyEnabledAdaptiveSyncDpys(const NVDevEvoRec *pDevEvo)
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{
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NVDispEvoPtr pDispEvo;
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@@ -202,7 +195,7 @@ static NvBool AnyEnabledAdaptiveSyncDpys(const NVDevEvoRec *pDevEvo)
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const NVDispHeadStateEvoRec *pHeadState =
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&pDispEvo->headState[head];
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if (IsAdaptiveSyncDpyVrrType(pHeadState->timings.vrr.type)) {
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if (nvIsAdaptiveSyncDpyVrrType(pHeadState->timings.vrr.type)) {
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return TRUE;
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}
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}
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@@ -286,7 +279,7 @@ void nvAdjustHwModeTimingsForVrrEvo(NVHwModeTimingsEvoPtr pTimings,
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// Allow overriding the EDID min refresh rate on Adaptive-Sync
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// displays.
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if (IsAdaptiveSyncDpyVrrType(vrrType) && vrrOverrideMinRefreshRate) {
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if (nvIsAdaptiveSyncDpyVrrType(vrrType) && vrrOverrideMinRefreshRate) {
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NvU32 minMinRefreshRate, maxMinRefreshRate;
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NvU32 clampedMinRefreshRate;
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@@ -737,7 +730,7 @@ void nvDisableVrr(NVDevEvoPtr pDevEvo)
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NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head];
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if ((pHeadState->pConnectorEvo != NULL) &&
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IsAdaptiveSyncDpyVrrType(pHeadState->timings.vrr.type)) {
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nvIsAdaptiveSyncDpyVrrType(pHeadState->timings.vrr.type)) {
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if (nvConnectorUsesDPLib(pHeadState->pConnectorEvo)) {
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nvDPLibSetAdaptiveSync(pDispEvo, head, FALSE);
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} else {
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@@ -799,7 +792,7 @@ void nvGetDpyMinRefreshRateValidValues(
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{
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NvU32 edidMinRefreshRate;
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if (IsAdaptiveSyncDpyVrrType(vrrType)) {
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if (nvIsAdaptiveSyncDpyVrrType(vrrType)) {
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/*
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* Adaptive-Sync monitors must always define a nonzero minimum refresh
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* rate in the EDID, and a modeset may override this within a range
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@@ -860,7 +853,7 @@ void nvEnableVrr(NVDevEvoPtr pDevEvo)
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NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head];
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if ((pHeadState->pConnectorEvo != NULL) &&
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IsAdaptiveSyncDpyVrrType(pHeadState->timings.vrr.type)) {
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nvIsAdaptiveSyncDpyVrrType(pHeadState->timings.vrr.type)) {
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if (nvConnectorUsesDPLib(pHeadState->pConnectorEvo)) {
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nvDPLibSetAdaptiveSync(pDispEvo, head, TRUE);
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} else {
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