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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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515.43.04
This commit is contained in:
Andy Ritger
183
src/common/inc/nveGPUConfig.h
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183
src/common/inc/nveGPUConfig.h
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _NVEGPUCONFIG_H_
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#define _NVEGPUCONFIG_H_
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#include <nvtypes.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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#define EGPU_INLINE NV_FORCEINLINE
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#else //!__cplusplus
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#if defined(NV_UNIX) || defined(NVCPU_RISCV64) || defined(NV_MODS)
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#define EGPU_INLINE static NV_INLINE
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#else //NV_UNIX
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#define EGPU_INLINE NV_INLINE
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#endif //NV_UNIX
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#endif //!__cplusplus
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// Surprise removal capable TB3 and TB2 BUS Device ID
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#define BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01 0x1578
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#define BUS_DEVICE_ID_TB3_02 0x1576
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#define BUS_DEVICE_ID_TB3_03 0x15C0
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#define BUS_DEVICE_ID_TB3_04 0x15D3
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#define BUS_DEVICE_ID_TB3_05 0x15DA
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#define BUS_DEVICE_ID_TB3_06 0x15EA
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#define BUS_DEVICE_ID_TB3_07 0x15E7
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#define BUS_DEVICE_ID_TB3_08 0x15EF
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#define BUS_DEVICE_ID_TB3_09 0x1133
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#define BUS_DEVICE_ID_TB3_10 0x1136
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// IceLake-U TB3 device ids. Below TB3 would be integrated to CPU.
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#define BUS_DEVICE_ID_ICELAKE_TB3_01 0x8A1D
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#define BUS_DEVICE_ID_ICELAKE_TB3_02 0x8A1F
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#define BUS_DEVICE_ID_ICELAKE_TB3_03 0x8A21
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#define BUS_DEVICE_ID_ICELAKE_TB3_04 0x8A23
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#define BUS_DEVICE_ID_ICELAKE_TB3_05 0x8A0D
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#define BUS_DEVICE_ID_ICELAKE_TB3_06 0x8A17
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// TigerLake Thunderbolt device ids.
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#define BUS_DEVICE_ID_TIGERLAKE_TB3_01 0x9A1B
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#define BUS_DEVICE_ID_TIGERLAKE_TB3_02 0x9A1D
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#define BUS_DEVICE_ID_TIGERLAKE_TB3_03 0x9A1F
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#define BUS_DEVICE_ID_TIGERLAKE_TB3_04 0x9A21
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#define BUS_DEVICE_ID_TIGERLAKE_TB3_05 0x9A23
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#define BUS_DEVICE_ID_TIGERLAKE_TB3_06 0x9A25
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#define BUS_DEVICE_ID_TIGERLAKE_TB3_07 0x9A27
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#define BUS_DEVICE_ID_TIGERLAKE_TB3_08 0x9A29
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#define BUS_DEVICE_ID_TIGERLAKE_TB3_09 0x9A2B
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#define BUS_DEVICE_ID_TIGERLAKE_TB3_10 0x9A2D
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//#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_01 0X156C // obsolete
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#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02 0X156D
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#define BUS_DEVICE_ID_TB2_03 0x157E
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#define BUS_DEVICE_ID_TB2_04 0x156B
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#define BUS_DEVICE_ID_TB2_05 0x1567
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#define BUS_DEVICE_ID_TB2_06 0x1569
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//#define BUS_DEVICE_ID_TB2_07 0x1548 // obsolete
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#define BUS_DEVICE_ID_TB2_08 0x151B
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#define BUS_DEVICE_ID_TB2_09 0x1549
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#define BUS_DEVICE_ID_TB2_10 0x1513
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//*****************************************************************************
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// Function: isTB3DeviceID
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//
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// Routine Description:
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//
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// Function to match the specified Device ID with the known TB3 BUS's
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// device IDs.
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//
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// Arguments:
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//
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// deviceID[IN]: Device ID to match with the TB3 Bus
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//
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// Return Value:
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//
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// true: When the passed Dev ID match with TB3's BUS Device ID
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// false: When the passed Dev ID is not matching with known TB3's
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// BUS Device ID
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//*****************************************************************************
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EGPU_INLINE NvBool isTB3DeviceID(NvU16 deviceID)
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{
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NvU32 index;
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NvU16 tb3DeviceIDList[]={ BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01,
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BUS_DEVICE_ID_TB3_02,
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BUS_DEVICE_ID_TB3_03,
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BUS_DEVICE_ID_TB3_04,
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BUS_DEVICE_ID_TB3_05,
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BUS_DEVICE_ID_TB3_06,
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BUS_DEVICE_ID_TB3_07,
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BUS_DEVICE_ID_TB3_08,
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BUS_DEVICE_ID_TB3_09,
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BUS_DEVICE_ID_TB3_10,
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BUS_DEVICE_ID_ICELAKE_TB3_01,
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BUS_DEVICE_ID_ICELAKE_TB3_02,
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BUS_DEVICE_ID_ICELAKE_TB3_03,
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BUS_DEVICE_ID_ICELAKE_TB3_04,
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BUS_DEVICE_ID_ICELAKE_TB3_05,
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BUS_DEVICE_ID_ICELAKE_TB3_06,
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BUS_DEVICE_ID_TIGERLAKE_TB3_01,
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BUS_DEVICE_ID_TIGERLAKE_TB3_02,
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BUS_DEVICE_ID_TIGERLAKE_TB3_03,
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BUS_DEVICE_ID_TIGERLAKE_TB3_04,
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BUS_DEVICE_ID_TIGERLAKE_TB3_05,
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BUS_DEVICE_ID_TIGERLAKE_TB3_06,
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BUS_DEVICE_ID_TIGERLAKE_TB3_07,
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BUS_DEVICE_ID_TIGERLAKE_TB3_08,
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BUS_DEVICE_ID_TIGERLAKE_TB3_09,
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BUS_DEVICE_ID_TIGERLAKE_TB3_10
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};
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for (index = 0; index < (sizeof(tb3DeviceIDList)/sizeof(NvU16)); index++)
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{
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if (deviceID == tb3DeviceIDList[index])
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{
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return NV_TRUE;
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}
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}
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return NV_FALSE;
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} // isTB3DeviceID
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//*****************************************************************************
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// Function: isTB2DeviceID
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//
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// Routine Description:
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//
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// Function to match the specified Device ID with the known TB2 BUS's
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// device IDs.
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//
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// Arguments:
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//
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// deviceID[IN]: Device ID to match with the TB2 Bus
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//
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// Return Value:
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//
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// true: When the passed Dev ID match with TB2's BUS Device ID
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// false: When the passed Dev ID is not matching with known TB2's
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// BUS Device ID
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//*****************************************************************************
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EGPU_INLINE NvBool isTB2DeviceID(NvU16 deviceID)
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{
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NvU32 index;
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NvU16 tb2DeviceIDList[]={ BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02,
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BUS_DEVICE_ID_TB2_03, BUS_DEVICE_ID_TB2_04,
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BUS_DEVICE_ID_TB2_05, BUS_DEVICE_ID_TB2_06,
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BUS_DEVICE_ID_TB2_08, BUS_DEVICE_ID_TB2_09,
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BUS_DEVICE_ID_TB2_10
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};
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for (index = 0; index < (sizeof(tb2DeviceIDList)/sizeof(NvU16)); index++)
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{
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if (deviceID == tb2DeviceIDList[index])
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{
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return NV_TRUE;
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}
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}
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return NV_FALSE;
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} // isTB2DeviceID
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#ifdef __cplusplus
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}
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#endif
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#endif //_NVEGPUCONFIG_H_
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