mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-04-21 23:09:14 +00:00
515.43.04
This commit is contained in:
Andy Ritger
437
src/common/nvswitch/kernel/inc/io_nvswitch.h
Normal file
437
src/common/nvswitch/kernel/inc/io_nvswitch.h
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@@ -0,0 +1,437 @@
|
||||
/*
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||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
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||||
*/
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#ifndef _IO_NVSWITCH_H_
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#define _IO_NVSWITCH_H_
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// NVSWITCH_REG_* MMIO wrappers are to be used for absolute symbolic BAR0 offset
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// register references like SMC, CLOCK, BUS, and PRIV_MASTER.
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//
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||||
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||||
#define NVSWITCH_REG_RD32(_d, _dev, _reg) \
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||||
( \
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NVSWITCH_PRINT(_d, MMIO, \
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"%s: MEM_RD: %s, %s (+%04x)\n", \
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||||
__FUNCTION__, \
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||||
#_dev, #_reg, NV ## _dev ## _reg) \
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||||
, \
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nvswitch_reg_read_32(_d, NV##_dev##_reg) \
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||||
); \
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||||
((void)(_d))
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||||
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#define NVSWITCH_REG_WR32(_d, _dev, _reg, _data) \
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NVSWITCH_PRINT(_d, MMIO, \
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||||
"%s: MEM_WR: %s, %s (+%04x) 0x%08x\n", \
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||||
__FUNCTION__, \
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||||
#_dev, #_reg, NV ## _dev ## _reg, _data); \
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nvswitch_reg_write_32(_d, NV##_dev##_reg, _data); \
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((void)(_d))
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||||
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//
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// NVSWITCH_OFF_* MMIO wrappers are used to access a fully formed BAR0 offset.
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//
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||||
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#define NVSWITCH_OFF_RD32(_d, _off) \
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nvswitch_reg_read_32(_d, _off); \
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||||
((void)(_d))
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||||
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||||
#define NVSWITCH_OFF_WR32(_d, _off, _data) \
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nvswitch_reg_write_32(_d, _off, _data); \
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((void)(_d))
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||||
|
||||
#define NVSWITCH_ENGINE_DESCRIPTOR_UC_SIZE 64
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||||
#define NVSWITCH_ENGINE_DESCRIPTOR_MC_SIZE 3
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||||
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#define NVSWITCH_ENGINE_INSTANCE_INVALID ((NvU32) (~0))
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||||
|
||||
typedef struct engine_descriptor
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||||
{
|
||||
const char *eng_name;
|
||||
NvU32 eng_id; // REGISTER_RW_ENGINE_*
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NvU32 eng_count;
|
||||
NvU32 uc_addr[NVSWITCH_ENGINE_DESCRIPTOR_UC_SIZE];
|
||||
NvU32 bc_addr;
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||||
NvU32 mc_addr[NVSWITCH_ENGINE_DESCRIPTOR_MC_SIZE];
|
||||
NvU32 mc_addr_count;
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} NVSWITCH_ENGINE_DESCRIPTOR_TYPE;
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#define NVSWITCH_DECLARE_IO_DESCRIPTOR(_engine, _bcast) \
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NVSWITCH_ENGINE_DESCRIPTOR_TYPE _engine;
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||||
|
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#define NVSWITCH_BASE_ADDR_INVALID ((NvU32) (~0))
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||||
|
||||
//
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// All IP-based (0-based register manuals) engines that ever existed on *ANY*
|
||||
// architecture(s) must be listed here in order to use the common IO wrappers.
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||||
// New engines need to be added here as well as in the chip-specific lists in
|
||||
// their respective headers that generate chip-specific handlers.
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||||
// Absolute BAR0 offset-based units are legacy units in which the unit's offset
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||||
// in BAR0 is included in the register definition in the manuals. For these
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||||
// legacy units the discovered base is not used since it is already part of the
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// register. Legacy units (e.g. PSMC, CLOCK, BUS, and PRIV_MASTER) should use
|
||||
// NVSWITCH_REG_RD/WR IO wrappers.
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||||
//
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||||
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#define NVSWITCH_LIST_ALL_ENGINES(_op) \
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_op(XVE) \
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_op(SAW) \
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_op(SOE) \
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||||
_op(SMR) \
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||||
_op(GIN) \
|
||||
_op(XAL) \
|
||||
_op(XAL_FUNC) \
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||||
_op(XPL) \
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||||
_op(XTL) \
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||||
_op(XTL_CONFIG) \
|
||||
_op(UXL) \
|
||||
_op(GPU_PTOP) \
|
||||
_op(PMC) \
|
||||
_op(PBUS) \
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||||
_op(ROM2) \
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||||
_op(GPIO) \
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||||
_op(FSP) \
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||||
_op(SYSCTRL) \
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||||
_op(CLKS_SYS) \
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||||
_op(CLKS_SYSB) \
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||||
_op(CLKS_P0) \
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||||
_op(SAW_PM) \
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||||
_op(PCIE_PM) \
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||||
_op(PRT_PRI_HUB) \
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||||
_op(PRT_PRI_RS_CTRL) \
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||||
_op(SYS_PRI_HUB) \
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||||
_op(SYS_PRI_RS_CTRL) \
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||||
_op(SYSB_PRI_HUB) \
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||||
_op(SYSB_PRI_RS_CTRL) \
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||||
_op(PRI_MASTER_RS) \
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||||
_op(PTIMER) \
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||||
\
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||||
_op(NPG) \
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||||
_op(NPORT) \
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||||
\
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||||
_op(NVLW) \
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||||
_op(MINION) \
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||||
_op(NVLIPT) \
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||||
_op(NVLIPT_LNK) \
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||||
_op(NVLTLC) \
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||||
_op(NVLDL) \
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_op(CPR) \
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||||
\
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||||
_op(NXBAR) \
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_op(TILE) \
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||||
_op(TILEOUT) \
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||||
\
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||||
_op(NPG_PERFMON) \
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||||
_op(NPORT_PERFMON) \
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||||
\
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||||
_op(NVLW_PERFMON) \
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_op(RX_PERFMON) \
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||||
_op(TX_PERFMON) \
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||||
\
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||||
_op(NXBAR_PERFMON) \
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||||
_op(TILE_PERFMON) \
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||||
_op(TILEOUT_PERFMON) \
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||||
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||||
#define ENGINE_ID_LIST(_eng) \
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NVSWITCH_ENGINE_ID_##_eng,
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||||
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||||
//
|
||||
// ENGINE_IDs are the complete list of all engines that are supported on
|
||||
// *ANY* architecture(s) that may support them. Any one architecture may or
|
||||
// may not understand how to operate on any one specific engine.
|
||||
// Architectures that share a common ENGINE_ID are not guaranteed to have
|
||||
// compatible manuals.
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//
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typedef enum nvswitch_engine_id
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||||
{
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NVSWITCH_LIST_ALL_ENGINES(ENGINE_ID_LIST)
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NVSWITCH_ENGINE_ID_SIZE,
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} NVSWITCH_ENGINE_ID;
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//
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||||
// NVSWITCH_ENG_* MMIO wrappers are to be used for top level discovered
|
||||
// devices like SAW, FUSE, PMGR, XVE, etc.
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||||
//
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||||
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#define NVSWITCH_GET_ENG_DESC_TYPE 0
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#define NVSWITCH_GET_ENG_DESC_TYPE_UNICAST NVSWITCH_GET_ENG_DESC_TYPE
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#define NVSWITCH_GET_ENG_DESC_TYPE_BCAST 1
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#define NVSWITCH_GET_ENG_DESC_TYPE_MULTICAST 2
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#define NVSWITCH_GET_ENG(_d, _eng, _bcast, _engidx) \
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((_d)->hal.nvswitch_get_eng_base( \
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_d, \
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||||
NVSWITCH_ENGINE_ID_##_eng, \
|
||||
NVSWITCH_GET_ENG_DESC_TYPE##_bcast, \
|
||||
_engidx))
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||||
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||||
#define NVSWITCH_ENG_COUNT(_d, _eng, _bcast) \
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((_d)->hal.nvswitch_get_eng_count( \
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||||
_d, \
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||||
NVSWITCH_ENGINE_ID_##_eng, \
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||||
NVSWITCH_GET_ENG_DESC_TYPE##_bcast))
|
||||
|
||||
#define NVSWITCH_ENG_IS_VALID(_d, _eng, _engidx) \
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||||
( \
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NVSWITCH_GET_ENG(_d, _eng, , _engidx) != NVSWITCH_BASE_ADDR_INVALID \
|
||||
)
|
||||
|
||||
#define NVSWITCH_ENG_WR32(_d, _eng, _bcast, _engidx, _dev, _reg, _data) \
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||||
{ \
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NVSWITCH_PRINT(_d, MMIO, \
|
||||
"%s: MEM_WR %s[%d]: %s, %s (%06x+%04x) 0x%08x\n", \
|
||||
__FUNCTION__, \
|
||||
#_eng#_bcast, _engidx, \
|
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#_dev, #_reg, \
|
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NVSWITCH_GET_ENG(_d, _eng, _bcast, _engidx), \
|
||||
NV ## _dev ## _reg, _data); \
|
||||
\
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||||
((_d)->hal.nvswitch_eng_wr( \
|
||||
_d, \
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||||
NVSWITCH_ENGINE_ID_##_eng, \
|
||||
NVSWITCH_GET_ENG_DESC_TYPE##_bcast, \
|
||||
_engidx, \
|
||||
NV ## _dev ## _reg, _data)); \
|
||||
}
|
||||
|
||||
#define NVSWITCH_ENG_RD32(_d, _eng, _bcast, _engidx, _dev, _reg) \
|
||||
( \
|
||||
NVSWITCH_PRINT(_d, MMIO, \
|
||||
"%s: MEM_RD %s[%d]: %s, %s (%06x+%04x)\n", \
|
||||
__FUNCTION__, \
|
||||
#_eng#_bcast, _engidx, \
|
||||
#_dev, #_reg, \
|
||||
NVSWITCH_GET_ENG(_d, _eng, _bcast, _engidx), \
|
||||
NV ## _dev ## _reg) \
|
||||
, \
|
||||
((_d)->hal.nvswitch_eng_rd( \
|
||||
_d, \
|
||||
NVSWITCH_ENGINE_ID_##_eng, \
|
||||
NVSWITCH_GET_ENG_DESC_TYPE##_bcast, \
|
||||
_engidx, \
|
||||
NV ## _dev ## _reg)) \
|
||||
); \
|
||||
((void)(_d))
|
||||
|
||||
#define NVSWITCH_ENG_WR32_IDX(_d, _eng, _bcast, _engidx, _dev, _reg, _idx, _data) \
|
||||
{ \
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||||
NVSWITCH_PRINT(_d, MMIO, \
|
||||
"%s: MEM_WR %s[%d]: %s, %s(%d) (%06x+%04x) 0x%08x\n", \
|
||||
__FUNCTION__, \
|
||||
#_eng#_bcast, _engidx, \
|
||||
#_dev, #_reg, _idx, \
|
||||
NVSWITCH_GET_ENG(_d, _eng, _bcast, _engidx), \
|
||||
NV ## _dev ## _reg(_idx), _data); \
|
||||
\
|
||||
((_d)->hal.nvswitch_eng_wr( \
|
||||
_d, \
|
||||
NVSWITCH_ENGINE_ID_##_eng, \
|
||||
NVSWITCH_GET_ENG_DESC_TYPE##_bcast, \
|
||||
_engidx, \
|
||||
NV ## _dev ## _reg(_idx), _data)); \
|
||||
}
|
||||
|
||||
#define NVSWITCH_ENG_RD32_IDX(_d, _eng, _bcast, _engidx, _dev, _reg, _idx) \
|
||||
( \
|
||||
NVSWITCH_PRINT(_d, MMIO, \
|
||||
"%s: MEM_RD %s[%d]: %s, %s(%d) (%06x+%04x)\n", \
|
||||
__FUNCTION__, \
|
||||
#_eng#_bcast, _engidx, \
|
||||
#_dev, #_reg, _idx, \
|
||||
NVSWITCH_GET_ENG(_d, _eng, _bcast, _engidx), \
|
||||
NV ## _dev ## _reg(_idx)) \
|
||||
, \
|
||||
((_d)->hal.nvswitch_eng_rd( \
|
||||
_d, \
|
||||
NVSWITCH_ENGINE_ID_##_eng, \
|
||||
NVSWITCH_GET_ENG_DESC_TYPE##_bcast, \
|
||||
_engidx, \
|
||||
NV ## _dev ## _reg(_idx))) \
|
||||
); \
|
||||
((void)(_d))
|
||||
|
||||
#define NVSWITCH_ENG_OFF_WR32(_d, _eng, _bcast, _engidx, _offset, _data) \
|
||||
{ \
|
||||
NVSWITCH_PRINT(_d, MMIO, \
|
||||
"%s: MEM_WR %s[%d]: 0x%x (%06x+%04x) 0x%08x\n", \
|
||||
__FUNCTION__, \
|
||||
#_eng#_bcast, _engidx, \
|
||||
_offset, \
|
||||
NVSWITCH_GET_ENG(_d, _eng, _bcast, _engidx), \
|
||||
_offset, _data); \
|
||||
((_d)->hal.nvswitch_eng_wr( \
|
||||
_d, \
|
||||
NVSWITCH_ENGINE_ID_##_eng, \
|
||||
NVSWITCH_GET_ENG_DESC_TYPE##_bcast, \
|
||||
_engidx, \
|
||||
_offset, _data)); \
|
||||
}
|
||||
|
||||
#define NVSWITCH_ENG_OFF_RD32(_d, _eng, _bcast, _engidx, _offset) \
|
||||
( \
|
||||
NVSWITCH_PRINT(_d, MMIO, \
|
||||
"%s: MEM_RD %s[%d]: 0x%x (%06x+%04x)\n", \
|
||||
__FUNCTION__, \
|
||||
#_eng#_bcast, _engidx, \
|
||||
_offset, \
|
||||
NVSWITCH_GET_ENG(_d, _eng, _bcast, _engidx), \
|
||||
_offset) \
|
||||
, \
|
||||
((_d)->hal.nvswitch_eng_rd( \
|
||||
_d, \
|
||||
NVSWITCH_ENGINE_ID_##_eng, \
|
||||
NVSWITCH_GET_ENG_DESC_TYPE##_bcast, \
|
||||
_engidx, \
|
||||
_offset)) \
|
||||
)
|
||||
|
||||
//
|
||||
// Per-link information
|
||||
//
|
||||
|
||||
#define NVSWITCH_MAX_LINK_COUNT 64
|
||||
|
||||
#define NVSWITCH_MAX_SEED_BUFFER_SIZE NVSWITCH_MAX_SEED_NUM + 1
|
||||
|
||||
#define NVSWITCH_MAX_INBAND_BUFFER_SIZE 256*8
|
||||
#define NVSWITCH_MAX_INBAND_BITS_SENT_AT_ONCE 32
|
||||
#define NVSWITCH_MAX_INBAND_BUFFER_ENTRIES NVSWITCH_MAX_INBAND_BUFFER_SIZE/NVSWITCH_MAX_INBAND_BITS_SENT_AT_ONCE
|
||||
|
||||
//
|
||||
// Inband data structure
|
||||
//
|
||||
struct nvswitch_inband_data
|
||||
{
|
||||
// Inband bufer at sender Minion
|
||||
NvU32 sendBuffer[NVSWITCH_MAX_INBAND_BUFFER_ENTRIES];
|
||||
|
||||
// Inband buffer at receiver Minion
|
||||
NvU32 receiveBuffer[NVSWITCH_MAX_INBAND_BUFFER_ENTRIES];
|
||||
|
||||
// Is the current Minion a sender or receiver of Inband Data?
|
||||
NvBool bIsSenderMinion;
|
||||
|
||||
// Bool to say fail or not
|
||||
NvBool bTransferFail;
|
||||
|
||||
// # of transmisions done - count
|
||||
// NvU32 txCount;
|
||||
};
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvBool valid;
|
||||
NvU32 link_clock_khz;
|
||||
|
||||
NvBool fatal_error_occurred;
|
||||
NvBool ingress_packet_latched;
|
||||
NvBool egress_packet_latched;
|
||||
|
||||
NvBool nea; // Near end analog
|
||||
NvBool ned; // Near end digital
|
||||
|
||||
NvU32 lane_rxdet_status_mask;
|
||||
|
||||
NvBool bIsRepeaterMode;
|
||||
|
||||
// Minion Inband Data structure
|
||||
struct nvswitch_inband_data inBandData;
|
||||
|
||||
} NVSWITCH_LINK_TYPE;
|
||||
|
||||
//
|
||||
// Per link register access routines
|
||||
// LINK_* MMIO wrappers are used to reference per-link engine instances
|
||||
//
|
||||
|
||||
#define NVSWITCH_LINK_COUNT(_d) \
|
||||
(nvswitch_get_num_links(_d))
|
||||
|
||||
#define NVSWITCH_GET_LINK_ENG_INST(_d, _linknum, _eng) \
|
||||
nvswitch_get_link_eng_inst(_d, _linknum, NVSWITCH_ENGINE_ID_##_eng)
|
||||
|
||||
#define NVSWITCH_IS_LINK_ENG_VALID(_d, _linknum, _eng) \
|
||||
( \
|
||||
(NVSWITCH_GET_ENG(_d, _eng, , \
|
||||
NVSWITCH_GET_LINK_ENG_INST(_d, _linknum, _eng)) \
|
||||
!= NVSWITCH_BASE_ADDR_INVALID) && \
|
||||
nvswitch_is_link_valid(_d, _linknum) \
|
||||
)
|
||||
|
||||
#define NVSWITCH_LINK_OFFSET(_d, _physlinknum, _eng, _dev, _reg) \
|
||||
( \
|
||||
NVSWITCH_ASSERT(NVSWITCH_IS_LINK_ENG_VALID(_d, _physlinknum, _eng)) \
|
||||
, \
|
||||
NVSWITCH_PRINT(_d, MMIO, \
|
||||
"%s: LINK_OFFSET link[%d] %s: %s,%s (+%04x)\n", \
|
||||
__FUNCTION__, \
|
||||
_physlinknum, \
|
||||
#_eng, #_dev, #_reg, NV ## _dev ## _reg) \
|
||||
, \
|
||||
NVSWITCH_GET_ENG(_d, _eng, , \
|
||||
NVSWITCH_GET_LINK_ENG_INST(_d, _physlinknum, _eng)) + \
|
||||
NV##_dev##_reg \
|
||||
)
|
||||
|
||||
#define NVSWITCH_LINK_WR32(_d, _physlinknum, _eng, _dev, _reg, _data) \
|
||||
NVSWITCH_ASSERT(NVSWITCH_IS_LINK_ENG_VALID(_d, _physlinknum, _eng)); \
|
||||
NVSWITCH_PRINT(_d, MMIO, \
|
||||
"%s: LINK_WR link[%d] %s: %s,%s (+%04x) 0x%08x\n", \
|
||||
__FUNCTION__, \
|
||||
_physlinknum, \
|
||||
#_eng, #_dev, #_reg, NV ## _dev ## _reg, _data); \
|
||||
((_d)->hal.nvswitch_eng_wr( \
|
||||
_d, \
|
||||
NVSWITCH_ENGINE_ID_##_eng, \
|
||||
NVSWITCH_GET_ENG_DESC_TYPE_UNICAST, \
|
||||
NVSWITCH_GET_LINK_ENG_INST(_d, _physlinknum, _eng), \
|
||||
NV ## _dev ## _reg, _data)); \
|
||||
((void)(_d))
|
||||
|
||||
#define NVSWITCH_LINK_RD32(_d, _physlinknum, _eng, _dev, _reg) \
|
||||
( \
|
||||
NVSWITCH_ASSERT(NVSWITCH_IS_LINK_ENG_VALID(_d, _physlinknum, _eng)) \
|
||||
, \
|
||||
NVSWITCH_PRINT(_d, MMIO, \
|
||||
"%s: LINK_RD link[%d] %s: %s,%s (+%04x)\n", \
|
||||
__FUNCTION__, \
|
||||
_physlinknum, \
|
||||
#_eng, #_dev, #_reg, NV ## _dev ## _reg) \
|
||||
, \
|
||||
((_d)->hal.nvswitch_eng_rd( \
|
||||
_d, \
|
||||
NVSWITCH_ENGINE_ID_##_eng, \
|
||||
NVSWITCH_GET_ENG_DESC_TYPE_UNICAST, \
|
||||
NVSWITCH_GET_LINK_ENG_INST(_d, _physlinknum, _eng), \
|
||||
NV ## _dev ## _reg)) \
|
||||
); \
|
||||
((void)(_d))
|
||||
|
||||
#define NVSWITCH_LINK_WR32_IDX(_d, _physlinknum, _eng, _dev, _reg, _idx, _data) \
|
||||
NVSWITCH_LINK_WR32(_d, _physlinknum, _eng, _dev, _reg(_idx), _data); \
|
||||
((void)(_d))
|
||||
|
||||
#define NVSWITCH_LINK_RD32_IDX(_d, _physlinknum, _eng, _dev, _reg, _idx) \
|
||||
NVSWITCH_LINK_RD32(_d, _physlinknum, _eng, _dev, _reg(_idx)); \
|
||||
((void)(_d))
|
||||
|
||||
#endif //_IO_NVSWITCH_H_
|
||||
Reference in New Issue
Block a user