mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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515.43.04
This commit is contained in:
Andy Ritger
2655
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
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src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
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src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
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src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
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src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h
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src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _HALDEFS_SOE_NVSWITCH_H_
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#define _HALDEFS_SOE_NVSWITCH_H_
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#include "nvstatus.h"
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#include "flcnifcmn.h"
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#include "flcn/haldefs_flcnable_nvswitch.h"
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struct SOE;
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typedef struct {
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// needs to be the first thing in this struct so that a soe_hal* can be
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// re-interpreted as a flcnable_hal* and vise-versa.
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flcnable_hal base;
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//add any hal functions specific to SOE here
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NV_STATUS (*processMessages)(
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struct nvswitch_device *device,
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struct SOE *pSoe);
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NV_STATUS (*waitForInitAck)(
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struct nvswitch_device *device,
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struct SOE *pSoe);
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NvU32 (*service)(
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struct nvswitch_device *device,
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struct SOE *pSoe);
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void (*serviceHalt)(
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struct nvswitch_device *device,
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struct SOE *pSoe);
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void (*ememTransfer)(
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struct nvswitch_device *device,
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struct SOE *pSoe,
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NvU32 dmemAddr,
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NvU8 *pBuf,
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NvU32 sizeBytes,
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NvU8 port,
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NvBool bCopyFrom);
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NvU32 (*getEmemSize)(
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struct nvswitch_device *device,
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struct SOE *pSoe);
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NvU32 (*getEmemStartOffset)(
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struct nvswitch_device *device,
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struct SOE *pSoe);
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NV_STATUS (*ememPortToRegAddr)(
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struct nvswitch_device *device,
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struct SOE *pSoe,
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NvU32 port,
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NvU32 *pEmemCAddr,
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NvU32 *pEmemDAddr);
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void (*serviceExterr)(
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struct nvswitch_device *device,
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struct SOE *pSoe);
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NV_STATUS (*getExtErrRegAddrs)(
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struct nvswitch_device *device,
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struct SOE *pSoe,
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NvU32 *pExtErrAddr,
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NvU32 *pExtErrStat);
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NvU32 (*ememPortSizeGet)(
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struct nvswitch_device *device,
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struct SOE *pSoe);
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NvBool (*isCpuHalted)(
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struct nvswitch_device *device,
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struct SOE *pSoe);
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NvlStatus (*testDma)(
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struct nvswitch_device *device);
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NvlStatus (*setPexEOM)(
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struct nvswitch_device *device,
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NvU8 mode,
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NvU8 nblks,
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NvU8 nerrs,
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NvU8 berEyeSel);
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NvlStatus (*getPexEomStatus)(
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struct nvswitch_device *device,
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NvU8 mode,
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NvU8 nblks,
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NvU8 nerrs,
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NvU8 berEyeSel,
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NvU32 laneMask,
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NvU16 *pEomStatus);
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NvlStatus (*getUphyDlnCfgSpace)(
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struct nvswitch_device *device,
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NvU32 regAddress,
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NvU32 laneSelectMask,
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NvU16 *pRegValue);
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NvlStatus (*forceThermalSlowdown)(
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struct nvswitch_device *device,
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NvBool slowdown,
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NvU32 periodUs);
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NvlStatus (*setPcieLinkSpeed)(
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struct nvswitch_device *device,
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NvU32 linkSpeed);
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} soe_hal;
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// HAL functions
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void soeSetupHal_LR10(struct SOE *pSoe);
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#endif //_HALDEFS_SOE_NVSWITCH_H_
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61
src/common/nvswitch/kernel/inc/soe/soe_nvswitch.h
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src/common/nvswitch/kernel/inc/soe/soe_nvswitch.h
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@@ -0,0 +1,61 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _SOE_NVSWITCH_H_
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#define _SOE_NVSWITCH_H_
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#include "nvlink_errors.h"
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#include "nvtypes.h"
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#include "nvstatus.h"
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typedef struct SOE SOE, *PSOE;
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struct FLCNABLE;
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struct nvswitch_device;
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SOE *soeAllocNew(void);
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NvlStatus soeInit(struct nvswitch_device *device, PSOE pSoe, NvU32 pci_device_id);
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void soeDestroy(struct nvswitch_device *device, PSOE pSoe);
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//HAL functions
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NV_STATUS soeProcessMessages (struct nvswitch_device *device, PSOE pSoe);
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NV_STATUS soeWaitForInitAck (struct nvswitch_device *device, PSOE pSoe);
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NvU32 soeService_HAL (struct nvswitch_device *device, PSOE pSoe);
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void soeServiceHalt_HAL (struct nvswitch_device *device, PSOE pSoe);
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void soeEmemTransfer_HAL (struct nvswitch_device *device, PSOE pSoe, NvU32 dmemAddr, NvU8 *pBuf, NvU32 sizeBytes, NvU8 port, NvBool bCopyFrom);
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NvU32 soeGetEmemSize_HAL (struct nvswitch_device *device, PSOE pSoe);
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NvU32 soeGetEmemStartOffset_HAL (struct nvswitch_device *device, PSOE pSoe);
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NV_STATUS soeEmemPortToRegAddr_HAL (struct nvswitch_device *device, PSOE pSoe, NvU32 port, NvU32 *pEmemCAddr, NvU32 *pEmemDAddr);
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void soeServiceExterr_HAL (struct nvswitch_device *device, PSOE pSoe);
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NV_STATUS soeGetExtErrRegAddrs_HAL (struct nvswitch_device *device, PSOE pSoe, NvU32 *pExtErrAddr, NvU32 *pExtErrStat);
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NvU32 soeEmemPortSizeGet_HAL (struct nvswitch_device *device, PSOE pSoe);
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NvBool soeIsCpuHalted_HAL (struct nvswitch_device *device, PSOE pSoe);
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NvlStatus soeTestDma_HAL (struct nvswitch_device *device, PSOE pSoe);
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NvlStatus soeSetPexEOM_HAL (struct nvswitch_device *device, NvU8 mode, NvU8 nblks, NvU8 nerrs, NvU8 berEyeSel);
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NvlStatus soeGetPexEomStatus_HAL (struct nvswitch_device *device, NvU8 mode, NvU8 nblks, NvU8 nerrs, NvU8 berEyeSel, NvU32 laneMask, NvU16 *pEomStatus);
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NvlStatus soeGetUphyDlnCfgSpace_HAL (struct nvswitch_device *device, NvU32 regAddress, NvU32 laneSelectMask, NvU16 *pRegValue);
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NvlStatus soeForceThermalSlowdown_HAL (struct nvswitch_device *device, NvBool slowdown, NvU32 periodUs);
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NvlStatus soeSetPcieLinkSpeed_HAL (struct nvswitch_device *device, NvU32 linkSpeed);
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#endif //_SOE_NVSWITCH_H_
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60
src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h
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src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h
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@@ -0,0 +1,60 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _SOE_PRIV_NVSWITCH_H_
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#define _SOE_PRIV_NVSWITCH_H_
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#include "soe/haldefs_soe_nvswitch.h"
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#include "soe/soeifcmn.h"
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#include "flcn/flcnqueue_nvswitch.h"
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#include "flcn/flcnable_nvswitch.h"
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#define SOE_DMEM_ALIGNMENT (4)
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struct SOE
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{
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// needs to be the first thing in this struct so that a PSOE can be
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// re-interpreted as a PFLCNABLE and vise-versa. While it is possible
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// to remove this restriction by using (&pSoe->parent) instead of a cast,
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// 1) the reverse (getting a PSOE from a PFLCNABLE) would be difficult and
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// spooky 2) that would force anybody wanting to do the conversion
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// to know the layout of an SOE object (not a big deal, but still annoying)
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union {
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// pointer to our function table - should always be the first thing in any object (including parent)
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soe_hal *pHal;
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FLCNABLE parent;
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} base;
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// Other member variables specific to SOE go here
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/*!
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* Structure tracking all information for active and inactive SEC2 sequences.
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*/
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FLCN_QMGR_SEQ_INFO seqInfo[RM_SOE_MAX_NUM_SEQUENCES];
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/*! The event descriptor for the Thermal event handler */
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NvU32 thermEvtDesc;
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};
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#endif //_SOE_PRIV_NVSWITCH_H_
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