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Andy Ritger
2022-05-09 13:18:59 -07:00
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73
src/common/sdk/nvidia/inc/Nvcm.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************* Operating System Interface Routines *******************\
* *
* Module: NVCM.H *
* Windows Configuration Manager defines and prototypes. *
* *
* ***IMPORTANT*** The interfaces defined in this file are *deprecated* *
* ***IMPORTANT*** in favor of RmControl. *
* ***IMPORTANT*** Try hard to not use this file at all and definitely *
* ***IMPORTANT*** do not add or modify interfaces here. *
* Ref: bug 488474: delete CFG and CFG_EX *
* *
\***************************************************************************/
#ifndef _NVCM_H_
#define _NVCM_H_
#include "nvdeprecated.h"
#if NV_DEPRECATED_COMPAT(RM_CONFIG_GET_SET)
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(XAPIGEN) /* avoid duplicate generated xapi fns */
#include "nvgputypes.h"
#ifndef _H2INC
#include "rmcd.h"
#endif
#include "nverror.h"
#endif /* !XAPIGEN */
#define NV_ROBUST_CHANNEL_ALLOCFAIL_CLIENT 0x00000001
#define NV_ROBUST_CHANNEL_ALLOCFAIL_DEVICE 0x00000002
#define NV_ROBUST_CHANNEL_ALLOCFAIL_SUBDEVICE 0x00000004
#define NV_ROBUST_CHANNEL_ALLOCFAIL_CHANNEL 0x00000008
#define NV_ROBUST_CHANNEL_ALLOCFAIL_CTXDMA 0x00000010
#define NV_ROBUST_CHANNEL_ALLOCFAIL_EVENT 0x00000020
#define NV_ROBUST_CHANNEL_ALLOCFAIL_MEMORY 0x00000040
#define NV_ROBUST_CHANNEL_ALLOCFAIL_OBJECT 0x00000080
#define NV_ROBUST_CHANNEL_ALLOCFAIL_HEAP 0x00000100
#define NV_ROBUST_CHANNEL_BREAKONERROR_DEFAULT 0x00000000
#define NV_ROBUST_CHANNEL_BREAKONERROR_DISABLE 0x00000001
#define NV_ROBUST_CHANNEL_BREAKONERROR_ENABLE 0x00000002
#endif // NV_DEPRECATED_RM_CONFIG_GET_SET
#endif // _NVCM_H_

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src/common/sdk/nvidia/inc/class/cl0000.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0000_h_
#define _cl0000_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#include "nvlimits.h"
/* object NV01_NULL_OBJECT */
#define NV01_NULL_OBJECT (0x00000000)
/* obsolete alises */
#define NV1_NULL_OBJECT NV01_NULL_OBJECT
/*event values*/
#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0)
#define NV0000_NOTIFIERS_EVENT_NONE_PENDING (1)
#define NV0000_NOTIFIERS_VM_START (2)
#define NV0000_NOTIFIERS_GPU_BIND_EVENT (3)
#define NV0000_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (4)
#define NV0000_NOTIFIERS_MAXCOUNT (5)
/*Status definitions for NV0000_NOTIFIERS_DISPLAY_CHANGE event*/
#define NV0000_NOTIFIERS_STATUS_ACPI_DISPLAY_DEVICE_CYCLE (0)
//---------------------------------------------------------------------------
#define NV01_ROOT (0x00000000)
/* NvNotification[] fields and values */
#define NV000_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* NvAlloc parameteters */
typedef struct {
NvHandle hClient; /* CORERM-2934: hClient must remain the first member until all allocations use these params */
NvU32 processID;
char processName[NV_PROC_NAME_MAX_LENGTH];
} NV0000_ALLOC_PARAMETERS;
/* pio method data structure */
typedef volatile struct _cl0000_tag0 {
NvV32 Reserved00[0x7c0];
} Nv000Typedef, Nv01Root;
/* obsolete aliases */
#define NV000_TYPEDEF Nv01Root
#define Nv1Root Nv01Root
#define nv1Root Nv01Root
#define nv01Root Nv01Root
/*event values*/
#define NV0000_NOTIFIERS_ENABLE_CPU_UTIL_CTRL (1)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0000_h_ */

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src/common/sdk/nvidia/inc/class/cl0001.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0001_h_
#define _cl0001_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV01_ROOT_NON_PRIV (0x00000001)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0001_h_ */

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src/common/sdk/nvidia/inc/class/cl0002.h Normal file
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/*
* Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0002_h_
#define _cl0002_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV01_CONTEXT_DMA_FROM_MEMORY (0x00000002)
/* NvNotification[] fields and values */
#define NV002_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0002_tag0 {
NvV32 Reserved00[0x7c0];
} Nv002Typedef, Nv01ContextDmaFromMemory;
#define NV002_TYPEDEF Nv01ContextDmaFromMemory
/* obsolete stuff */
#define NV1_CONTEXT_DMA_FROM_MEMORY (0x00000002)
#define NV01_CONTEXT_DMA (0x00000002)
#define Nv1ContextDmaFromMemory Nv01ContextDmaFromMemory
#define nv1ContextDmaFromMemory Nv01ContextDmaFromMemory
#define nv01ContextDmaFromMemory Nv01ContextDmaFromMemory
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0002_h_ */

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src/common/sdk/nvidia/inc/class/cl0004.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0004_h_
#define _cl0004_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV01_TIMER (0x00000004)
/* NvNotification[] elements */
#define NV004_NOTIFIERS_SET_ALARM_NOTIFY (0)
#define NV004_NOTIFIERS_MAXCOUNT (1)
/* mapped timer registers */
typedef volatile struct _Nv01TimerMapTypedef {
NvU32 Reserved00[0x100];
NvU32 PTimerTime0; /* 0x00009400 */
NvU32 Reserved01[0x3];
NvU32 PTimerTime1; /* 0x00009410 */
} Nv01TimerMap;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0004_h_ */

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src/common/sdk/nvidia/inc/class/cl0005.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0005_h_
#define _cl0005_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV01_EVENT (0x00000005)
/* NvNotification[] fields and values */
#define NV003_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0005_tag0 {
NvV32 Reserved00[0x7c0];
} Nv005Typedef, Nv01Event;
#define NV005_TYPEDEF Nv01Event
/* obsolete stuff */
#define NV1_TIMER (0x00000004)
#define Nv1Event Nv01Event
#define nv1Event Nv01Event
#define nv01Event Nv01Event
/* NvRmAlloc() parameters */
typedef struct {
NvHandle hParentClient;
NvHandle hSrcResource;
NvV32 hClass;
NvV32 notifyIndex;
NvP64 data NV_ALIGN_BYTES(8);
} NV0005_ALLOC_PARAMETERS;
/* NV0005_ALLOC_PARAMETERS's notifyIndex field is overloaded to contain the
* notifyIndex value itself, plus flags, and optionally a subdevice field if
* flags contains NV01_EVENT_SUBDEVICE_SPECIFIC. Note that NV01_EVENT_*
* contain the full 32-bit flag value that is OR'd into notifyIndex, not the
* contents of the FLAGS field (i.e. NV01_EVENT_* are pre-shifted into place).
*/
#define NV0005_NOTIFY_INDEX_INDEX 15:0
#define NV0005_NOTIFY_INDEX_SUBDEVICE 23:16
#define NV0005_NOTIFY_INDEX_FLAGS 31:24
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0005_h_ */

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src/common/sdk/nvidia/inc/class/cl000f.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl000f_h_
#define _cl000f_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define FABRIC_MANAGER_SESSION (0x0000000F)
#define NV000F_NOTIFIERS_FABRIC_EVENT (0)
#define NV000F_FLAGS_CHANNEL_RECOVERY 0:0
#define NV000F_FLAGS_CHANNEL_RECOVERY_ENABLED 0x0
#define NV000F_FLAGS_CHANNEL_RECOVERY_DISABLED 0x1
typedef struct
{
//
// capDescriptor is a file descriptor for unix RM clients, but a void
// pointer for windows RM clients.
//
// capDescriptor is transparent to RM clients i.e. RM's user-mode shim
// populates this field on behalf of clients.
//
NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8);
NvU32 flags;
} NV000F_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl000f_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0020_h_
#define _cl0020_h_
#include "nvtypes.h"
#define NV0020_GPU_MANAGEMENT (0x00000020)
#endif /* _cl0020_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0030_h_
#define _cl0030_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV01_NULL (0x00000030)
/* NvNotification[] fields and values */
#define NV030_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0030_tag0 {
NvV32 Reserved00[0x7c0];
} Nv030Typedef, Nv01Null;
#define NV030_TYPEDEF Nv01Null
/* obsolete stuff */
#define NV1_NULL (0x00000030)
#define Nv1Null Nv01Null
#define nv1Null Nv01Null
#define nv01Null Nv01Null
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0030_h_ */

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/*
* Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl003e_h_
#define _cl003e_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV01_CONTEXT_ERROR_TO_MEMORY (0x0000003E)
#define NV01_MEMORY_SYSTEM (0x0000003E)
/* NvNotification[] fields and values */
#define NV03E_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl003e_tag0 {
NvV32 Reserved00[0x7c0];
} Nv03eTypedef, Nv01ContextErrorToMemory;
#define NV03E_TYPEDEF Nv01ContextErrorToMemory
/* obsolete stuff */
#define NV1_CONTEXT_ERROR_TO_MEMORY (0x0000003E)
#define Nv1ContextErrorToMemory Nv01ContextErrorToMemory
#define nv1ContextErrorToMemory Nv01ContextErrorToMemory
#define nv01ContextErrorToMemory Nv01ContextErrorToMemory
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl003e_h_ */

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/*
* Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl003f_h_
#define _cl003f_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV01_MEMORY_LOCAL_PRIVILEGED (0x0000003F)
/* NvNotification[] fields and values */
#define NV03F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
#ifndef AMD64
typedef volatile struct _cl003f_tag0 {
#else
typedef struct {
#endif
NvV32 Reserved00[0x7c0];
} Nv01MemoryLocalPrivileged;
#define NV03F_TYPEDEF Nv01MemoryLocalPrivileged
typedef Nv01MemoryLocalPrivileged Nv03fTypedef;
/* obsolete stuff */
#define NV01_MEMORY_PRIVILEGED (0x0000003F)
#define NV1_MEMORY_PRIVILEGED (0x0000003F)
#define Nv01MemoryPrivileged Nv01MemoryLocalPrivileged
#define nv01MemoryPrivileged Nv01MemoryLocalPrivileged
#define Nv1MemoryPrivileged Nv01MemoryLocalPrivileged
#define nv1MemoryPrivileged Nv01MemoryLocalPrivileged
#define nv01MemoryLocalPrivileged Nv01MemoryLocalPrivileged
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl003f_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2001 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0040_h_
#define _cl0040_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV01_MEMORY_LOCAL_USER (0x00000040)
/* NvNotification[] fields and values */
#define NV040_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0040_tag0 {
NvV32 Reserved00[0x7c0];
} Nv040Typedef, Nv01MemoryLocalUser;
#define NV040_TYPEDEF Nv01MemoryLocalUser
/* obsolete stuff */
#define NV01_MEMORY_USER (0x00000040)
#define NV1_MEMORY_USER (0x00000040)
#define Nv01MemoryUser Nv01MemoryLocalUser
#define nv01MemoryUser Nv01MemoryLocalUser
#define Nv1MemoryUser Nv01MemoryLocalUser
#define nv1MemoryUser Nv01MemoryLocalUser
#define nv01MemoryLocalUser Nv01MemoryLocalUser
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0040_h_ */

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/*
* Copyright (c) 2001-2005, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0041_h_
#define _cl0041_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV04_MEMORY (0x00000041)
/* NvNotification[] fields and values */
#define NV041_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0041_tag0 {
NvV32 Reserved00[0x7c0];
} Nv041Typedef, Nv04Memory;
#define NV041_TYPEDEF Nv04Memory;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0041_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#ifndef _cl0060_h_
#define _cl0060_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV0060_SYNC_GPU_BOOST (0x00000060)
/*!
*/
typedef struct {
NvU32 gpuBoostGroupId;
} NV0060_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl0060_h

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/*
* Copyright (c) 2001-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0070_h_
#define _cl0070_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV01_MEMORY_VIRTUAL (0x00000070)
#define NV01_MEMORY_SYSTEM_DYNAMIC (0x00000070)
/*
* NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS
*
* Allocation params for NV01_MEMORY_VIRTUAL.
*
* NV01_MEMORY_SYSTEM_DYNAMIC is an alias for NV01_MEMORY_VIRTUAL. This
* was traditionally allocated with RmAllocMemory64(). The default GPU
* virtual address space is used, and the limit of this address space is
* returned in limit. The NV01_MEMORY_SYSTEM_DYNAMIC handle can be
* passed to RmAllocContextDma2() with an offset/limit. The context dma
* handle can then be used as the hDma handle for RmMapMemoryDma.
*
* This behavior is maintained in the RM compatibility shim.
*
* NV01_MEMORY_VIRTUAL replaces this behavior with a single object.
*
* hVASpace - if hVASpace is NV01_NULL_OBJECT the default GPU VA space is
* selected. Alternatively a FERMI_VASPACE_A handle may be specified.
*
* The NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE is used for by the
* compatibility layer to emulate NV01_MEMORY_SYSTEM_DYNAMIC semantics.
*
* offset - An offset into the virtual address space may be specified. This
* will limit range of the GPU VA returned by RmMapMemoryDma to be
* above offset.
*
* limit - When limit is zero the maximum limit used. If a non-zero limit
* is specified then it will be used. The final limit is returned.
*/
typedef struct
{
NvU64 offset NV_ALIGN_BYTES(8); // [IN] - offset into address space
NvU64 limit NV_ALIGN_BYTES(8); // [IN/OUT] - limit of address space
NvHandle hVASpace; // [IN] - Address space handle
} NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS;
#define NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE (0xffffffffu)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0070_h_ */

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/*
* Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0071_h_
#define _cl0071_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV01_MEMORY_SYSTEM_OS_DESCRIPTOR (0x00000071)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0071_h_ */

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/*
* Copyright (c) 2001-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0073_h_
#define _cl0073_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV04_DISPLAY_COMMON (0x00000073)
/* event values */
#define NV0073_NOTIFIERS_SW (0)
#define NV0073_NOTIFIERS_MAXCOUNT (5)
#define NV0073_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NV0073_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000)
#define NV0073_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000)
#define NV0073_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000)
#define NV0073_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
/* pio method data structure */
typedef volatile struct _cl0073_tag0 {
NvV32 Reserved00[0x7c0];
} Nv073Typedef, Nv04DisplayCommon;
#define NV073_TYPEDEF Nv04DisplayCommon
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0073_h_ */

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/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0076_h_
#define _cl0076_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV01_MEMORY_FRAMEBUFFER_CONSOLE (0x00000076)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0076_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl007d_h_
#define _cl007d_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV04_SOFTWARE_TEST (0x0000007D)
#define NV07D 0x00001fff:0x00000000
/* NvNotification[] elements */
#define NV07D_NOTIFIERS_NOTIFY (0)
#define NV07D_NOTIFIERS_MAXCOUNT (1)
/* NvNotification[] fields and values */
#define NV07D_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NV07D_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
#define NV07D_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
#define NV07D_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x1000)
#define NV07D_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x0800)
#define NV07D_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
/* pio method data structures */
typedef volatile struct _cl007d_tag0 {
NvV32 NoOperation; /* ignored 0100-0103*/
NvV32 Notify; /* NV07D_NOTIFY_* 0104-0107*/
NvV32 Reserved0104[0x78/4];
NvV32 SetContextDmaNotifies; /* NV01_CONTEXT_DMA 0180-0183*/
NvV32 Reserved0184[0x1f7c/4];
} Nv07dTypedef, Nv04SoftwareTest;
#define NV07D_TYPEDEF Nv04SoftwareTest
/* dma method offsets, fields, and values */
#define NV07D_SET_OBJECT (0x00000000)
#define NV07D_NO_OPERATION (0x00000100)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl007d_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0080_h_
#define _cl0080_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvlimits.h"
#include "nvtypes.h"
#define NV01_DEVICE_0 (0x00000080)
/* NvNotification[] fields and values */
#define NV080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0080_tag0 {
NvV32 Reserved00[0x7c0];
} Nv080Typedef, Nv01Device0;
#define NV080_TYPEDEF Nv01Device0
/* NvAlloc parameteters */
#define NV0080_MAX_DEVICES NV_MAX_DEVICES
/**
* @brief Alloc param
*
* @param vaMode mode for virtual address space allocation
* Three modes:
* NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES
* NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE
* NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES
* Detailed description of these modes is in nvos.h
**/
typedef struct {
NvU32 deviceId;
NvHandle hClientShare;
NvHandle hTargetClient;
NvHandle hTargetDevice;
NvV32 flags;
NvU64 vaSpaceSize NV_ALIGN_BYTES(8);
NvU64 vaStartInternal NV_ALIGN_BYTES(8);
NvU64 vaLimitInternal NV_ALIGN_BYTES(8);
NvV32 vaMode;
} NV0080_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0080_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0090_h_
#define _cl0090_h_
#include "nvtypes.h"
#define KERNEL_GRAPHICS_CONTEXT (0x00000090)
#endif /* _cl0090_h_ */

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/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef SDK_CL0092_H
#define SDK_CL0092_H
#include "nvtypes.h"
/*
* This RgLineCallback class allows RM clients to register/unregister the RG line callback functions.
*
* Must be allocated with kernel access rights.
*
* Allocation params:
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the NV04_DISPLAY_COMMON parent device to which the
* operation should be directed.
* head
* This parameter specifies the head for which the callback is to be egistered/unregistered. This value must be
* less than the maximum number of heads supported by the GPU subdevice.
* rgLineNum
* This indicates the RG scanout line number on which the callback will be executed.
* 1/ Client should set the proper RG line number based on mode in which the display head is running and
* subsequent possible modeset that may affect the line number.
* 2/ Client is expected to clear/set the interrupts around modesets or power-transitions (like s3/hibernation).
* 3/ Client should make sure that this param does not exceed the raster settings.
* pCallbkFn
* Pointer to callback function. Cannot be NULL.
* pCallbkParams
* Pointer to the ctrl call param struct.
*/
#define NV0092_RG_LINE_CALLBACK 0x0092
typedef void (*NV0092_REGISTER_RG_LINE_CALLBACK_FN)(NvU32 rgIntrLine, void *param1, NvBool bIsIrqlIsr);
typedef struct
{
NvU32 subDeviceInstance;
NvU32 head;
NvU32 rgLineNum;
NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallbkFn;
void *pCallbkParams;
} NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS;
#endif // SDK_CL0092_H

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/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _CL00B1_H_
#define _CL00B1_H_
#define NV01_MEMORY_HW_RESOURCES 0x00b1
#endif // _CL00B1_H_

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/*
* Copyright (c) 2018-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl00c1_h_
#define _cl00c1_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#include "nvlimits.h"
#define NV_FB_SEGMENT (0x000000C1)
/*
* NV_FB_SEGMENT_ALLOCATION_PARAMS - Allocation params to create FB segment through
* NvRmAlloc.
*/
typedef struct
{
NvHandle hCtxDma;
NvU32 subDeviceIDMask NV_ALIGN_BYTES(8);
NvU64 dmaOffset NV_ALIGN_BYTES(8);
NvU64 VidOffset NV_ALIGN_BYTES(8);
NvU64 Offset NV_ALIGN_BYTES(8); // To be deprecated
NvU64 pOffset[NV_MAX_SUBDEVICES] NV_ALIGN_BYTES(8);
NvU64 Length NV_ALIGN_BYTES(8);
NvU64 ValidLength NV_ALIGN_BYTES(8);
NvP64 pPageArray NV_ALIGN_BYTES(8);
NvU32 startPageIndex;
NvHandle AllocHintHandle;
NvU32 Flags;
NvHandle hMemory; // Not used in NvRmAlloc path; only used in CTRL path
NvHandle hClient; // Not used in NvRmAlloc path; only used in CTRL path
NvHandle hDevice; // Not used in NvRmAlloc path; only used in CTRL path
NvP64 pCpuAddress NV_ALIGN_BYTES(8); // To be deprecated
NvP64 ppCpuAddress[NV_MAX_SUBDEVICES] NV_ALIGN_BYTES(8);
NvU64 GpuAddress NV_ALIGN_BYTES(8); // To be deprecated
NvU64 pGpuAddress[NV_MAX_SUBDEVICES] NV_ALIGN_BYTES(8);
NvHandle hAllocHintClient;
NvU32 kind;
NvU32 compTag;
} NV_FB_SEGMENT_ALLOCATION_PARAMS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl00c1_h_ */

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/*
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl00c2_h_
#define _cl00c2_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV01_MEMORY_LOCAL_PHYSICAL (0x000000c2)
typedef struct
{
NvU64 memSize NV_ALIGN_BYTES(8); // [OUT]
NvU32 format; // [IN] - PTE format to use
NvU32 pageSize; // [IN] - Page size to use
} NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl00c2_h_ */

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/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef SDK_CL00C3_H
#define SDK_CL00C3_H
#include "nvtypes.h"
#define NV01_MEMORY_SYNCPOINT 0x00C3
/*
* NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS - Allocation params to create syncpoint
through NvRmAlloc.
*/
typedef struct
{
NvU32 syncpointId;
} NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS;
#endif // SDK_CL00C3_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl00db_h_
#define _cl00db_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV40_DEBUG_BUFFER (0x000000db)
/* NvRmAlloc() parameters */
typedef struct {
NvU32 size; /* Desired message size / actual size returned */
NvU32 tag; /* Protobuf tag for message location in dump message */
} NV00DB_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl00db_h_ */

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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#ifndef _cl00f2_h_
#define _cl00f2_h_
#ifdef __cplusplus
extern "C" {
#endif
#define IO_VASPACE_A (0x000000f2)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl00f2_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
/*
* Class definition for creating a memory descriptor from a FLA range in RmAllocMemory.
* No memory is allocated, only a memory descriptor and memory object is created
* for later use in other calls. These classes are used by clients who tries to
* import the memory exported by other GPU(s)/FAM/process. The range, size and
* other parameters are passed as Nv01MemoryFla structure.
*/
#ifndef _cl00f3_h_
#define _cl00f3_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV01_MEMORY_FLA (0x000000f3)
/*
* Structure of NV_FLA_MEMORY_ALLOCATION_PARAMS
*
*
*/
typedef struct {
NvU32 type; /* FBMEM: NVOS32_TYPE_* */
NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */
NvU32 attr; /* FBMEM: NVOS32_ATTR_* */
NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */
NvU64 base; /* base of FLA range */
NvU64 align; /* alignment for FLA range*/
NvU64 limit NV_ALIGN_BYTES(8);
//
// For Direct connected systems, clients need to program this hSubDevice with
// the exporting GPU, for RM to route the traffic to the destination GPU
// Clients need not program this for NvSwitch connected systems
//
NvHandle hExportSubdevice; /* hSubdevice of the exporting GPU */
//
// Instead of base and limit, clients can also pass the FLA handle (or hExportHandle)
// being exported from destination side to import on the access side
//
NvHandle hExportHandle; /* FLA handle being exported or Export handle */
// The RM client used to export memory
NvHandle hExportClient;
NvU32 flagsOs02;
} NV_FLA_MEMORY_ALLOCATION_PARAMS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl00f3_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
/*
* Class definition for allocating a contiguous or discontiguous FLA.
*/
#ifndef _cl00f8_h_
#define _cl00f8_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV_MEMORY_FABRIC (0x000000f8)
/*
* alignment [IN]
* Alignment for the allocation.
* Should be at least the requested page size.
*
* allocSize [IN]
* Size of the FLA VA.
*
* pageSize [IN]
* Requested page size. Can be any of the NV_MEMORY_FABRIC_PAGE_SIZE_*
*
* allocFlags [IN]
* Can be any of the NV00F8_ALLOC_FLAGS_*
* DEFAULT (sticky)
* The FLA -> PA mappings will be stuck to the object, i.e, once the mapping is created
* there is no way to unmap it explicitly.
* The FLA object must be destroyed to release the mappings.
* The FLA object can't be duped or exported until it has a mapping associated with it.
* Partial FLA->PA mappings will NOT be allowed.
* FLEXIBLE_FLA
* The FLA -> PA mappings can be modified anytime irrespective of the FLA object is duped
* or exported.
* Partial FLA mappings are allowed.
* FORCE_NONCONTIGUOUS
* The allocator may pick contiguous memory whenever possible. This flag forces the
* allocator to always allocate noncontiguous memory. This flag is mainly used for
* testing purpose. So, use with caution.
* FORCE_CONTIGUOUS
* This flag forces the allocator to always allocate contiguous memory.
* READ_ONLY
* The FLA -> PA mappings will be created read-only. This option is only available on
* debug/develop builds due to security concerns. The security concerns are due to the
* fact that FLA access errors (a.k.a PRIV errors) are not aways context attributable.
*
* map.offset [IN]
* Offset into the physical memory descriptor.
* Must be physical memory page size aligned.
*
* map.hVidMem [IN]
* Handle to the physical video memory. Must be passed when the sticky flag is set so that the
* FLA -> PA mapping can happen during object creation.
* Phys memory with 2MB pages is supported.
* Phys memory handle can be NV01_NULL_OBJECT if FLEXIBLE_FLA flag is passed.
* hVidMem should belong the same device and client which is allocating FLA.
*
* map.flags [IN]
* Reserved for future use.
* Clients should pass 0 as of now.
*/
#define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000
#define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000
#define NV00F8_ALLOC_FLAGS_DEFAULT 0
#define NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA NVBIT(0)
#define NV00F8_ALLOC_FLAGS_FORCE_NONCONTIGUOUS NVBIT(1)
#define NV00F8_ALLOC_FLAGS_FORCE_CONTIGUOUS NVBIT(2)
#define NV00F8_ALLOC_FLAGS_READ_ONLY NVBIT(3)
typedef struct {
NV_DECLARE_ALIGNED(NvU64 alignment, 8);
NV_DECLARE_ALIGNED(NvU64 allocSize, 8);
NvU32 pageSize;
NvU32 allocFlags;
struct {
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NvHandle hVidMem;
NvU32 flags;
} map;
} NV00F8_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl00f8_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#ifndef _cl00fc_h_
#define _cl00fc_h_
#ifdef __cplusplus
extern "C" {
#endif
#define FABRIC_VASPACE_A (0x000000fc)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl00fc_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2002-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl2080_h_
#define _cl2080_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#include "nvlimits.h"
#define NV20_SUBDEVICE_0 (0x00002080)
/* event values */
#define NV2080_NOTIFIERS_SW (0)
#define NV2080_NOTIFIERS_HOTPLUG (1)
#define NV2080_NOTIFIERS_POWER_CONNECTOR (2)
#define NV2080_NOTIFIERS_THERMAL_SW (3)
#define NV2080_NOTIFIERS_THERMAL_HW (4)
#define NV2080_NOTIFIERS_FULL_SCREEN_CHANGE (5)
#define NV2080_NOTIFIERS_EVENTBUFFER (6)
#define NV2080_NOTIFIERS_DP_IRQ (7)
#define NV2080_NOTIFIERS_GR_DEBUG_INTR (8)
#define NV2080_NOTIFIERS_PMU_EVENT (9)
#define NV2080_NOTIFIERS_PMU_COMMAND (10)
#define NV2080_NOTIFIERS_TIMER (11)
#define NV2080_NOTIFIERS_GRAPHICS (12)
#define NV2080_NOTIFIERS_PPP (13)
#define NV2080_NOTIFIERS_VLD (14) // also known as BSP
#define NV2080_NOTIFIERS_NVDEC0 NV2080_NOTIFIERS_VLD
#define NV2080_NOTIFIERS_NVDEC1 (15)
#define NV2080_NOTIFIERS_NVDEC2 (16)
#define NV2080_NOTIFIERS_NVDEC3 (17)
#define NV2080_NOTIFIERS_NVDEC4 (18)
#define NV2080_NOTIFIERS_RESERVED19 (19)
#define NV2080_NOTIFIERS_RESERVED20 (20)
#define NV2080_NOTIFIERS_RESERVED21 (21)
#define NV2080_NOTIFIERS_PDEC (22) // also known as VP
#define NV2080_NOTIFIERS_CE0 (23)
#define NV2080_NOTIFIERS_CE1 (24)
#define NV2080_NOTIFIERS_CE2 (25)
#define NV2080_NOTIFIERS_CE3 (26)
#define NV2080_NOTIFIERS_CE4 (27)
#define NV2080_NOTIFIERS_CE5 (28)
#define NV2080_NOTIFIERS_CE6 (29)
#define NV2080_NOTIFIERS_CE7 (30)
#define NV2080_NOTIFIERS_CE8 (31)
#define NV2080_NOTIFIERS_CE9 (32)
#define NV2080_NOTIFIERS_PSTATE_CHANGE (33)
#define NV2080_NOTIFIERS_HDCP_STATUS_CHANGE (34)
#define NV2080_NOTIFIERS_FIFO_EVENT_MTHD (35)
#define NV2080_NOTIFIERS_PRIV_RING_HANG (36)
#define NV2080_NOTIFIERS_RC_ERROR (37)
#define NV2080_NOTIFIERS_MSENC (38)
#define NV2080_NOTIFIERS_NVENC0 NV2080_NOTIFIERS_MSENC
#define NV2080_NOTIFIERS_NVENC1 (39)
#define NV2080_NOTIFIERS_NVENC2 (40)
#define NV2080_NOTIFIERS_UNUSED_0 (41) // Unused
#define NV2080_NOTIFIERS_ACPI_NOTIFY (42)
#define NV2080_NOTIFIERS_COOLER_DIAG_ZONE (43)
#define NV2080_NOTIFIERS_THERMAL_DIAG_ZONE (44)
#define NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST (45)
#define NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE (46)
#define NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT (47)
#define NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT (48)
#define NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT (49)
#define NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT (50)
#define NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT (51)
#define NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT (52)
#define NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT (53)
#define NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT (54)
#define NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT (55)
#define NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT (56)
#define NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT (57)
#define NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT (58)
#define NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT (59)
#define NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT (60)
#define NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT (61)
#define NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT (62)
#define NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT (63)
#define NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT (64)
#define NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT (65)
#define NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT (66)
#define NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT (67)
#define NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT (68)
#define NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT (69)
#define NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT (70)
#define NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT (71)
#define NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT (72)
#define NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT (73)
#define NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT (74)
#define NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT (75)
#define NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT (76)
#define NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT (77)
#define NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT (78)
#define NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT (79)
#define NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT (80)
#define NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT (81)
#define NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT (82)
#define NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT (83)
#define NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT (84)
#define NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT (85)
#define NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT (86)
#define NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT (87)
#define NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT (88)
#define NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT (89)
#define NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT (90)
#define NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT (91)
#define NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT (92)
#define NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT (93)
#define NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT (94)
#define NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT (95)
#define NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT (96)
#define NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT (97)
#define NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT (98)
#define NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT (99)
#define NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT (100)
#define NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT (101)
#define NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT (102)
#define NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT (103)
#define NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT (104)
#define NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT (105)
#define NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT (106)
#define NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT (107)
#define NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT (108)
#define NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT (109)
#define NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT (110)
#define NV2080_NOTIFIERS_ECC_SBE (111)
#define NV2080_NOTIFIERS_ECC_DBE (112)
#define NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION (113)
#define NV2080_NOTIFIERS_GC5_GPU_READY (114)
#define NV2080_NOTIFIERS_SEC2 (115)
#define NV2080_NOTIFIERS_GC6_REFCOUNT_INC (116)
#define NV2080_NOTIFIERS_GC6_REFCOUNT_DEC (117)
#define NV2080_NOTIFIERS_POWER_EVENT (118)
#define NV2080_NOTIFIERS_CLOCKS_CHANGE (119)
#define NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE (120)
#define NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT (121)
#define NV2080_NOTIFIERS_RESERVED_122 (122)
#define NV2080_NOTIFIERS_NVLINK_ERROR_FATAL (123)
#define NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT (124)
#define NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED (125)
#define NV2080_NOTIFIERS_NVJPG (126)
#define NV2080_NOTIFIERS_NVJPEG0 NV2080_NOTIFIERS_NVJPG
#define NV2080_NOTIFIERS_RESERVED127 (127)
#define NV2080_NOTIFIERS_RESERVED128 (128)
#define NV2080_NOTIFIERS_RESERVED129 (129)
#define NV2080_NOTIFIERS_RESERVED130 (130)
#define NV2080_NOTIFIERS_RESERVED131 (131)
#define NV2080_NOTIFIERS_RESERVED132 (132)
#define NV2080_NOTIFIERS_RESERVED133 (133)
#define NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE (134)
#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE (135)
#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE (136)
#define NV2080_NOTIFIERS_RUNLIST_IDLE (137)
#define NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE (138)
#define NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE (139)
#define NV2080_NOTIFIERS_CTXSW_TIMEOUT (140)
#define NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED (141)
#define NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (142)
#define NV2080_NOTIFIERS_DSTATE_XUSB_PPC (143)
#define NV2080_NOTIFIERS_FECS_CTX_SWITCH (144)
#define NV2080_NOTIFIERS_XUSB_PPC_CONNECTED (145)
#define NV2080_NOTIFIERS_GR0 NV2080_NOTIFIERS_GRAPHICS
#define NV2080_NOTIFIERS_GR1 (146)
#define NV2080_NOTIFIERS_GR2 (147)
#define NV2080_NOTIFIERS_GR3 (148)
#define NV2080_NOTIFIERS_GR4 (149)
#define NV2080_NOTIFIERS_GR5 (150)
#define NV2080_NOTIFIERS_GR6 (151)
#define NV2080_NOTIFIERS_GR7 (152)
#define NV2080_NOTIFIERS_OFA (153)
#define NV2080_NOTIFIERS_DSTATE_HDA (154)
#define NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL (155)
#define NV2080_NOTIFIERS_POISON_ERROR_FATAL (156)
#define NV2080_NOTIFIERS_UCODE_RESET (157)
#define NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE (158)
#define NV2080_NOTIFIERS_SMC_CONFIG_UPDATE (159)
#define NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED (160)
#define NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED (161)
#define NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST (162)
#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163)
#define NV2080_NOTIFIERS_POSSIBLE_ERROR (164)
#define NV2080_NOTIFIERS_MAXCOUNT (165)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x-1)))
#define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7)))
// Indexed CE notifier reference
#define NV2080_NOTIFIERS_CE(x) (NV2080_NOTIFIERS_CE0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_CE(x) (((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9))
// Indexed MSENC notifier reference
#define NV2080_NOTIFIERS_NVENC(x) (NV2080_NOTIFIERS_NVENC0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) (((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2))
// Indexed NVDEC notifier reference
#define NV2080_NOTIFIERS_NVDEC(x) (NV2080_NOTIFIERS_NVDEC0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC4))
// Indexed NVJPEG notifier reference
#define NV2080_NOTIFIERS_NVJPEG(x) (NV2080_NOTIFIERS_NVJPEG0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG0))
#define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT+(pin))
#define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT+(pin))
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
/* exported engine defines */
#define NV2080_ENGINE_TYPE_NULL (0x00000000)
#define NV2080_ENGINE_TYPE_GRAPHICS (0x00000001)
#define NV2080_ENGINE_TYPE_GR0 NV2080_ENGINE_TYPE_GRAPHICS
#define NV2080_ENGINE_TYPE_GR1 (0x00000002)
#define NV2080_ENGINE_TYPE_GR2 (0x00000003)
#define NV2080_ENGINE_TYPE_GR3 (0x00000004)
#define NV2080_ENGINE_TYPE_GR4 (0x00000005)
#define NV2080_ENGINE_TYPE_GR5 (0x00000006)
#define NV2080_ENGINE_TYPE_GR6 (0x00000007)
#define NV2080_ENGINE_TYPE_GR7 (0x00000008)
#define NV2080_ENGINE_TYPE_COPY0 (0x00000009)
#define NV2080_ENGINE_TYPE_COPY1 (0x0000000a)
#define NV2080_ENGINE_TYPE_COPY2 (0x0000000b)
#define NV2080_ENGINE_TYPE_COPY3 (0x0000000c)
#define NV2080_ENGINE_TYPE_COPY4 (0x0000000d)
#define NV2080_ENGINE_TYPE_COPY5 (0x0000000e)
#define NV2080_ENGINE_TYPE_COPY6 (0x0000000f)
#define NV2080_ENGINE_TYPE_COPY7 (0x00000010)
#define NV2080_ENGINE_TYPE_COPY8 (0x00000011)
#define NV2080_ENGINE_TYPE_COPY9 (0x00000012)
#define NV2080_ENGINE_TYPE_BSP (0x00000013)
#define NV2080_ENGINE_TYPE_NVDEC0 NV2080_ENGINE_TYPE_BSP
#define NV2080_ENGINE_TYPE_NVDEC1 (0x00000014)
#define NV2080_ENGINE_TYPE_NVDEC2 (0x00000015)
#define NV2080_ENGINE_TYPE_NVDEC3 (0x00000016)
#define NV2080_ENGINE_TYPE_NVDEC4 (0x00000017)
#define NV2080_ENGINE_TYPE_RESERVED18 (0x00000018)
#define NV2080_ENGINE_TYPE_RESERVED19 (0x00000019)
#define NV2080_ENGINE_TYPE_RESERVED1A (0x0000001a)
#define NV2080_ENGINE_TYPE_MSENC (0x0000001b)
#define NV2080_ENGINE_TYPE_NVENC0 NV2080_ENGINE_TYPE_MSENC /* Mutually exclusive alias */
#define NV2080_ENGINE_TYPE_NVENC1 (0x0000001c)
#define NV2080_ENGINE_TYPE_NVENC2 (0x0000001d)
#define NV2080_ENGINE_TYPE_VP (0x0000001e)
#define NV2080_ENGINE_TYPE_ME (0x0000001f)
#define NV2080_ENGINE_TYPE_PPP (0x00000020)
#define NV2080_ENGINE_TYPE_MPEG (0x00000021)
#define NV2080_ENGINE_TYPE_SW (0x00000022)
#define NV2080_ENGINE_TYPE_CIPHER (0x00000023)
#define NV2080_ENGINE_TYPE_TSEC NV2080_ENGINE_TYPE_CIPHER
#define NV2080_ENGINE_TYPE_VIC (0x00000024)
#define NV2080_ENGINE_TYPE_MP (0x00000025)
#define NV2080_ENGINE_TYPE_SEC2 (0x00000026)
#define NV2080_ENGINE_TYPE_HOST (0x00000027)
#define NV2080_ENGINE_TYPE_DPU (0x00000028)
#define NV2080_ENGINE_TYPE_PMU (0x00000029)
#define NV2080_ENGINE_TYPE_FBFLCN (0x0000002a)
#define NV2080_ENGINE_TYPE_NVJPG (0x0000002b)
#define NV2080_ENGINE_TYPE_NVJPEG0 NV2080_ENGINE_TYPE_NVJPG
#define NV2080_ENGINE_TYPE_RESERVED2C (0x0000002c)
#define NV2080_ENGINE_TYPE_RESERVED2D (0x0000002d)
#define NV2080_ENGINE_TYPE_RESERVED2E (0x0000002e)
#define NV2080_ENGINE_TYPE_RESERVED2F (0x0000002f)
#define NV2080_ENGINE_TYPE_RESERVED30 (0x00000030)
#define NV2080_ENGINE_TYPE_RESERVED31 (0x00000031)
#define NV2080_ENGINE_TYPE_RESERVED32 (0x00000032)
#define NV2080_ENGINE_TYPE_OFA (0x00000033)
#define NV2080_ENGINE_TYPE_LAST (0x00000034)
#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff)
#define NV2080_ENGINE_TYPE_COPY_SIZE 10
#define NV2080_ENGINE_TYPE_NVENC_SIZE 3
#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 1
#define NV2080_ENGINE_TYPE_NVDEC_SIZE 5
#define NV2080_ENGINE_TYPE_GR_SIZE 8
// Indexed engines
#define NV2080_ENGINE_TYPE_COPY(i) (NV2080_ENGINE_TYPE_COPY0+(i))
#define NV2080_ENGINE_TYPE_IS_COPY(i) (((i) >= NV2080_ENGINE_TYPE_COPY0) && ((i) < NV2080_ENGINE_TYPE_COPY(NV2080_ENGINE_TYPE_COPY_SIZE)))
#define NV2080_ENGINE_TYPE_COPY_IDX(i) ((i) - NV2080_ENGINE_TYPE_COPY0)
#define NV2080_ENGINE_TYPE_NVENC(i) (NV2080_ENGINE_TYPE_NVENC0+(i))
#define NV2080_ENGINE_TYPE_IS_NVENC(i) (((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) < NV2080_ENGINE_TYPE_NVENC(NV2080_ENGINE_TYPE_NVENC_SIZE)))
#define NV2080_ENGINE_TYPE_NVENC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVENC0)
#define NV2080_ENGINE_TYPE_NVDEC(i) (NV2080_ENGINE_TYPE_NVDEC0+(i))
#define NV2080_ENGINE_TYPE_IS_NVDEC(i) (((i) >= NV2080_ENGINE_TYPE_NVDEC0) && ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE)))
#define NV2080_ENGINE_TYPE_NVDEC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVDEC0)
#define NV2080_ENGINE_TYPE_NVJPEG(i) (NV2080_ENGINE_TYPE_NVJPEG0+(i))
#define NV2080_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) && ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE)))
#define NV2080_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVJPEG0)
#define NV2080_ENGINE_TYPE_GR(i) (NV2080_ENGINE_TYPE_GR0 + (i))
#define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE)))
#define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0)
#define NV2080_ENGINE_TYPE_IS_VALID(i) (((i) > (NV2080_ENGINE_TYPE_NULL)) && ((i) < (NV2080_ENGINE_TYPE_LAST)))
/* exported client defines */
#define NV2080_CLIENT_TYPE_TEX (0x00000001)
#define NV2080_CLIENT_TYPE_COLOR (0x00000002)
#define NV2080_CLIENT_TYPE_DEPTH (0x00000003)
#define NV2080_CLIENT_TYPE_DA (0x00000004)
#define NV2080_CLIENT_TYPE_FE (0x00000005)
#define NV2080_CLIENT_TYPE_SCC (0x00000006)
#define NV2080_CLIENT_TYPE_WID (0x00000007)
#define NV2080_CLIENT_TYPE_MSVLD (0x00000008)
#define NV2080_CLIENT_TYPE_MSPDEC (0x00000009)
#define NV2080_CLIENT_TYPE_MSPPP (0x0000000a)
#define NV2080_CLIENT_TYPE_VIC (0x0000000b)
#define NV2080_CLIENT_TYPE_ALLCLIENTS (0xffffffff)
/* GC5 Gpu Ready event defines */
#define NV2080_GC5_EXIT_COMPLETE (0x00000001)
#define NV2080_GC5_ENTRY_ABORTED (0x00000002)
/* Platform Power Mode event defines */
#define NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION (0x00000000)
#define NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION (0x00000001)
/* NvNotification[] fields and values */
#define NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl2080_tag0 {
NvV32 Reserved00[0x7c0];
} Nv2080Typedef, Nv20Subdevice0;
#define NV2080_TYPEDEF Nv20Subdevice0
/* NvAlloc parameteters */
#define NV2080_MAX_SUBDEVICES NV_MAX_SUBDEVICES
typedef struct {
NvU32 subDeviceId;
} NV2080_ALLOC_PARAMETERS;
/* HDCP Status change notification information */
typedef struct Nv2080HdcpStatusChangeNotificationRec {
NvU32 displayId;
NvU32 hdcpStatusChangeNotif;
} Nv2080HdcpStatusChangeNotification;
/* Pstate change notification information */
typedef struct Nv2080PStateChangeNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
NvU32 NewPstate;
} Nv2080PStateChangeNotification;
/* Clocks change notification information */
typedef struct Nv2080ClocksChangeNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
} Nv2080ClocksChangeNotification;
/* WorkLoad Modulation state change notification information*/
typedef struct Nv2080WorkloadModulationChangeNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
NvBool WorkloadModulationEnabled;
} Nv2080WorkloadModulationChangeNotification;
/* Hotplug notification information */
typedef struct {
NvU32 plugDisplayMask;
NvU32 unplugDisplayMask;
} Nv2080HotplugNotification;
/* Power state changing notification information */
typedef struct {
NvBool bSwitchToAC;
NvBool bGPUCapabilityChanged;
NvU32 displayMaskAffected;
} Nv2080PowerEventNotification;
/* DP IRQ notification information */
typedef struct Nv2080DpIrqNotificationRec {
NvU32 displayId;
} Nv2080DpIrqNotification;
/* XUSB/PPC D-State change notification information */
typedef struct Nv2080DstateXusbPpcNotificationRec {
NvU32 dstateXusb;
NvU32 dstatePpc;
} Nv2080DstateXusbPpcNotification;
/* XUSB/PPC Connection status notification information */
typedef struct Nv2080XusbPpcConnectStateNotificationRec {
NvBool bConnected;
} Nv2080XusbPpcConnectStateNotification;
/* ACPI event notification information */
typedef struct Nv2080ACPIEvent {
NvU32 event;
} Nv2080ACPIEvent;
/* Cooler Zone notification information */
typedef struct _NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC {
NvU32 currentZone;
} NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC;
/* Thermal Zone notification information */
typedef struct _NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC {
NvU32 currentZone;
} NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC;
/* HDCP ref count change notification information */
typedef struct Nv2080AudioHdcpRequestRec {
NvU32 displayId;
NvU32 requestedState;
} Nv2080AudioHdcpRequest;
/* Gpu ready event information */
typedef struct Nv2080GC5GpuReadyParams {
NvU32 event;
NvU32 sciIntr0;
NvU32 sciIntr1;
} Nv2080GC5GpuReadyParams;
/* Priv reg access fault notification information */
typedef struct {
NvU32 errAddr;
} Nv2080PrivRegAccessFaultNotification;
/* HDA D-State change notification information
* See @HDACODEC_DSTATE for definitions
*/
typedef struct Nv2080DstateHdaCodecNotificationRec {
NvU32 dstateHdaCodec;
} Nv2080DstateHdaCodecNotification;
/*
* Platform Power Mode event information
*/
typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS {
NvU8 platformPowerModeIndex;
NvU8 platformPowerModeMask;
NvU8 eventReason;
} NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS;
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON 23:16
/*
* ENGINE_INFO_TYPE_NV2080 of the engine for which the QOS interrupt has been raised
*/
typedef struct {
NvU32 engineType;
} Nv2080QosIntrNotification;
typedef struct {
NvU64 physAddress NV_ALIGN_BYTES(8);
} Nv2080EccDbeNotification;
/*
* LPWR DIFR Prefetch Request - Size of L2 Cache
*/
typedef struct {
NvU32 l2CacheSize;
} Nv2080LpwrDifrPrefetchNotification;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl2080_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl2081_h_
#define _cl2081_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV2081_BINAPI (0x00002081)
typedef struct{
NvU32 reserved;
}NV2081_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl2082_h_
#define _cl2082_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV2082_BINAPI_PRIVILEGED (0x00002082)
typedef struct{
NvU32 reserved;
}NV2082_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2006 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl208f_h_
#define _cl208f_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
/* Class within the subdevice used for diagnostic purpose*/
#define NV20_SUBDEVICE_DIAG (0x0000208f)
/* event values */
#define NV208F_NOTIFIERS_SW (0)
#define NV208F_NOTIFIERS_MAXCOUNT (1)
/* NvNotification[] fields and values */
#define NV208f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl208f_tag0 {
NvV32 Reserved00[0x7c0];
} Nv208fTypedef, Nv20SubdeviceDiag;
#define NV208f_TYPEDEF Nv20SubdeviceDiag
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl208f_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl30f1_h_
#define _cl30f1_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
/* class NV30_GSYNC */
#define NV30_GSYNC (0x000030F1)
/*
* A client should use NV01_EVENT_OS_EVENT as hClass and NV30F1_GSYNC_NOTIFIERS_* as
* notify index when allocating event, if separate event notifications are needed for
* separate event types.
*
* A client should use NV01_EVENT_KERNEL_CALLBACK as hClass and
* NV30F1_GSYNC_NOTIFIERS_ALL as notify index, if a single event is required.
* In this case RM would set event data equal to a pointer to NvNotification structure.
* The info32 field of NvNotification structure would be equal a bitmask of
* NV30F1_GSYNC_NOTIFIERS_* values.
*/
/* NvNotification[] fields and values */
/* Framelock sync gain and loss events. These are connector specific events. */
#define NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(c) (0x00+(c))
#define NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(c) (0x04+(c))
/* Framelock stereo gain and loss events. These are connector specific events. */
#define NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(c) (0x08+(c))
#define NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(c) (0x0C+(c))
/* House cable gain(plug in) and loss(plug out) events. */
#define NV30F1_GSYNC_NOTIFIERS_HOUSE_GAIN (0x10)
#define NV30F1_GSYNC_NOTIFIERS_HOUSE_LOSS (0x11)
/* RJ45 cable gain(plug in) and loss(plug out) events. */
#define NV30F1_GSYNC_NOTIFIERS_RJ45_GAIN (0x12)
#define NV30F1_GSYNC_NOTIFIERS_RJ45_LOSS (0x13)
#define NV30F1_GSYNC_NOTIFIERS_MAXCOUNT (0x14)
/*
* For handling all event types.
* Note for Windows, it only handles NV01_EVENT_KERNEL_CALLBACK_EX; as for NV01_EVENT_OS_EVENT, it can only
* signal an event but not handle over any information.
*/
#define NV30F1_GSYNC_NOTIFIERS_ALL NV30F1_GSYNC_NOTIFIERS_MAXCOUNT
#define NV30F1_GSYNC_CONNECTOR_ONE (0)
#define NV30F1_GSYNC_CONNECTOR_TWO (1)
#define NV30F1_GSYNC_CONNECTOR_THREE (2)
#define NV30F1_GSYNC_CONNECTOR_FOUR (3)
#define NV30F1_GSYNC_CONNECTOR_PRIMARY NV30F1_GSYNC_CONNECTOR_ONE
#define NV30F1_GSYNC_CONNECTOR_SECONDARY NV30F1_GSYNC_CONNECTOR_TWO
#define NV30F1_GSYNC_CONNECTOR_COUNT (4)
/* NvRmAlloc parameters */
#define NV30F1_MAX_GSYNCS (0x0000004)
typedef struct {
NvU32 gsyncInstance;
} NV30F1_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl30f1_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl402c_h_
#define _cl402c_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
/* I2C operations */
#define NV40_I2C (0x0000402c)
typedef volatile struct _cl402c_tag0 {
NvV32 Reserved00[0x7c0];
} Nv402cTypedef, Nv40I2c;
#define NV402C_TYPEDEF Nv40I2c
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl402c_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl503b_h_
#define _cl503b_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV50_P2P (0x0000503b)
#define NV503B_FLAGS_P2P_TYPE 0:0
#define NV503B_FLAGS_P2P_TYPE_GPA 0
#define NV503B_FLAGS_P2P_TYPE_SPA 1
/* NvRmAlloc parameters */
typedef struct {
NvHandle hSubDevice; /* subDevice handle of local GPU */
NvHandle hPeerSubDevice; /* subDevice handle of peer GPU */
NvU32 subDevicePeerIdMask; /* Bit mask of peer ID for SubDevice
* A value of 0 defaults to RM selected
* PeerIdMasks must match in loopback */
NvU32 peerSubDevicePeerIdMask; /* Bit mask of peer ID for PeerSubDevice
* A value of 0 defaults to RM selected
* PeerIdMasks must match in loopback */
NvU64 mailboxBar1Addr; /* P2P Mailbox area base offset in BAR1
* Must have the same value across the GPUs */
NvU32 mailboxTotalSize; /* Size of the P2P Mailbox area
* Must have the same value across the GPUs */
NvU32 flags; /* Flag to indicate types/attib of p2p */
} NV503B_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl503b_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl503c_h_
#define _cl503c_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV50_THIRD_PARTY_P2P (0x0000503c)
/* NvRmAlloc parameters */
typedef struct {
NvU32 flags;
} NV503C_ALLOC_PARAMETERS;
#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE 1:0
#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_PROPRIETARY (0x00000000)
#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_BAR1 (0x00000001)
#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_NVLINK (0x00000002)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl503c_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl506f_h_
#define _cl506f_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
/* class NV50_CHANNEL_GPFIFO */
#define NV50_CHANNEL_GPFIFO (0x0000506F)
/* NvNotification[] elements */
#define NV506F_NOTIFIERS_RC (0)
#define NV506F_NOTIFIERS_SW (1)
#define NV506F_NOTIFIERS_GR_DEBUG_INTR (2)
#define NV506F_NOTIFIERS_MAXCOUNT (3)
/* NvNotification[] fields and values */
#define NV506f_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
#define NV506f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl506f_tag0 {
NvV32 Reserved00[0x7c0];
} Nv506fTypedef, Nv50ChannelGPFifo;
#define NV506F_TYPEDEF Nv50ChannelGPFifo
/* pio flow control data structure */
typedef volatile struct _cl506f_tag1 {
NvU32 Ignored00[0x010]; /* 0000-0039*/
NvU32 Put; /* put offset, read/write 0040-0043*/
NvU32 Get; /* get offset, read only 0044-0047*/
NvU32 Reference; /* reference value, read only 0048-004b*/
NvU32 PutHi; /* high order put offset bits 004c-004f*/
NvU32 SetReference; /* set reference value 0050-0053*/
NvU32 Ignored02[0x001]; /* 0054-0057*/
NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
NvU32 GetHi; /* high order get offset bits 0060-0063*/
NvU32 Ignored03[0x007]; /* 0064-007f*/
NvU32 Yield; /* engine yield, write only 0080-0083*/
NvU32 Ignored04[0x001]; /* 0084-0087*/
NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
NvU32 Ignored05[0x3dc];
} Nv506fControl, Nv50ControlGPFifo;
/* fields and values */
#define NV506F_NUMBER_OF_SUBCHANNELS (8)
#define NV506F_SET_OBJECT (0x00000000)
#define NV506F_SET_REFERENCE (0x00000050)
#define NV506F_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
#define NV506F_SEMAPHORE_OFFSET (0x00000064)
#define NV506F_SEMAPHORE_ACQUIRE (0x00000068)
#define NV506F_SEMAPHORE_RELEASE (0x0000006c)
#define NV506F_YIELD (0x00000080)
//
// GPFIFO entry format
//
#define NV506F_GP_ENTRY__SIZE 8
#define NV506F_GP_ENTRY0_DISABLE 0:0
#define NV506F_GP_ENTRY0_DISABLE_NOT 0x00000000
#define NV506F_GP_ENTRY0_DISABLE_SKIP 0x00000001
#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH 1:1
#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH_FALSE 0x00000000
#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH_TRUE 0x00000001
#define NV506F_GP_ENTRY0_GET 31:2
#define NV506F_GP_ENTRY1_GET_HI 7:0
#define NV506F_GP_ENTRY1_PRIV 8:8
#define NV506F_GP_ENTRY1_PRIV_USER 0x00000000
#define NV506F_GP_ENTRY1_PRIV_KERNEL 0x00000001
#define NV506F_GP_ENTRY1_LEVEL 9:9
#define NV506F_GP_ENTRY1_LEVEL_MAIN 0x00000000
#define NV506F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
#define NV506F_GP_ENTRY1_LENGTH 31:10
/* dma method descriptor formats */
#define NV506F_DMA_PRIMARY_OPCODE 1:0
#define NV506F_DMA_PRIMARY_OPCODE_USES_SECONDARY (0x00000000)
#define NV506F_DMA_PRIMARY_OPCODE_RESERVED (0x00000003)
#define NV506F_DMA_METHOD_ADDRESS 12:2
#define NV506F_DMA_METHOD_SUBCHANNEL 15:13
#define NV506F_DMA_TERT_OP 17:16
#define NV506F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
#define NV506F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
#define NV506F_DMA_TERT_OP_GRP0_DOUBLE_HEADER (0x00000003)
#define NV506F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
#define NV506F_DMA_TERT_OP_GRP2_RESERVED01 (0x00000001)
#define NV506F_DMA_TERT_OP_GRP2_RESERVED10 (0x00000002)
#define NV506F_DMA_TERT_OP_GRP2_RESERVED11 (0x00000003)
#define NV506F_DMA_METHOD_COUNT 28:18
#define NV506F_DMA_SEC_OP 31:29
#define NV506F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
#define NV506F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
#define NV506F_DMA_SEC_OP_GRP3_RESERVED (0x00000003)
#define NV506F_DMA_SEC_OP_GRP4_RESERVED (0x00000004)
#define NV506F_DMA_SEC_OP_GRP5_RESERVED (0x00000005)
#define NV506F_DMA_SEC_OP_GRP6_RESERVED (0x00000006)
#define NV506F_DMA_SEC_OP_GRP7_RESERVED (0x00000007)
#define NV506F_DMA_LONG_COUNT 31:0
/* dma legacy method descriptor format */
#define NV506F_DMA_OPCODE2 1:0
#define NV506F_DMA_OPCODE2_NONE (0x00000000)
#define NV506F_DMA_OPCODE 31:29
#define NV506F_DMA_OPCODE_METHOD (0x00000000)
#define NV506F_DMA_OPCODE_NONINC_METHOD (0x00000002)
#define NV506F_DMA_OPCODE3_NONE (0x00000000)
/* dma data format */
#define NV506F_DMA_DATA 31:0
/* dma double header descriptor format */
#define NV506F_DMA_DH_OPCODE2 1:0
#define NV506F_DMA_DH_OPCODE2_NONE (0x00000000)
#define NV506F_DMA_DH_METHOD_ADDRESS 12:2
#define NV506F_DMA_DH_METHOD_SUBCHANNEL 15:13
#define NV506F_DMA_DH_OPCODE3 17:16
#define NV506F_DMA_DH_OPCODE3_DOUBLE_HEADER (0x00000003)
#define NV506F_DMA_DH_OPCODE 31:29
#define NV506F_DMA_DH_OPCODE_METHOD (0x00000000)
/* dma double header method count format */
#define NV506F_DMA_DH_METHOD_COUNT 23:0
/* dma double header data format */
#define NV506F_DMA_DH_DATA 31:0
/* dma nop format */
#define NV506F_DMA_NOP (0x00000000)
/* dma set subdevice mask format */
#define NV506F_DMA_SET_SUBDEVICE_MASK (0x00010000)
#define NV506F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
#define NV506F_DMA_OPCODE3 17:16
#define NV506F_DMA_OPCODE3_SET_SUBDEVICE_MASK (0x00000001)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl506f_h_ */

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/*
* Copyright (c) 1993-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl5070_h_
#define _cl5070_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV50_DISPLAY (0x00005070)
/* event values */
#define NV5070_NOTIFIERS_SW (0)
#define NV5070_NOTIFIERS_MAXCOUNT (1)
#define NV5070_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NV5070_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000)
#define NV5070_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000)
#define NV5070_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000)
#define NV5070_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV5070_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl5070_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2002 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl5080_h_
#define _cl5080_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV50_DEFERRED_API_CLASS (0x00005080)
/* NvRmAlloc parameters */
typedef struct {
// Should the deferred api completion trigger an event
NvBool notifyCompletion;
} NV5080_ALLOC_PARAMS;
/* dma method offsets, fields, and values */
#define NV5080_SET_OBJECT (0x00000000)
#define NV5080_NO_OPERATION (0x00000100)
#define NV5080_DEFERRED_API (0x00000200)
#define NV5080_DEFERRED_API_HANDLE 31:0
// Class-specific allocation capabilities
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl5080_h_ */

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/*
* Copyright (c) 2005, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl50a0_h_
#define _cl50a0_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV50_MEMORY_VIRTUAL (0x000050a0)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl50a0_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl83de_h_
#define _cl83de_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define GT200_DEBUGGER (0x000083de)
/*
* Creating the GT200_DEBUGGER object:
* - The debug object is instantiated as a child of either the compute or the
* 3D-class object.
* - The Cuda/GR debugger uses the NV83DE_ALLOC_PARAMETERS to fill in the Client
* and 3D-Class handles of the debuggee and passes this to the NvRmAlloc.
* e.g:
NV83DE_ALLOC_PARAMETERS params;
* memset (&params, 0, sizeof (NV83DE_ALLOC_PARAMETERS));
* params.hAppClient = DebuggeeClient;
* params.hClass3dObject = 3DClassHandle;
* NvRmAlloc(hDebuggerClient, hDebuggerClient, hDebugger, GT200_DEBUGGER, &params);
*/
typedef struct {
NvHandle hDebuggerClient_Obsolete; // No longer supported (must be zero)
NvHandle hAppClient;
NvHandle hClass3dObject;
} NV83DE_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl83de_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl844c_h_
#define _cl844c_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define G84_PERFBUFFER (0x0000844C)
/* pio method data structure */
typedef volatile struct _cl844c_tag0 {
NvV32 Reserved00[0x7c0];
} G844cTypedef, G84PerfBuffer;
#define G844C_TYPEDEF G84PerfBuffer
#define G844C_PERFBUFFER_MEMORY_HANDLE (0x844C0001)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl844c_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl84A0_h_
#define _cl84A0_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
/*
* Class definitions for creating a memory descriptor from a list of page numbers
* in RmAllocMemory. No memory is allocated: only a memory descriptor and
* memory object are created for later use in other calls. These classes
* are used by vGPU to create references to memory assigned to a guest VM.
* In all cases, the list is passed as reference, in the pAddress argument
* of RmAllocMemory, to a Nv01MemoryList structure (cast to a void **).
*/
/* List of system memory physical page numbers */
#define NV01_MEMORY_LIST_SYSTEM (0x00000081)
/* List of frame buffer physical page numbers */
#define NV01_MEMORY_LIST_FBMEM (0x00000082)
/* List of page numbers relative to the start of the specified object */
#define NV01_MEMORY_LIST_OBJECT (0x00000083)
/*
* List structure of NV01_MEMORY_LIST_* classes
*
* The pageNumber array is variable in length, with pageCount elements,
* so the allocated size of the structure must reflect that.
*
* FBMEM items apply only to NV01_MEMORY_LIST_FBMEM and to
* NV01_MEMORY_LIST_OBJECT when the underlying object is
* FBMEM (must be zero for other cases)
*
* Nv01MemoryList is deprecated. NV_MEMORY_LIST_ALLOCATION_PARAMS should be used
* instead.
*/
typedef struct Nv01MemoryListRec {
NvHandle hClient; /* client to which object belongs
* (may differ from client creating the mapping).
* May be NV01_NULL_OBJECT, in which case client
* handle is used */
NvHandle hParent; /* device with which object is associated.
* Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT.
* Must not be NV01_NULL_OBJECT if hClient is
* not NV01_NULL_OBJECT. */
NvHandle hObject; /* object to which pages are relative
* (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM
* and NV01_MEMORY_LIST_FBMEM) */
NvHandle hHwResClient;/* client associated with the backdoor vnc surface*/
NvHandle hHwResDevice;/* device associated to the bacdoor vnc surface*/
NvHandle hHwResHandle;/* handle to hardware resources allocated to
* backdoor vnc surface*/
NvU32 pteAdjust; /* offset of data in first page */
NvU32 type; /* FBMEM: NVOS32_TYPE_* */
NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */
NvU32 attr; /* FBMEM: NVOS32_ATTR_* */
NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */
NvU32 height; /* FBMEM: height in pixels */
NvU32 width; /* FBMEM: width in pixels */
NvU32 format; /* FBMEM: memory kind */
NvU32 comprcovg; /* FBMEM: compression coverage */
NvU32 zcullcovg; /* FBMEM: Z-cull coverage */
NvU32 pageCount; /* count of elements in pageNumber array */
NvU32 heapOwner; /* heap owner information from client */
NvU32 reserved_1; /* reserved: must be 0 */
NvU64 NV_DECLARE_ALIGNED(guestId,8);
/* ID of the guest VM. e.g., domain ID in case of Xen */
NvU64 NV_DECLARE_ALIGNED(rangeBegin,8);
/* preferred VA range start address */
NvU64 NV_DECLARE_ALIGNED(rangeEnd,8);
/* preferred VA range end address */
NvU32 pitch;
NvU32 ctagOffset;
NvU64 size;
NvU64 align;
NvU64 pageNumber[1]; /* variable length array of page numbers */
} Nv01MemoryList;
/*
* NV_MEMORY_LIST_ALLOCATION_PARAMS - Allocation params to create memory list
* through NvRmAlloc.
*/
typedef struct
{
NvHandle hClient; /* client to which object belongs
* (may differ from client creating the mapping).
* May be NV01_NULL_OBJECT, in which case client
* handle is used */
NvHandle hParent; /* device with which object is associated.
* Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT.
* Must not be NV01_NULL_OBJECT if hClient is
* not NV01_NULL_OBJECT. */
NvHandle hObject; /* object to which pages are relative
* (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM
* and NV01_MEMORY_LIST_FBMEM) */
NvHandle hHwResClient;/* client associated with the backdoor vnc surface*/
NvHandle hHwResDevice;/* device associated to the bacdoor vnc surface*/
NvHandle hHwResHandle;/* handle to hardware resources allocated to
* backdoor vnc surface*/
NvU32 pteAdjust; /* offset of data in first page */
NvU32 reserved_0; /* reserved: must be 0 */
NvU32 type; /* FBMEM: NVOS32_TYPE_* */
NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */
NvU32 attr; /* FBMEM: NVOS32_ATTR_* */
NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */
NvU32 height; /* FBMEM: height in pixels */
NvU32 width; /* FBMEM: width in pixels */
NvU32 format; /* FBMEM: memory kind */
NvU32 comprcovg; /* FBMEM: compression coverage */
NvU32 zcullcovg; /* FBMEM: Z-cull coverage */
NvU32 pageCount; /* count of elements in pageNumber array */
NvU32 heapOwner; /* heap owner information from client */
NvU64 NV_DECLARE_ALIGNED(guestId,8);
/* ID of the guest VM. e.g., domain ID in case of Xen */
NvU64 NV_DECLARE_ALIGNED(rangeBegin,8);
/* preferred VA range start address */
NvU64 NV_DECLARE_ALIGNED(rangeEnd,8);
/* preferred VA range end address */
NvU32 pitch;
NvU32 ctagOffset;
NvU64 size;
NvU64 align;
NvP64 pageNumberList NV_ALIGN_BYTES(8);
NvU64 limit NV_ALIGN_BYTES(8);
NvU32 flagsOs02;
} NV_MEMORY_LIST_ALLOCATION_PARAMS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl84A0_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#ifndef _cl85b5sw_h_
#define _cl85b5sw_h_
#ifdef __cplusplus
extern "C" {
#endif
/* This file is *not* auto-generated. */
typedef struct
{
NvU32 version; // set to 0
NvU32 engineInstance; // CE instance
} NV85B5_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl85b5sw_h_

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/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl900e_h_
#define _cl900e_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define MPS_COMPUTE (0x0000900E)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl900e_h_ */

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/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef SDK_CL9010_H
#define SDK_CL9010_H
#include "nvtypes.h"
#define NV9010_VBLANK_CALLBACK 0x9010
typedef void (*OSVBLANKCALLBACKPROC)(void * pParm1, void * pParm2);
typedef struct
{
OSVBLANKCALLBACKPROC pProc; // Routine to call at vblank time
NvV32 LogicalHead; // Logical Head
void *pParm1; // pParm1
void *pParm2; // pParm2
} NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS;
#endif // SDK_CL9010_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#ifndef _cl9067_h_
#define _cl9067_h_
#ifdef __cplusplus
extern "C" {
#endif
#define FERMI_CONTEXT_SHARE_A (0x00009067)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl9067_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl906f_h_
#define _cl906f_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
/* class GF100_CHANNEL_GPFIFO */
/*
* Documentation for GF100_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
* chapter "User Control Registers". It is documented as device NV_UDMA.
* The GPFIFO format itself is also documented in dev_pbdma.ref,
* NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
* chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
*
*/
#define GF100_CHANNEL_GPFIFO (0x0000906F)
/* pio method data structure */
typedef volatile struct _cl906f_tag0 {
NvV32 Reserved00[0x7c0];
} Nv906fTypedef, GF100ChannelGPFifo;
#define NV906F_TYPEDEF GF100ChannelGPFifo
/* dma flow control data structure */
typedef volatile struct _cl906f_tag1 {
NvU32 Ignored00[0x010]; /* 0000-0043*/
NvU32 Put; /* put offset, read/write 0040-0043*/
NvU32 Get; /* get offset, read only 0044-0047*/
NvU32 Reference; /* reference value, read only 0048-004b*/
NvU32 PutHi; /* high order put offset bits 004c-004f*/
NvU32 SetReferenceThreshold; /* set reference value threshold 0050-0053*/
NvU32 Ignored01[0x001]; /* 0054-0057*/
NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
NvU32 GetHi; /* high order get offset bits 0060-0063*/
NvU32 Ignored02[0x007]; /* 0064-007f*/
NvU32 Ignored03; /* used to be engine yield 0080-0083*/
NvU32 Ignored04[0x001]; /* 0084-0087*/
NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
NvU32 Ignored05[0x3dc];
} Nv906fControl, GF100ControlGPFifo;
/* fields and values */
#define NV906F_NUMBER_OF_SUBCHANNELS (8)
#define NV906F_SET_OBJECT (0x00000000)
#define NV906F_SET_OBJECT_NVCLASS 15:0
#define NV906F_SET_OBJECT_ENGINE 20:16
#define NV906F_SET_OBJECT_ENGINE_SW 0x0000001f
#define NV906F_ILLEGAL (0x00000004)
#define NV906F_ILLEGAL_HANDLE 31:0
#define NV906F_NOP (0x00000008)
#define NV906F_NOP_HANDLE 31:0
#define NV906F_SEMAPHOREA (0x00000010)
#define NV906F_SEMAPHOREA_OFFSET_UPPER 7:0
#define NV906F_SEMAPHOREB (0x00000014)
#define NV906F_SEMAPHOREB_OFFSET_LOWER 31:2
#define NV906F_SEMAPHOREC (0x00000018)
#define NV906F_SEMAPHOREC_PAYLOAD 31:0
#define NV906F_SEMAPHORED (0x0000001C)
#define NV906F_SEMAPHORED_OPERATION 3:0
#define NV906F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
#define NV906F_SEMAPHORED_OPERATION_RELEASE 0x00000002
#define NV906F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
#define NV906F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
#define NV906F_SEMAPHORED_ACQUIRE_SWITCH 12:12
#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
#define NV906F_SEMAPHORED_RELEASE_WFI 20:20
#define NV906F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
#define NV906F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
#define NV906F_SEMAPHORED_RELEASE_SIZE 24:24
#define NV906F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
#define NV906F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
#define NV906F_NON_STALL_INTERRUPT (0x00000020)
#define NV906F_NON_STALL_INTERRUPT_HANDLE 31:0
#define NV906F_FB_FLUSH (0x00000024)
#define NV906F_FB_FLUSH_HANDLE 31:0
#define NV906F_MEM_OP_A (0x00000028)
#define NV906F_MEM_OP_A_OPERAND_LOW 31:2
#define NV906F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2
#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30
#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000
#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002
#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003
#define NV906F_MEM_OP_B (0x0000002c)
#define NV906F_MEM_OP_B_OPERAND_HIGH 7:0
#define NV906F_MEM_OP_B_OPERATION 31:27
#define NV906F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005
#define NV906F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006
#define NV906F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009
#define NV906F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
#define NV906F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
#define NV906F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
#define NV906F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010
#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0
#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000
#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001
#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1
#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000
#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001
#define NV906F_SET_REFERENCE (0x00000050)
#define NV906F_SET_REFERENCE_COUNT 31:0
#define NV906F_CRC_CHECK (0x0000007c)
#define NV906F_CRC_CHECK_VALUE 31:0
#define NV906F_YIELD (0x00000080)
#define NV906F_YIELD_OP 1:0
#define NV906F_YIELD_OP_NOP 0x00000000
/* GPFIFO entry format */
#define NV906F_GP_ENTRY__SIZE 8
#define NV906F_GP_ENTRY0_FETCH 0:0
#define NV906F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
#define NV906F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH 1:1
#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH_FALSE 0x00000000
#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH_TRUE 0x00000001
#define NV906F_GP_ENTRY0_GET 31:2
#define NV906F_GP_ENTRY0_OPERAND 31:0
#define NV906F_GP_ENTRY1_GET_HI 7:0
#define NV906F_GP_ENTRY1_PRIV 8:8
#define NV906F_GP_ENTRY1_PRIV_USER 0x00000000
#define NV906F_GP_ENTRY1_PRIV_KERNEL 0x00000001
#define NV906F_GP_ENTRY1_LEVEL 9:9
#define NV906F_GP_ENTRY1_LEVEL_MAIN 0x00000000
#define NV906F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
#define NV906F_GP_ENTRY1_LENGTH 30:10
#define NV906F_GP_ENTRY1_SYNC 31:31
#define NV906F_GP_ENTRY1_SYNC_PROCEED 0x00000000
#define NV906F_GP_ENTRY1_SYNC_WAIT 0x00000001
#define NV906F_GP_ENTRY1_OPCODE 7:0
#define NV906F_GP_ENTRY1_OPCODE_NOP 0x00000000
#define NV906F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
#define NV906F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
#define NV906F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
/* dma method formats */
#define NV906F_DMA_METHOD_ADDRESS_OLD 12:2
#define NV906F_DMA_METHOD_ADDRESS 11:0
#define NV906F_DMA_SUBDEVICE_MASK 15:4
#define NV906F_DMA_METHOD_SUBCHANNEL 15:13
#define NV906F_DMA_TERT_OP 17:16
#define NV906F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
#define NV906F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
#define NV906F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
#define NV906F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
#define NV906F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
#define NV906F_DMA_METHOD_COUNT_OLD 28:18
#define NV906F_DMA_METHOD_COUNT 28:16
#define NV906F_DMA_IMMD_DATA 28:16
#define NV906F_DMA_SEC_OP 31:29
#define NV906F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
#define NV906F_DMA_SEC_OP_INC_METHOD (0x00000001)
#define NV906F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
#define NV906F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
#define NV906F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
#define NV906F_DMA_SEC_OP_ONE_INC (0x00000005)
#define NV906F_DMA_SEC_OP_RESERVED6 (0x00000006)
#define NV906F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
/* dma incrementing method format */
#define NV906F_DMA_INCR_ADDRESS 11:0
#define NV906F_DMA_INCR_SUBCHANNEL 15:13
#define NV906F_DMA_INCR_COUNT 28:16
#define NV906F_DMA_INCR_OPCODE 31:29
#define NV906F_DMA_INCR_OPCODE_VALUE (0x00000001)
#define NV906F_DMA_INCR_DATA 31:0
/* dma non-incrementing method format */
#define NV906F_DMA_NONINCR_ADDRESS 11:0
#define NV906F_DMA_NONINCR_SUBCHANNEL 15:13
#define NV906F_DMA_NONINCR_COUNT 28:16
#define NV906F_DMA_NONINCR_OPCODE 31:29
#define NV906F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
#define NV906F_DMA_NONINCR_DATA 31:0
/* dma increment-once method format */
#define NV906F_DMA_ONEINCR_ADDRESS 11:0
#define NV906F_DMA_ONEINCR_SUBCHANNEL 15:13
#define NV906F_DMA_ONEINCR_COUNT 28:16
#define NV906F_DMA_ONEINCR_OPCODE 31:29
#define NV906F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
#define NV906F_DMA_ONEINCR_DATA 31:0
/* dma no-operation format */
#define NV906F_DMA_NOP (0x00000000)
/* dma immediate-data format */
#define NV906F_DMA_IMMD_ADDRESS 11:0
#define NV906F_DMA_IMMD_SUBCHANNEL 15:13
#define NV906F_DMA_IMMD_DATA 28:16
#define NV906F_DMA_IMMD_OPCODE 31:29
#define NV906F_DMA_IMMD_OPCODE_VALUE (0x00000004)
/* dma set sub-device mask format */
#define NV906F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
#define NV906F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
#define NV906F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
/* dma store sub-device mask format */
#define NV906F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
#define NV906F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
#define NV906F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
/* dma use sub-device mask format */
#define NV906F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
#define NV906F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
/* dma end-segment format */
#define NV906F_DMA_ENDSEG_OPCODE 31:29
#define NV906F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
/* dma legacy incrementing/non-incrementing formats */
#define NV906F_DMA_ADDRESS 12:2
#define NV906F_DMA_SUBCH 15:13
#define NV906F_DMA_OPCODE3 17:16
#define NV906F_DMA_OPCODE3_NONE (0x00000000)
#define NV906F_DMA_COUNT 28:18
#define NV906F_DMA_OPCODE 31:29
#define NV906F_DMA_OPCODE_METHOD (0x00000000)
#define NV906F_DMA_OPCODE_NONINC_METHOD (0x00000002)
#define NV906F_DMA_DATA 31:0
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl906f_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl906f_sw_h_
#define _cl906f_sw_h_
/* NvNotification[] elements */
#define NV906F_NOTIFIERS_RC (0)
#define NV906F_NOTIFIERS_REFCNT (1)
#define NV906F_NOTIFIERS_NONSTALL (2)
#define NV906F_NOTIFIERS_EVENTBUFFER (3)
#define NV906F_NOTIFIERS_IDLECHANNEL (4)
#define NV906F_NOTIFIERS_ENDCTX (5)
#define NV906F_NOTIFIERS_SW (6)
#define NV906F_NOTIFIERS_GR_DEBUG_INTR (7)
#define NV906F_NOTIFIERS_MAXCOUNT (8)
/* NvNotification[] fields and values */
#define NV906f_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
#define NV906f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
#endif /* _cl906f_sw_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9072_h_
#define _cl9072_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define GF100_DISP_SW 0x00009072
#define NV9072_NOTIFIERS_NOTIFY_ON_VBLANK (9)
#define NV9072_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
typedef struct
{
NvU32 logicalHeadId;
/*
* 0 implies use Head argument only (i.e. whatever is currently setup on this head)
*/
NvU32 displayMask;
NvU32 caps;
} NV9072_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9072_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9074_h_
#define _cl9074_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define GF100_TIMED_SEMAPHORE_SW (0x00009074)
/* NvNotification[] fields and values */
#define NV9074_NOTIFICATION_STATUS_PENDING (0x8000)
#define NV9074_NOTIFICATION_STATUS_DONE_FLUSHED (0x0001)
#define NV9074_NOTIFICATION_STATUS_DONE (0x0000)
#define NV9074_SET_NOTIFIER_HI_V 7:0
#define NV9074_SET_SEMAPHORE_HI_V 7:0
#define NV9074_SCHEDULE_SEMAPHORE_RELEASE_NOTIFY 1:0
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9074_h_ */

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/*
* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl907d_sw_spare_h_
#define _cl907d_sw_spare_h_
/* This file is *not* auto-generated. */
#define NV907D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF 1:0
#define NV907D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_NO_PREF (0x00000000)
#define NV907D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_GSYNC (0x00000001)
#define NV907D_PIOR_SET_SW_SPARE_A_CODE_FOR_LOCK_SIGNAL_PROPAGATION_ONLY 1:0
#define NV907D_PIOR_SET_SW_SPARE_A_CODE_FOR_LOCK_SIGNAL_PROPAGATION_ONLY_FALSE (0x00000000)
#define NV907D_PIOR_SET_SW_SPARE_A_CODE_FOR_LOCK_SIGNAL_PROPAGATION_ONLY_TRUE (0x00000001)
#endif // _cl907d_sw_spare_h_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9096_h_
#define _cl9096_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define GF100_ZBC_CLEAR (0x00009096)
#define NV9096_TYPEDEF GF100ZBCClear
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9096_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl90cc_h_
#define _cl90cc_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define GF100_PROFILER (0x000090CC)
/*
* Creating the GF100_PROFILER object:
* - The profiler object is instantiated as a child of either the subdevice or
* a channel group or channel, depending on whether reservations
* should be global to the subdevice or per-context. When the profiler
* requests a reservation or information about outstanding reservations, the
* scope of the request is determined by the profiler object's parent class.
*/
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl90cc_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl90cd_h_
#define _cl90cd_h_
#ifdef __cplusplus
extern "C" {
#endif
/*
* NV_EVENT_BUFFER
* An event buffer is shared between user (RO) and kernel(RW).
* It holds debug/profile event data provided by the kernel.
*
*/
#define NV_EVENT_BUFFER (0x000090CD)
/*
* NV_EVENT_BUFFER_HEADER
* This structure holds the get and put values used to index/consume event buffer.
* Along with other RO data shared with the user.
*
* recordGet/Put: These "pointers" work in the traditional sense:
* - when GET==PUT, the fifo is empty
* - when GET==PUT+1, the fifo is full
* This implies a full fifo always has one "wasted" element.
*
* recordCount: This is the total number of records added to the buffer by the kernel
* This information is filled out when the buffer is setup to keep newest records.
* recordCount = number of records currently in the buffer + overflow count.
*
* recordDropcount: This is the number of event records that are dropped because the
* buffer is full.
* This information is filled out when event buffer is setup to keep oldest records.
*
* vardataDropcount: Event buffer provides a dual stream of data, where the record can contain
* an optional offset to a variable length data buffer.
* This is the number of variable data records that are dropped because the
* buffer is full.
* This information is filled out when event buffer is setup to keep oldest records.
*/
typedef struct
{
NvU32 recordGet;
NvU32 recordPut;
NvU64 recordCount;
NvU64 recordDropcount;
NvU64 vardataDropcount;
} NV_EVENT_BUFFER_HEADER;
/*
* NV_EVENT_BUFFER_RECORD_HEADER
* This is the header added to each event record.
* This helps identify the event type and variable length data is associated with it.
*/
typedef struct
{
NvU16 type;
NvU16 subtype;
NvU32 varData; // [31: 5] = (varDataOffset >> 5); 0 < vardataOffset <= vardataBufferSize
// [ 4: 1] = reserved for future use
// [ 0: 0] = isVardataStartOffsetZero
} NV_EVENT_BUFFER_RECORD_HEADER;
/*
* NV_EVENT_BUFFER_RECORD
* This structure defines a generic event record.
* The size of this record is fixed for a given event buffer.
* It is configured by the user during allocation.
*/
typedef struct
{
NV_EVENT_BUFFER_RECORD_HEADER recordHeader;
NvU64 inlinePayload[1] NV_ALIGN_BYTES(8); // 1st element of the payload/data
// Do not add more elements here, inlinePayload can contain more than one elements
} NV_EVENT_BUFFER_RECORD;
#define NV_EVENT_VARDATA_GRANULARITY 32
#define NV_EVENT_VARDATA_OFFSET_MASK (~(NV_EVENT_VARDATA_GRANULARITY - 1))
#define NV_EVENT_VARDATA_START_OFFSET_ZERO 0x01
/*
* NV_EVENT_BUFFER_ALLOC_PARAMETERS
*
* bufferHeader [OUT]
* This is the user VA offset pointing to the base of NV_EVENT_BUFFER_HEADER.
*
* recordBuffer [OUT]
* This is the user VA offset pointing to the base of the event record buffer.
* This buffer will contain NV_EVENT_BUFFER_RECORDs added by the kernel.
*
* recordSize [IN]
* This is the size of NV_EVENT_BUFFER_RECORD used by this buffer
*
* recordCount [IN]
* This is the number of records that recordBuffer can hold.
*
* vardataBuffer [OUT]
* This is the user VA offset pointing to the base of the variable data buffer.
*
* vardataBufferSize [IN]
* Size of the variable data buffer in bytes.
*
* recordsFreeThreshold [IN]
* This is the notification threshold for the event record buffer.
* This felid specifies the number of records that the buffer can
* still hold before it gets full.
*
* vardataFreeThreshold [IN]
* This is the notification threshold for the vardata buffer.
* This felid specifies the number of bytes that the buffer can
* still hold before it gets full.
*
* notificationHandle [IN]
* When recordsFreeThreshold or vardataFreeThreshold is met, kernel will notify
* user on this handle. If notificationHandle = NULL, event notification
* is disabled. This is an OS specific notification handle.
* It is a Windows event handle or a fd pointer on Linux.
*
* hSubDevice [IN]
* An event buffer can either hold sub-device related events or system events.
* This handle specifies the sub-device to associate this buffer with.
* If this parameter is NULL, then the buffer is tied to the client instead.
*
* flags [IN]
* Set to 0 by default.
* This field can hold any future flags to configure the buffer if needed.
*
* hBufferHeader [IN]
* The backing memory object for the buffer header. Must be a NV01_MEMORY_DEVICELESS object.
* On Windows platforms, a buffer will be internally generated if hBufferHeader is 0.
*
* hRecordBuffer [IN]
* The backing memory object for the record buffer. Must be a NV01_MEMORY_DEVICELESS object.
* On Windows platforms, a buffer will be internally generated if hRecordBuffer is 0.
*
* hVardataBuffer [IN]
* The backing memory object for the vardata buffer. Must be a NV01_MEMORY_DEVICELESS object.
* On Windows platforms, a buffer will be internally generated if hVardataBuffer is 0.
*
*/
typedef struct
{
NvP64 bufferHeader NV_ALIGN_BYTES(8);
NvP64 recordBuffer NV_ALIGN_BYTES(8);
NvU32 recordSize;
NvU32 recordCount;
NvP64 vardataBuffer NV_ALIGN_BYTES(8);
NvU32 vardataBufferSize;
NvU32 recordsFreeThreshold;
NvU64 notificationHandle NV_ALIGN_BYTES(8);
NvU32 vardataFreeThreshold;
NvHandle hSubDevice;
NvU32 flags;
NvHandle hBufferHeader;
NvHandle hRecordBuffer;
NvHandle hVardataBuffer;
} NV_EVENT_BUFFER_ALLOC_PARAMETERS;
/*
* NV_EVENT_BUFFER_BIND
* This class is used to allocate an Event Type object bound to a given event buffer.
* This allocation call associates an event type with an event buffer.
* Multiple event types can be associated with the same buffer as long as they belong to
* the same category i.e. either sub-device or system.
* When event buffer is enabled, if an event bound to this buffer occurs,
* some relevant data gets added to it.
* cl2080.h has a list of sub-device events that can be associated with a buffer
* cl0000.h has a list of system events that can be associated with a buffer
* These defines are also used in class NV01_EVENT_OS_EVENT (0x79) to get event notification
* and class NV01_EVENT_KERNEL_CALLBACK_EX (0x7E) to get kernel callbacks.
* This class extends that support to additionally get relevant data in an event buffer
*
*/
#define NV_EVENT_BUFFER_BIND (0x0000007F)
/*
* NV_EVENT_BUFFER_BIND_PARAMETERS
*
* bufferHandle [IN]
* Event buffer handle used to bind the given event type
*
* eventType [IN]
* This is one of the eventTypeIDs from cl2080.h/cl000.h
* e.g. NV2080_NOTIFIERS_PSTATE_CHANGE
*
* eventSubtype [IN]
* Event subtype for a given type of event.
* This field is optional depending on if an eventtype has a subtype.
*
* hClientTarget [IN]
* Handle of the target client whose events are to be bound to the given buffer
* e.g. context switch events can be tracked for a given client.
* This field is optional depending on the event type.
* e.g. pstate change events are per gpu but do not depend on a client.
*
* hSrcResource [IN]
* source resource handle for the event type
* e.g. channel handle: RC/context switch can be tracked for a given channel
* This field is optional depending on the event type.
* e.g. pstate change events are per gpu and cannot be sub-categorized
*
* KernelCallbackdata [IN]
* This field is reserved for KERNEL ONLY clients.
*
*/
typedef struct
{
NvHandle bufferHandle;
NvU16 eventType;
NvU16 eventSubtype;
NvHandle hClientTarget;
NvHandle hSrcResource;
NvP64 KernelCallbackdata NV_ALIGN_BYTES(8);
} NV_EVENT_BUFFER_BIND_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl90cd_h_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl90cdFecs_h_
#define _cl90cdFecs_h_
/* This file defines parameters for FECS context switch events*/
#define NV_EVENT_BUFFER_FECS_VERSION 2
/*
* These are the types of context switch events
* This field gets added to NV_EVENT_BUFFER_FECS_RECORD to specify the sub type of fecs event
* Do *not* edit these as they are defined to maintain consistency with Tegra tools
*/
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SO 0x00
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_CTXSW_REQ_BY_HOST 0x01
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK 0x02
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_WFI 0x0a
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_GFXP 0x0b
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_CTAP 0x0c
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK_CILP 0x0d
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SAVE_END 0x03
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_RESTORE_START 0x04
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_CONTEXT_START 0x05
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_START 0x06
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_END 0x07
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_ENGINE_RESET 0xfe
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_INVALID_TIMESTAMP 0xff
#define NV_EVENT_BUFFER_FECS_CTXSWTAG_LAST NV_EVENT_BUFFER_FECS_EVENTS_CTXSWTAG_INVALID_TIMESTAMP
/*
* Bit fields used to enable a particular sub type of event
*/
#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SO NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SO)
#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_CTXSW_REQ_BY_HOST NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_CTXSW_REQ_BY_HOST)
#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_FE_ACK NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_FE_ACK)
#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SAVE_END NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SAVE_END)
#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_RESTORE_START NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_RESTORE_START)
#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_CONTEXT_START NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_CONTEXT_START)
#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SIMPLE_START NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_START)
#define NV_EVENT_BUFFER_FECS_BITMASK_CTXSWTAG_SIMPLE_END NVBIT(NV_EVENT_BUFFER_FECS_CTXSWTAG_SIMPLE_END)
/* context_id is set to this value if fecs info doesn't match a known channel/tsg handle*/
#define NV_EVENT_BUFFER_INVALID_CONTEXT 0xFFFFFFFF
/*
* PID/context_id are set to these values if the data is from another user's
* client and the current user is not an administrator
*/
#define NV_EVENT_BUFFER_HIDDEN_PID 0x0
#define NV_EVENT_BUFFER_HIDDEN_CONTEXT 0x0
/*
* PID/context_id are set to these values if the data is from a kernel client
* and the data is being read by a user client
*/
#define NV_EVENT_BUFFER_KERNEL_PID 0xFFFFFFFF
#define NV_EVENT_BUFFER_KERNEL_CONTEXT 0xFFFFFFFF
// V1 ------------------------------------------------------------------------
typedef struct
{
NvU8 tag; ///< NV_EVENT_BUFFER_FECS_CTXSWTAG_*
NvU8 vmid;
NvU16 seqno; ///< used to detect drop
NvU32 context_id; ///< channel/tsg handle
NvU64 pid NV_ALIGN_BYTES(8); ///< process id
NvU64 timestamp NV_ALIGN_BYTES(8);
/* Do *not* edit items above this to maintain consistency with tegra tools
Always add to the end of this structure to retain backward compatibility */
} NV_EVENT_BUFFER_FECS_RECORD_V1;
// V2 ------------------------------------------------------------------------
typedef struct
{
NvU8 tag; ///< NV_EVENT_BUFFER_FECS_CTXSWTAG_*
NvU8 vmid;
NvU16 seqno; ///< used to detect drop
NvU32 context_id; ///< channel/tsg handle
NvU32 pid; ///< process id
NvU16 reserved0;
NvU8 migGpuInstanceId;
NvU8 migComputeInstanceId;
NvU64 timestamp NV_ALIGN_BYTES(8);
/* Do *not* edit items above this to maintain consistency with tegra tools
Always add to the end of this structure to retain backward compatibility */
} NV_EVENT_BUFFER_FECS_RECORD_V2;
typedef NV_EVENT_BUFFER_FECS_RECORD_V1 NV_EVENT_BUFFER_FECS_RECORD_V0;
typedef NV_EVENT_BUFFER_FECS_RECORD_V1 NV_EVENT_BUFFER_FECS_RECORD;
#endif /* _cl90cdFecs_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl90cdtypes_h_
#define _cl90cdtypes_h_
#ifdef __cplusplus
extern "C" {
#endif
//
// Legacy values record type values have been kept for backward
// compatibility. New values should be added sequentially.
//
#define NV_EVENT_BUFFER_RECORD_TYPE_INVALID (0)
#define NV_EVENT_BUFFER_RECORD_TYPE_VIDEO_TRACE (1)
#define NV_EVENT_BUFFER_RECORD_TYPE_FECS_CTX_SWITCH_V2 (2)
#define NV_EVENT_BUFFER_RECORD_TYPE_NVTELEMETRY_REPORT_EVENT_SYSTEM (4)
#define NV_EVENT_BUFFER_RECORD_TYPE_NVTELEMETRY_REPORT_EVENT_SUBDEVICE (132)
#define NV_EVENT_BUFFER_RECORD_TYPE_FECS_CTX_SWITCH (134)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl90cdtypes_h_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl90ce_h_
#define _cl90ce_h_
#ifdef __cplusplus
extern "C" {
#endif
/*
* NV_MEMORY_DEVICELESS
* Memory that is not associated with a device
*/
#define NV01_MEMORY_DEVICELESS (0x000090CE)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl90ce_h_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl90e6_h_
#define _cl90e6_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define GF100_SUBDEVICE_MASTER (0x000090e6)
typedef struct {
NvU32 Reserved00[0x400]; /* NV_PMC 0x00000FFF:0x00000000 */
} Nv90e6MapTypedef, GF100MASTERMap;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl90e6_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl90ec_h_
#define _cl90ec_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
/* Class within the subdevice used for communicating with HDACODEC*/
#define GF100_HDACODEC (0x000090EC)
/* pio method data structure */
typedef volatile struct _cl90ec_tag0 {
NvV32 Reserved00[0x7c0];
} Nv90ECTypedef, GF100Hdacodec;
#define NV90EC_TYPEDEF GF100Hdacodec
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9071_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#ifndef _cl90f1_h_
#define _cl90f1_h_
#ifdef __cplusplus
extern "C" {
#endif
#define FERMI_VASPACE_A (0x000090f1)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl90f1_h

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/*
* Copyright (c) 1993-2004, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9170_h_
#define _cl9170_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV9170_DISPLAY (0x00009170)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9170_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9170_h_ */

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/*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9171_h_
#define _cl9171_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV9171_DISP_SF_USER 0x9171
typedef volatile struct _cl9171_tag0 {
NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */
} _Nv9171DispSfUser, Nv9171DispSfUserMap;
#define NV9171_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */
#define NV9171_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */
#define NV9171_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */
#define NV9171_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */
#define NV9171_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */
#define NV9171_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */
#define NV9171_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */
#define NV9171_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */
#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NV9171_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */
#define NV9171_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */
#define NV9171_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */
#define NV9171_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NV9171_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */
#define NV9171_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */
#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */
#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */
#define NV9171_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */
#define NV9171_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */
#define NV9171_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */
#define NV9171_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */
#define NV9171_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NV9171_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NV9171_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */
#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */
#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */
#define NV9171_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */
#define NV9171_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */
#define NV9171_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */
#define NV9171_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */
#define NV9171_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */
#define NV9171_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */
#define NV9171_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */
#define NV9171_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */
#define NV9171_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */
#define NV9171_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */
#define NV9171_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */
#define NV9171_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */
#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */
#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */
#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */
#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */
#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */
#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */
#define NV9171_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl9171_h_

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/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl917a_h_
#define _cl917a_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV917A_CURSOR_CHANNEL_PIO (0x0000917A)
typedef volatile struct {
NvV32 Reserved00[0x2];
NvV32 Free; // 0x00000008 - 0x0000000B
NvV32 Reserved01[0x1D];
NvV32 Update; // 0x00000080 - 0x00000083
NvV32 SetCursorHotSpotPointsOut[2]; // 0x00000084 - 0x0000008B
NvV32 Reserved02[0x3DD];
} GK104DispCursorControlPio;
#define NV917A_FREE (0x00000008)
#define NV917A_FREE_COUNT 5:0
#define NV917A_UPDATE (0x00000080)
#define NV917A_UPDATE_INTERLOCK_WITH_CORE 0:0
#define NV917A_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NV917A_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT(b) (0x00000084 + (b)*0x00000004)
#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT_X 15:0
#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT_Y 31:16
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl917a_h

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/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl917b_h_
#define _cl917b_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV917B_OVERLAY_IMM_CHANNEL_PIO (0x0000917B)
typedef volatile struct {
NvV32 Reserved00[0x2];
NvV32 Free; // 0x00000008 - 0x0000000B
NvV32 Reserved01[0x1D];
NvV32 Update; // 0x00000080 - 0x00000083
NvV32 SetPointsOut[2]; // 0x00000084 - 0x0000008B
NvV32 Reserved02[0x1];
NvV32 AwakenOnceFlippedTo; // 0x00000090 - 0x00000093
NvV32 Reserved03[0x3DB];
} GK104DispOverlayImmControlPio;
#define NV917B_FREE (0x00000008)
#define NV917B_FREE_COUNT 5:0
#define NV917B_UPDATE (0x00000080)
#define NV917B_UPDATE_INTERLOCK_WITH_CORE 0:0
#define NV917B_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NV917B_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NV917B_SET_POINTS_OUT(b) (0x00000084 + (b)*0x00000004)
#define NV917B_SET_POINTS_OUT_X 15:0
#define NV917B_SET_POINTS_OUT_Y 31:16
#define NV917B_AWAKEN_ONCE_FLIPPED_TO (0x00000090)
#define NV917B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT 11:0
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl917b_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl917c_h_
#define _cl917c_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV917C_BASE_CHANNEL_DMA (0x0000917C)
#define NV_DISP_BASE_NOTIFIER_1 0x00000000
#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004
#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000
#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0
#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16
#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30
#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000
#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001
#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002
#define NV_DISP_NOTIFICATION_2 0x00000000
#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010
#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000
#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0
#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001
#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0
#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002
#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0
#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003
#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0
#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8
#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9
#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16
#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000
#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF
#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000
#define NV_DISP_NOTIFICATION_INFO16 0x00000000
#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002
#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000
#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0
#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8
#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9
#define NV_DISP_NOTIFICATION_STATUS 0x00000000
#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002
#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000
#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0
#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000
#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF
#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000
// dma opcode instructions
#define NV917C_DMA 0x00000000
#define NV917C_DMA_OPCODE 31:29
#define NV917C_DMA_OPCODE_METHOD 0x00000000
#define NV917C_DMA_OPCODE_JUMP 0x00000001
#define NV917C_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NV917C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NV917C_DMA_OPCODE 31:29
#define NV917C_DMA_OPCODE_METHOD 0x00000000
#define NV917C_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NV917C_DMA_METHOD_COUNT 27:18
#define NV917C_DMA_METHOD_OFFSET 11:2
#define NV917C_DMA_DATA 31:0
#define NV917C_DMA_DATA_NOP 0x00000000
#define NV917C_DMA_OPCODE 31:29
#define NV917C_DMA_OPCODE_JUMP 0x00000001
#define NV917C_DMA_JUMP_OFFSET 11:2
#define NV917C_DMA_OPCODE 31:29
#define NV917C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NV917C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NV917C_PUT (0x00000000)
#define NV917C_PUT_PTR 11:2
#define NV917C_GET (0x00000004)
#define NV917C_GET_PTR 11:2
#define NV917C_GET_SCANLINE (0x00000010)
#define NV917C_GET_SCANLINE_LINE 15:0
#define NV917C_UPDATE (0x00000080)
#define NV917C_UPDATE_INTERLOCK_WITH_CORE 0:0
#define NV917C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NV917C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NV917C_UPDATE_SPECIAL_HANDLING 25:24
#define NV917C_UPDATE_SPECIAL_HANDLING_NONE (0x00000000)
#define NV917C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001)
#define NV917C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002)
#define NV917C_UPDATE_SPECIAL_HANDLING_REASON 23:16
#define NV917C_SET_PRESENT_CONTROL (0x00000084)
#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8
#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002)
#define NV917C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE 3:3
#define NV917C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_PAIR_FLIP (0x00000000)
#define NV917C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_AT_ANY_FRAME (0x00000001)
#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE 2:2
#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
#define NV917C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4
#define NV917C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16
#define NV917C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10
#define NV917C_SET_PRESENT_CONTROL_MODE 1:0
#define NV917C_SET_PRESENT_CONTROL_MODE_MONO (0x00000000)
#define NV917C_SET_PRESENT_CONTROL_MODE_STEREO (0x00000001)
#define NV917C_SET_PRESENT_CONTROL_MODE_SPEC_FLIP (0x00000002)
#define NV917C_SET_SEMAPHORE_CONTROL (0x00000088)
#define NV917C_SET_SEMAPHORE_CONTROL_OFFSET 11:2
#define NV917C_SET_SEMAPHORE_CONTROL_DELAY 26:26
#define NV917C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE (0x00000000)
#define NV917C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE (0x00000001)
#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT 28:28
#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000)
#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001)
#define NV917C_SET_SEMAPHORE_ACQUIRE (0x0000008C)
#define NV917C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0
#define NV917C_SET_SEMAPHORE_RELEASE (0x00000090)
#define NV917C_SET_SEMAPHORE_RELEASE_VALUE 31:0
#define NV917C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094)
#define NV917C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0
#define NV917C_SET_NOTIFIER_CONTROL (0x000000A0)
#define NV917C_SET_NOTIFIER_CONTROL_MODE 30:30
#define NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NV917C_SET_NOTIFIER_CONTROL_OFFSET 11:2
#define NV917C_SET_NOTIFIER_CONTROL_DELAY 26:26
#define NV917C_SET_NOTIFIER_CONTROL_DELAY_DISABLE (0x00000000)
#define NV917C_SET_NOTIFIER_CONTROL_DELAY_ENABLE (0x00000001)
#define NV917C_SET_NOTIFIER_CONTROL_FORMAT 28:28
#define NV917C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000)
#define NV917C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001)
#define NV917C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4)
#define NV917C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
#define NV917C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004)
#define NV917C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
#define NV917C_SET_BASE_LUT_LO (0x000000E0)
#define NV917C_SET_BASE_LUT_LO_ENABLE 31:30
#define NV917C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV917C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001)
#define NV917C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000002)
#define NV917C_SET_BASE_LUT_LO_MODE 27:24
#define NV917C_SET_BASE_LUT_LO_MODE_LORES (0x00000000)
#define NV917C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001)
#define NV917C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003)
#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004)
#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005)
#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006)
#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007)
#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008)
#define NV917C_SET_BASE_LUT_HI (0x000000E4)
#define NV917C_SET_BASE_LUT_HI_ORIGIN 31:0
#define NV917C_SET_OUTPUT_LUT_LO (0x000000E8)
#define NV917C_SET_OUTPUT_LUT_LO_ENABLE 31:30
#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001)
#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000002)
#define NV917C_SET_OUTPUT_LUT_LO_MODE 27:24
#define NV917C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000)
#define NV917C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001)
#define NV917C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003)
#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004)
#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005)
#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006)
#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007)
#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008)
#define NV917C_SET_OUTPUT_LUT_HI (0x000000EC)
#define NV917C_SET_OUTPUT_LUT_HI_ORIGIN 31:0
#define NV917C_SET_CONTEXT_DMA_LUT (0x000000FC)
#define NV917C_SET_CONTEXT_DMA_LUT_HANDLE 31:0
#define NV917C_SET_PROCESSING (0x00000110)
#define NV917C_SET_PROCESSING_USE_GAIN_OFS 0:0
#define NV917C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000)
#define NV917C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001)
#define NV917C_SET_CONVERSION_RED (0x00000114)
#define NV917C_SET_CONVERSION_RED_GAIN 15:0
#define NV917C_SET_CONVERSION_RED_OFS 31:16
#define NV917C_SET_CONVERSION_GRN (0x00000118)
#define NV917C_SET_CONVERSION_GRN_GAIN 15:0
#define NV917C_SET_CONVERSION_GRN_OFS 31:16
#define NV917C_SET_CONVERSION_BLU (0x0000011C)
#define NV917C_SET_CONVERSION_BLU_GAIN 15:0
#define NV917C_SET_CONVERSION_BLU_OFS 31:16
#define NV917C_SET_TIMESTAMP_ORIGIN_LO (0x00000130)
#define NV917C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0
#define NV917C_SET_TIMESTAMP_ORIGIN_HI (0x00000134)
#define NV917C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0
#define NV917C_SET_UPDATE_TIMESTAMP_LO (0x00000138)
#define NV917C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0
#define NV917C_SET_UPDATE_TIMESTAMP_HI (0x0000013C)
#define NV917C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0
#define NV917C_SET_CSC_RED2RED (0x00000140)
#define NV917C_SET_CSC_RED2RED_OWNER 31:31
#define NV917C_SET_CSC_RED2RED_OWNER_CORE (0x00000000)
#define NV917C_SET_CSC_RED2RED_OWNER_BASE (0x00000001)
#define NV917C_SET_CSC_RED2RED_COEFF 18:0
#define NV917C_SET_CSC_GRN2RED (0x00000144)
#define NV917C_SET_CSC_GRN2RED_COEFF 18:0
#define NV917C_SET_CSC_BLU2RED (0x00000148)
#define NV917C_SET_CSC_BLU2RED_COEFF 18:0
#define NV917C_SET_CSC_CONSTANT2RED (0x0000014C)
#define NV917C_SET_CSC_CONSTANT2RED_COEFF 18:0
#define NV917C_SET_CSC_RED2GRN (0x00000150)
#define NV917C_SET_CSC_RED2GRN_COEFF 18:0
#define NV917C_SET_CSC_GRN2GRN (0x00000154)
#define NV917C_SET_CSC_GRN2GRN_COEFF 18:0
#define NV917C_SET_CSC_BLU2GRN (0x00000158)
#define NV917C_SET_CSC_BLU2GRN_COEFF 18:0
#define NV917C_SET_CSC_CONSTANT2GRN (0x0000015C)
#define NV917C_SET_CSC_CONSTANT2GRN_COEFF 18:0
#define NV917C_SET_CSC_RED2BLU (0x00000160)
#define NV917C_SET_CSC_RED2BLU_COEFF 18:0
#define NV917C_SET_CSC_GRN2BLU (0x00000164)
#define NV917C_SET_CSC_GRN2BLU_COEFF 18:0
#define NV917C_SET_CSC_BLU2BLU (0x00000168)
#define NV917C_SET_CSC_BLU2BLU_COEFF 18:0
#define NV917C_SET_CSC_CONSTANT2BLU (0x0000016C)
#define NV917C_SET_CSC_CONSTANT2BLU_COEFF 18:0
#define NV917C_SET_SPARE (0x000003BC)
#define NV917C_SET_SPARE_UNUSED 31:0
#define NV917C_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004)
#define NV917C_SET_SPARE_NOOP_UNUSED 31:0
#define NV917C_SURFACE_SET_OFFSET(a,b) (0x00000400 + (a)*0x00000020 + (b)*0x00000004)
#define NV917C_SURFACE_SET_OFFSET_ORIGIN 31:0
#define NV917C_SURFACE_SET_SIZE(a) (0x00000408 + (a)*0x00000020)
#define NV917C_SURFACE_SET_SIZE_WIDTH 15:0
#define NV917C_SURFACE_SET_SIZE_HEIGHT 31:16
#define NV917C_SURFACE_SET_STORAGE(a) (0x0000040C + (a)*0x00000020)
#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV917C_SURFACE_SET_STORAGE_PITCH 20:8
#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24
#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV917C_SURFACE_SET_PARAMS(a) (0x00000410 + (a)*0x00000020)
#define NV917C_SURFACE_SET_PARAMS_FORMAT 15:8
#define NV917C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NV917C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F)
#define NV917C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E)
#define NV917C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV917C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV917C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV917C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022)
#define NV917C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NV917C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NV917C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV917C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NV917C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NV917C_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0
#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV917C_SURFACE_SET_PARAMS_GAMMA 2:2
#define NV917C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000)
#define NV917C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001)
#define NV917C_SURFACE_SET_PARAMS_LAYOUT 5:4
#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000)
#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001)
#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl917c_h

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/*
* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl917c_sw_spare_h_
#define _cl917c_sw_spare_h_
/* This file is *not* auto-generated. */
/* NV917C_SET_SPARE_PRE_UPDATE_TRAP is an alias of NV917C_SET_SPARE_NOOP(0) */
#define NV917C_SET_SPARE_PRE_UPDATE_TRAP (0x000003C0)
#define NV917C_SET_SPARE_PRE_UPDATE_TRAP_UNUSED 31:0
/* NV917C_SET_SPARE_POST_UPDATE_TRAP is an alias of NV917C_SET_SPARE_NOOP(1) */
#define NV917C_SET_SPARE_POST_UPDATE_TRAP (0x000003C4)
#define NV917C_SET_SPARE_POST_UPDATE_TRAP_UNUSED 31:0
#endif /* _cl917c_sw_spare_h_ */

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/*
* Copyright (c) 2003-2010, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __cl917dcrcnotif_h__
#define __cl917dcrcnotif_h__
/* This file is autogenerated. Do not edit */
#define NV917D_NOTIFIER_CRC_1_STATUS_0 0x00000000
#define NV917D_NOTIFIER_CRC_1_STATUS_0_DONE 0:0
#define NV917D_NOTIFIER_CRC_1_STATUS_0_DONE_FALSE 0x00000000
#define NV917D_NOTIFIER_CRC_1_STATUS_0_DONE_TRUE 0x00000001
#define NV917D_NOTIFIER_CRC_1_STATUS_0_COMPOSITOR_OVERFLOW 3:3
#define NV917D_NOTIFIER_CRC_1_STATUS_0_COMPOSITOR_OVERFLOW_FALSE 0x00000000
#define NV917D_NOTIFIER_CRC_1_STATUS_0_COMPOSITOR_OVERFLOW_TRUE 0x00000001
#define NV917D_NOTIFIER_CRC_1_STATUS_0_PRIMARY_OUTPUT_OVERFLOW 4:4
#define NV917D_NOTIFIER_CRC_1_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_FALSE 0x00000000
#define NV917D_NOTIFIER_CRC_1_STATUS_0_PRIMARY_OUTPUT_OVERFLOW_TRUE 0x00000001
#define NV917D_NOTIFIER_CRC_1_STATUS_0_COUNT 31:24
#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_3 0x00000003
#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_3_COMPOSITOR_CRC 31:0
#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_4 0x00000004
#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY0_4_PRIMARY_OUTPUT_CRC 31:0
#define NV917D_NOTIFIER_CRC_1_CRC_ENTRY1_8 0x00000008
#endif // __cl917dcrcnotif_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl917e_h_
#define _cl917e_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV917E_OVERLAY_CHANNEL_DMA (0x0000917E)
#define NV_DISP_NOTIFICATION_2 0x00000000
#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010
#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000
#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0
#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001
#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0
#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002
#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0
#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003
#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0
#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8
#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9
#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16
#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000
#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF
#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000
#define NV_DISP_NOTIFICATION_INFO16 0x00000000
#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002
#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000
#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0
#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8
#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9
#define NV_DISP_NOTIFICATION_STATUS 0x00000000
#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002
#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000
#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0
#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000
#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF
#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000
// dma opcode instructions
#define NV917E_DMA 0x00000000
#define NV917E_DMA_OPCODE 31:29
#define NV917E_DMA_OPCODE_METHOD 0x00000000
#define NV917E_DMA_OPCODE_JUMP 0x00000001
#define NV917E_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NV917E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NV917E_DMA_OPCODE 31:29
#define NV917E_DMA_OPCODE_METHOD 0x00000000
#define NV917E_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NV917E_DMA_METHOD_COUNT 27:18
#define NV917E_DMA_METHOD_OFFSET 11:2
#define NV917E_DMA_DATA 31:0
#define NV917E_DMA_DATA_NOP 0x00000000
#define NV917E_DMA_OPCODE 31:29
#define NV917E_DMA_OPCODE_JUMP 0x00000001
#define NV917E_DMA_JUMP_OFFSET 11:2
#define NV917E_DMA_OPCODE 31:29
#define NV917E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NV917E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NV917E_PUT (0x00000000)
#define NV917E_PUT_PTR 11:2
#define NV917E_GET (0x00000004)
#define NV917E_GET_PTR 11:2
#define NV917E_UPDATE (0x00000080)
#define NV917E_UPDATE_INTERLOCK_WITH_CORE 0:0
#define NV917E_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NV917E_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NV917E_UPDATE_SPECIAL_HANDLING 25:24
#define NV917E_UPDATE_SPECIAL_HANDLING_NONE (0x00000000)
#define NV917E_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001)
#define NV917E_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002)
#define NV917E_UPDATE_SPECIAL_HANDLING_REASON 23:16
#define NV917E_SET_PRESENT_CONTROL (0x00000084)
#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0
#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000)
#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003)
#define NV917E_SET_PRESENT_CONTROL_STEREO_FLIP_MODE 3:3
#define NV917E_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_PAIR_FLIP (0x00000000)
#define NV917E_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_AT_ANY_FRAME (0x00000001)
#define NV917E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4
#define NV917E_SET_PRESENT_CONTROL_MODE 11:10
#define NV917E_SET_PRESENT_CONTROL_MODE_MONO (0x00000000)
#define NV917E_SET_PRESENT_CONTROL_MODE_STEREO (0x00000001)
#define NV917E_SET_PRESENT_CONTROL_MODE_SPEC_FLIP (0x00000002)
#define NV917E_SET_SEMAPHORE_ACQUIRE (0x00000088)
#define NV917E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0
#define NV917E_SET_SEMAPHORE_RELEASE (0x0000008C)
#define NV917E_SET_SEMAPHORE_RELEASE_VALUE 31:0
#define NV917E_SET_SEMAPHORE_CONTROL (0x00000090)
#define NV917E_SET_SEMAPHORE_CONTROL_OFFSET 11:2
#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT 28:28
#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000)
#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001)
#define NV917E_SET_CONTEXT_DMA_SEMAPHORE (0x00000094)
#define NV917E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0
#define NV917E_SET_NOTIFIER_CONTROL (0x000000A0)
#define NV917E_SET_NOTIFIER_CONTROL_MODE 30:30
#define NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NV917E_SET_NOTIFIER_CONTROL_OFFSET 11:2
#define NV917E_SET_NOTIFIER_CONTROL_FORMAT 28:28
#define NV917E_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000)
#define NV917E_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001)
#define NV917E_SET_CONTEXT_DMA_NOTIFIER (0x000000A4)
#define NV917E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
#define NV917E_SET_CONTEXT_DMA_LUT (0x000000B0)
#define NV917E_SET_CONTEXT_DMA_LUT_HANDLE 31:0
#define NV917E_SET_OVERLAY_LUT_LO (0x000000B4)
#define NV917E_SET_OVERLAY_LUT_LO_ENABLE 31:31
#define NV917E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV917E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE (0x00000001)
#define NV917E_SET_OVERLAY_LUT_LO_MODE 27:24
#define NV917E_SET_OVERLAY_LUT_LO_MODE_LORES (0x00000000)
#define NV917E_SET_OVERLAY_LUT_LO_MODE_HIRES (0x00000001)
#define NV917E_SET_OVERLAY_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003)
#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004)
#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005)
#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006)
#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007)
#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008)
#define NV917E_SET_OVERLAY_LUT_HI (0x000000B8)
#define NV917E_SET_OVERLAY_LUT_HI_ORIGIN 31:0
#define NV917E_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004)
#define NV917E_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
#define NV917E_SET_POINT_IN (0x000000E0)
#define NV917E_SET_POINT_IN_X 14:0
#define NV917E_SET_POINT_IN_Y 30:16
#define NV917E_SET_SIZE_IN (0x000000E4)
#define NV917E_SET_SIZE_IN_WIDTH 14:0
#define NV917E_SET_SIZE_IN_HEIGHT 30:16
#define NV917E_SET_SIZE_OUT (0x000000E8)
#define NV917E_SET_SIZE_OUT_WIDTH 14:0
#define NV917E_SET_COMPOSITION_CONTROL (0x00000100)
#define NV917E_SET_COMPOSITION_CONTROL_MODE 3:0
#define NV917E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000)
#define NV917E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001)
#define NV917E_SET_COMPOSITION_CONTROL_MODE_OPAQUE (0x00000002)
#define NV917E_SET_KEY_COLOR_LO (0x00000104)
#define NV917E_SET_KEY_COLOR_LO_COLOR 31:0
#define NV917E_SET_KEY_COLOR_HI (0x00000108)
#define NV917E_SET_KEY_COLOR_HI_COLOR 31:0
#define NV917E_SET_KEY_MASK_LO (0x0000010C)
#define NV917E_SET_KEY_MASK_LO_MASK 31:0
#define NV917E_SET_KEY_MASK_HI (0x00000110)
#define NV917E_SET_KEY_MASK_HI_MASK 31:0
#define NV917E_SET_PROCESSING (0x00000118)
#define NV917E_SET_PROCESSING_USE_GAIN_OFS 0:0
#define NV917E_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000)
#define NV917E_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001)
#define NV917E_SET_CONVERSION_RED (0x0000011C)
#define NV917E_SET_CONVERSION_RED_GAIN 15:0
#define NV917E_SET_CONVERSION_RED_OFS 31:16
#define NV917E_SET_CONVERSION_GRN (0x00000120)
#define NV917E_SET_CONVERSION_GRN_GAIN 15:0
#define NV917E_SET_CONVERSION_GRN_OFS 31:16
#define NV917E_SET_CONVERSION_BLU (0x00000124)
#define NV917E_SET_CONVERSION_BLU_GAIN 15:0
#define NV917E_SET_CONVERSION_BLU_OFS 31:16
#define NV917E_SET_TIMESTAMP_ORIGIN_LO (0x00000130)
#define NV917E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0
#define NV917E_SET_TIMESTAMP_ORIGIN_HI (0x00000134)
#define NV917E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0
#define NV917E_SET_UPDATE_TIMESTAMP_LO (0x00000138)
#define NV917E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0
#define NV917E_SET_UPDATE_TIMESTAMP_HI (0x0000013C)
#define NV917E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0
#define NV917E_SET_CSC_RED2RED (0x00000140)
#define NV917E_SET_CSC_RED2RED_COEFF 18:0
#define NV917E_SET_CSC_GRN2RED (0x00000144)
#define NV917E_SET_CSC_GRN2RED_COEFF 18:0
#define NV917E_SET_CSC_BLU2RED (0x00000148)
#define NV917E_SET_CSC_BLU2RED_COEFF 18:0
#define NV917E_SET_CSC_CONSTANT2RED (0x0000014C)
#define NV917E_SET_CSC_CONSTANT2RED_COEFF 18:0
#define NV917E_SET_CSC_RED2GRN (0x00000150)
#define NV917E_SET_CSC_RED2GRN_COEFF 18:0
#define NV917E_SET_CSC_GRN2GRN (0x00000154)
#define NV917E_SET_CSC_GRN2GRN_COEFF 18:0
#define NV917E_SET_CSC_BLU2GRN (0x00000158)
#define NV917E_SET_CSC_BLU2GRN_COEFF 18:0
#define NV917E_SET_CSC_CONSTANT2GRN (0x0000015C)
#define NV917E_SET_CSC_CONSTANT2GRN_COEFF 18:0
#define NV917E_SET_CSC_RED2BLU (0x00000160)
#define NV917E_SET_CSC_RED2BLU_COEFF 18:0
#define NV917E_SET_CSC_GRN2BLU (0x00000164)
#define NV917E_SET_CSC_GRN2BLU_COEFF 18:0
#define NV917E_SET_CSC_BLU2BLU (0x00000168)
#define NV917E_SET_CSC_BLU2BLU_COEFF 18:0
#define NV917E_SET_CSC_CONSTANT2BLU (0x0000016C)
#define NV917E_SET_CSC_CONSTANT2BLU_COEFF 18:0
#define NV917E_SET_SPARE (0x000003BC)
#define NV917E_SET_SPARE_UNUSED 31:0
#define NV917E_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004)
#define NV917E_SET_SPARE_NOOP_UNUSED 31:0
#define NV917E_SURFACE_SET_OFFSET(b) (0x00000400 + (b)*0x00000004)
#define NV917E_SURFACE_SET_OFFSET_ORIGIN 31:0
#define NV917E_SURFACE_SET_SIZE (0x00000408)
#define NV917E_SURFACE_SET_SIZE_WIDTH 15:0
#define NV917E_SURFACE_SET_SIZE_HEIGHT 31:16
#define NV917E_SURFACE_SET_STORAGE (0x0000040C)
#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV917E_SURFACE_SET_STORAGE_PITCH 20:8
#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24
#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV917E_SURFACE_SET_PARAMS (0x00000410)
#define NV917E_SURFACE_SET_PARAMS_FORMAT 15:8
#define NV917E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028)
#define NV917E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029)
#define NV917E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV917E_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022)
#define NV917E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV917E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV917E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NV917E_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0
#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000)
#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001)
#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl917e_h

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src/common/sdk/nvidia/inc/class/cl9270.h Normal file
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/*
* Copyright (c) 1993-2010, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9270_h_
#define _cl9270_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV9270_DISPLAY (0x00009270)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9270_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9270_h_ */

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/*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9271_h_
#define _cl9271_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV9271_DISP_SF_USER 0x9271
typedef volatile struct _cl9271_tag0 {
NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */
} _Nv9271DispSfUser, Nv9271DispSfUserMap;
#define NV9271_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */
#define NV9271_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */
#define NV9271_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */
#define NV9271_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */
#define NV9271_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */
#define NV9271_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */
#define NV9271_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */
#define NV9271_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */
#define NV9271_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NV9271_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */
#define NV9271_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */
#define NV9271_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */
#define NV9271_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NV9271_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */
#define NV9271_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */
#define NV9271_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */
#define NV9271_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */
#define NV9271_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */
#define NV9271_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */
#define NV9271_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */
#define NV9271_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */
#define NV9271_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NV9271_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NV9271_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */
#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */
#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */
#define NV9271_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */
#define NV9271_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */
#define NV9271_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */
#define NV9271_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */
#define NV9271_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */
#define NV9271_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */
#define NV9271_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */
#define NV9271_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */
#define NV9271_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */
#define NV9271_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */
#define NV9271_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */
#define NV9271_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */
#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */
#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */
#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */
#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */
#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */
#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */
#define NV9271_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl9271_h_

299
src/common/sdk/nvidia/inc/class/cl927c.h Normal file
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@@ -0,0 +1,299 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl927c_h_
#define _cl927c_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV927C_BASE_CHANNEL_DMA (0x0000927C)
#define NV_DISP_BASE_NOTIFIER_1 0x00000000
#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004
#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000
#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0
#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16
#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30
#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000
#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001
#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002
#define NV_DISP_NOTIFICATION_2 0x00000000
#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010
#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000
#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0
#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001
#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0
#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002
#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0
#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003
#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0
#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8
#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9
#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16
#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000
#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF
#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000
#define NV_DISP_NOTIFICATION_INFO16 0x00000000
#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002
#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000
#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0
#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8
#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9
#define NV_DISP_NOTIFICATION_STATUS 0x00000000
#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002
#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000
#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0
#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000
#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF
#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000
// dma opcode instructions
#define NV927C_DMA 0x00000000
#define NV927C_DMA_OPCODE 31:29
#define NV927C_DMA_OPCODE_METHOD 0x00000000
#define NV927C_DMA_OPCODE_JUMP 0x00000001
#define NV927C_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NV927C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NV927C_DMA_OPCODE 31:29
#define NV927C_DMA_OPCODE_METHOD 0x00000000
#define NV927C_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NV927C_DMA_METHOD_COUNT 27:18
#define NV927C_DMA_METHOD_OFFSET 11:2
#define NV927C_DMA_DATA 31:0
#define NV927C_DMA_DATA_NOP 0x00000000
#define NV927C_DMA_OPCODE 31:29
#define NV927C_DMA_OPCODE_JUMP 0x00000001
#define NV927C_DMA_JUMP_OFFSET 11:2
#define NV927C_DMA_OPCODE 31:29
#define NV927C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NV927C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NV927C_PUT (0x00000000)
#define NV927C_PUT_PTR 11:2
#define NV927C_GET (0x00000004)
#define NV927C_GET_PTR 11:2
#define NV927C_GET_SCANLINE (0x00000010)
#define NV927C_GET_SCANLINE_LINE 15:0
#define NV927C_UPDATE (0x00000080)
#define NV927C_UPDATE_INTERLOCK_WITH_CORE 0:0
#define NV927C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NV927C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NV927C_UPDATE_SPECIAL_HANDLING 25:24
#define NV927C_UPDATE_SPECIAL_HANDLING_NONE (0x00000000)
#define NV927C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001)
#define NV927C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002)
#define NV927C_UPDATE_SPECIAL_HANDLING_REASON 23:16
#define NV927C_SET_PRESENT_CONTROL (0x00000084)
#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8
#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002)
#define NV927C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE 3:3
#define NV927C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_PAIR_FLIP (0x00000000)
#define NV927C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE_AT_ANY_FRAME (0x00000001)
#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE 2:2
#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
#define NV927C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4
#define NV927C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16
#define NV927C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10
#define NV927C_SET_PRESENT_CONTROL_MODE 1:0
#define NV927C_SET_PRESENT_CONTROL_MODE_MONO (0x00000000)
#define NV927C_SET_PRESENT_CONTROL_MODE_STEREO (0x00000001)
#define NV927C_SET_PRESENT_CONTROL_MODE_SPEC_FLIP (0x00000002)
#define NV927C_SET_SEMAPHORE_CONTROL (0x00000088)
#define NV927C_SET_SEMAPHORE_CONTROL_OFFSET 11:2
#define NV927C_SET_SEMAPHORE_CONTROL_DELAY 26:26
#define NV927C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE (0x00000000)
#define NV927C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE (0x00000001)
#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT 28:28
#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000)
#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001)
#define NV927C_SET_SEMAPHORE_ACQUIRE (0x0000008C)
#define NV927C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0
#define NV927C_SET_SEMAPHORE_RELEASE (0x00000090)
#define NV927C_SET_SEMAPHORE_RELEASE_VALUE 31:0
#define NV927C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094)
#define NV927C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0
#define NV927C_SET_NOTIFIER_CONTROL (0x000000A0)
#define NV927C_SET_NOTIFIER_CONTROL_MODE 30:30
#define NV927C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NV927C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NV927C_SET_NOTIFIER_CONTROL_OFFSET 11:2
#define NV927C_SET_NOTIFIER_CONTROL_DELAY 26:26
#define NV927C_SET_NOTIFIER_CONTROL_DELAY_DISABLE (0x00000000)
#define NV927C_SET_NOTIFIER_CONTROL_DELAY_ENABLE (0x00000001)
#define NV927C_SET_NOTIFIER_CONTROL_FORMAT 28:28
#define NV927C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000)
#define NV927C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001)
#define NV927C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4)
#define NV927C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
#define NV927C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004)
#define NV927C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
#define NV927C_SET_BASE_LUT_LO (0x000000E0)
#define NV927C_SET_BASE_LUT_LO_ENABLE 31:30
#define NV927C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV927C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001)
#define NV927C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000002)
#define NV927C_SET_BASE_LUT_LO_MODE 27:24
#define NV927C_SET_BASE_LUT_LO_MODE_LORES (0x00000000)
#define NV927C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001)
#define NV927C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003)
#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004)
#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005)
#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006)
#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007)
#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008)
#define NV927C_SET_BASE_LUT_HI (0x000000E4)
#define NV927C_SET_BASE_LUT_HI_ORIGIN 31:0
#define NV927C_SET_OUTPUT_LUT_LO (0x000000E8)
#define NV927C_SET_OUTPUT_LUT_LO_ENABLE 31:30
#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001)
#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000002)
#define NV927C_SET_OUTPUT_LUT_LO_MODE 27:24
#define NV927C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000)
#define NV927C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001)
#define NV927C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003)
#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004)
#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005)
#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006)
#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007)
#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008)
#define NV927C_SET_OUTPUT_LUT_HI (0x000000EC)
#define NV927C_SET_OUTPUT_LUT_HI_ORIGIN 31:0
#define NV927C_SET_CONTEXT_DMA_LUT (0x000000FC)
#define NV927C_SET_CONTEXT_DMA_LUT_HANDLE 31:0
#define NV927C_SET_PROCESSING (0x00000110)
#define NV927C_SET_PROCESSING_USE_GAIN_OFS 0:0
#define NV927C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000)
#define NV927C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001)
#define NV927C_SET_CONVERSION_RED (0x00000114)
#define NV927C_SET_CONVERSION_RED_GAIN 15:0
#define NV927C_SET_CONVERSION_RED_OFS 31:16
#define NV927C_SET_CONVERSION_GRN (0x00000118)
#define NV927C_SET_CONVERSION_GRN_GAIN 15:0
#define NV927C_SET_CONVERSION_GRN_OFS 31:16
#define NV927C_SET_CONVERSION_BLU (0x0000011C)
#define NV927C_SET_CONVERSION_BLU_GAIN 15:0
#define NV927C_SET_CONVERSION_BLU_OFS 31:16
#define NV927C_SET_TIMESTAMP_ORIGIN_LO (0x00000130)
#define NV927C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0
#define NV927C_SET_TIMESTAMP_ORIGIN_HI (0x00000134)
#define NV927C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0
#define NV927C_SET_UPDATE_TIMESTAMP_LO (0x00000138)
#define NV927C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0
#define NV927C_SET_UPDATE_TIMESTAMP_HI (0x0000013C)
#define NV927C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0
#define NV927C_SET_CSC_RED2RED (0x00000140)
#define NV927C_SET_CSC_RED2RED_OWNER 31:31
#define NV927C_SET_CSC_RED2RED_OWNER_CORE (0x00000000)
#define NV927C_SET_CSC_RED2RED_OWNER_BASE (0x00000001)
#define NV927C_SET_CSC_RED2RED_COEFF 18:0
#define NV927C_SET_CSC_GRN2RED (0x00000144)
#define NV927C_SET_CSC_GRN2RED_COEFF 18:0
#define NV927C_SET_CSC_BLU2RED (0x00000148)
#define NV927C_SET_CSC_BLU2RED_COEFF 18:0
#define NV927C_SET_CSC_CONSTANT2RED (0x0000014C)
#define NV927C_SET_CSC_CONSTANT2RED_COEFF 18:0
#define NV927C_SET_CSC_RED2GRN (0x00000150)
#define NV927C_SET_CSC_RED2GRN_COEFF 18:0
#define NV927C_SET_CSC_GRN2GRN (0x00000154)
#define NV927C_SET_CSC_GRN2GRN_COEFF 18:0
#define NV927C_SET_CSC_BLU2GRN (0x00000158)
#define NV927C_SET_CSC_BLU2GRN_COEFF 18:0
#define NV927C_SET_CSC_CONSTANT2GRN (0x0000015C)
#define NV927C_SET_CSC_CONSTANT2GRN_COEFF 18:0
#define NV927C_SET_CSC_RED2BLU (0x00000160)
#define NV927C_SET_CSC_RED2BLU_COEFF 18:0
#define NV927C_SET_CSC_GRN2BLU (0x00000164)
#define NV927C_SET_CSC_GRN2BLU_COEFF 18:0
#define NV927C_SET_CSC_BLU2BLU (0x00000168)
#define NV927C_SET_CSC_BLU2BLU_COEFF 18:0
#define NV927C_SET_CSC_CONSTANT2BLU (0x0000016C)
#define NV927C_SET_CSC_CONSTANT2BLU_COEFF 18:0
#define NV927C_SET_SPARE (0x000003BC)
#define NV927C_SET_SPARE_UNUSED 31:0
#define NV927C_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004)
#define NV927C_SET_SPARE_NOOP_UNUSED 31:0
#define NV927C_SURFACE_SET_OFFSET(a,b) (0x00000400 + (a)*0x00000020 + (b)*0x00000004)
#define NV927C_SURFACE_SET_OFFSET_ORIGIN 31:0
#define NV927C_SURFACE_SET_SIZE(a) (0x00000408 + (a)*0x00000020)
#define NV927C_SURFACE_SET_SIZE_WIDTH 15:0
#define NV927C_SURFACE_SET_SIZE_HEIGHT 31:16
#define NV927C_SURFACE_SET_STORAGE(a) (0x0000040C + (a)*0x00000020)
#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV927C_SURFACE_SET_STORAGE_PITCH 20:8
#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24
#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV927C_SURFACE_SET_PARAMS(a) (0x00000410 + (a)*0x00000020)
#define NV927C_SURFACE_SET_PARAMS_FORMAT 15:8
#define NV927C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NV927C_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0
#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV927C_SURFACE_SET_PARAMS_GAMMA 2:2
#define NV927C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000)
#define NV927C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001)
#define NV927C_SURFACE_SET_PARAMS_LAYOUT 5:4
#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000)
#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001)
#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl927c_h

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/*
* Copyright (c) 1993-2012, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9470_h_
#define _cl9470_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV9470_DISPLAY (0x00009470)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9470_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9470_h_ */

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/*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9471_h_
#define _cl9471_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV9471_DISP_SF_USER 0x9471
typedef volatile struct _cl9471_tag0 {
NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */
} _Nv9471DispSfUser, Nv9471DispSfUserMap;
#define NV9471_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */
#define NV9471_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */
#define NV9471_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */
#define NV9471_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */
#define NV9471_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */
#define NV9471_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */
#define NV9471_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */
#define NV9471_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */
#define NV9471_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NV9471_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */
#define NV9471_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */
#define NV9471_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */
#define NV9471_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NV9471_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */
#define NV9471_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */
#define NV9471_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */
#define NV9471_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */
#define NV9471_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */
#define NV9471_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */
#define NV9471_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */
#define NV9471_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */
#define NV9471_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NV9471_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NV9471_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */
#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */
#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */
#define NV9471_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */
#define NV9471_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */
#define NV9471_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */
#define NV9471_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */
#define NV9471_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */
#define NV9471_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */
#define NV9471_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */
#define NV9471_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */
#define NV9471_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */
#define NV9471_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */
#define NV9471_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */
#define NV9471_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */
#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */
#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */
#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */
#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */
#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */
#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */
#define NV9471_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl9471_h_

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src/common/sdk/nvidia/inc/class/cl947d.h Normal file
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src/common/sdk/nvidia/inc/class/cl9570.h Normal file
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/*
* Copyright (c) 1993-2013, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9570_h_
#define _cl9570_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV9570_DISPLAY (0x00009570)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9570_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9570_h_ */

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src/common/sdk/nvidia/inc/class/cl9571.h Normal file
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/*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9571_h_
#define _cl9571_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV9571_DISP_SF_USER 0x9571
typedef volatile struct _cl9571_tag0 {
NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x00690FFF:0x00690000 */
} _Nv9571DispSfUser, Nv9571DispSfUserMap;
#define NV9571_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */
#define NV9571_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */
#define NV9571_SF_HDMI_INFO_IDX_GCP 0x00000003 /* */
#define NV9571_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */
#define NV9571_SF_HDMI_INFO_CTRL(i,j) (0x00690000-0x00690000+(i)*1024+(j)*64) /* RWX4A */
#define NV9571_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */
#define NV9571_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */
#define NV9571_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */
#define NV9571_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NV9571_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */
#define NV9571_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */
#define NV9571_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */
#define NV9571_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NV9571_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */
#define NV9571_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */
#define NV9571_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */
#define NV9571_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */
#define NV9571_SF_HDMI_INFO_STATUS(i,j) (0x00690004-0x00690000+(i)*1024+(j)*64) /* R--4A */
#define NV9571_SF_HDMI_INFO_STATUS__SIZE_1 4 /* */
#define NV9571_SF_HDMI_INFO_STATUS__SIZE_2 5 /* */
#define NV9571_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */
#define NV9571_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NV9571_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NV9571_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */
#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */
#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_HEADER(i) (0x00690048-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_GENERIC_HEADER__SIZE_1 4 /* */
#define NV9571_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x0069004C-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 4 /* */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x00690050-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x00690054-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 4 /* */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x00690058-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x0069005C-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 4 /* */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x00690060-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 4 /* */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x00690064-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 4 /* */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x00690068-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 4 /* */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */
#define NV9571_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GCP_SUBPACK(i) (0x006900CC-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_GCP_SUBPACK__SIZE_1 4 /* */
#define NV9571_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */
#define NV9571_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */
#define NV9571_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */
#define NV9571_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */
#define NV9571_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */
#define NV9571_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_HEADER(i) (0x00690108-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_VSI_HEADER__SIZE_1 4 /* */
#define NV9571_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */
#define NV9571_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */
#define NV9571_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */
#define NV9571_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x0069010C-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 4 /* */
#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x00690110-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x00690114-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 4 /* */
#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x00690118-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x0069011C-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 4 /* */
#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x00690120-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 4 /* */
#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x00690124-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 4 /* */
#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x00690128-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 4 /* */
#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */
#define NV9571_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl9571_h_

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/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9770_h_
#define _cl9770_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV9770_DISPLAY (0x00009770)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9770_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9770_h_ */

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/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9870_h_
#define _cl9870_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV9870_DISPLAY (0x00009870)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9870_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9870_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#ifndef _cla06c_h_
#define _cla06c_h_
#ifdef __cplusplus
extern "C" {
#endif
#define KEPLER_CHANNEL_GROUP_A (0x0000A06C)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cla06c_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clA06f_h_
#define _clA06f_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
/* class KEPLER_CHANNEL_GPFIFO */
/*
* Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
* chapter "User Control Registers". It is documented as device NV_UDMA.
* The GPFIFO format itself is also documented in dev_pbdma.ref,
* NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
* chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
*
*/
#define KEPLER_CHANNEL_GPFIFO_A (0x0000A06F)
/* pio method data structure */
typedef volatile struct _cla06f_tag0 {
NvV32 Reserved00[0x7c0];
} NvA06FTypedef, KEPLER_ChannelGPFifo;
#define NVA06F_TYPEDEF KEPLER_CHANNELChannelGPFifo
/* dma flow control data structure */
typedef volatile struct _cla06f_tag1 {
NvU32 Ignored00[0x010]; /* 0000-0043*/
NvU32 Put; /* put offset, read/write 0040-0043*/
NvU32 Get; /* get offset, read only 0044-0047*/
NvU32 Reference; /* reference value, read only 0048-004b*/
NvU32 PutHi; /* high order put offset bits 004c-004f*/
NvU32 Ignored01[0x002]; /* 0050-0057*/
NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
NvU32 GetHi; /* high order get offset bits 0060-0063*/
NvU32 Ignored02[0x007]; /* 0064-007f*/
NvU32 Ignored03; /* used to be engine yield 0080-0083*/
NvU32 Ignored04[0x001]; /* 0084-0087*/
NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
NvU32 Ignored05[0x5c];
} NvA06FControl, KeplerAControlGPFifo;
/* fields and values */
#define NVA06F_NUMBER_OF_SUBCHANNELS (8)
#define NVA06F_SET_OBJECT (0x00000000)
#define NVA06F_SET_OBJECT_NVCLASS 15:0
#define NVA06F_SET_OBJECT_ENGINE 20:16
#define NVA06F_SET_OBJECT_ENGINE_SW 0x0000001f
#define NVA06F_ILLEGAL (0x00000004)
#define NVA06F_ILLEGAL_HANDLE 31:0
#define NVA06F_NOP (0x00000008)
#define NVA06F_NOP_HANDLE 31:0
#define NVA06F_SEMAPHOREA (0x00000010)
#define NVA06F_SEMAPHOREA_OFFSET_UPPER 7:0
#define NVA06F_SEMAPHOREB (0x00000014)
#define NVA06F_SEMAPHOREB_OFFSET_LOWER 31:2
#define NVA06F_SEMAPHOREC (0x00000018)
#define NVA06F_SEMAPHOREC_PAYLOAD 31:0
#define NVA06F_SEMAPHORED (0x0000001C)
#define NVA06F_SEMAPHORED_OPERATION 3:0
#define NVA06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
#define NVA06F_SEMAPHORED_OPERATION_RELEASE 0x00000002
#define NVA06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
#define NVA06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH 12:12
#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
#define NVA06F_SEMAPHORED_RELEASE_WFI 20:20
#define NVA06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
#define NVA06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
#define NVA06F_SEMAPHORED_RELEASE_SIZE 24:24
#define NVA06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
#define NVA06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
#define NVA06F_NON_STALL_INTERRUPT (0x00000020)
#define NVA06F_NON_STALL_INTERRUPT_HANDLE 31:0
#define NVA06F_FB_FLUSH (0x00000024)
#define NVA06F_FB_FLUSH_HANDLE 31:0
#define NVA06F_MEM_OP_A (0x00000028)
#define NVA06F_MEM_OP_A_OPERAND_LOW 31:2
#define NVA06F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2
#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30
#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000
#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002
#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003
#define NVA06F_MEM_OP_B (0x0000002c)
#define NVA06F_MEM_OP_B_OPERAND_HIGH 7:0
#define NVA06F_MEM_OP_B_OPERATION 31:27
#define NVA06F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005
#define NVA06F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006
#define NVA06F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009
#define NVA06F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
#define NVA06F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
#define NVA06F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
#define NVA06F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010
#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0
#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000
#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001
#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1
#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000
#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001
#define NVA06F_SET_REFERENCE (0x00000050)
#define NVA06F_SET_REFERENCE_COUNT 31:0
#define NVA06F_CRC_CHECK (0x0000007c)
#define NVA06F_CRC_CHECK_VALUE 31:0
#define NVA06F_YIELD (0x00000080)
#define NVA06F_YIELD_OP 1:0
#define NVA06F_YIELD_OP_NOP 0x00000000
/* GPFIFO entry format */
#define NVA06F_GP_ENTRY__SIZE 8
#define NVA06F_GP_ENTRY0_FETCH 0:0
#define NVA06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
#define NVA06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
#define NVA06F_GP_ENTRY0_GET 31:2
#define NVA06F_GP_ENTRY0_OPERAND 31:0
#define NVA06F_GP_ENTRY1_GET_HI 7:0
#define NVA06F_GP_ENTRY1_PRIV 8:8
#define NVA06F_GP_ENTRY1_PRIV_USER 0x00000000
#define NVA06F_GP_ENTRY1_PRIV_KERNEL 0x00000001
#define NVA06F_GP_ENTRY1_LEVEL 9:9
#define NVA06F_GP_ENTRY1_LEVEL_MAIN 0x00000000
#define NVA06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
#define NVA06F_GP_ENTRY1_LENGTH 30:10
#define NVA06F_GP_ENTRY1_SYNC 31:31
#define NVA06F_GP_ENTRY1_SYNC_PROCEED 0x00000000
#define NVA06F_GP_ENTRY1_SYNC_WAIT 0x00000001
#define NVA06F_GP_ENTRY1_OPCODE 7:0
#define NVA06F_GP_ENTRY1_OPCODE_NOP 0x00000000
#define NVA06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
#define NVA06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
#define NVA06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
/* dma method formats */
#define NVA06F_DMA_METHOD_ADDRESS_OLD 12:2
#define NVA06F_DMA_METHOD_ADDRESS 11:0
#define NVA06F_DMA_SUBDEVICE_MASK 15:4
#define NVA06F_DMA_METHOD_SUBCHANNEL 15:13
#define NVA06F_DMA_TERT_OP 17:16
#define NVA06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
#define NVA06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
#define NVA06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
#define NVA06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
#define NVA06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
#define NVA06F_DMA_METHOD_COUNT_OLD 28:18
#define NVA06F_DMA_METHOD_COUNT 28:16
#define NVA06F_DMA_IMMD_DATA 28:16
#define NVA06F_DMA_SEC_OP 31:29
#define NVA06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
#define NVA06F_DMA_SEC_OP_INC_METHOD (0x00000001)
#define NVA06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
#define NVA06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
#define NVA06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
#define NVA06F_DMA_SEC_OP_ONE_INC (0x00000005)
#define NVA06F_DMA_SEC_OP_RESERVED6 (0x00000006)
#define NVA06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
/* dma incrementing method format */
#define NVA06F_DMA_INCR_ADDRESS 11:0
#define NVA06F_DMA_INCR_SUBCHANNEL 15:13
#define NVA06F_DMA_INCR_COUNT 28:16
#define NVA06F_DMA_INCR_OPCODE 31:29
#define NVA06F_DMA_INCR_OPCODE_VALUE (0x00000001)
#define NVA06F_DMA_INCR_DATA 31:0
/* dma non-incrementing method format */
#define NVA06F_DMA_NONINCR_ADDRESS 11:0
#define NVA06F_DMA_NONINCR_SUBCHANNEL 15:13
#define NVA06F_DMA_NONINCR_COUNT 28:16
#define NVA06F_DMA_NONINCR_OPCODE 31:29
#define NVA06F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
#define NVA06F_DMA_NONINCR_DATA 31:0
/* dma increment-once method format */
#define NVA06F_DMA_ONEINCR_ADDRESS 11:0
#define NVA06F_DMA_ONEINCR_SUBCHANNEL 15:13
#define NVA06F_DMA_ONEINCR_COUNT 28:16
#define NVA06F_DMA_ONEINCR_OPCODE 31:29
#define NVA06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
#define NVA06F_DMA_ONEINCR_DATA 31:0
/* dma no-operation format */
#define NVA06F_DMA_NOP (0x00000000)
/* dma immediate-data format */
#define NVA06F_DMA_IMMD_ADDRESS 11:0
#define NVA06F_DMA_IMMD_SUBCHANNEL 15:13
#define NVA06F_DMA_IMMD_DATA 28:16
#define NVA06F_DMA_IMMD_OPCODE 31:29
#define NVA06F_DMA_IMMD_OPCODE_VALUE (0x00000004)
/* dma set sub-device mask format */
#define NVA06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
#define NVA06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
#define NVA06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
/* dma store sub-device mask format */
#define NVA06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
#define NVA06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
#define NVA06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
/* dma use sub-device mask format */
#define NVA06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
#define NVA06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
/* dma end-segment format */
#define NVA06F_DMA_ENDSEG_OPCODE 31:29
#define NVA06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
/* dma legacy incrementing/non-incrementing formats */
#define NVA06F_DMA_ADDRESS 12:2
#define NVA06F_DMA_SUBCH 15:13
#define NVA06F_DMA_OPCODE3 17:16
#define NVA06F_DMA_OPCODE3_NONE (0x00000000)
#define NVA06F_DMA_COUNT 28:18
#define NVA06F_DMA_OPCODE 31:29
#define NVA06F_DMA_OPCODE_METHOD (0x00000000)
#define NVA06F_DMA_OPCODE_NONINC_METHOD (0x00000002)
#define NVA06F_DMA_DATA 31:0
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _clA06F_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cla06fsubch_h_
#define _cla06fsubch_h_
#define NVA06F_SUBCHANNEL_2D 3
#define NVA06F_SUBCHANNEL_COPY_ENGINE 4
#endif // _cla06fsubch_h_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cla06f_sw_h_
#define _cla06f_sw_h_
#define NVA06F_NOTIFIERS_RC (0)
#define NVA06F_NOTIFIERS_REFCNT (1)
#define NVA06F_NOTIFIERS_NONSTALL (2)
#define NVA06F_NOTIFIERS_EVENTBUFFER (3)
#define NVA06F_NOTIFIERS_IDLECHANNEL (4)
#define NVA06F_NOTIFIERS_ENDCTX (5)
#define NVA06F_NOTIFIERS_SW (6)
#define NVA06F_NOTIFIERS_GR_DEBUG_INTR (7)
#define NVA06F_NOTIFIERS_MAXCOUNT (8)
/* NvNotification[] fields and values */
#define NVA06F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
#define NVA06F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
#endif /* _cla06f_sw_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cla097_h_
#define _cla097_h_
#define KEPLER_A 0xA097
#endif // _cla097_h_

39
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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#ifndef _cla0b0_h_
#define _cla0b0_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVA0B0_VIDEO_DECODER (0x0000A0B0)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cla0b0_h

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/*******************************************************************************
Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
#include "nvtypes.h"
#ifndef _cla0b5_h_
#define _cla0b5_h_
#ifdef __cplusplus
extern "C" {
#endif
#define KEPLER_DMA_COPY_A (0x0000A0B5)
#define NVA0B5_NOP (0x00000100)
#define NVA0B5_NOP_PARAMETER 31:0
#define NVA0B5_PM_TRIGGER (0x00000140)
#define NVA0B5_PM_TRIGGER_V 31:0
#define NVA0B5_SET_SEMAPHORE_A (0x00000240)
#define NVA0B5_SET_SEMAPHORE_A_UPPER 7:0
#define NVA0B5_SET_SEMAPHORE_B (0x00000244)
#define NVA0B5_SET_SEMAPHORE_B_LOWER 31:0
#define NVA0B5_SET_SEMAPHORE_PAYLOAD (0x00000248)
#define NVA0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0
#define NVA0B5_SET_RENDER_ENABLE_A (0x00000254)
#define NVA0B5_SET_RENDER_ENABLE_A_UPPER 7:0
#define NVA0B5_SET_RENDER_ENABLE_B (0x00000258)
#define NVA0B5_SET_RENDER_ENABLE_B_LOWER 31:0
#define NVA0B5_SET_RENDER_ENABLE_C (0x0000025C)
#define NVA0B5_SET_RENDER_ENABLE_C_MODE 2:0
#define NVA0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000)
#define NVA0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001)
#define NVA0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002)
#define NVA0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003)
#define NVA0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004)
#define NVA0B5_SET_SRC_PHYS_MODE (0x00000260)
#define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0
#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
#define NVA0B5_SET_DST_PHYS_MODE (0x00000264)
#define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0
#define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
#define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
#define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
#define NVA0B5_LAUNCH_DMA (0x00000300)
#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0
#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000)
#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001)
#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002)
#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2
#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000)
#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002)
#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5
#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000)
#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001)
#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002)
#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7
#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001)
#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8
#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001)
#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9
#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000)
#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001)
#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE 10:10
#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000)
#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001)
#define NVA0B5_LAUNCH_DMA_BYPASS_L2 11:11
#define NVA0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000)
#define NVA0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001)
#define NVA0B5_LAUNCH_DMA_SRC_TYPE 12:12
#define NVA0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000)
#define NVA0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001)
#define NVA0B5_LAUNCH_DMA_DST_TYPE 13:13
#define NVA0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000)
#define NVA0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMUL (0x0000000D)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMUL (0x0000000E)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000)
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001)
#define NVA0B5_OFFSET_IN_UPPER (0x00000400)
#define NVA0B5_OFFSET_IN_UPPER_UPPER 7:0
#define NVA0B5_OFFSET_IN_LOWER (0x00000404)
#define NVA0B5_OFFSET_IN_LOWER_VALUE 31:0
#define NVA0B5_OFFSET_OUT_UPPER (0x00000408)
#define NVA0B5_OFFSET_OUT_UPPER_UPPER 7:0
#define NVA0B5_OFFSET_OUT_LOWER (0x0000040C)
#define NVA0B5_OFFSET_OUT_LOWER_VALUE 31:0
#define NVA0B5_PITCH_IN (0x00000410)
#define NVA0B5_PITCH_IN_VALUE 31:0
#define NVA0B5_PITCH_OUT (0x00000414)
#define NVA0B5_PITCH_OUT_VALUE 31:0
#define NVA0B5_LINE_LENGTH_IN (0x00000418)
#define NVA0B5_LINE_LENGTH_IN_VALUE 31:0
#define NVA0B5_LINE_COUNT (0x0000041C)
#define NVA0B5_LINE_COUNT_VALUE 31:0
#define NVA0B5_SET_REMAP_CONST_A (0x00000700)
#define NVA0B5_SET_REMAP_CONST_A_V 31:0
#define NVA0B5_SET_REMAP_CONST_B (0x00000704)
#define NVA0B5_SET_REMAP_CONST_B_V 31:0
#define NVA0B5_SET_REMAP_COMPONENTS (0x00000708)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X 2:0
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y 6:4
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z 10:8
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W 14:12
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005)
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006)
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002)
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003)
#define NVA0B5_SET_DST_BLOCK_SIZE (0x0000070C)
#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0
#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E)
#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000)
#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4
#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000)
#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001)
#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002)
#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003)
#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8
#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000)
#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001)
#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002)
#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003)
#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004)
#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005)
#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12
#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000)
#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001)
#define NVA0B5_SET_DST_WIDTH (0x00000710)
#define NVA0B5_SET_DST_WIDTH_V 31:0
#define NVA0B5_SET_DST_HEIGHT (0x00000714)
#define NVA0B5_SET_DST_HEIGHT_V 31:0
#define NVA0B5_SET_DST_DEPTH (0x00000718)
#define NVA0B5_SET_DST_DEPTH_V 31:0
#define NVA0B5_SET_DST_LAYER (0x0000071C)
#define NVA0B5_SET_DST_LAYER_V 31:0
#define NVA0B5_SET_DST_ORIGIN (0x00000720)
#define NVA0B5_SET_DST_ORIGIN_X 15:0
#define NVA0B5_SET_DST_ORIGIN_Y 31:16
#define NVA0B5_SET_SRC_BLOCK_SIZE (0x00000728)
#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0
#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E)
#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000)
#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4
#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000)
#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001)
#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002)
#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003)
#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8
#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000)
#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001)
#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002)
#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003)
#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004)
#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005)
#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12
#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000)
#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001)
#define NVA0B5_SET_SRC_WIDTH (0x0000072C)
#define NVA0B5_SET_SRC_WIDTH_V 31:0
#define NVA0B5_SET_SRC_HEIGHT (0x00000730)
#define NVA0B5_SET_SRC_HEIGHT_V 31:0
#define NVA0B5_SET_SRC_DEPTH (0x00000734)
#define NVA0B5_SET_SRC_DEPTH_V 31:0
#define NVA0B5_SET_SRC_LAYER (0x00000738)
#define NVA0B5_SET_SRC_LAYER_V 31:0
#define NVA0B5_SET_SRC_ORIGIN (0x0000073C)
#define NVA0B5_SET_SRC_ORIGIN_X 15:0
#define NVA0B5_SET_SRC_ORIGIN_Y 31:16
#define NVA0B5_PM_TRIGGER_END (0x00001114)
#define NVA0B5_PM_TRIGGER_END_V 31:0
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cla0b5_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl_kepler_compute_a_h_
#define _cl_kepler_compute_a_h_
/* AUTO GENERATED FILE -- DO NOT EDIT */
/* Command: ../../class/bin/sw_header.pl kepler_compute_a */
#include "nvtypes.h"
#define KEPLER_COMPUTE_A 0xA0C0
#define NVA0C0_SET_OBJECT 0x0000
#define NVA0C0_SET_OBJECT_CLASS_ID 15:0
#define NVA0C0_SET_OBJECT_ENGINE_ID 20:16
#define NVA0C0_NO_OPERATION 0x0100
#define NVA0C0_NO_OPERATION_V 31:0
#define NVA0C0_SET_NOTIFY_A 0x0104
#define NVA0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0
#define NVA0C0_SET_NOTIFY_B 0x0108
#define NVA0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0
#define NVA0C0_NOTIFY 0x010c
#define NVA0C0_NOTIFY_TYPE 31:0
#define NVA0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000
#define NVA0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001
#define NVA0C0_WAIT_FOR_IDLE 0x0110
#define NVA0C0_WAIT_FOR_IDLE_V 31:0
#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130
#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0
#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134
#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0
#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138
#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0
#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000
#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001
#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002
#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003
#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004
#define NVA0C0_SEND_GO_IDLE 0x013c
#define NVA0C0_SEND_GO_IDLE_V 31:0
#define NVA0C0_PM_TRIGGER 0x0140
#define NVA0C0_PM_TRIGGER_V 31:0
#define NVA0C0_PM_TRIGGER_WFI 0x0144
#define NVA0C0_PM_TRIGGER_WFI_V 31:0
#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150
#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0
#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154
#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0
#define NVA0C0_LINE_LENGTH_IN 0x0180
#define NVA0C0_LINE_LENGTH_IN_VALUE 31:0
#define NVA0C0_LINE_COUNT 0x0184
#define NVA0C0_LINE_COUNT_VALUE 31:0
#define NVA0C0_OFFSET_OUT_UPPER 0x0188
#define NVA0C0_OFFSET_OUT_UPPER_VALUE 7:0
#define NVA0C0_OFFSET_OUT 0x018c
#define NVA0C0_OFFSET_OUT_VALUE 31:0
#define NVA0C0_PITCH_OUT 0x0190
#define NVA0C0_PITCH_OUT_VALUE 31:0
#define NVA0C0_SET_DST_BLOCK_SIZE 0x0194
#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0
#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000
#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4
#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000
#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001
#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002
#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003
#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004
#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005
#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8
#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000
#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001
#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002
#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003
#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004
#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005
#define NVA0C0_SET_DST_WIDTH 0x0198
#define NVA0C0_SET_DST_WIDTH_V 31:0
#define NVA0C0_SET_DST_HEIGHT 0x019c
#define NVA0C0_SET_DST_HEIGHT_V 31:0
#define NVA0C0_SET_DST_DEPTH 0x01a0
#define NVA0C0_SET_DST_DEPTH_V 31:0
#define NVA0C0_SET_DST_LAYER 0x01a4
#define NVA0C0_SET_DST_LAYER_V 31:0
#define NVA0C0_SET_DST_ORIGIN_BYTES_X 0x01a8
#define NVA0C0_SET_DST_ORIGIN_BYTES_X_V 19:0
#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac
#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0
#define NVA0C0_LAUNCH_DMA 0x01b0
#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0
#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000
#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001
#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4
#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000
#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001
#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002
#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8
#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000
#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001
#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12
#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000
#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001
#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1
#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000
#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001
#define NVA0C0_LAUNCH_DMA_REDUCTION_OP 15:13
#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000
#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001
#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002
#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003
#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004
#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005
#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006
#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007
#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2
#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6
#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000
#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001
#define NVA0C0_LOAD_INLINE_DATA 0x01b4
#define NVA0C0_LOAD_INLINE_DATA_V 31:0
#define NVA0C0_SET_I2M_SEMAPHORE_A 0x01dc
#define NVA0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0
#define NVA0C0_SET_I2M_SEMAPHORE_B 0x01e0
#define NVA0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0
#define NVA0C0_SET_I2M_SEMAPHORE_C 0x01e4
#define NVA0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0
#define NVA0C0_SET_I2M_SPARE_NOOP00 0x01f0
#define NVA0C0_SET_I2M_SPARE_NOOP00_V 31:0
#define NVA0C0_SET_I2M_SPARE_NOOP01 0x01f4
#define NVA0C0_SET_I2M_SPARE_NOOP01_V 31:0
#define NVA0C0_SET_I2M_SPARE_NOOP02 0x01f8
#define NVA0C0_SET_I2M_SPARE_NOOP02_V 31:0
#define NVA0C0_SET_I2M_SPARE_NOOP03 0x01fc
#define NVA0C0_SET_I2M_SPARE_NOOP03_V 31:0
#define NVA0C0_PERFMON_TRANSFER 0x0210
#define NVA0C0_PERFMON_TRANSFER_V 31:0
#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214
#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0
#define NVA0C0_INVALIDATE_SHADER_CACHES 0x021c
#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0
#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000
#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001
#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA 4:4
#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000
#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001
#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12
#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000
#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001
#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1
#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000
#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001
#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2
#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000
#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001
#define NVA0C0_SET_CWD_CONTROL 0x0240
#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION 0:0
#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000
#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001
#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244
#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0
#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000
#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001
#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4
#define NVA0C0_SET_CWD_REF_COUNTER 0x0248
#define NVA0C0_SET_CWD_REF_COUNTER_SELECT 5:0
#define NVA0C0_SET_CWD_REF_COUNTER_VALUE 23:8
#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274
#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0
#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278
#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0
#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c
#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0
#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31
#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000
#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001
#define NVA0C0_SET_COMPUTE_CLASS_VERSION 0x0280
#define NVA0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0
#define NVA0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16
#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284
#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0
#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16
#define NVA0C0_SET_QMD_VERSION 0x0288
#define NVA0C0_SET_QMD_VERSION_CURRENT 15:0
#define NVA0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16
#define NVA0C0_CHECK_QMD_VERSION 0x0290
#define NVA0C0_CHECK_QMD_VERSION_CURRENT 15:0
#define NVA0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16
#define NVA0C0_SET_CWD_SLOT_COUNT 0x02b0
#define NVA0C0_SET_CWD_SLOT_COUNT_V 7:0
#define NVA0C0_SEND_PCAS_A 0x02b4
#define NVA0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0
#define NVA0C0_SEND_PCAS_B 0x02b8
#define NVA0C0_SEND_PCAS_B_FROM 23:0
#define NVA0C0_SEND_PCAS_B_DELTA 31:24
#define NVA0C0_SEND_SIGNALING_PCAS_B 0x02bc
#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0
#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000
#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001
#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1
#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000
#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0
#define NVA0C0_SET_SPA_VERSION 0x0310
#define NVA0C0_SET_SPA_VERSION_MINOR 7:0
#define NVA0C0_SET_SPA_VERSION_MAJOR 15:8
#define NVA0C0_SET_FALCON00 0x0500
#define NVA0C0_SET_FALCON00_V 31:0
#define NVA0C0_SET_FALCON01 0x0504
#define NVA0C0_SET_FALCON01_V 31:0
#define NVA0C0_SET_FALCON02 0x0508
#define NVA0C0_SET_FALCON02_V 31:0
#define NVA0C0_SET_FALCON03 0x050c
#define NVA0C0_SET_FALCON03_V 31:0
#define NVA0C0_SET_FALCON04 0x0510
#define NVA0C0_SET_FALCON04_V 31:0
#define NVA0C0_SET_FALCON05 0x0514
#define NVA0C0_SET_FALCON05_V 31:0
#define NVA0C0_SET_FALCON06 0x0518
#define NVA0C0_SET_FALCON06_V 31:0
#define NVA0C0_SET_FALCON07 0x051c
#define NVA0C0_SET_FALCON07_V 31:0
#define NVA0C0_SET_FALCON08 0x0520
#define NVA0C0_SET_FALCON08_V 31:0
#define NVA0C0_SET_FALCON09 0x0524
#define NVA0C0_SET_FALCON09_V 31:0
#define NVA0C0_SET_FALCON10 0x0528
#define NVA0C0_SET_FALCON10_V 31:0
#define NVA0C0_SET_FALCON11 0x052c
#define NVA0C0_SET_FALCON11_V 31:0
#define NVA0C0_SET_FALCON12 0x0530
#define NVA0C0_SET_FALCON12_V 31:0
#define NVA0C0_SET_FALCON13 0x0534
#define NVA0C0_SET_FALCON13_V 31:0
#define NVA0C0_SET_FALCON14 0x0538
#define NVA0C0_SET_FALCON14_V 31:0
#define NVA0C0_SET_FALCON15 0x053c
#define NVA0C0_SET_FALCON15_V 31:0
#define NVA0C0_SET_FALCON16 0x0540
#define NVA0C0_SET_FALCON16_V 31:0
#define NVA0C0_SET_FALCON17 0x0544
#define NVA0C0_SET_FALCON17_V 31:0
#define NVA0C0_SET_FALCON18 0x0548
#define NVA0C0_SET_FALCON18_V 31:0
#define NVA0C0_SET_FALCON19 0x054c
#define NVA0C0_SET_FALCON19_V 31:0
#define NVA0C0_SET_FALCON20 0x0550
#define NVA0C0_SET_FALCON20_V 31:0
#define NVA0C0_SET_FALCON21 0x0554
#define NVA0C0_SET_FALCON21_V 31:0
#define NVA0C0_SET_FALCON22 0x0558
#define NVA0C0_SET_FALCON22_V 31:0
#define NVA0C0_SET_FALCON23 0x055c
#define NVA0C0_SET_FALCON23_V 31:0
#define NVA0C0_SET_FALCON24 0x0560
#define NVA0C0_SET_FALCON24_V 31:0
#define NVA0C0_SET_FALCON25 0x0564
#define NVA0C0_SET_FALCON25_V 31:0
#define NVA0C0_SET_FALCON26 0x0568
#define NVA0C0_SET_FALCON26_V 31:0
#define NVA0C0_SET_FALCON27 0x056c
#define NVA0C0_SET_FALCON27_V 31:0
#define NVA0C0_SET_FALCON28 0x0570
#define NVA0C0_SET_FALCON28_V 31:0
#define NVA0C0_SET_FALCON29 0x0574
#define NVA0C0_SET_FALCON29_V 31:0
#define NVA0C0_SET_FALCON30 0x0578
#define NVA0C0_SET_FALCON30_V 31:0
#define NVA0C0_SET_FALCON31 0x057c
#define NVA0C0_SET_FALCON31_V 31:0
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794
#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0
#define NVA0C0_SET_SHADER_CACHE_CONTROL 0x0d94
#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0
#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000
#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001
#define NVA0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4
#define NVA0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0
#define NVA0C0_SET_SPARE_NOOP12 0x0f44
#define NVA0C0_SET_SPARE_NOOP12_V 31:0
#define NVA0C0_SET_SPARE_NOOP13 0x0f48
#define NVA0C0_SET_SPARE_NOOP13_V 31:0
#define NVA0C0_SET_SPARE_NOOP14 0x0f4c
#define NVA0C0_SET_SPARE_NOOP14_V 31:0
#define NVA0C0_SET_SPARE_NOOP15 0x0f50
#define NVA0C0_SET_SPARE_NOOP15_V 31:0
#define NVA0C0_SET_SPARE_NOOP00 0x1040
#define NVA0C0_SET_SPARE_NOOP00_V 31:0
#define NVA0C0_SET_SPARE_NOOP01 0x1044
#define NVA0C0_SET_SPARE_NOOP01_V 31:0
#define NVA0C0_SET_SPARE_NOOP02 0x1048
#define NVA0C0_SET_SPARE_NOOP02_V 31:0
#define NVA0C0_SET_SPARE_NOOP03 0x104c
#define NVA0C0_SET_SPARE_NOOP03_V 31:0
#define NVA0C0_SET_SPARE_NOOP04 0x1050
#define NVA0C0_SET_SPARE_NOOP04_V 31:0
#define NVA0C0_SET_SPARE_NOOP05 0x1054
#define NVA0C0_SET_SPARE_NOOP05_V 31:0
#define NVA0C0_SET_SPARE_NOOP06 0x1058
#define NVA0C0_SET_SPARE_NOOP06_V 31:0
#define NVA0C0_SET_SPARE_NOOP07 0x105c
#define NVA0C0_SET_SPARE_NOOP07_V 31:0
#define NVA0C0_SET_SPARE_NOOP08 0x1060
#define NVA0C0_SET_SPARE_NOOP08_V 31:0
#define NVA0C0_SET_SPARE_NOOP09 0x1064
#define NVA0C0_SET_SPARE_NOOP09_V 31:0
#define NVA0C0_SET_SPARE_NOOP10 0x1068
#define NVA0C0_SET_SPARE_NOOP10_V 31:0
#define NVA0C0_SET_SPARE_NOOP11 0x106c
#define NVA0C0_SET_SPARE_NOOP11_V 31:0
#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288
#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0
#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000
#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001
#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4
#define NVA0C0_INVALIDATE_SAMPLER_CACHE 0x1330
#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0
#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000
#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001
#define NVA0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4
#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334
#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0
#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000
#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001
#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4
#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338
#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0
#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000
#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001
#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4
#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424
#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0
#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000
#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001
#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4
#define NVA0C0_SET_SHADER_EXCEPTIONS 0x1528
#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0
#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000
#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001
#define NVA0C0_SET_RENDER_ENABLE_A 0x1550
#define NVA0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0
#define NVA0C0_SET_RENDER_ENABLE_B 0x1554
#define NVA0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0
#define NVA0C0_SET_RENDER_ENABLE_C 0x1558
#define NVA0C0_SET_RENDER_ENABLE_C_MODE 2:0
#define NVA0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000
#define NVA0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001
#define NVA0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002
#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003
#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004
#define NVA0C0_SET_TEX_SAMPLER_POOL_A 0x155c
#define NVA0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0
#define NVA0C0_SET_TEX_SAMPLER_POOL_B 0x1560
#define NVA0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0
#define NVA0C0_SET_TEX_SAMPLER_POOL_C 0x1564
#define NVA0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0
#define NVA0C0_SET_TEX_HEADER_POOL_A 0x1574
#define NVA0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0
#define NVA0C0_SET_TEX_HEADER_POOL_B 0x1578
#define NVA0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0
#define NVA0C0_SET_TEX_HEADER_POOL_C 0x157c
#define NVA0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0
#define NVA0C0_SET_PROGRAM_REGION_A 0x1608
#define NVA0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0
#define NVA0C0_SET_PROGRAM_REGION_B 0x160c
#define NVA0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0
#define NVA0C0_SET_SHADER_CONTROL 0x1690
#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0
#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000
#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001
#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698
#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0
#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000
#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001
#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4
#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000
#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001
#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12
#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000
#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001
#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944
#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0
#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000
#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001
#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002
#define NVA0C0_PIPE_NOP 0x1a2c
#define NVA0C0_PIPE_NOP_V 31:0
#define NVA0C0_SET_SPARE00 0x1a30
#define NVA0C0_SET_SPARE00_V 31:0
#define NVA0C0_SET_SPARE01 0x1a34
#define NVA0C0_SET_SPARE01_V 31:0
#define NVA0C0_SET_SPARE02 0x1a38
#define NVA0C0_SET_SPARE02_V 31:0
#define NVA0C0_SET_SPARE03 0x1a3c
#define NVA0C0_SET_SPARE03_V 31:0
#define NVA0C0_SET_REPORT_SEMAPHORE_A 0x1b00
#define NVA0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0
#define NVA0C0_SET_REPORT_SEMAPHORE_B 0x1b04
#define NVA0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0
#define NVA0C0_SET_REPORT_SEMAPHORE_C 0x1b08
#define NVA0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0
#define NVA0C0_SET_REPORT_SEMAPHORE_D 0x1b0c
#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0
#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000
#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003
#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20
#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000
#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001
#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28
#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001
#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2
#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000
#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVA0C0_SET_BINDLESS_TEXTURE 0x2608
#define NVA0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0
#define NVA0C0_SET_TRAP_HANDLER 0x260c
#define NVA0C0_SET_TRAP_HANDLER_OFFSET 31:0
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4)
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4)
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4)
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4)
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc
#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0
#define NVA0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4)
#define NVA0C0_SET_MME_SHADOW_SCRATCH_V 31:0
#endif /* _cl_kepler_compute_a_h_ */

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src/common/sdk/nvidia/inc/class/cla0c0qmd.h Normal file
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@@ -0,0 +1,658 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __CLA0C0QMD_H__
#define __CLA0C0QMD_H__
/*
** Queue Meta Data, Version 00_06
*/
// The below C preprocessor definitions describe "multi-word" structures, where
// fields may have bit numbers beyond 32. For example, MW(127:96) means
// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)"
// syntax is to distinguish from similar "X:Y" single-word definitions: the
// macros historically used for single-word definitions would fail with
// multi-word definitions.
//
// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel
// interface layer of nvidia.ko for an example of how to manipulate
// these MW(X:Y) definitions.
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127)
#define NVA0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192)
#define NVA0C0_QMDV00_06_QMD_RESERVED_A MW(199:197)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001
#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202)
#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000
#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001
#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203)
#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000
#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001
#define NVA0C0_QMDV00_06_QMD_RESERVED_B MW(207:204)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224)
#define NVA0C0_QMDV00_06_QMD_RESERVED_C MW(249:249)
#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250)
#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251)
#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252)
#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253)
#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254)
#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255)
#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320)
#define NVA0C0_QMDV00_06_QMD_RESERVED_D MW(335:328)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352)
#define NVA0C0_QMDV00_06_QMD_RESERVED_E MW(365:358)
#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366)
#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368)
#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001
#define NVA0C0_QMDV00_06_THROTTLED MW(372:372)
#define NVA0C0_QMDV00_06_THROTTLED_FALSE 0x00000000
#define NVA0C0_QMDV00_06_THROTTLED_TRUE 0x00000001
#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376)
#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377)
#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378)
#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000
#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379)
#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000
#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001
#define NVA0C0_QMDV00_06_SAMPLER_INDEX MW(382:382)
#define NVA0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
#define NVA0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
#define NVA0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383)
#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384)
#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416)
#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432)
#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448)
#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480)
#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512)
#define NVA0C0_QMDV00_06_QMD_RESERVED_F MW(542:536)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001
#define NVA0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544)
#define NVA0C0_QMDV00_06_QMD_RESERVED_G MW(575:562)
#define NVA0C0_QMDV00_06_QMD_VERSION MW(579:576)
#define NVA0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580)
#define NVA0C0_QMDV00_06_QMD_RESERVED_H MW(591:584)
#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592)
#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608)
#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624)
#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1))
#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000
#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001
#define NVA0C0_QMDV00_06_QMD_RESERVED_I MW(668:648)
#define NVA0C0_QMDV00_06_L1_CONFIGURATION MW(671:669)
#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001
#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002
#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672)
#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704)
#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736)
#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768)
#define NVA0C0_QMDV00_06_QMD_RESERVED_J MW(783:776)
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788)
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007
#define NVA0C0_QMDV00_06_QMD_RESERVED_K MW(791:791)
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792)
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794)
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799)
#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001
#define NVA0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800)
#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832)
#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864)
#define NVA0C0_QMDV00_06_QMD_RESERVED_L MW(879:872)
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884)
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007
#define NVA0C0_QMDV00_06_QMD_RESERVED_M MW(887:887)
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888)
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890)
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895)
#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001
#define NVA0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896)
#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64))
#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64))
#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64))
#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64))
#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64))
#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440)
#define NVA0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464)
#define NVA0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467)
#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472)
#define NVA0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496)
#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504)
#define NVA0C0_QMDV00_06_SASS_VERSION MW(1535:1528)
#define NVA0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536)
#define NVA0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568)
#define NVA0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600)
#define NVA0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632)
#define NVA0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664)
#define NVA0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696)
#define NVA0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728)
#define NVA0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760)
#define NVA0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792)
#define NVA0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824)
#define NVA0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856)
#define NVA0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888)
#define NVA0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920)
#define NVA0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952)
#define NVA0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984)
#define NVA0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016)
/*
** Queue Meta Data, Version 01_06
*/
#define NVA0C0_QMDV01_06_OUTER_PUT MW(30:0)
#define NVA0C0_QMDV01_06_OUTER_OVERFLOW MW(31:31)
#define NVA0C0_QMDV01_06_OUTER_GET MW(62:32)
#define NVA0C0_QMDV01_06_OUTER_STICKY_OVERFLOW MW(63:63)
#define NVA0C0_QMDV01_06_INNER_GET MW(94:64)
#define NVA0C0_QMDV01_06_INNER_OVERFLOW MW(95:95)
#define NVA0C0_QMDV01_06_INNER_PUT MW(126:96)
#define NVA0C0_QMDV01_06_INNER_STICKY_OVERFLOW MW(127:127)
#define NVA0C0_QMDV01_06_QMD_RESERVED_A_A MW(159:128)
#define NVA0C0_QMDV01_06_SCHEDULER_NEXT_QMD_POINTER MW(191:160)
#define NVA0C0_QMDV01_06_QMD_GROUP_ID MW(197:192)
#define NVA0C0_QMDV01_06_QMD_RESERVED_A MW(199:198)
#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(200:200)
#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201)
#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202)
#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000
#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001
#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203)
#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000
#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001
#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS MW(204:204)
#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000
#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001
#define NVA0C0_QMDV01_06_QMD_RESERVED_B MW(207:205)
#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_ADDR MW(222:208)
#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID MW(223:223)
#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_FALSE 0x00000000
#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_TRUE 0x00000001
#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_SIZE MW(248:224)
#define NVA0C0_QMDV01_06_QMD_RESERVED_C MW(249:249)
#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250)
#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251)
#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252)
#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253)
#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254)
#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255)
#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_PROGRAM_OFFSET MW(287:256)
#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288)
#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320)
#define NVA0C0_QMDV01_06_QMD_RESERVED_D MW(335:328)
#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336)
#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_ID MW(357:352)
#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358)
#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE MW(366:366)
#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367)
#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE MW(369:368)
#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS MW(370:370)
#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000
#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001
#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371)
#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_THROTTLED MW(372:372)
#define NVA0C0_QMDV01_06_THROTTLED_FALSE 0x00000000
#define NVA0C0_QMDV01_06_THROTTLED_TRUE 0x00000001
#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR MW(376:376)
#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_LEGACY 0x00000000
#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001
#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR MW(377:377)
#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000
#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001
#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT MW(378:378)
#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT__32 0x00000000
#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING MW(379:379)
#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000
#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001
#define NVA0C0_QMDV01_06_SAMPLER_INDEX MW(382:382)
#define NVA0C0_QMDV01_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
#define NVA0C0_QMDV01_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION MW(383:383)
#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000
#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001
#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH MW(415:384)
#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT MW(431:416)
#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH MW(447:432)
#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH_RESUME MW(479:448)
#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT_RESUME MW(495:480)
#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH_RESUME MW(511:496)
#define NVA0C0_QMDV01_06_LAUNCH_QUOTA MW(535:512)
#define NVA0C0_QMDV01_06_QMD_RESERVED_F MW(542:536)
#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE MW(543:543)
#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_SHARED_MEMORY_SIZE MW(561:544)
#define NVA0C0_QMDV01_06_QMD_RESERVED_G MW(575:562)
#define NVA0C0_QMDV01_06_QMD_VERSION MW(579:576)
#define NVA0C0_QMDV01_06_QMD_MAJOR_VERSION MW(583:580)
#define NVA0C0_QMDV01_06_QMD_RESERVED_H MW(591:584)
#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION0 MW(607:592)
#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION1 MW(623:608)
#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION2 MW(639:624)
#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1))
#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000
#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001
#define NVA0C0_QMDV01_06_QMD_RESERVED_I MW(668:648)
#define NVA0C0_QMDV01_06_L1_CONFIGURATION MW(671:669)
#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001
#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002
#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003
#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_LOWER MW(703:672)
#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_UPPER MW(735:704)
#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_LOWER MW(767:736)
#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_UPPER MW(775:768)
#define NVA0C0_QMDV01_06_QMD_RESERVED_J MW(783:776)
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP MW(790:788)
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007
#define NVA0C0_QMDV01_06_QMD_RESERVED_K MW(791:791)
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT MW(793:792)
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE MW(794:794)
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE MW(799:799)
#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001
#define NVA0C0_QMDV01_06_RELEASE0_PAYLOAD MW(831:800)
#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_LOWER MW(863:832)
#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_UPPER MW(871:864)
#define NVA0C0_QMDV01_06_QMD_RESERVED_L MW(879:872)
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP MW(886:884)
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007
#define NVA0C0_QMDV01_06_QMD_RESERVED_M MW(887:887)
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT MW(889:888)
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE MW(890:890)
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE MW(895:895)
#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001
#define NVA0C0_QMDV01_06_RELEASE1_PAYLOAD MW(927:896)
#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64))
#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64))
#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64))
#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64))
#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64))
#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440)
#define NVA0C0_QMDV01_06_QMD_RESERVED_N MW(1466:1464)
#define NVA0C0_QMDV01_06_BARRIER_COUNT MW(1471:1467)
#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472)
#define NVA0C0_QMDV01_06_REGISTER_COUNT MW(1503:1496)
#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504)
#define NVA0C0_QMDV01_06_SASS_VERSION MW(1535:1528)
#define NVA0C0_QMDV01_06_HW_ONLY_INNER_GET MW(1566:1536)
#define NVA0C0_QMDV01_06_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567)
#define NVA0C0_QMDV01_06_HW_ONLY_INNER_PUT MW(1598:1568)
#define NVA0C0_QMDV01_06_HW_ONLY_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(1599:1599)
#define NVA0C0_QMDV01_06_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(1606:1600)
#define NVA0C0_QMDV01_06_QMD_RESERVED_Q MW(1609:1607)
#define NVA0C0_QMDV01_06_COALESCE_WAITING_PERIOD MW(1617:1610)
#define NVA0C0_QMDV01_06_QMD_RESERVED_R MW(1631:1618)
#define NVA0C0_QMDV01_06_QMD_SPARE_D MW(1663:1632)
#define NVA0C0_QMDV01_06_QMD_SPARE_E MW(1695:1664)
#define NVA0C0_QMDV01_06_QMD_SPARE_F MW(1727:1696)
#define NVA0C0_QMDV01_06_QMD_SPARE_G MW(1759:1728)
#define NVA0C0_QMDV01_06_QMD_SPARE_H MW(1791:1760)
#define NVA0C0_QMDV01_06_QMD_SPARE_I MW(1823:1792)
#define NVA0C0_QMDV01_06_QMD_SPARE_J MW(1855:1824)
#define NVA0C0_QMDV01_06_QMD_SPARE_K MW(1887:1856)
#define NVA0C0_QMDV01_06_QMD_SPARE_L MW(1919:1888)
#define NVA0C0_QMDV01_06_QMD_SPARE_M MW(1951:1920)
#define NVA0C0_QMDV01_06_QMD_SPARE_N MW(1983:1952)
#define NVA0C0_QMDV01_06_DEBUG_ID_UPPER MW(2015:1984)
#define NVA0C0_QMDV01_06_DEBUG_ID_LOWER MW(2047:2016)
/*
** Queue Meta Data, Version 01_07
*/
#define NVA0C0_QMDV01_07_OUTER_PUT MW(30:0)
#define NVA0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31)
#define NVA0C0_QMDV01_07_OUTER_GET MW(62:32)
#define NVA0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63)
#define NVA0C0_QMDV01_07_INNER_GET MW(94:64)
#define NVA0C0_QMDV01_07_INNER_OVERFLOW MW(95:95)
#define NVA0C0_QMDV01_07_INNER_PUT MW(126:96)
#define NVA0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127)
#define NVA0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128)
#define NVA0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160)
#define NVA0C0_QMDV01_07_QMD_GROUP_ID MW(197:192)
#define NVA0C0_QMDV01_07_QMD_RESERVED_A MW(200:198)
#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201)
#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202)
#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000
#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001
#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203)
#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000
#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001
#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204)
#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000
#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001
#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205)
#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206)
#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000
#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001
#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207)
#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000
#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001
#define NVA0C0_QMDV01_07_QMD_RESERVED_B MW(223:208)
#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224)
#define NVA0C0_QMDV01_07_QMD_RESERVED_C MW(249:249)
#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250)
#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251)
#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252)
#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253)
#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254)
#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255)
#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
#define NVA0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256)
#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288)
#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320)
#define NVA0C0_QMDV01_07_QMD_RESERVED_D MW(335:328)
#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336)
#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352)
#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358)
#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366)
#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367)
#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368)
#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370)
#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000
#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001
#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371)
#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV01_07_THROTTLED MW(372:372)
#define NVA0C0_QMDV01_07_THROTTLED_FALSE 0x00000000
#define NVA0C0_QMDV01_07_THROTTLED_TRUE 0x00000001
#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376)
#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000
#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001
#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377)
#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000
#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001
#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378)
#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000
#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379)
#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000
#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001
#define NVA0C0_QMDV01_07_SAMPLER_INDEX MW(382:382)
#define NVA0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
#define NVA0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383)
#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000
#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001
#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384)
#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416)
#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432)
#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448)
#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480)
#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496)
#define NVA0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512)
#define NVA0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522)
#define NVA0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544)
#define NVA0C0_QMDV01_07_QMD_RESERVED_G MW(575:562)
#define NVA0C0_QMDV01_07_QMD_VERSION MW(579:576)
#define NVA0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580)
#define NVA0C0_QMDV01_07_QMD_RESERVED_H MW(591:584)
#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592)
#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608)
#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624)
#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1))
#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000
#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001
#define NVA0C0_QMDV01_07_QMD_RESERVED_I MW(668:648)
#define NVA0C0_QMDV01_07_L1_CONFIGURATION MW(671:669)
#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001
#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002
#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003
#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672)
#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704)
#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736)
#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768)
#define NVA0C0_QMDV01_07_QMD_RESERVED_J MW(783:776)
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788)
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007
#define NVA0C0_QMDV01_07_QMD_RESERVED_K MW(791:791)
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792)
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794)
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799)
#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001
#define NVA0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800)
#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832)
#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864)
#define NVA0C0_QMDV01_07_QMD_RESERVED_L MW(879:872)
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884)
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007
#define NVA0C0_QMDV01_07_QMD_RESERVED_M MW(887:887)
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888)
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890)
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000
#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001
#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895)
#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001
#define NVA0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896)
#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64))
#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64))
#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64))
#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64))
#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64))
#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440)
#define NVA0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464)
#define NVA0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467)
#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472)
#define NVA0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496)
#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504)
#define NVA0C0_QMDV01_07_SASS_VERSION MW(1535:1528)
#define NVA0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536)
#define NVA0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567)
#define NVA0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568)
#define NVA0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599)
#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600)
#define NVA0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630)
#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631)
#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000
#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001
#define NVA0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632)
#define NVA0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664)
#define NVA0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696)
#define NVA0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728)
#define NVA0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760)
#define NVA0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792)
#define NVA0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824)
#define NVA0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856)
#define NVA0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888)
#define NVA0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920)
#define NVA0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952)
#define NVA0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984)
#define NVA0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016)
#endif // #ifndef __CLA0C0QMD_H__

29
src/common/sdk/nvidia/inc/class/cla140.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cla140_h_
#define _cla140_h_
#define KEPLER_INLINE_TO_MEMORY_B 0xA140
#endif // _cla140_h_

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src/common/sdk/nvidia/inc/class/cla16f.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cla16f_h_
#define _cla16f_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
/* class KEPLER_CHANNEL_GPFIFO */
/*
* Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
* chapter "User Control Registers". It is documented as device NV_UDMA.
* The GPFIFO format itself is also documented in dev_pbdma.ref,
* NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
* chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
*
*/
#define KEPLER_CHANNEL_GPFIFO_B (0x0000A16F)
/* pio method data structure */
typedef volatile struct _cla16f_tag0 {
NvV32 Reserved00[0x7c0];
} NvA16FTypedef, KEPLER_ChannelGPFifoB;
#define NVA16F_TYPEDEF KEPLER_CHANNELChannelGPFifo
/* dma flow control data structure */
typedef volatile struct _cla16f_tag1 {
NvU32 Ignored00[0x010]; /* 0000-003f*/
NvU32 Put; /* put offset, read/write 0040-0043*/
NvU32 Get; /* get offset, read only 0044-0047*/
NvU32 Reference; /* reference value, read only 0048-004b*/
NvU32 PutHi; /* high order put offset bits 004c-004f*/
NvU32 Ignored01[0x002]; /* 0050-0057*/
NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
NvU32 GetHi; /* high order get offset bits 0060-0063*/
NvU32 Ignored02[0x007]; /* 0064-007f*/
NvU32 Ignored03; /* used to be engine yield 0080-0083*/
NvU32 Ignored04[0x001]; /* 0084-0087*/
NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
NvU32 Ignored05[0x5c];
} NvA16FControl, KeplerBControlGPFifo;
/* fields and values */
#define NVA16F_NUMBER_OF_SUBCHANNELS (8)
#define NVA16F_SET_OBJECT (0x00000000)
#define NVA16F_SET_OBJECT_NVCLASS 15:0
#define NVA16F_SET_OBJECT_ENGINE 20:16
#define NVA16F_SET_OBJECT_ENGINE_SW 0x0000001f
#define NVA16F_ILLEGAL (0x00000004)
#define NVA16F_ILLEGAL_HANDLE 31:0
#define NVA16F_NOP (0x00000008)
#define NVA16F_NOP_HANDLE 31:0
#define NVA16F_SEMAPHOREA (0x00000010)
#define NVA16F_SEMAPHOREA_OFFSET_UPPER 7:0
#define NVA16F_SEMAPHOREB (0x00000014)
#define NVA16F_SEMAPHOREB_OFFSET_LOWER 31:2
#define NVA16F_SEMAPHOREC (0x00000018)
#define NVA16F_SEMAPHOREC_PAYLOAD 31:0
#define NVA16F_SEMAPHORED (0x0000001C)
#define NVA16F_SEMAPHORED_OPERATION 4:0
#define NVA16F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
#define NVA16F_SEMAPHORED_OPERATION_RELEASE 0x00000002
#define NVA16F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
#define NVA16F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
#define NVA16F_SEMAPHORED_OPERATION_REDUCTION 0x00000010
#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH 12:12
#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
#define NVA16F_SEMAPHORED_RELEASE_WFI 20:20
#define NVA16F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
#define NVA16F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
#define NVA16F_SEMAPHORED_RELEASE_SIZE 24:24
#define NVA16F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
#define NVA16F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
#define NVA16F_SEMAPHORED_REDUCTION 30:27
#define NVA16F_SEMAPHORED_REDUCTION_MIN 0x00000000
#define NVA16F_SEMAPHORED_REDUCTION_MAX 0x00000001
#define NVA16F_SEMAPHORED_REDUCTION_XOR 0x00000002
#define NVA16F_SEMAPHORED_REDUCTION_AND 0x00000003
#define NVA16F_SEMAPHORED_REDUCTION_OR 0x00000004
#define NVA16F_SEMAPHORED_REDUCTION_ADD 0x00000005
#define NVA16F_SEMAPHORED_REDUCTION_INC 0x00000006
#define NVA16F_SEMAPHORED_REDUCTION_DEC 0x00000007
#define NVA16F_SEMAPHORED_FORMAT 31:31
#define NVA16F_SEMAPHORED_FORMAT_SIGNED 0x00000000
#define NVA16F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001
#define NVA16F_NON_STALL_INTERRUPT (0x00000020)
#define NVA16F_NON_STALL_INTERRUPT_HANDLE 31:0
#define NVA16F_FB_FLUSH (0x00000024)
#define NVA16F_FB_FLUSH_HANDLE 31:0
#define NVA16F_MEM_OP_A (0x00000028)
#define NVA16F_MEM_OP_A_OPERAND_LOW 31:2
#define NVA16F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2
#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30
#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000
#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002
#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003
#define NVA16F_MEM_OP_B (0x0000002c)
#define NVA16F_MEM_OP_B_OPERAND_HIGH 7:0
#define NVA16F_MEM_OP_B_OPERATION 31:27
#define NVA16F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005
#define NVA16F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006
#define NVA16F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009
#define NVA16F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
#define NVA16F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
#define NVA16F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
#define NVA16F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010
#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0
#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000
#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001
#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1
#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000
#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001
#define NVA16F_SET_REFERENCE (0x00000050)
#define NVA16F_SET_REFERENCE_COUNT 31:0
#define NVA16F_WFI (0x00000078)
#define NVA16F_WFI_HANDLE 31:0
#define NVA16F_CRC_CHECK (0x0000007c)
#define NVA16F_CRC_CHECK_VALUE 31:0
#define NVA16F_YIELD (0x00000080)
#define NVA16F_YIELD_OP 1:0
#define NVA16F_YIELD_OP_NOP 0x00000000
/* GPFIFO entry format */
#define NVA16F_GP_ENTRY__SIZE 8
#define NVA16F_GP_ENTRY0_FETCH 0:0
#define NVA16F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
#define NVA16F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
#define NVA16F_GP_ENTRY0_GET 31:2
#define NVA16F_GP_ENTRY0_OPERAND 31:0
#define NVA16F_GP_ENTRY1_GET_HI 7:0
#define NVA16F_GP_ENTRY1_PRIV 8:8
#define NVA16F_GP_ENTRY1_PRIV_USER 0x00000000
#define NVA16F_GP_ENTRY1_PRIV_KERNEL 0x00000001
#define NVA16F_GP_ENTRY1_LEVEL 9:9
#define NVA16F_GP_ENTRY1_LEVEL_MAIN 0x00000000
#define NVA16F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
#define NVA16F_GP_ENTRY1_LENGTH 30:10
#define NVA16F_GP_ENTRY1_SYNC 31:31
#define NVA16F_GP_ENTRY1_SYNC_PROCEED 0x00000000
#define NVA16F_GP_ENTRY1_SYNC_WAIT 0x00000001
#define NVA16F_GP_ENTRY1_OPCODE 7:0
#define NVA16F_GP_ENTRY1_OPCODE_NOP 0x00000000
#define NVA16F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
#define NVA16F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
#define NVA16F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
/* dma method formats */
#define NVA16F_DMA_METHOD_ADDRESS_OLD 12:2
#define NVA16F_DMA_METHOD_ADDRESS 11:0
#define NVA16F_DMA_SUBDEVICE_MASK 15:4
#define NVA16F_DMA_METHOD_SUBCHANNEL 15:13
#define NVA16F_DMA_TERT_OP 17:16
#define NVA16F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
#define NVA16F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
#define NVA16F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
#define NVA16F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
#define NVA16F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
#define NVA16F_DMA_METHOD_COUNT_OLD 28:18
#define NVA16F_DMA_METHOD_COUNT 28:16
#define NVA16F_DMA_IMMD_DATA 28:16
#define NVA16F_DMA_SEC_OP 31:29
#define NVA16F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
#define NVA16F_DMA_SEC_OP_INC_METHOD (0x00000001)
#define NVA16F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
#define NVA16F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
#define NVA16F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
#define NVA16F_DMA_SEC_OP_ONE_INC (0x00000005)
#define NVA16F_DMA_SEC_OP_RESERVED6 (0x00000006)
#define NVA16F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
/* dma incrementing method format */
#define NVA16F_DMA_INCR_ADDRESS 11:0
#define NVA16F_DMA_INCR_SUBCHANNEL 15:13
#define NVA16F_DMA_INCR_COUNT 28:16
#define NVA16F_DMA_INCR_OPCODE 31:29
#define NVA16F_DMA_INCR_OPCODE_VALUE (0x00000001)
#define NVA16F_DMA_INCR_DATA 31:0
/* dma non-incrementing method format */
#define NVA16F_DMA_NONINCR_ADDRESS 11:0
#define NVA16F_DMA_NONINCR_SUBCHANNEL 15:13
#define NVA16F_DMA_NONINCR_COUNT 28:16
#define NVA16F_DMA_NONINCR_OPCODE 31:29
#define NVA16F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
#define NVA16F_DMA_NONINCR_DATA 31:0
/* dma increment-once method format */
#define NVA16F_DMA_ONEINCR_ADDRESS 11:0
#define NVA16F_DMA_ONEINCR_SUBCHANNEL 15:13
#define NVA16F_DMA_ONEINCR_COUNT 28:16
#define NVA16F_DMA_ONEINCR_OPCODE 31:29
#define NVA16F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
#define NVA16F_DMA_ONEINCR_DATA 31:0
/* dma no-operation format */
#define NVA16F_DMA_NOP (0x00000000)
/* dma immediate-data format */
#define NVA16F_DMA_IMMD_ADDRESS 11:0
#define NVA16F_DMA_IMMD_SUBCHANNEL 15:13
#define NVA16F_DMA_IMMD_DATA 28:16
#define NVA16F_DMA_IMMD_OPCODE 31:29
#define NVA16F_DMA_IMMD_OPCODE_VALUE (0x00000004)
/* dma set sub-device mask format */
#define NVA16F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
/* dma store sub-device mask format */
#define NVA16F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
/* dma use sub-device mask format */
#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
/* dma end-segment format */
#define NVA16F_DMA_ENDSEG_OPCODE 31:29
#define NVA16F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
/* dma legacy incrementing/non-incrementing formats */
#define NVA16F_DMA_ADDRESS 12:2
#define NVA16F_DMA_SUBCH 15:13
#define NVA16F_DMA_OPCODE3 17:16
#define NVA16F_DMA_OPCODE3_NONE (0x00000000)
#define NVA16F_DMA_COUNT 28:18
#define NVA16F_DMA_OPCODE 31:29
#define NVA16F_DMA_OPCODE_METHOD (0x00000000)
#define NVA16F_DMA_OPCODE_NONINC_METHOD (0x00000002)
#define NVA16F_DMA_DATA 31:0
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cla16F_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cla16f_sw_h_
#define _cla16f_sw_h_
#define NVA16F_NOTIFIERS_RC (0)
#define NVA16F_NOTIFIERS_REFCNT (1)
#define NVA16F_NOTIFIERS_NONSTALL (2)
#define NVA16F_NOTIFIERS_EVENTBUFFER (3)
#define NVA16F_NOTIFIERS_IDLECHANNEL (4)
#define NVA16F_NOTIFIERS_ENDCTX (5)
#define NVA16F_NOTIFIERS_SW (6)
#define NVA16F_NOTIFIERS_GR_DEBUG_INTR (7)
#define NVA16F_NOTIFIERS_MAXCOUNT (8)
/* NvNotification[] fields and values */
#define NVA16F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
#define NVA16F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
#endif /* _cla16f_sw_h_ */

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