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Andy Ritger
2022-05-09 13:18:59 -07:00
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72
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV01_ROOT (client) control commands and parameters */
#define NV0000_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0000,NV0000_CTRL_##cat,idx)
/* Client command categories (6bits) */
#define NV0000_CTRL_RESERVED (0x00)
#define NV0000_CTRL_SYSTEM (0x01)
#define NV0000_CTRL_GPU (0x02)
#define NV0000_CTRL_GSYNC (0x03)
#define NV0000_CTRL_DIAG (0x04)
#define NV0000_CTRL_EVENT (0x05)
#define NV0000_CTRL_NVD (0x06)
#define NV0000_CTRL_SWINSTR (0x07)
#define NV0000_CTRL_GSPC (0x08)
#define NV0000_CTRL_PROC (0x09)
#define NV0000_CTRL_SYNC_GPU_BOOST (0x0A)
#define NV0000_CTRL_GPUACCT (0x0B)
#define NV0000_CTRL_VGPU (0x0C)
#define NV0000_CTRL_CLIENT (0x0D)
// per-OS categories start at highest category and work backwards
#define NV0000_CTRL_OS_WINDOWS (0x3F)
#define NV0000_CTRL_OS_MACOS (0x3E)
#define NV0000_CTRL_OS_UNIX (0x3D)
/*
* NV0000_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0000_CTRL_CMD_NULL (0x0) /* finn: Evaluated from "(FINN_NV01_ROOT_RESERVED_INTERFACE_ID << 8) | 0x0" */
/* _ctrl0000_base_h_ */

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src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000client.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"
#include "class/cl0000.h"
#include "rs_access.h"
/*
* NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE
*
* This command may be used to query memory address space type associated with an object
*
* Parameters:
* hObject[IN]
* handle of the object to look up
* addrSpaceType[OUT]
* addrSpaceType with associated memory descriptor
*
* Possible status values are:
* NV_OK
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_OBJECT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE (0xd01) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS {
NvHandle hObject; /* [in] - Handle of object to look up */
NvU32 mapFlags; /* [in] - Flags that will be used when mapping the object */
NvU32 addrSpaceType; /* [out] - Memory Address Space Type */
} NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS;
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID 0x00000000
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM 0x00000001
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM 0x00000002
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM 0x00000003
#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC 0x00000004
/*
* NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO
*
* This command may be used to query information on a handle
*/
#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO (0xd02) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS {
NvHandle hObject; /* [in] - Handle of object to look up */
NvU32 index; /* [in] - Type of lookup */
union {
NvHandle hResult; /* [out] - Result of lookup when result is a handle type */
NV_DECLARE_ALIGNED(NvU64 iResult, 8); /* [out] - Result of lookup when result is a integer */
} data;
} NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS;
#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID 0x00000000
#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT 0x00000001
#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID 0x00000002
/*
* NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS
*
* This command may be used to get this client's access rights for an object
* The object to which access rights are checked does not have to be owned by
* the client calling the command, it is owned by the hClient parameter
*/
#define NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS (0xd03) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS {
NvHandle hObject; /* [in] - Handle of object to look up */
NvHandle hClient; /* [in] - Handle of client which owns hObject */
RS_ACCESS_MASK maskResult; /* [out] - Result of lookup */
} NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS;
/*
* NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY
*
* DEPRECATED: Calls NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT with hObject=hClient
*
* This command will modify a client's inherited share policy list
* The policy is applied in the same way that NvRmShare applies policies,
* except to the client's inherited policy list instead of an object's policy list
*/
#define NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY (0xd04) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS {
RS_SHARE_POLICY sharePolicy; /* [in] - Share Policy to apply */
} NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS;
/*
* NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE
*
* This command may be used to get a handle of a child of a given type
*/
#define NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE (0xd05) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS {
NvHandle hParent; /* [in] - Handle of parent object */
NvU32 classId; /* [in] - Class ID of the child object */
NvHandle hObject; /* [out] - Handle of the child object (0 if not found) */
} NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS;
/*
* NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT
*
* This command is meant to imitate the NvRmShare API.
* Applies a share policy to an object, which should be owned by the caller's client.
* The policy is applied in the same way that NvRmShare applies policies.
*
* This ctrl command is only meant to be used in older branches. For releases after R450,
* use NvRmShare directly instead.
*/
#define NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT (0xd06) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS {
NvHandle hObject; /* [in] - Handle of object to share */
RS_SHARE_POLICY sharePolicy; /* [in] - Share Policy to apply */
} NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS;
/* _ctrl0000client_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000diag.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"
/* NV01_ROOT (client) system control commands and parameters */
/*
* NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE
*
* This command returns the current lock meter logging state.
*
* state
* This parameter returns the current lock meter logging state.
* NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED
* This value indicates lock metering is disabled.
* NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED
* This value indicates lock metering is enabled.
* count
* This parameter returns the total number of lock metering entries
* (NV0000_CTRL_DIAG_LOCK_METER_ENTRY) available. This value will
* not exceed NV0000_CTRL_DIAG_LOCK_METER_MAX_ENTRIES. When lock metering
* is enabled this parameter will return zero.
* missedCount
* This parameter returns the number of lock metering entries that had
* to be discarded due to a full lock metering table. This value will
* not exceed NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES. When lock
* metering is enabled this parameter will return zero.
* bCircularBuffer
* This parameter returns type of buffer.
* TRUE
* Buffer is circular
* FALSE
* Buffer is sequential
*
* Possible status values returned are:
* NV_OK
*/
#define NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE (0x480) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID (0x80U)
typedef struct NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS {
NvU32 state;
NvU32 count;
NvU32 missedCount;
NvBool bCircularBuffer;
} NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS;
/* valid lock metering state values */
#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED (0x00000000)
#define NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED (0x00000001)
/* maximum possible number of lock metering entries stored internally */
#define NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES (0x20000)
/*
* NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE
*
* This command sets the current lock meter logging state.
*
* state
* This parameter specifies the new state of the lock metering mechanism.
* Legal state values are:
* NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE
* This value disables lock metering.
* NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE
* This value enables lock metering.
* NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET
* This value resets, or clears, all lock metering state. Lock
* metering must be disabled prior to attempting a reset.
* bCircularBuffer
* This parameter specifies type of buffer.
* Possible values are:
* TRUE
* For circular buffer.
* FALSE
* For sequential buffer.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE (0x481) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID (0x81U)
typedef struct NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS {
NvU32 state;
NvBool bCircularBuffer;
} NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS;
/* valid lock metering state values */
#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE (0x00000000)
#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE (0x00000001)
#define NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET (0x00000002)
/*
* NV0000_CTRL_DIAG_LOCK_METER_ENTRY
*
* This structure represents a single lock meter entry.
*
* counter
* This field contains the number of nanonseconds elapsed since the
* the last system boot when the lock meter entry was generated.
* freq
* This field contains the CPU performance counter frequency in units
* of ticks per second.
* line
* This field contains the relevant line number.
* filename
* This field contains the relevant file name.
* tag
* This field contains a tag uniquely identifying the user of the metered
* lock operations.
* cpuNum
* This field contains the CPU number from which the metered operation
* was initiated.
* irql
* This field contains the IRQL at which the metered operation was
* initiated.
* data0
* data1
* data2
* These fields contain tag-specific data.
*/
#define NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH (0xc)
typedef struct NV0000_CTRL_DIAG_LOCK_METER_ENTRY {
NV_DECLARE_ALIGNED(NvU64 counter, 8);
NvU32 line;
NvU8 filename[NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH];
NvU16 tag;
NvU8 cpuNum;
NvU8 irql;
NV_DECLARE_ALIGNED(NvU64 threadId, 8);
NvU32 data0;
NvU32 data1;
NvU32 data2;
} NV0000_CTRL_DIAG_LOCK_METER_ENTRY;
/* valid lock meter entry tag values */
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA (0x00000001)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED (0x00000002)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND (0x00000003)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA (0x00000004)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API (0x00000010)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API (0x00000011)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS (0x00000020)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS (0x00000021)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA (0x00000100)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL (0x00001000)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET (0x00002000)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET (0x00002001)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX (0x00002002)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX (0x00002003)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP (0x00003000)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM (0x00003001)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM (0x00003002)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA (0x00003003)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA (0x00003004)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC (0x00004000)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM (0x00004001)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT (0x00004010)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT (0x00005000)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE (0x00005001)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE (0x00005002)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG (0x00005003)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP (0x00005004)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN (0x00005005)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL (0x00005006)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG (0x00005007)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP (0x00005008)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY (0x00005009)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM (0x0000500A)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT (0x0000500B)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT (0x0000500C)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS (0x00006000)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA (0x00007000)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA (0x00007001)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR (0x0000F000)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC (0x0000F00F)
/*
* NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES
*
* This command returns lock metering data in a fixed-sized array of entries.
* Each request will return up NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_MAX_ENTRIES
* entries.
*
* It is up to the caller to repeat these requests to retrieve the total number
* of entries reported by NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE.
*
* entryCount
* This parameter returns the total number of valid entries returned
* in the entries array. This value will not exceed
* NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX but may be less.
* A value of zero indicates there are no more valid entries.
* entries
* This parameter contains the storage into which lock metering entry
* data is returned.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES (0x485) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID" */
/* total number of entries returned */
#define NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX (0x40)
#define NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID (0x85U)
typedef struct NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS {
NvU32 entryCount;
NV_DECLARE_ALIGNED(NV0000_CTRL_DIAG_LOCK_METER_ENTRY entries[NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX], 8);
} NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS;
/*
* NV0000_CTRL_CMD_DIAG_PROFILE_RPC
*
* This command returns the RPC runtime information, and
* will only return valid when it is running inside VGX mode.
*
* rpcProfileCmd:
* RPC profiler command issued by rpc profiler utility
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_DIAG_PROFILE_RPC (0x488) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID" */
typedef struct RPC_METER_ENTRY {
NV_DECLARE_ALIGNED(NvU64 startTimeInNs, 8);
NV_DECLARE_ALIGNED(NvU64 endTimeInNs, 8);
NV_DECLARE_ALIGNED(NvU64 rpcDataTag, 8);
NV_DECLARE_ALIGNED(NvU64 rpcExtraData, 8);
} RPC_METER_ENTRY;
#define NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID (0x88U)
typedef struct NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS {
NvU32 rpcProfileCmd;
} NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS;
#define NV0000_CTRL_PROFILE_RPC_CMD_DISABLE (0x00000000)
#define NV0000_CTRL_PROFILE_RPC_CMD_ENABLE (0x00000001)
#define NV0000_CTRL_PROFILE_RPC_CMD_RESET (0x00000002)
/*
* NV0000_CTRL_CMD_DIAG_DUMP_RPC
*
* This command returns the RPC runtime information, which
* will be logged by NV0000_CTRL_CMD_DIAG_PROFILE_RPC command
* when running inside VGX mode.
*
* When issuing this command, the RPC profiler has to be disabled.
*
* firstEntryOffset:
* [IN] offset for first entry.
*
* outputEntryCout:
* [OUT] number of entries returned in rpcProfilerBuffer.
*
* remainingEntryCount:
* [OUT] number of entries remaining.
*
* elapsedTimeInNs:
* [OUT] runtime for the RPC profiler tool.
*
* rpcProfilerBuffer:
* [OUT] buffer to store the RPC entries
*/
#define NV0000_CTRL_CMD_DIAG_DUMP_RPC (0x489) /* finn: Evaluated from "(FINN_NV01_ROOT_DIAG_INTERFACE_ID << 8) | NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_DIAG_RPC_MAX_ENTRIES (100)
#define NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV0000_CTRL_DIAG_DUMP_RPC_PARAMS {
NvU32 firstEntryOffset;
NvU32 outputEntryCount;
NvU32 remainingEntryCount;
NV_DECLARE_ALIGNED(NvU64 elapsedTimeInNs, 8);
NV_DECLARE_ALIGNED(RPC_METER_ENTRY rpcProfilerBuffer[NV0000_CTRL_DIAG_RPC_MAX_ENTRIES], 8);
} NV0000_CTRL_DIAG_DUMP_RPC_PARAMS;
/* _ctrl0000diag_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000event.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"
#include "class/cl0000.h"
/*
* NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* This command sets event notification for the system events.
*
* event
* This parameter specifies the type of event to which the specified
* action is to be applied. The valid event values can be found in
* cl0000.h.
*
* action
* This parameter specifies the desired event notification action.
* Valid notification actions include:
* NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
* This action disables event notification for the specified
* event.
* NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
* This action enables single-shot event notification for the
* specified event.
* NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
* This action enables repeated event notification for the
* specified event.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_CLIENT
*
*/
#define NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION (0x501) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
NvU32 event;
NvU32 action;
} NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
/*
* NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS
*
* This command returns the status of the specified system event type.
* See the description of NV01_EVENT for details on registering events.
*
* event
* This parameter specifies the event type. Valid event type values
* can be found in cl0000.h.
* status
* This parameter returns the status for a given event type. Valid
* status values can be found in cl0000.h.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_CLIENT
*
*/
#define NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS (0x502) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS {
NvU32 event;
NvU32 status;
} NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS;
/* _ctrl0000event_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gpu.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrl0000/ctrl0000system.h"
#include "ctrl/ctrlxxxx.h"
#include "nvlimits.h"
/* NV01_ROOT (client) GPU control commands and parameters */
/*
* NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS
*
* This command returns a table of attached gpuId values.
* The table is NV0000_CTRL_GPU_MAX_ATTACHED_GPUS entries in size.
*
* gpuIds[]
* This parameter returns the table of attached GPU IDs.
* The GPU ID is an opaque platform-dependent value that can be used
* with the NV0000_CTRL_CMD_GPU_GET_ID_INFO command to retrieve
* additional information about the GPU. The valid entries in gpuIds[]
* are contiguous, with a value of NV0000_CTRL_GPU_INVALID_ID indicating
* the invalid entries.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32
#define NV0000_CTRL_GPU_INVALID_ID (0xffffffff)
#define NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS {
NvU32 gpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS];
} NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS;
/*
* Deprecated. Please use NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 instead.
*/
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_SZNAME 128
#define NV0000_CTRL_NO_NUMA_NODE (-1)
#define NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS {
NvU32 gpuId;
NvU32 gpuFlags;
NvU32 deviceInstance;
NvU32 subDeviceInstance;
NV_DECLARE_ALIGNED(NvP64 szName, 8);
NvU32 sliStatus;
NvU32 boardId;
NvU32 gpuInstance;
NvS32 numaId;
} NV0000_CTRL_GPU_GET_ID_INFO_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2
* This command returns GPU instance information for the specified GPU.
*
* [in] gpuId
* This parameter should specify a valid GPU ID value. If there
* is no GPU present with the specified ID, a status of
* NV_ERR_INVALID_ARGUMENT is returned.
* [out] gpuFlags
* This parameter returns various flags values for the specified GPU.
* Valid flag values include:
* NV0000_CTRL_GPU_ID_INFO_IN_USE
* When true this flag indicates there are client references
* to the GPU in the form of device class instantiations (see
* NV01_DEVICE or NV03_DEVICE descriptions for details).
* NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE
* When true this flag indicates the GPU is linked into an
* active SLI device.
* NV0000_CTRL_GPU_ID_INFO_MOBILE
* When true this flag indicates the GPU is a mobile GPU.
* NV0000_CTRL_GPU_ID_BOOT_MASTER
* When true this flag indicates the GPU is the boot master GPU.
* NV0000_CTRL_GPU_ID_INFO_SOC
* When true this flag indicates the GPU is part of a
* System-on-Chip (SOC).
* NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED
* When ATS is enabled on the system.
* [out] deviceInstance
* This parameter returns the broadcast device instance number associated
* with the specified GPU. This value can be used to instantiate
* a broadcast reference to the GPU using the NV01_DEVICE classes.
* [out] subDeviceInstance
* This parameter returns the unicast subdevice instance number
* associated with the specified GPU. This value can be used to
* instantiate a unicast reference to the GPU using the NV20_SUBDEVICE
* classes.
* [out] sliStatus
* This parameters returns the SLI status for the specified GPU.
* Legal values for this member are described by NV0000_CTRL_SLI_STATUS.
* [out] boardId
* This parameter returns the board ID value with which the
* specified GPU is associated. Multiple GPUs can share the
* same board ID in multi-GPU configurations.
* [out] gpuInstance
* This parameter returns the GPU instance number for the specified GPU.
* GPU instance numbers are assigned in bus-probe order beginning with
* zero and are limited to one less the number of GPUs in the system.
* [out] numaId
* This parameter returns the ID of NUMA node for the specified GPU.
* In case there is no NUMA node, NV0000_CTRL_NO_NUMA_NODE is returned.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS {
NvU32 gpuId;
NvU32 gpuFlags;
NvU32 deviceInstance;
NvU32 subDeviceInstance;
NvU32 sliStatus;
NvU32 boardId;
NvU32 gpuInstance;
NvS32 numaId;
} NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS;
/* valid flags values */
#define NV0000_CTRL_GPU_ID_INFO_IN_USE 0:0
#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE 1:1
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_MOBILE 2:2
#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER 3:3
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_SOC 5:5
#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED 6:6
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001)
/*
* NV0000_CTRL_CMD_GPU_GET_INIT_STATUS
*
* This command returns the initialization status for the specified GPU, and
* will return NV_ERR_INVALID_STATE if called prior to GPU
* initialization.
*
* gpuId
* This parameter should specify a valid GPU ID value. If there
* is no GPU present with the specified ID, a status of
* NV_ERR_INVALID_ARGUMENT is returned.
* status
* This parameter returns the status code identifying the initialization
* state of the GPU. If this parameter has the value NV_OK,
* then no errors were detected during GPU initialization. Otherwise, this
* parameter specifies the top-level error that was detected during GPU
* initialization. Note that a value of NV_OK only means that
* no errors were detected during the actual GPU initialization, and other
* errors may have occurred that prevent the GPU from being attached or
* accessible via the NV01_DEVICE or NV20_SUBDEVICE classes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS {
NvU32 gpuId;
NvU32 status;
} NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS
*
* This command returns a mask of valid device IDs. These device IDs
* can be used to instantiate the NV01_DEVICE_0 class (see NV01_DEVICE_0
* for more information).
*
* deviceIds
* This parameter returns the mask of valid device IDs. Each enabled bit
* in the mask corresponds to a valid device instance. Valid device
* instances can be used to initialize the NV0080_ALLOC_PARAMETERS
* structure when using NvRmAlloc to instantiate device handles. The
* number of device IDs will not exceed NV_MAX_DEVICES in number.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS {
NvU32 deviceIds;
} NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_PROBED_IDS
*
* This command returns a table of probed gpuId values.
* The table is NV0000_CTRL_GPU_MAX_PROBED_GPUS entries in size.
*
* gpuIds[]
* This parameter returns the table of probed GPU IDs.
* The GPU ID is an opaque platform-dependent value that can
* be used with the NV0000_CTRL_CMD_GPU_ATTACH_IDS and
* NV0000_CTRL_CMD_GPU_DETACH_ID commands to attach and detach
* the GPU.
* The valid entries in gpuIds[] are contiguous, with a value
* of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries.
* excludedGpuIds[]
* This parameter returns the table of excluded GPU IDs.
* An excluded GPU ID is an opaque platform-dependent value that
* can be used with NV0000_CTRL_CMD_GPU_GET_PCI_INFO and
* NV0000_CTRL_CMD_GPU_GET_UUID_INFO.
* The valid entries in excludedGpuIds[] are contiguous, with a value
* of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_PROBED_GPUS NV_MAX_DEVICES
#define NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID (0x14U)
typedef struct NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS {
NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS];
NvU32 excludedGpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS];
} NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_PCI_INFO
*
* This command takes a gpuId and returns PCI bus information about
* the device. If the OS does not support returning PCI bus
* information, this call will return NV_ERR_NOT_SUPPORTED
*
* gpuId
* This parameter should specify a valid GPU ID value. If there
* is no GPU present with the specified ID, a status of
* NV_ERR_INVALID_ARGUMENT is returned.
*
* domain
* This parameter returns the PCI domain of the GPU.
*
* bus
* This parameter returns the PCI bus of the GPU.
*
* slot
* This parameter returns the PCI slot of the GPU.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21b) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1BU)
typedef struct NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS {
NvU32 gpuId;
NvU32 domain;
NvU16 bus;
NvU16 slot;
} NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_ATTACH_IDS
*
* This command attaches the GPUs with the gpuIds matching those in
* the table provided by the client.
* The table is NV0000_CTRL_GPU_MAX_PROBED_GPUS entries in size.
*
* gpuIds[]
* This parameter holds the table of gpuIds to attach. At least
* one gpuId must be specified; clients may use the special
* gpuId value NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS to indicate
* that all probed GPUs are to be attached.
* The entries in gpuIds[] must be contiguous, with a value of
* NV0000_CTRL_GPU_INVALID_ID to indicate the first invalid
* entry.
* If one or more of the gpuId values do not specify a GPU found
* in the system, the NV_ERR_INVALID_ARGUMENT error
* status is returned.
*
* failedId
* If NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS is specified and
* a GPU cannot be attached, the NV0000_CTRL_CMD_GPU_ATTACH_IDS
* command returns an error code and saves the failing GPU's
* gpuId in this field.
*
* If a table of gpuIds is provided, these gpuIds will be validated
* against the RM's table of probed gpuIds and attached in turn,
* if valid; if NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS is used, all
* probed gpuIds will be attached, in the order the associated GPUs
* were probed in by the RM.
*
* If a gpuId fails to attach, this gpuId is stored in the failedId
* field. Any GPUs attached by the command prior the failure are
* detached.
*
* If multiple clients use NV0000_CTRL_CMD_GPU_ATTACH_IDS to attach
* a gpuId, the RM ensures that the gpuId won't be detached until
* all clients have issued a call to NV0000_CTRL_CMD_GPU_DETACH_IDS
* to detach the gpuId (or have terminated).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OPERATING_SYSTEM
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_IRQ_EDGE_TRIGGERED
* NV_ERR_IRQ_NOT_FIRING
*/
#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffff)
#define NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID (0x15U)
typedef struct NV0000_CTRL_GPU_ATTACH_IDS_PARAMS {
NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS];
NvU32 failedId;
} NV0000_CTRL_GPU_ATTACH_IDS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_DETACH_IDS
*
* This command detaches the GPUs with the gpuIds matching those in
* the table provided by the client.
* The table is NV0000_CTRL_GPU_MAX_ATTACHED_GPUS entries in size.
*
* gpuIds[]
* This parameter holds the table of gpuIds to detach. At least
* one gpuId must be specified; clients may use the special
* gpuId NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS to indicate that
* all attached GPUs are to be detached.
* The entries in gpuIds[] must be contiguous, with a value of
* NV0000_CTRL_GPU_INVALID_ID to indicate the first invalid
* entry.
* If one or more of the gpuId values do not specify a GPU found
* in the system, the NV_ERR_INVALID_ARGUMENT error
* status is returned.
*
* If a table of gpuIds is provided, these gpuIds will be validated
* against the RM's list of attached gpuIds; each valid gpuId is
* detached immediately if it's no longer in use (i.e. if there are
* no client references to the associated GPU in the form of
* device class instantiations (see the NV01_DEVICE or NV03_DEVICE
* descriptions for details)) and if no other client still requires
* the associated GPU to be attached.
*
* If a given gpuId can't be detached immediately, it will instead
* be detached when the last client reference is freed or when
* the last client that issued NV0000_CTRL_CMD_GPU_ATTACH_IDS for
* this gpuId either issues NV0000_CTRL_CMD_GPU_DETACH_IDS or exits
* without detaching the gpuId explicitly.
*
* Clients may use the NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS command
* to obtain a table of the attached gpuIds.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OPERATING_SYSTEM
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffff)
#define NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID (0x16U)
typedef struct NV0000_CTRL_GPU_DETACH_IDS_PARAMS {
NvU32 gpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS];
} NV0000_CTRL_GPU_DETACH_IDS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_SVM_SIZE
*
* This command is used to get the SVM size.
*
* gpuId
* This parameter uniquely identifies the GPU whose associated
* SVM size is to be returned. The value of this field must
* match one of those in the table returned by
* NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS
*
* SvmSize
* SVM size is returned in this.
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*
*/
#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID (0x40U)
typedef struct NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS {
NvU32 gpuId;
NvU32 svmSize;
} NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_UUID_INFO
*
* This command returns requested information pertaining to the GPU
* specified by the GPU UUID passed in.
*
* Generally only GPUs that have been attached are visible to this call. Therefore
* queries on unattached GPUs will fail with NV_ERR_OBJECT_NOT_FOUND. However,
* a query for a SHA1 UUID may succeed for an unattached GPU in cases where the GID
* is cached, such as an excluded GPU.
*
* gpuGuid (INPUT)
* The GPU UUID of the gpu whose parameters are to be returned. Refer to
* NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
*
* flags (INPUT)
* The _FORMAT* flags designate ascii string format or a binary format.
*
* The _TYPE* flags designate either SHA-1-based (32-hex-character) or
* SHA-256-based (64-hex-character).
*
* gpuId (OUTPUT)
* The GPU ID of the GPU identified by gpuGuid. Refer to
* NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
*
* deviceInstance (OUTPUT)
* The device instance of the GPU identified by gpuGuid. Refer to
* NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
*
* subdeviceInstance (OUTPUT)
* The subdevice instance of the GPU identified by gpuGuid. Refer to
* NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
*
*/
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */
/* maximum possible number of bytes of GID information */
#define NV0000_GPU_MAX_GID_LENGTH (0x00000100)
#define NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID (0x74U)
typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS {
NvU8 gpuUuid[NV0000_GPU_MAX_GID_LENGTH];
NvU32 flags;
NvU32 gpuId;
NvU32 deviceInstance;
NvU32 subdeviceInstance;
} NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS;
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT 1:0
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE 2:2
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001)
/*
* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID
*
* This command returns the GPU UUID for the provided GPU ID.
* Note that only GPUs that have been attached are visible to this call.
* Therefore queries on unattached GPUs will fail
* with NV_ERR_OBJECT_NOT_FOUND.
*
* gpuId (INPUT)
* The GPU ID whose parameters are to be returned. Refer to
* NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
*
* flags (INPUT)
*
* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII
* This value is used to request the GPU UUID in ASCII format.
* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY
* This value is used to request the GPU UUID in binary format.
*
* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1
* This value is used to request that the GPU UUID value
* be SHA1-based (32-hex-character).
* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256
* This value is used to request that the GPU UUID value
* be SHA256-based (64-hex-character).
*
* gpuUuid[NV0000_GPU_MAX_GID_LENGTH] (OUTPUT)
* The GPU UUID of the GPU identified by GPU ID. Refer to
* NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
*
* uuidStrLen (OUTPUT)
* The length of the UUID returned which is related to the format that
* was requested using flags.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID (0x75U)
typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS {
NvU32 gpuId;
NvU32 flags;
NvU8 gpuUuid[NV0000_GPU_MAX_GID_LENGTH];
NvU32 uuidStrLen;
} NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS;
/* valid format values */
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT 1:0
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002)
/*valid type values*/
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE 2:2
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001)
/*
* NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE
*
* This command is used to enter or exit the so called "drain" state.
* When this state is enabled, the existing clients continue executing
* as usual, however no new client connections are allowed.
* This is done in order to "drain" the system of the running clients
* in preparation to selectively powering down the GPU.
* No GPU can enter a bleed state if that GPU is in an SLI group.
* In that case, NV_ERR_IN_USE is returned.
* Requires administrator privileges.
*
* It is expected, that the "drain" state will be eventually deprecated
* and replaced with another mechanism to quiesce a GPU (Bug 1718113).
*
* gpuId (INPUT)
* This parameter should specify a valid GPU ID value. If there
* is no GPU present with the specified ID, a status of
* NV_ERR_INVALID_ARGUMENT is returned.
* newState (INPUT)
* This input parameter is used to enter or exit the "drain"
* software state of the GPU specified by the gpuId parameter.
* Possible values are:
* NV0000_CTRL_GPU_DRAIN_STATE_ENABLED
* NV0000_CTRL_GPU_DRAIN_STATE_DISABLED
* flags (INPUT)
* NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE
* if set, upon reaching quiescence, a request will be made to
* the OS to "forget" the PCI device associated with the
* GPU specified by the gpuId parameter, in case such a request
* is supported by the OS. Otherwise, NV_ERR_NOT_SUPPORTED
* will be returned.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_IN_USE
*/
#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
/* Possible values of newState */
#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000)
#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001)
/* Defined bits for the "flags" argument */
#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001)
#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002)
#define NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x78U)
typedef struct NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS {
NvU32 gpuId;
NvU32 newState;
NvU32 flags;
} NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE
*
* gpuId (INPUT)
* This parameter should specify a valid GPU ID value. If there
* is no GPU present with the specified ID, a status of
* NVOS_STATUS_ERROR_INVALID_ARGUMENT is returned.
* drainState (OUTPUT)
* This parameter returns a value indicating if the "drain"
* state is currently enabled or not for the specified GPU. See the
* description of NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE.
* Possible values are:
* NV0000_CTRL_GPU_DRAIN_STATE_ENABLED
* NV0000_CTRL_GPU_DRAIN_STATE_DISABLED
* flags (OUTPUT)
* NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE
* if set, upon reaching quiesence, the GPU device will be
* removed automatically from the kernel space, similar
* to what writing "1" to the sysfs "remove" node does.
* NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE
* after removing the GPU, also disable the parent bridge's
* PCIe link. This flag can only be set in conjunction with
* NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE, and then
* only when the GPU is already idle (not attached).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x79U)
typedef struct NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS {
NvU32 gpuId;
NvU32 drainState;
NvU32 flags;
} NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_DISCOVER
*
* This request asks the OS to scan the PCI tree or a sub-tree for GPUs,
* that are not yet known to the OS, and to make them available for use.
* If all of domain:bus:slot.function are zeros, the entire tree is scanned,
* otherwise the parameters identify the bridge device, that roots the
* subtree to be scanned.
* Requires administrator privileges.
*
* domain (INPUT)
* PCI domain of the bridge
* bus (INPUT)
* PCI bus of the bridge
* slot (INPUT)
* PCI slot of the bridge
* function (INPUT)
* PCI function of the bridge
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_DEVICE
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_OPERATING_SYSTEM
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27a) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */
typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS {
NvU32 domain;
NvU8 bus;
NvU8 slot;
NvU8 function;
} NV0000_CTRL_GPU_DISCOVER_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE
*
* This command is used to get the content of the MemOp (CUDA Memory Operation)
* enablement mask, which can be overridden by using the MemOpOverride RegKey.
*
* The enableMask member must be treated as a bitmask, where each bit controls
* the enablement of a feature.
*
* So far, the only feature which is defined controls to whole MemOp APIs.
*
* Possible status values returned are:
* NV_OK
*
*/
#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27b) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID (0x7BU)
typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS {
NvU32 enableMask;
} NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS;
#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001)
/*
* NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT
*
* This privileged command is used to disable initialization for the NVLinks
* provided in the mask.
*
* The mask must be applied before the GPU is attached. DISABLE_NVLINK_INIT
* is an NOP for non-NVLink GPUs.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_DEVICE
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_INVALID_STATE
* NV_ERR_IN_USE
*
*/
#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID (0x81U)
typedef struct NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS {
NvU32 gpuId;
NvU32 mask;
NvBool bSkipHwNvlinkDisable;
} NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS;
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5
/*
* NV0000_CTRL_CMD_GPU_LEGACY_CONFIG
*
* Path to use legacy RM GetConfig/Set API. This API is being phased out.
*/
#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG (0x282) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID (0x82U)
typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
NvHandle hContext; /* [in] - Handle of object to perform operation on (Device, Subdevice, etc) */
NvU32 opType; /* [in] - Type of API */
NvV32 index; /* [in] - command type */
NvU32 dataType; /* [out] - data union type */
union {
struct {
NvV32 value;
} configGet;
struct {
NvU32 newValue;
NvU32 oldValue;
} configSet;
struct {
NvU8 paramData[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA];
NvU32 paramSize;
} configEx;
struct {
NvU32 propertyId;
NvU32 propertyIn[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN];
NvU32 propertyOut[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT];
} reservedProperty;
} data;
} NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS;
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET (0x00000000)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004)
/*
* NV0000_CTRL_CMD_IDLE_CHANNELS
*/
#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x83U)
typedef struct NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS {
NvHandle hDevice;
NvHandle hChannel;
NvV32 numChannels;
/* C form: NvP64 phClients NV_ALIGN_BYTES(8); */
NV_DECLARE_ALIGNED(NvP64 phClients, 8);
/* C form: NvP64 phDevices NV_ALIGN_BYTES(8); */
NV_DECLARE_ALIGNED(NvP64 phDevices, 8);
/* C form: NvP64 phChannels NV_ALIGN_BYTES(8); */
NV_DECLARE_ALIGNED(NvP64 phChannels, 8);
NvV32 flags;
NvV32 timeout;
} NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS;
/* _ctrl0000gpu_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
/*
* NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE
*
* This command is used to enable or disable the per process GPU accounting.
* This is part of GPU's software state and will persist if persistent
* software state is enabled. Refer to the description of
* NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE for more information.
*
* gpuId
* This parameter should specify a valid GPU ID value. Refer to the
* description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more
* information. If there is no GPU present with the specified ID,
* a status of NV_ERR_INVALID_ARGUMENT is returned.
* pid
* This input parameter specifies the process id of the process for which
* the accounting state needs to be set.
* In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This
* parameter is set only when this RM control is called from VGPU plugin,
* otherwise it is zero meaning set/reset the accounting state for the
* specified GPU.
* newState
* This input parameter is used to enable or disable the GPU accounting.
* Possible values are:
* NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED
* NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE (0xb01) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID" */
/* Possible values of persistentSwState */
#define NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED (0x00000000)
#define NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED (0x00000001)
#define NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS {
NvU32 gpuId;
NvU32 pid;
NvU32 newState;
} NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS;
/*
* NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE
*
* This command is used to get the current state of GPU accounting.
*
* gpuId
* This parameter should specify a valid GPU ID value. Refer to the
* description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more
* information. If there is no GPU present with the specified ID,
* a status of NV_ERR_INVALID_ARGUMENT is returned.
* pid
* This input parameter specifies the process id of the process of which the
* accounting state needs to be queried.
* In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This
* parameter is set only when this RM control is called from VGPU plugin,
* otherwise it is zero meaning the accounting state needs to be queried for
* the specified GPU.
* state
* This parameter returns a value indicating if per process GPU accounting
* is currently enabled or not for the specified GPU. See the
* description of NV0000_CTRL_CMD_GPU_SET_ACCOUNTING_STATE.
* Possible values are:
* NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED
* NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE (0xb02) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS {
NvU32 gpuId;
NvU32 pid;
NvU32 state;
} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS;
/*
* NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS
*
* This command returns GPU accounting data for the process.
*
* gpuId
* This parameter should specify a valid GPU ID value. Refer to the
* description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more
* information. If there is no GPU present with the specified ID,
* a status of NV_ERR_INVALID_ARGUMENT is returned.
* pid
* This parameter specifies the PID of the process for which information is
* to be queried.
* In case of VGX host, this parameter specifies VGPU plugin(VM) pid inside
* which the subPid is running. This parameter is set to VGPU plugin pid
* when this RM control is called from VGPU plugin.
* subPid
* In case of VGX host, this parameter specifies the PID of the process for
* which information is to be queried. In other cases, it is zero.
* gpuUtil
* This parameter returns the average GR utilization during the process's
* lifetime.
* fbUtil
* This parameter returns the average FB bandwidth utilization during the
* process's lifetime.
* maxFbUsage
* This parameter returns the maximum FB allocated (in bytes) by the process.
* startTime
* This parameter returns the time stamp value in micro seconds at the time
* process started utilizing GPU.
* stopTime
* This parameter returns the time stamp value in micro seconds at the time
* process stopped utilizing GPU.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO (0xb03) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS {
NvU32 gpuId;
NvU32 pid;
NvU32 subPid;
NvU32 gpuUtil;
NvU32 fbUtil;
NV_DECLARE_ALIGNED(NvU64 maxFbUsage, 8);
NV_DECLARE_ALIGNED(NvU64 startTime, 8);
NV_DECLARE_ALIGNED(NvU64 endTime, 8);
} NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS;
/*
* NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS
*
* This command is used to get the PIDS of processes with accounting
* information in the driver.
*
* gpuId
* This parameter should specify a valid GPU ID value. Refer to the
* description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more
* information. If there is no GPU present with the specified ID,
* a status of NV_ERR_INVALID_ARGUMENT is returned.
* pid
* This input parameter specifies the process id of the process of which the
* information needs to be queried.
* In case of VGX host, this parameter specifies VGPU plugin(VM) pid. This
* parameter is set only when this RM control is called from VGPU plugin,
* otherwise it is zero meaning get the pid list of the all the processes
* running on the specified GPU.
* pidTbl
* This parameter returns the table of all PIDs for which driver has
* accounting info.
* pidCount
* This parameter returns the number of entries in the PID table.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS (0xb04) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID" */
/* max size of pidTable */
#define NV0000_GPUACCT_PID_MAX_COUNT 4000
#define NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS {
NvU32 gpuId;
NvU32 pid;
NvU32 pidTbl[NV0000_GPUACCT_PID_MAX_COUNT];
NvU32 pidCount;
} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS;
/*
* NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA
*
* This command is used to clear previously collected GPU accounting data. This
* will have no affect on data for the running processes, accounting data for
* these processes will not be cleared and will still be logged for these
* processes. In order to clear ALL accounting data, accounting needs to be
* disabled using NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE before executing
* this command.
*
* gpuId
* This parameter should specify a valid GPU ID value. Refer to the
* description of NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS for more
* information. If there is no GPU present with the specified ID,
* a status of NV_ERR_INVALID_ARGUMENT is returned.
* pid
* This input parameter specifies the process id of the process for which
* the accounting data needs to be cleared.
* In case of VGX host, this parameter specifies VGPU plugin(VM) pid for
* which the accounting data needs to be cleared. This parameter is set only
* when this RM control is called from VGPU plugin, otherwise it is zero
* meaning clear the accounting data of processes running on baremetal
* system.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA (0xb05) /* finn: Evaluated from "(FINN_NV01_ROOT_GPUACCT_INTERFACE_ID << 8) | NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS {
NvU32 gpuId;
NvU32 pid;
} NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS;

32
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/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gspc.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gsync.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"
#include "class/cl30f1.h"
/* NV01_ROOT (client) system controller control commands and parameters */
/*
* NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS
*
* This command returns a table of attached gsyncId values.
* The table is NV0000_CTRL_GSYNC_MAX_ATTACHED_GSYNCS entries in size.
*
* gsyncIds[]
* This parameter returns the table of attached gsync IDs.
* The gsync ID is an opaque platform-dependent value that
* can be used with the NV0000_CTRL_CMD_GSYNC_GET_ID_INFO command to
* retrieve additional information about the gsync device.
* The valid entries in gsyncIds[] are contiguous, with a value
* of NV0000_CTRL_GSYNC_INVALID_ID indicating the invalid entries.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS (0x301) /* finn: Evaluated from "(FINN_NV01_ROOT_GSYNC_INTERFACE_ID << 8) | NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS {
NvU32 gsyncIds[NV30F1_MAX_GSYNCS];
} NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS;
/* this value marks entries in gsyncIds[] as invalid */
#define NV0000_CTRL_GSYNC_INVALID_ID (0xffffffff)
/*
* NV0000_CTRL_CMD_GSYNC_GET_ID_INFO
*
* This command returns gsync instance information for the
* specified gsync device.
*
* gsyncId
* This parameter should specify a valid gsync ID value.
* If there is no gsync present with the specified ID, a
* status of NV_ERR_INVALID_ARGUMENT is returned.
* gsyncFlags
* This parameter returns the current state of the gsync device.
* gsyncInstance
* This parameter returns the instance number associated with the
* specified gsync. This value can be used to instantiate
* a reference to the gsync using one of the NV30_GSYNC
* classes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GSYNC_GET_ID_INFO (0x302) /* finn: Evaluated from "(FINN_NV01_ROOT_GSYNC_INTERFACE_ID << 8) | NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS {
NvU32 gsyncId;
NvU32 gsyncFlags;
NvU32 gsyncInstance;
} NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS;
/* _ctrl0000gsync_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000nvd.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"
/* NV01_ROOT (client) nvd control commands and parameters */
/*
* NV0080_CTRL_NVD_DUMP_COMPONENT
*
* The following dump components are used to describe legal ranges in
* commands below:
*
* NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_SYS
* This is the system dump component.
* NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_NVLOG
* This is the nvlog dump component.
* NV0080_CTRL_CMD_NVD_DUMP_COMPONENT_RESERVED
* This component is reserved.
*
* See nvdump.h for more information on dump component values.
*/
#define NV0000_CTRL_NVD_DUMP_COMPONENT_SYS (0x400)
#define NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG (0x800)
#define NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED (0xB00)
/*
* NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE
*
* This command gets the expected dump size of a particular system
* dump component. Note that events that occur between this command
* and a later NV0000_CTRL_CMD_NVD_GET_DUMP command could alter the size of
* the buffer required.
*
* component
* This parameter specifies the system dump component for which the
* dump size is desired. Legal values for this parameter must
* be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_SYS and
* less than NV0000_CTRL_NVD_GET_DUMP_COMPONENT_NVLOG.
* size
* This parameter returns the expected size in bytes. The maximum
* value of this call is NV0000_CTRL_NVD_MAX_DUMP_SIZE.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT if components are invalid.
*/
#define NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE (0x601) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS {
NvU32 component;
NvU32 size;
} NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS;
/* Max size that a GET_DUMP_SIZE_PARAMS call can return */
#define NV0000_CTRL_NVD_MAX_DUMP_SIZE (1000000)
/*
* NV0000_CTRL_CMD_NVD_GET_DUMP
*
* This command gets a dump of a particular system dump component. If triggers
* is non-zero, the command waits for the trigger to occur before it returns.
*
* pBuffer
* This parameter points to the buffer for the data.
* component
* This parameter specifies the system dump component for which the
* dump is to be retrieved. Legal values for this parameter must
* be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_SYS and
* less than NV0000_CTRL_NVD_GET_DUMP_COMPONENT_NVLOG.
* size
* On entry, this parameter specifies the maximum length for
* the returned data. On exit, it specifies the number of bytes
* returned.
*
* Possible status values returned are:
* NV_OK
* NVOS_ERROR_INVALID_ARGUMENT if components are invalid.
* NVOS_ERROR_INVALID_ADDRESS if pBuffer is invalid
* NVOS_ERROR_INVALID_???? if the buffer was too small
*/
#define NV0000_CTRL_CMD_NVD_GET_DUMP (0x602) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_NVD_GET_DUMP_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pBuffer, 8);
NvU32 component;
NvU32 size;
} NV0000_CTRL_NVD_GET_DUMP_PARAMS;
/*
* NV0000_CTRL_CMD_NVD_GET_TIMESTAMP
*
* This command returns the current value of the timestamp used
* by the RM in NvDebug dumps. It is provided to keep the RM and NvDebug
* clients on the same time base.
*
* cpuClkId
* See also NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO
* This parameter specifies the source of the CPU clock. Legal values for
* this parameter include:
* NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT and NV0000_NVD_CPU_TIME_CLK_ID_OSTIME
* This clock id will provide real time in microseconds since 00:00:00 UTC on January 1, 1970.
* It is calculated as follows:
* (seconds * 1000000) + uSeconds
* NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API
* This clock id will provide time stamp that is constant-rate, high
* precision using platform API that is also available in the user mode.
* NV0000_NVD_CPU_TIME_CLK_ID_TSC
* This clock id will provide time stamp using CPU's time stamp counter.
*
* timestamp
* Retrieved timestamp
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT (0x00000000)
#define NV0000_NVD_CPU_TIME_CLK_ID_OSTIME (0x00000001)
#define NV0000_NVD_CPU_TIME_CLK_ID_TSC (0x00000002)
#define NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API (0x00000003)
#define NV0000_CTRL_CMD_NVD_GET_TIMESTAMP (0x603) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS {
NV_DECLARE_ALIGNED(NvU64 timestamp, 8);
NvU8 cpuClkId;
} NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS;
/*
* NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO
*
* This command gets the current state of the NvLog buffer system.
*
* component (in)
* This parameter specifies the system dump component for which the
* NvLog info is desired. Legal values for this parameter must
* be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG and
* less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED.
* version (out)
* This parameter returns the version of the Nvlog subsystem.
* runtimeSizes (out)
* This parameter returns the array of sizes for all supported printf
* specifiers. This information is necessary to know how many bytes
* to decode when given a certain specifier (such as %d).
* The following describes the contents of each array entry:
* NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED
* This array entry has special meaning and is unused in the
* runtimeSizes array.
* NV0000_CTRL_NVD_RUNTIME_SIZE_INT
* This array entry returns the size of integer types for use in
* interpreting the %d, %u, %x, %X, %i, %o specifiers.
* NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG
* This array entry returns the size of long long integer types for
* using in interpreting the %lld, %llu, %llx, %llX, %lli, %llo
* specifiers.
* NV0000_CTRL_NVD_RUNTIME_SIZE_STRING
* This array entry returns zero as strings are not allowed.
* NV0000_CTRL_NVD_RUNTIME_SIZE_PTR
* This array entry returns the size of the pointer type for use
* in interpreting the %p specifier.
* NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR
* This array entry returns the size of the char type for use in
* intpreting the %c specifier.
* NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT
* This array entry returns the size of the float types for use in
* in interpreting the %f, %g, %e, %F, %G, %E specifiers.
* All remaining entries are reserved and return 0.
* printFlags (out)
* This parameter returns the flags of the NvLog system.
* NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_BUFFER_FLAGS
* See NV0000_CTRL_CMD_NVD_GET_NVLOG_BUF_INFO for more details.
* NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_BUFFER_SIZE
* This field returns the buffer size in KBytes. A value of zero
* is returned when logging is disabled.
* NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP
* This field returns the format of the timestamp. Legal values
* for this parameter include:
* NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_NONE
* This value indicates no timestamp.
* NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_32BIT
* This value indicates a 32-bit timestamp.
* NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_64BIT
* This value indicates a 64-bit timestamp.
* NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_TIMESTAMP_32BIT_DIFF
* This value indicates a 32-bit differential timestamp.
* NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_RESERVED
* This field is reserved.
* NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_RUNTIME_LEVEL
* This field returns the lowest debug level for which logging
* is enabled by default.
* NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT
* This field indicates if logging for the specified component has
* been initialized. Legal values for this parameter include:
* NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT_NO
* This value indicates NvLog is uninitialized.
* NV0000_CTRL_NVD_NVLOG_PRINT_FLAGS_INIT_YES
* This value indicates NvLog has been initialized.
* signature (out)
* This parameter is the signature of the database
* required to decode these logs, autogenerated at buildtime.
* bufferTags (out)
* This parameter identifies the buffer tag used during allocation
* or a value of '0' if buffer is unallocated for each possible
* buffer.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT if components are invalid.
*/
#define NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO (0x604) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID" */
/* maximum size of the runtimeSizes array */
#define NV0000_CTRL_NVD_MAX_RUNTIME_SIZES (16)
/* size of signature parameter */
#define NV0000_CTRL_NVD_SIGNATURE_SIZE (4)
/* Maximum number of buffers */
#define NV0000_CTRL_NVD_MAX_BUFFERS (256)
#define NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS {
NvU32 component;
NvU32 version;
NvU8 runtimeSizes[NV0000_CTRL_NVD_MAX_RUNTIME_SIZES];
NvU32 printFlags;
NvU32 signature[NV0000_CTRL_NVD_SIGNATURE_SIZE];
NvU32 bufferTags[NV0000_CTRL_NVD_MAX_BUFFERS];
} NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS;
/* runtimeSize array indices */
#define NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED (0)
#define NV0000_CTRL_NVD_RUNTIME_SIZE_INT (1)
#define NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG (2)
#define NV0000_CTRL_NVD_RUNTIME_SIZE_STRING (3)
#define NV0000_CTRL_NVD_RUNTIME_SIZE_PTR (4)
#define NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR (5)
#define NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT (6)
/* printFlags fields and values */
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_INFO 7:0
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE 23:8
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE (0x00000000)
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT (0x00000004)
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_RUNTIME_LEVEL 28:25
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP 30:29
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE (0x00000000)
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32 (0x00000001)
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64 (0x00000002)
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF (0x00000003)
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED 31:31
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO (0x00000000)
#define NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES (0x00000001)
/*
* NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO
*
* This command gets the current state of a specific buffer in the NvLog
* buffer system.
*
* component (in)
* This parameter specifies the system dump component for which the
* NvLog info is desired. Legal values for this parameter must
* be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG and
* less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED.
* buffer (in/out)
* This parameter specifies the buffer number from which to retrieve the
* buffer information. Valid values are 0 to (NV0000_CTRL_NVD_MAX_BUFFERS - 1).
* If the buffer is specified using the 'tag' parameter, the buffer
* number is returned through this one.
* tag (in/out)
* If this parameter is non-zero, it will be used to specify the buffer,
* instead of 'buffer' parameter. It returns the tag of the specified buffer
* size (out)
* This parameter returns the size of the specified buffer.
* flags (in/out)
* On input, this parameter sets the following behavior:
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE
* This flag controls if the nvlog system should pause output
* to this buffer.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES
* The buffer should be paused until another command
* unpauses this buffer.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO
* The buffer should not be paused.
* On output, this parameter returns the flags of a specified buffer:
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED
* This flag indicates if logging to the specified buffer is
* disabled or not.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE
* This flag indicates the buffer logging type:
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING
* This type value indicates logging to the buffer wraps.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP
* This type value indicates logging to the buffer does not wrap.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE
* This flag indicates if the buffer size is expandable.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO
* The buffer is not expandable.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES
* The buffer is expandable.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGED
* This flag indicates if the buffer occupies non-paged or pageable
* memory.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGED_NO
* The buffer is in pageable memory.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NON_PAGES_YES
* The buffer is in non-paged memory.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING
* This flag indicates the locking mode for the specified buffer.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE
* This locking value indicates that no locking is performed. This
* locking mode is typically used for inherently single-threaded
* buffers.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE
* This locking value indicates that the buffer is locked only
* during state changes and that memory copying is unlocked. This
* mode should not be used tiny buffers that overflow every write
* or two.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL
* This locking value indicates the buffer is locked for the full
* duration of the write.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA
* This flag indicates if the buffer is stored in OCA dumps.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO
* The buffer is not included in OCA dumps.
* NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES
* The buffer is included in OCA dumps.
* pos (out)
* This parameter is the current position of the tracker/cursor in the
* buffer.
* overflow (out)
* This parameter is the number of times the buffer has overflowed.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT if components are invalid.
*/
#define NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO (0x605) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS {
NvU32 component;
NvU32 buffer;
NvU32 tag;
NvU32 size;
NvU32 flags;
NvU32 pos;
NvU32 overflow;
} NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS;
/* flags fields and values */
/* input */
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE 0:0
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO (0x00000000)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES (0x00000001)
/* output */
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED 0:0
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO (0x00000000)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES (0x00000001)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE 1:1
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING (0x00000000)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP (0x00000001)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE 2:2
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO (0x00000000)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES (0x00000001)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED 3:3
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO (0x00000000)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES (0x00000001)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING 5:4
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE (0x00000000)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE (0x00000001)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL (0x00000002)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA 6:6
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO (0x00000000)
#define NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES (0x00000001)
/*
* NV0000_CTRL_CMD_NVD_GET_NVLOG
*
* This command retrieves the specified dump block from the specified
* NvLog buffer. To retrieve the entire buffer, the caller should start
* with blockNum set to 0 and continue issuing calls with an incremented
* blockNum until the returned size value is less than
* NV0000_CTRL_NVD_NVLOG_MAX_BLOCK_SIZE.
*
* component (in)
* This parameter specifies the system dump component for which the NvLog
* dump operation is to be directed. Legal values for this parameter
* must be greater than or equal to NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG
* and less than NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED.
* buffer (in)
* This parameter specifies the NvLog buffer to dump.
* blockNum (in)
* This parameter specifies the block number for which data is to be
* dumped.
* size (in/out)
* On entry, this parameter specifies the maximum length in bytes for
* the returned data (should be set to NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE).
* On exit, it specifies the number of bytes returned.
* data (out)
* This parameter returns the data for the specified block. The size
* patameter values indicates the number of valid bytes returned.
*
* Possible status values returned are:
* NV_OK
* NVOS_ERROR_INVALID_ARGUMENT if components are invalid.
*/
#define NV0000_CTRL_CMD_NVD_GET_NVLOG (0x606) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE (4000)
#define NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0000_CTRL_NVD_GET_NVLOG_PARAMS {
NvU32 component;
NvU32 buffer;
NvU32 blockNum;
NvU32 size;
NvU8 data[NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE];
} NV0000_CTRL_NVD_GET_NVLOG_PARAMS;
/*
* NV0000_CTRL_CMD_NVD_GET_RCERR_RPT
*
* This command returns block of registers that were recorded at the time
* of an RC error for the current process.
*
* reqIdx:
* [IN] the index of the report being requested.
* index rolls over to 0.
* if the requested index is not in the circular buffer, then no data is
* transferred & either NV_ERR_INVALID_INDEX (indicating the specified
* index is not in the table) is returned.
*
* rptIdx:
* [OUT] the index of the report being returned.
* if the requested index is not in the circular buffer, then the value is
* undefined, no data istransferred & NV_ERR_INVALID_INDEX is returned.
* if the the specified index is present, but does not meet the requested
* criteria (refer to the owner & processId fields). the rptIdx will be
* set to a value that does not match the reqIdx, and no data will be
* transferred. NV_ERR_INSUFFICIENT_PERMISSIONS is still returned.
*
* gpuTag:
* [OUT] id of the GPU whose data was collected.
*
* rptTimeInNs:
* [OUT] the timestamp for when the report was created.
*
* startIdx:
* [OUT] the index of the oldest start record for the first report that
* matches the specified criteria (refer to the owner & processId
* fields). If no records match the specified criteria, this value is
* undefined, the failure code NV_ERR_MISSING_TABLE_ENTRY will
* be returned, and no data will be transferred.
*
* endIdx:
* [OUT] the index of the newest end record for the most recent report that
* matches the specified criteria (refer to the owner & processId
* fields). If no records match the specified criteria, this value is
* undefined, the failure code NV_ERR_MISSING_TABLE_ENTRY will
* be returned, and no data will be transferred.
*
* rptType:
* [OUT] indicator of what data is in the report.
*
* flags
* [OUT] a set odf flags indicating attributes of the record
* NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST -- indicates this is the first record of a report.
* NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST -- indicates this is the last record of the report.
* NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID -- indicates this is the response contains a valid
* index range.
* Note, this may be set when an error is returned indicating a valid range was found, but event of
* the requested index was not.
* NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID -- indicates this is the response contains valid data.
*
* rptCount:
* [OUT] number of entries returned in report.
*
* owner:
* [IN] Entries are only returned if they have the same owner as the specified owner or the specified
* owner Id is NV0000_CTRL_CMD_NVD_RPT_ANY_OWNER_ID.
* if the requested index is not owned by the specified owner, the rptIdx
* will be set to a value that does not match the reqIdx, and no data will
* be transferred. NV_ERR_INSUFFICIENT_PERMISSIONS is returned.
*
* processId:
* [IN] Deprecated
* report:
* [OUT] array of rptCount enum/value pair entries containing the data from the report.
* entries beyond rptCount are undefined.
*
*
* Possible status values returned are:
* NV_OK -- we found & transferred the requested record.
* NV_ERR_MISSING_TABLE_ENTRY -- we don't find any records that meet the criteria.
* NV_ERR_INVALID_INDEX -- the requested index was not found in the buffer.
* NV_ERR_INSUFFICIENT_PERMISSIONS -- the requested record was found, but it did not meet the criteria.
* NV_ERR_BUSY_RETRY -- We could not access the circular buffer.
*
*/
#define NV0000_CTRL_CMD_NVD_GET_RCERR_RPT (0x607) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES 200
// report types
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST 0
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS 1
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS 2
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS 3
// pseudo register enums attribute content
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY 0x00000000
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED 0x00000001 // number of missed entries.
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG 0x0000000f
// Flags Definitions
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST 0x00000001 // indicates this is the first record of a report.
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST 0x00000002 // indicates this is the last record of the report.
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID 0x00000004 // indicates this is the response contains a valid range
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID 0x00000008 // indicates this is the response contains valid data
// Attribute Definitions
#define TPC_REG_ATTR(gpcId, tpcId) ((gpcId << 8) | (tpcId))
#define ROP_REG_ATTR(gpcId, ropId) ((gpcId << 8) | (ropId))
#define SM_REG_ATTR(gpcId, tpcId, smId) ((((gpcId) << 16) | ((tpcId) << 8)) | (smId))
// Process Id Pseudo values
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID 0x00000000 // get report for any process ID
#define NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID 0xFFFFFFFF // get report for any owner ID
typedef struct NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY {
NvU32 tag;
NvU32 value;
NvU32 attribute;
} NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY;
#define NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS {
NvU16 reqIdx;
NvU16 rptIdx;
NvU32 GPUTag;
NvU32 rptTime; // time in seconds since 1/1/1970
NvU16 startIdx;
NvU16 endIdx;
NvU16 rptType;
NvU32 flags;
NvU16 rptCount;
NvU32 owner; // indicating whose reports to get
NvU32 processId; // deprecated field
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY report[NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES];
} NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS;
/*
* NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS
*
* This command returns the time stamp information that are collected from
* the execution of various DPCs/ISRs. This time stamp information is for
* debugging purposes only and would help with analyzing regressions and
* latencies for DPC/ISR execution times.
*
* tsBufferSize
* This field specifies the size of the buffer that the caller allocates.
* tsBuffer
* THis field specifies a pointer in the callers address space to the
* buffer into which the timestamp info on DPC/ISR is to be returned.
* This buffer must at least be as big as tsBufferSize.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS (0x608) /* finn: Evaluated from "(FINN_NV01_ROOT_NVD_INTERFACE_ID << 8) | NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS {
NvU32 tsBufferSize;
NV_DECLARE_ALIGNED(NvP64 pTSBuffer, 8);
} NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS;
/* _ctrl0000nvd_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000proc.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "nvlimits.h"
/*
* NV0000_CTRL_CMD_SET_SUB_PROCESS_ID
*
* Save the sub process ID and sub process name in client database
* subProcID
* Sub process ID
* subProcessName
* Sub process name
*
* In vGPU environment, sub process means the guest user/kernel process running
* within a single VM. It also refers to any sub process (or sub-sub process)
* within a parent process.
*
* Please refer to the wiki for more details about sub process concept: Resource_Server
*
* Possible return values are:
* NV_OK
*/
#define NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS {
NvU32 subProcessID;
char subProcessName[NV_PROC_NAME_MAX_LENGTH];
} NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS;
/*
* NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION
*
* Disable sub process USERD isolation.
* bIsSubProcIsolated
* NV_TRUE to disable sub process USERD isolation
*
* USERD allocated by different domains should not be put into the same physical page.
* This provides the basic security isolation because a physical page is the unit of
* granularity at which OS can provide isolation between processes.
*
* GUEST_USER: USERD allocated by guest user process
* GUEST_KERNEL: USERD allocated by guest kernel process
* GUEST_INSECURE: USERD allocated by guest/kernel process,
* INSECURE means there is no isolation between guest user and guest kernel
* HOST_USER: USERD allocated by host user process
* HOST_KERNEL: USERD allocated by host kernel process
*
* When sub process USERD isolation is disabled, we won't distinguish USERD allocated by guest
* user and guest kernel. They all belong to the GUEST_INSECURE domain.
*
* Please refer to wiki for more details: RM_USERD_Isolation
*
* Possible return values are:
* NV_OK
*/
#define NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS {
NvBool bIsSubProcessDisabled;
} NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS;
#define NV0000_CTRL_CMD_SET_SUB_PROCESS_ID (0x901) /* finn: Evaluated from "(FINN_NV01_ROOT_PROC_INTERFACE_ID << 8) | NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION (0x902) /* finn: Evaluated from "(FINN_NV01_ROOT_PROC_INTERFACE_ID << 8) | NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID" */
/* _ctrl0000proc_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"
#include "nvtypes.h"
#include "nvlimits.h"
/* --------------------------- Macros ----------------------------------------*/
// There are at least 2 GPUs in a sync group. Hence max is half of max devices.
#define NV0000_SYNC_GPU_BOOST_MAX_GROUPS (0x10) /* finn: Evaluated from "((NV_MAX_DEVICES) >> 1)" */
#define NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID 0xFFFFFFFF
/*-------------------------Command Prototypes---------------------------------*/
/*!
* Query whether SYNC GPU BOOST MANAGER is enabled or disabled.
*/
#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO (0xa01) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0000_SYNC_GPU_BOOST_INFO_PARAMS {
// [out] Specifies if Sync Gpu Boost Manager is enabled or not.
NvBool bEnabled;
} NV0000_SYNC_GPU_BOOST_INFO_PARAMS;
/*!
* Creates a Synchronized GPU-Boost Group (SGBG)
*/
#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE (0xa02) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID" */
/*!
* Describes a Synchronized GPU-Boost Group configuration
*/
typedef struct NV0000_SYNC_GPU_BOOST_GROUP_CONFIG {
// [in] Number of elements in @ref gpuIds
NvU32 gpuCount;
// [in] IDs of GPUs to be put in the Sync Boost Group
NvU32 gpuIds[NV_MAX_DEVICES];
// [out] Unique ID of the SGBG, if created
NvU32 boostGroupId;
// [in] If this group represents bridgeless SLI
NvBool bBridgeless;
} NV0000_SYNC_GPU_BOOST_GROUP_CONFIG;
#define NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS {
NV0000_SYNC_GPU_BOOST_GROUP_CONFIG boostConfig;
} NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS;
/*!
* Destroys a previously created Synchronized GPU-Boost Group(SGBG)
*/
#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY (0xa03) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID" */
#define NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS {
// [[in] Unique ID of the SGBG to be destroyed
NvU32 boostGroupId;
} NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS;
/*!
* Get configuration information for all Synchronized Boost Groups in the system.
*/
#define NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO (0xa04) /* finn: Evaluated from "(FINN_NV01_ROOT_SYNC_GPU_BOOST_INTERFACE_ID << 8) | NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS {
// [out] Number of groups retrieved. @ref NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS::boostGroups
NvU32 groupCount;
// [out] @ref NV0000_SYNC_GPU_BOOST_GROUP_CONFIG
NV0000_SYNC_GPU_BOOST_GROUP_CONFIG pBoostGroups[NV0000_SYNC_GPU_BOOST_MAX_GROUPS];
} NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS;
/* _ctrl0000syncgpuboost_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000unix.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"
/* NV01_ROOT (client) Linux control commands and parameters */
/*
* NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE
*
* This command may be used to force a cache flush for a range of virtual addresses in
* memory. Can be used for either user or kernel addresses.
*
* offset, length
* These parameters specify the offset within the memory block
* and the number of bytes to flush/invalidate
* cacheOps
* This parameter flags whether to flush, invalidate or do both.
* Possible values are:
* NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH
* NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE
* NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE
* hDevice
* This parameter is the handle to the device
* hObject
* This parameter is the handle to the memory structure being operated on.
* internalOnly
* Intended for internal use unless client is running in MODS UNIX environment,
* in which case this parameter specify the virtual address of the memory block
* to flush.
*
* Possible status values are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_COMMAND
* NV_ERR_INVALID_LIMIT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE (0x3d02) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NV_DECLARE_ALIGNED(NvU64 length, 8);
NvU32 cacheOps;
NvHandle hDevice;
NvHandle hObject;
NV_DECLARE_ALIGNED(NvU64 internalOnly, 8);
} NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS;
#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH (0x00000001)
#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE (0x00000002)
#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE (0x00000003)
/*
* NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR
*
* This command is used to get the control file descriptor.
*
* Possible status values returned are:
* NV_OK
*
*/
#define NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR (0x3d04) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x4" */
typedef struct NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS {
NvS32 fd;
} NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS;
typedef enum NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE {
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE = 0,
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM = 1,
} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE;
typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECT {
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE type;
union {
struct {
NvHandle hDevice;
NvHandle hParent;
NvHandle hObject;
} rmObject;
} data;
} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT;
/*
* NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD
*
* This command may be used to export NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE
* object to file descriptor.
*
* Note that the 'fd' parameter is an input parameter at the kernel level, but
* an output parameter for usermode RMAPI clients -- the RMAPI library will
* open a new FD automatically if a usermode RMAPI client exports an object.
*
* Kernel-mode RM clients can export an object to an FD in two steps:
* 1. User client calls this RMControl with the flag 'EMPTY_FD_TRUE' to create
* an empty FD to receive the object, then passes that FD to the kernel-mode
* RM client.
* 2. Kernel-mode RM client fills in the rest of the
* NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS as usual and calls RM to
* associate its desired RM object with the empty FD from its usermode
* client.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_PARAMETER
*/
#define NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD (0x3d05) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS {
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT object; /* IN */
NvS32 fd; /* IN/OUT */
NvU32 flags; /* IN */
} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS;
/*
* If EMPTY_FD is TRUE, the 'fd' will be created but no object will be
* associated with it. The hDevice parameter is still required, to determine
* the correct device node on which to create the file descriptor.
* (An empty FD can then be passed to a kernel-mode driver to associate it with
* an actual object.)
*/
#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD 0:0
#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE (0x00000000)
#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE (0x00000001)
/*
* NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD
*
* This command may be used to import back
* NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE object from file descriptor.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_PARAMETER
*/
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD (0x3d06) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS {
NvS32 fd; /* IN */
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT object; /* IN */
} NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS;
/*
* NV0000_CTRL_CMD_OS_GET_GPU_INFO
*
* This command will query the OS specific info for the specified GPU.
*
* gpuId
* This parameter should specify a valid GPU ID value. If there
* is no GPU present with the specified ID, a status of
* NV_ERR_INVALID_ARGUMENT is returned.
* minorNum
* This parameter returns minor number of device node.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_OS_GET_GPU_INFO (0x3d07) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x7" */
typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS {
NvU32 gpuId; /* IN */
NvU32 minorNum; /* OUT */
} NV0000_CTRL_OS_GET_GPU_INFO_PARAMS;
/*
* NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO
*
* This command will query the deviceInstance for the specified FD
* which is referencing an exported object.
*
* fd
* File descriptor parameter is referencing an exported object on a Unix system.
*
* deviceInstatnce
* This parameter returns a deviceInstance on which the object is located.
*
* maxObjects
* This parameter returns the maximum number of object handles that may be
* contained in the file descriptor.
*
* metadata
* This parameter returns the user metadata passed into the
* _EXPORT_OBJECTS_TO_FD control call.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO (0x3d08) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE 64
#define NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS {
NvS32 fd; /* IN */
NvU32 deviceInstance; /* OUT */
NvU16 maxObjects; /* OUT */
NvU8 metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* OUT */
} NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS;
/*
* NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST
*
* This command will re-fetch probed GPUs information and update RMAPI library's
* internal detected GPU context information accordingly. Without this, GPUs
* attached to RM after RMAPI client initialization will not be accessible and
* all RMAPI library calls will fail on them.
* Currently this is used by NVSwitch Fabric Manager in conjunction with NVSwitch
* Shared Virtualization feature where GPUs are hot-plugged to OS/RM (by Hypervisor)
* and Fabric Manager is signaled externally by the Hypervisor to initialize those GPUs.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST (0x3d09) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x9" */
/*
* This control call has been deprecated. It will be deleted soon.
* Use NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD (singular) or
* NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD (plural) instead.
*/
#define NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD (0x3d0a) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE
#define NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS {
NvHandle hDevice; /* IN */
NvU16 maxObjects; /* IN */
NvU8 metadata[NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* IN */
NvS32 fd; /* IN/OUT */
} NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS;
/*
* NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD
*
* Exports RM handles to an fd that was provided, also creates an FD if
* requested.
*
* The objects in the 'handles' array are exported into the fd
* as the range [index, index + numObjects).
*
* If index + numObjects is greater than the maxObjects value used
* to create the file descriptor, NV_ERR_INVALID_PARAMETER is returned.
*
* If 'numObjects and 'index' overlap with a prior call, the newer call's RM object
* handles will overwrite the previously exported handles from the previous call.
* This overlapping behavior can also be used to unexport a handle by setting
* the appropriate object in 'objects' to 0.
*
* fd
* A file descriptor. If -1, a new FD will be created.
*
* hDevice
* The owning device of the objects to be exported (must be the same for
* all objects).
*
* maxObjects
* The total number of objects that the client wishes to export to the FD.
* This parameter will be honored only when the FD is getting created.
*
* metadata
* A buffer for clients to write some metadata to and pass to the importing
* client. This parameter will be honored only when the FD is getting
* created.
*
* objects
* Array of RM object handles to export to the fd.
*
* numObjects
* The number of handles the user wishes to export in this call.
*
* index
* The index into the export fd at which to start exporting the handles in
* 'objects' (for use in iterative calls).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OUT_OF_RANGE
* NV_ERR_NOT_SUPPORTED
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_OBJECT_HANDLE
*/
#define NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD (0x3d0b) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS 512
#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS {
NvS32 fd; /* IN/OUT */
NvHandle hDevice; /* IN */
NvU16 maxObjects; /* IN */
NvU8 metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* IN */
NvHandle objects[NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* IN */
NvU16 numObjects; /* IN */
NvU16 index; /* IN */
} NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS;
/*
* NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD
*
* This command can be used to import back RM handles
* that were exported to an fd using the
* NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD control call.
*
* If index + numObjects is greater than the maxObjects value used
* to create the file descriptor, NV_ERR_INVALID_PARAMETER is returned
* and no objects are imported.
*
* For each valid handle in the 'objects' array parameter at index 'i',
* the corresponding object handle at index ('i' + 'index') contained by
* the fd will be imported. If the object at index ('i' + 'index') has
* not been exported into the fd, no object will be imported.
*
* If any of handles contained in the 'objects' array parameter are invalid
* and the corresponding export object handle is valid,
* NV_ERR_INVALID_PARAMETER will be returned and no handles will be imported.
*
* fd
* The export fd on which to import handles out of.
*
* hParent
* The parent RM handle of which all of the exported objects will
* be duped under.
*
* objects
* An array of RM handles. The exported objects will be duped under
* these handles during the import process.
*
* objectTypes
* An array of RM handle types. The type _NONE will be returned if
* the object was not imported. Other possible object types are
* mentioned below.
*
* numObjects
* The number of valid object handles in the 'objects' array. This should
* be set to the number of objects that the client wishes to import.
*
* index
* The index into the fd in which to start importing from. For
* use in iterative calls.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OUT_OF_RANGE
* NV_ERR_NOT_SUPPORTED
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_PARAMETER
*/
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD (0x3d0c) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID" */
//
// TODO Bump this back up to 512 after the FLA revamp is complete
//
#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS 128
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE 0
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM 1
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3
#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS {
NvS32 fd; /* IN */
NvHandle hParent; /* IN */
NvHandle objects[NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* IN */
NvU8 objectTypes[NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* OUT */
NvU16 numObjects; /* IN */
NvU16 index; /* IN */
} NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS;
/* _ctrl0000unix_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0002.finn
//
#include "ctrl/ctrlxxxx.h"
#define NV0002_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0002, NV0002_CTRL_##cat, idx)
/* Client command categories (6bits) */
#define NV0002_CTRL_RESERVED (0x00)
#define NV0002_CTRL_DMA (0x01)
/*
* NV0002_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0002_CTRL_CMD_NULL (0x20000) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NV0002_CTRL_CMD_UPDATE_CONTEXTDMA
*
* This command will update the parameters of the specified context dma. The
* context dma must be bound to a display channel. The update is limited
* to the display view of the context dma. Other use cases will continue to
* use the original allocation parameters.
*
* This is used on platforms where memory may be moved by the operating
* system after allocation.
*
* This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag.
*
* baseAddress
* This parameter, if selected by flags, indicates the new baseAddress for
* the ctxdma
* limit
* This parameter, if selected by flags, indicates the new limit of the
* ctxdma.
* hCtxDma
* ContextDma handle on which to operate. Must match the handle given to the control
* call.
* hChannel
* Display channel handle. This field is ignored.
* hintHandle
* Hint value returned from HeapAllocHint which encodes information about
* the surface. This is used by chips without generic kind. Newer chips
* use the COMPR_INFO flag and the hintHandle must be zero.
* flags
* This parameter specifies flags which indicate which other parameters are
* valid.
* FLAGS_PAGESIZE updates the context DMA pagesize field, if not _DEFAULT
* FLAGS_USE_COMPR_INFO uses the surface format specified in the params, instead of hintHandle.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_OBJECT
* NV_ERR_INVALID_ARGUMENT
* NVOS_STATUS_NOT_SUPPORTED
*/
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA (0x20101) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS_MESSAGE_ID" */
#define NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS {
NV_DECLARE_ALIGNED(NvU64 baseAddress, 8);
NV_DECLARE_ALIGNED(NvU64 limit, 8);
NvHandle hSubDevice;
NvHandle hCtxDma;
NvHandle hChannel;
NvHandle hintHandle;
NvU32 flags;
} NV0002_CTRL_UPDATE_CONTEXTDMA_PARAMS;
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS 0:0
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS_INVALID (0x00000000)
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_BASEADDRESS_VALID (0x00000001)
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT 1:1
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT_INVALID (0x00000000)
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_LIMIT_VALID (0x00000001)
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT 2:2
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT_INVALID (0x00000000)
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_HINT_VALID (0x00000001)
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE 4:3
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_DEFAULT (0x00000000)
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_4K (0x00000001)
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_PAGESIZE_BIG (0x00000002)
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO 6:5
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_NONE (0x00000000)
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_FORMAT_PITCH (0x00000001)
#define NV0002_CTRL_CMD_UPDATE_CONTEXTDMA_FLAGS_USE_COMPR_INFO_FORMAT_BLOCK_LINEAR (0x00000002)
/*
* NV0002_CTRL_CMD_BIND_CONTEXTDMA
*
* Bind a context dma to a display channel. Binding is no longer required for
* Host channels, but does silently succeed.
*
* This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag.
*
* This control replaces the obsolete RmBindContextDma() API.
*
* hChannel
* The channel for ctxdma bind
*
* Possible error codes include
* NV_OK
* NV_ERR_TOO_MANY_PRIMARIES hash table is full
* NV_ERR_NO_MEMORY instance memory is full
* NV_ERR_INVALID_OFFSET surface is not correctly aligned
* NV_ERR_STATE_IN_USE context dma was already bound given channel
*/
#define NV0002_CTRL_CMD_BIND_CONTEXTDMA (0x20102) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_BIND_CONTEXTDMA_PARAMS_MESSAGE_ID" */
#define NV0002_CTRL_BIND_CONTEXTDMA_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0002_CTRL_BIND_CONTEXTDMA_PARAMS {
NvHandle hChannel;
} NV0002_CTRL_BIND_CONTEXTDMA_PARAMS;
/*
* NV0002_CTRL_CMD_UNBIND_CONTEXTDMA
*
* Unbind a context dma from a display channel.
*
* This control call supports the NVOS54_FLAGS_LOCK_BYPASS flag.
*
* hChannel
* The display channel to unbind from
*
* Possible error codes include
* NV_OK
* NV_ERR_INVALID_STATE channel was not bound
*/
#define NV0002_CTRL_CMD_UNBIND_CONTEXTDMA (0x20103) /* finn: Evaluated from "(FINN_NV01_CONTEXT_DMA_DMA_INTERFACE_ID << 8) | NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS_MESSAGE_ID" */
#define NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS {
NvHandle hChannel;
} NV0002_CTRL_UNBIND_CONTEXTDMA_PARAMS;
/* _ctrl0002.h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0004.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV01_TIMER control commands and parameters */
#define NV0004_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0004, NV0004_CTRL_##cat, idx)
/* NV01_TIMER command categories (8bits) */
#define NV0004_CTRL_RESERVED (0x00)
#define NV0004_CTRL_TMR (0x01)
/*
* NV0004_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0004_CTRL_CMD_NULL (0x40000) /* finn: Evaluated from "(FINN_NV01_TIMER_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NV0004_CTRL_CMD_TMR_SET_ALARM_NOTIFY
*
* This command can be used to set a PTIMER alarm to trigger at the
* specified time in the future on the subdevice associated with this
* NV01_TIMER object instance.
*
* hEvent
* This parameter specifies the handle of an NV01_EVENT object instance
* that is to be signaled when the alarm triggers. This NV01_EVENT
* object instance must have been allocated with this NV01_TIMER object
* instance as its parent. If this parameter is set to NV01_NULL_OBJECT
* then all NV01_EVENT object instances associated with this NV01_TIMER
* object instance are signaled.
* alarmTimeUsecs
* This parameter specifies the relative time in nanoseconds at which
* the alarm should trigger. Note that the accuracy between the alarm
* trigger and the subsequent notification to the caller can vary
* depending on system conditions.
*
* Possible status values returned include:
* NVOS_STATUS_SUCCES
* NVOS_STATUS_INVALID_PARAM_STRUCT
* NVOS_STATUS_INVALID_OBJECT_HANDLE
*/
#define NV0004_CTRL_CMD_TMR_SET_ALARM_NOTIFY (0x40110) /* finn: Evaluated from "(FINN_NV01_TIMER_TMR_INTERFACE_ID << 8) | NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS_MESSAGE_ID" */
#define NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS {
NvHandle hEvent;
NV_DECLARE_ALIGNED(NvU64 alarmTimeNsecs, 8);
} NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS;
/* _ctrl0004_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl000f.finn
//
#include "ctrl/ctrlxxxx.h"
#define NV000F_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x000f, NV000F_CTRL_##cat, idx)
/* Client command categories (6bits) */
#define NV000F_CTRL_RESERVED (0x00U)
#define NV000F_CTRL_FM (0x01U)
#define NV000F_CTRL_RESERVED2 (0x02U)
/*
* NV000f_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV000F_CTRL_CMD_NULL (0xf0000U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NV000F_CTRL_CMD_SET_FM_STATE
*
* This command will notify RM that the fabric manager is initialized.
*
* RM would block P2P operations such as P2P capability reporting, NV50_P2P object
* allocation etc. until the notification received.
*
* Possible status values returned are:
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_NOT_SUPPORTED
* NV_OK
*/
#define NV000F_CTRL_CMD_SET_FM_STATE (0xf0101U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID << 8) | 0x1" */
/*
* NV000F_CTRL_CMD_CLEAR_FM_STATE
*
* This command will notify RM that the fabric manager is uninitialized.
*
* RM would block P2P operations such as P2P capability reporting, NV50_P2P object
* allocation etc. as soon as the notification received.
*
* Possible status values returned are:
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_NOT_SUPPORTED
* NV_OK
*/
#define NV000F_CTRL_CMD_CLEAR_FM_STATE (0xf0102U) /* finn: Evaluated from "(FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID << 8) | 0x2" */
/* _ctrl000f.h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0020.finn
//
#include "ctrl/ctrlxxxx.h"
#define NV0020_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0x0020, NV0020_CTRL_##cat, idx)
/* NV0020_GPU_MANAGEMENT command categories (6bits) */
#define NV0020_CTRL_RESERVED (0x00)
#define NV0020_CTRL_GPU_MGMT (0x01)
/*
* NV0020_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0020_CTRL_CMD_NULL (0x200000) /* finn: Evaluated from "(FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID << 8) | 0x0" */
/* Maximum possible number of bytes of GID information */
#define NV0020_GPU_MAX_GID_LENGTH (0x00000100)
/*
* NV0020_CTRL_CMD_GPU_MGMT_SET_SHUTDOWN_STATE
*
* This command modifies GPU zero power state for the desired GPU in the
* database. This state is set by a privileged client, after the GPU is
* completely unregistered from RM as well as PCI subsystem. On Linux,
* clients perform this operation through pci-sysfs.
* This control call requires admin privileges.
*
* uuid (INPUT)
* The UUID of the gpu.
* Supports binary format and SHA-1 type.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0020_CTRL_CMD_GPU_MGMT_SET_SHUTDOWN_STATE (0x200101) /* finn: Evaluated from "(FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID << 8) | NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID" */
#define NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS {
NvU8 uuid[NV0020_GPU_MAX_GID_LENGTH];
} NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS;
/* _ctrl0020_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl003e.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV01_MEMORY_SYSTEM control commands and parameters */
#define NV003E_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x003E, NV003E_CTRL_##cat, idx)
/* NV01_MEMORY_SYSTEM command categories (6bits) */
#define NV003E_CTRL_RESERVED (0x00)
#define NV003E_CTRL_MEMORY (0x01)
/*
* NV003E_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV003E_CTRL_CMD_NULL (0x3e0000) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR
*
* This command returns attributes associated with the memory object
* at the given offset. The architecture dependent return parameter
* comprFormat determines the meaningfulness (or not) of comprOffset.
*
* This call is currently only supported in the MODS environment.
*
* memOffset
* This parameter is both an input and an output. As input, this
* parameter holds an offset into the memory surface. The return
* value is the physical address of the surface at the given offset.
* memFormat
* This parameter returns the memory kind of the surface.
* comprOffset
* This parameter returns the compression offset of the surface.
* comprFormat
* This parameter returns the type of compression of the surface.
* gpuCacheAttr
* gpuCacheAttr returns the gpu cache attribute of the surface.
* Legal return values for this field are
* NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN
* NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED
* NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED
* gpuP2PCacheAttr
* gpuP2PCacheAttr returns the gpu peer-to-peer cache attribute of the surface.
* Legal return values for this field are
* NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN
* NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED
* NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED
* mmuContext
* mmuContext returns the requested type of physical address
* Legal return values for this field are
* TEGRA_VASPACE_A -- return the non-GPU device physical address ( the system physical address itself) for Tegra engines.
* returns the system physical address, may change to use a class value in future.
* FERMI_VASPACE_A -- return the GPU device physical address( the system physical address, or the SMMU VA) for Big GPU engines.
* 0 -- return the GPU device physical address( the system physical address, or the SMMU VA) for Big GPU engines.
* use of zero may be deprecated in future.
* contigSegmentSize
* If the underlying surface is physically contiguous, this parameter
* returns the size in bytes of the piece of memory starting from
* the offset specified in the memOffset parameter extending to the last
* byte of the surface.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_BAD_OBJECT_HANDLE
* NVOS_STATUS_BAD_OBJECT_PARENT
* NVOS_STATUS_NOT_SUPPORTED
*
*/
#define NV003E_CTRL_CMD_GET_SURFACE_PHYS_ATTR (0x3e0101) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID" */
#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS {
NV_DECLARE_ALIGNED(NvU64 memOffset, 8);
NvU32 memFormat;
NvU32 comprOffset;
NvU32 comprFormat;
NvU32 gpuCacheAttr;
NvU32 gpuP2PCacheAttr;
NvU32 mmuContext;
NV_DECLARE_ALIGNED(NvU64 contigSegmentSize, 8);
} NV003E_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS;
/* valid gpuCacheAttr return values */
#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN (0x00000000)
#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED (0x00000001)
#define NV003E_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED (0x00000002)
/* NV003E_CTRL_CMD_GET_SURFACE_NUM_PHYS_PAGES
*
* This command returns the number of physical pages associated with the
* memory object.
*
* This call is currently only implemented on Linux and assumes that linux
* kernel in which RM module will be loaded has same page size as defined
* in linux kernel source with which RM module was built.
*
* numPages
* This parameter returns total number of physical pages associated with
* the memory object.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV003E_CTRL_CMD_GET_SURFACE_NUM_PHYS_PAGES (0x3e0102) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS_MESSAGE_ID" */
#define NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS {
NvU32 numPages;
} NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS;
/* NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES
*
* This command returns physical pages associated with the memory object.
*
* This call is currently only implemented on Linux and assumes that linux
* kernel in which RM module will be loaded has same page size as defined
* in linux kernel source with which RM module was built.
*
* pPages
* This parameter returns physical pages associated with the memory object.
*
* numPages
* This parameter is both an input and an output. As an input parameter,
* it's value indicates maximum number of physical pages to be copied to
* pPages. As an output parameter, it's value indicates number of physical
* pages copied to pPages.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES (0x3e0103) /* finn: Evaluated from "(FINN_NV01_MEMORY_SYSTEM_MEMORY_INTERFACE_ID << 8) | NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS_MESSAGE_ID" */
#define NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pPages, 8);
NvU32 numPages;
} NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS;
/* _ctrl003e_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0041.finn
//
#include "nvos.h"
#include "ctrl/ctrlxxxx.h"
/* NV04_MEMORY control commands and parameters */
#define NV0041_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0041, NV0041_CTRL_##cat, idx)
/* NV04_MEMORY command categories (6bits) */
#define NV0041_CTRL_RESERVED (0x00)
#define NV0041_CTRL_MEMORY (0x01)
/*
* NV0041_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0041_CTRL_CMD_NULL (0x410000) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR
*
* This command returns attributes associated with the memory object
* at the given offset. The architecture dependent return parameter
* comprFormat determines the meaningfulness (or not) of comprOffset.
*
* This call is only currently supported in the MODS environment.
*
* memOffset
* This parameter is both an input and an output. As input, this
* parameter holds an offset into the memory surface. The return
* value is the physical address of the surface at the given offset.
* memFormat
* This parameter returns the memory kind of the surface.
* comprOffset
* This parameter returns the compression offset of the surface.
* comprFormat
* This parameter returns the type of compression of the surface.
* memAperture
* The aperture of the surface is returned in this field.
* Legal return values for this parameter are
* NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM
* NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM
* gpuCacheAttr
* gpuCacheAttr returns the gpu cache attribute of the surface.
* Legal return values for this field are
* NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN
* NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED
* NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED
* gpuP2PCacheAttr
* gpuP2PCacheAttr returns the gpu peer-to-peer cache attribute of the surface.
* Legal return values for this field are
* NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN
* NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED
* NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED
* mmuContext
* mmuContext indicates the type of physical address to be returned (input parameter).
* Legal return values for this field are
* TEGRA_VASPACE_A -- return the device physical address for Tegra (non-GPU) engines. This is the system physical address itself.
* returns the system physical address. This may change to use a class value in future.
* FERMI_VASPACE_A -- return the device physical address for GPU engines. This can be a system physical address or a GPU SMMU virtual address.
* 0 -- return the device physical address for GPU engines. This can be a system physical address or a GPU SMMU virtual address.
* use of zero may be deprecated in future.
* contigSegmentSize
* If the underlying surface is physically contiguous, this parameter
* returns the size in bytes of the piece of memory starting from
* the offset specified in the memOffset parameter extending to the last
* byte of the surface.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_BAD_OBJECT_HANDLE
* NVOS_STATUS_BAD_OBJECT_PARENT
* NVOS_STATUS_NOT_SUPPORTED
*
*/
#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR (0x410103) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS {
NV_DECLARE_ALIGNED(NvU64 memOffset, 8);
NvU32 memFormat;
NvU32 comprOffset;
NvU32 comprFormat;
NvU32 memAperture;
NvU32 gpuCacheAttr;
NvU32 gpuP2PCacheAttr;
NvU32 mmuContext;
NV_DECLARE_ALIGNED(NvU64 contigSegmentSize, 8);
} NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS;
/* valid memAperture return values */
#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM (0x00000000)
#define NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM (0x00000001)
/* valid gpuCacheAttr return values */
#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN (0x00000000)
#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED (0x00000001)
#define NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED (0x00000002)
/*
* NV0041_CTRL_CMD_GET_SURFACE_ZCULL_ID
*
* This command returns the Z-cull identifier for a surface.
* The value of ~0 is returned if there is none associated.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_BAD_OBJECT_HANDLE
* NVOS_STATUS_BAD_OBJECT_PARENT
* NVOS_STATUS_NOT_SUPPORTED
*
*/
#define NV0041_CTRL_CMD_GET_SURFACE_ZCULL_ID (0x410104) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS {
NvU32 zcullId;
} NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS;
/*
* NV0041_CTRL_CMD_GET_SURFACE_PARTITION_STRIDE
*
* This command returns the partition stride (in bytes) for real memory
* associated with the memory object.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_BAD_OBJECT_HANDLE
* NVOS_STATUS_BAD_OBJECT_PARENT
* NVOS_STATUS_NOT_SUPPORTED
*
*/
#define NV0041_CTRL_CMD_GET_SURFACE_PARTITION_STRIDE (0x410105) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS {
NvU32 partitionStride;
} NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS;
// return values for 'tilingFormat'
// XXX - the names for these are misleading
#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_INVALID (0x00000000)
#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB (0x00000001)
#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB_1HIGH (0x00000002)
#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_FB_4HIGH (0x00000003)
#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_UMA_1HIGH (0x00000004)
#define NV0041_CTRL_CMD_GET_SURFACE_TILING_FORMAT_UMA_4HIGH (0x00000005)
/*
* NV0041_CTRL_SURFACE_INFO
*
* This structure represents a single 32bit surface value. Clients
* request a particular surface value by specifying a unique surface
* information index.
*
* Legal surface information index values are:
* NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS
* This index is used to request the set of hw attributes associated
* with the surface. Each distinct attribute is represented by a
* single bit flag in the returned value.
* Legal flags values for this index are:
* NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR
* This surface has compression resources bound to it.
* NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL
* This surface has zcull resources bound to it.
* NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE
* This index is used to request the compression coverage (if any)
* in units of 64K for the associated surface. A value of zero indicates
* there are no compression resources associated with the surface.
* Legal return values range from zero to a maximum number of 64K units
* that is GPU implementation dependent.
* NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE
* This index is used to request the physically allocated size in units
* of 4K(NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR) for the associated
* surface.
* NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR
* This index is used to request the surface attribute field. The returned
* field value can be decoded using the NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_*
* DRF-style macros provided below.
* NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE
* This index is used to request the surface address space type.
* Returned values are described by NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE.
*/
typedef struct NV0041_CTRL_SURFACE_INFO {
NvU32 index;
NvU32 data;
} NV0041_CTRL_SURFACE_INFO;
/* valid surface info index values */
#define NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS (0x00000001)
#define NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE (0x00000005)
#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_SIZE (0x00000007)
#define NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR (0x00000008)
#define NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE (0x00000009)
/*
* This define indicates the scale factor of the reported physical size to the
* actual size in bytes. We use the scale factor to save space from the
* interface and account for large surfaces. To get the actual size,
* use `(NvU64)reported_size * NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR`.
*/
#define NV0041_CTRL_SURFACE_INFO_PHYS_SIZE_SCALE_FACTOR (0x1000)
/* valid surface info attr flags */
#define NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR (0x00000002)
#define NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL (0x00000004)
/* Valid surface info page size */
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE NVOS32_ATTR_PAGE_SIZE
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_DEFAULT NVOS32_ATTR_PAGE_SIZE_DEFAULT
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_4KB NVOS32_ATTR_PAGE_SIZE_4KB
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_BIG NVOS32_ATTR_PAGE_SIZE_BIG
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE_HUGE NVOS32_ATTR_PAGE_SIZE_HUGE
/* Valid surface info CPU coherency */
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY NVOS32_ATTR_COHERENCY
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_UNCACHED NVOS32_ATTR_COHERENCY_UNCACHED
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_CACHED NVOS32_ATTR_COHERENCY_CACHED
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_COMBINE NVOS32_ATTR_COHERENCY_WRITE_COMBINE
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_THROUGH NVOS32_ATTR_COHERENCY_WRITE_THROUGH
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_PROTECT NVOS32_ATTR_COHERENCY_WRITE_PROTECT
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_BACK NVOS32_ATTR_COHERENCY_WRITE_BACK
/*
* NV0041_CTRL_CMD_GET_SURFACE_INFO
*
* This command returns surface information for the associated memory object.
* Requests to retrieve surface information use a list of one or more
* NV0041_CTRL_SURFACE_INFO structures.
*
* surfaceInfoListSize
* This field specifies the number of entries on the caller's
* surfaceInfoList.
* surfaceInfoList
* This field specifies a pointer in the caller's address space
* to the buffer into which the surface information is to be returned.
* This buffer must be at least as big as surfaceInfoListSize multiplied
* by the size of the NV0041_CTRL_SURFACE_INFO structure.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0041_CTRL_CMD_GET_SURFACE_INFO (0x410110) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_INFO_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_GET_SURFACE_INFO_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV0041_CTRL_GET_SURFACE_INFO_PARAMS {
NvU32 surfaceInfoListSize;
NV_DECLARE_ALIGNED(NvP64 surfaceInfoList, 8);
} NV0041_CTRL_GET_SURFACE_INFO_PARAMS;
/*
* NV0041_CTRL_CMD_GET_SURFACE_COMPRESSION_COVERAGE
*
* This command returns the percentage of surface compression tag coverage.
* The value of 0 is returned if there are no tags associated.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_BAD_OBJECT_HANDLE
* NVOS_STATUS_BAD_OBJECT_PARENT
* NVOS_STATUS_NOT_SUPPORTED
*
*/
#define NV0041_CTRL_CMD_GET_SURFACE_COMPRESSION_COVERAGE (0x410112) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_MESSAGE_ID (0x12U)
typedef struct NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS {
NvHandle hSubDevice; /* if non zero subDevice handle of local GPU */
NvU32 lineMin;
NvU32 lineMax;
NvU32 format;
} NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS;
/*
* NV0041_CTRL_CMD_GET_FBMEM_BUS_ADDR
*
* This command returns the BAR1 physical address of a
* Memory mapping made using NvRmMapMemory()
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_INVALID_DATA
* NV_ERR_INVALID_CLIENT
* NV_ERR_INVALID_OBJECT_HANDLE
*
*/
#define NV0041_CTRL_CMD_GET_FBMEM_BUS_ADDR (0x410114) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS_MESSAGE_ID (0x14U)
typedef struct NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pLinearAddress, 8); /* [in] Linear address of CPU mapping */
NV_DECLARE_ALIGNED(NvU64 busAddress, 8); /* [out] BAR1 address */
} NV0041_CTRL_GET_FBMEM_BUS_ADDR_PARAMS;
/*
* NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE
*
* This command flushes a cache on the GPU which all memory accesses go
* through. The types of flushes supported by this API may not be supported by
* all hardware. Attempting an unsupported flush type will result in an error.
*
* flags
* Contains flags to control various aspects of the flush. Valid values
* are defined in NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS*. Not all
* flags are valid for all GPUs.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NVOS_STATUS_INVALID_ARGUMENT
* NVOS_STATUS_INVALID_STATE
*
* See Also:
* NV0080_CTRL_CMD_DMA_FLUSH
* Performs flush operations in broadcast for the GPU cache and other hardware
* engines. Use this call if you want to flush all GPU caches in a
* broadcast device.
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
* Flushes the entire GPU cache or a set of physical addresses (if the
* hardware supports it). Use this call if you want to flush a set of
* addresses or the entire GPU cache in unicast mode.
*
*/
#define NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE (0x410116) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0x16U)
typedef struct NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS {
NvU32 flags;
} NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS;
#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK 0:0
#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO (0x00000000)
#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES (0x00000001)
#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE 1:1
#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO (0x00000000)
#define NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES (0x00000001)
/*
* NV0041_CTRL_CMD_GET_EME_PAGE_SIZE
*
* This command may be used to get the memory page size
*
* Parameters:
* pageSize [OUT]
* pageSize with associated memory descriptor
*
* Possible status values are:
* NV_OK
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_NOT_SUPPORTED
*/
#define NV0041_CTRL_CMD_GET_MEM_PAGE_SIZE (0x410118) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID (0x18U)
typedef struct NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS {
NvU32 pageSize; /* [out] - page size */
} NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS;
/*
* NV0041_CTRL_CMD_UPDATE_SURFACE_COMPRESSION
*
* Acquire/release compression for surface
*
* Parameters:
* bRelease [IN]
* true = release compression; false = acquire compression
*/
#define NV0041_CTRL_CMD_UPDATE_SURFACE_COMPRESSION (0x410119) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS_MESSAGE_ID (0x19U)
typedef struct NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS {
NvBool bRelease; /* [in] - acquire/release setting */
} NV0041_CTRL_UPDATE_SURFACE_COMPRESSION_PARAMS;
#define NV0041_CTRL_CMD_PRINT_LABELS_PARAMS_MESSAGE_ID (0x50U)
typedef struct NV0041_CTRL_CMD_PRINT_LABELS_PARAMS {
NvU32 tag; /* [in] */
} NV0041_CTRL_CMD_PRINT_LABELS_PARAMS;
#define NV0041_CTRL_CMD_SET_LABEL_PARAMS_MESSAGE_ID (0x51U)
typedef struct NV0041_CTRL_CMD_SET_LABEL_PARAMS {
NvU32 tag; /* [in] */
} NV0041_CTRL_CMD_SET_LABEL_PARAMS;
#define NV0041_CTRL_CMD_SET_LABEL (0x410151) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_SET_LABEL_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_CMD_GET_LABEL (0x410152) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_GET_LABEL_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_CMD_GET_LABEL_PARAMS_MESSAGE_ID (0x52U)
typedef struct NV0041_CTRL_CMD_GET_LABEL_PARAMS {
NvU32 tag; /* [in] */
} NV0041_CTRL_CMD_GET_LABEL_PARAMS;
/*
* NV0041_CTRL_CMD_SET_TAG
*
* This command sets memory allocation tag used for debugging.
* Every client has it's own memory allocation tag and tag is copying when object is duping.
* This control can be used for shared allocations to change it's tag.
*/
#define NV0041_CTRL_CMD_SET_TAG (0x410120) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_SET_TAG_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_CMD_SET_TAG_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV0041_CTRL_CMD_SET_TAG_PARAMS {
NvU32 tag; /* [in] */
} NV0041_CTRL_CMD_SET_TAG_PARAMS;
/*
* NV0041_CTRL_CMD_GET_TAG
*
* This command returns memory allocation tag used for debugging.
*/
#define NV0041_CTRL_CMD_GET_TAG (0x410121) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_CMD_GET_TAG_PARAMS_MESSAGE_ID" */
#define NV0041_CTRL_CMD_GET_TAG_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV0041_CTRL_CMD_GET_TAG_PARAMS {
NvU32 tag; /* [out] */
} NV0041_CTRL_CMD_GET_TAG_PARAMS;
/* _ctrl0041_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2015,2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073.finn
//
#include "ctrl/ctrlxxxx.h"
/* category-specific includes */
#include "ctrl0073/ctrl0073system.h"
#include "ctrl0073/ctrl0073specific.h"
#include "ctrl0073/ctrl0073stereo.h"
#include "ctrl0073/ctrl0073event.h"
#include "ctrl0073/ctrl0073internal.h"
#include "ctrl0073/ctrl0073dfp.h"
#include "ctrl0073/ctrl0073dp.h"
#include "ctrl0073/ctrl0073svp.h"
#include "ctrl0073/ctrl0073dpu.h"
#include "ctrl0073/ctrl0073psr.h"

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV04_DISPLAY_COMMON control commands and parameters */
#define NV0073_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0073, NV0073_CTRL_##cat, idx)
/* NV04_DISPLAY_COMMON command categories (6bits) */
#define NV0073_CTRL_RESERVED (0x00U)
#define NV0073_CTRL_SYSTEM (0x01U)
#define NV0073_CTRL_SPECIFIC (0x02U)
#define NV0073_CTRL_EVENT (0x03U)
#define NV0073_CTRL_INTERNAL (0x04U)
#define NV0073_CTRL_DFP (0x11U)
#define NV0073_CTRL_DP (0x13U)
#define NV0073_CTRL_SVP (0x14U)
#define NV0073_CTRL_DPU (0x15U)
#define NV0073_CTRL_PSR (0x16U)
#define NV0073_CTRL_STEREO (0x17U)
/*
* NV0073_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0073_CTRL_CMD_NULL (0x730000U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID << 8) | 0x0" */
/* _ctrl0073base_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073dpu.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073event.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073internal.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
#include "ctrl/ctrl0073/ctrl0073system.h"
#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID" */
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS {
NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS params;
} NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS;
/* ctrl0073internal_h */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073psr.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073stereo.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/*
* NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS
*
* Sets new video mode timings
* E.g. from display driver on mode set
*
* Parameters:
* [IN] subDeviceInstance - This parameter specifies the subdevice instance
* within the NV04_DISPLAY_COMMON parent device to which the operation
* should be directed. This parameter must specify a value between
* zero and the total number of subdevices within the parent device.
* This parameter should be set to zero for default behavior.
* [IN] head - head to be passed to stereoDongleControl
* [IN] timings - new timings to be set
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU
*/
#define NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS (0x731703U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS_MESSAGE_ID" */
typedef struct NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS {
NvU32 PixelClock;
NvU16 TotalWidth;
NvU16 VisibleImageWidth;
NvU16 HorizontalBlankStart;
NvU16 HorizontalBlankWidth;
NvU16 HorizontalSyncStart;
NvU16 HorizontalSyncWidth;
NvU16 TotalHeight;
NvU16 VisibleImageHeight;
NvU16 VerticalBlankStart;
NvU16 VerticalBlankHeight;
NvU16 VerticalSyncStart;
NvU16 VerticalSyncHeight;
NvU16 InterlacedMode;
NvU16 DoubleScanMode;
NvU16 MonitorVendorId;
NvU16 MonitorProductId;
} NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS;
#define NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS {
NvU32 subDeviceInstance;
NvU32 head;
NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS timings;
} NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS;
/*
* NV0073_CTRL_CMD_STEREO_DONGLE_ACTIVATE
*
* stereoDongleActivate wrapper / NV_STEREO_DONGLE_ACTIVATE_DATA_ACTIVE_YES
* Updates sbios of 3D stereo state active
*
* Parameters:
* [IN] subDeviceInstance - This parameter specifies the subdevice instance
* within the NV04_DISPLAY_COMMON parent device to which the operation
* should be directed. This parameter must specify a value between
* zero and the total number of subdevices within the parent device.
* This parameter should be set to zero for default behavior.
* [IN] head - head to be passed to stereoDongleActivate
* [IN] bSDA - enable stereo on DDC SDA
* [IN] bWorkStation - is workstation stereo?
* [IN] bDLP - is checkerboard DLP Stereo?
* [IN] IRPower - IR power value
* [IN] flywheel - FlyWheel value
* [IN] bRegIgnore - use reg?
* [IN] bI2cEmitter - Sets NV_STEREO_DONGLE_ACTVATE_DATA_I2C_EMITTER_YES and pStereo->bAegisDT
* [IN] bForcedSupported - Sets NV_STEREO_DONGLE_FORCED_SUPPORTED_YES and pStereo->GPIOControlledDongle
* [IN] bInfoFrame - Aegis DT with DP InfoFrame
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT - if (head > OBJ_MAX_HEADS)
* NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU
*/
#define NV0073_CTRL_CMD_STEREO_DONGLE_ACTIVATE (0x731704U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS {
NvU32 subDeviceInstance;
NvU32 head;
NvBool bSDA;
NvBool bWorkStation;
NvBool bDLP;
NvU8 IRPower;
NvU8 flywheel;
NvBool bRegIgnore;
NvBool bI2cEmitter;
NvBool bForcedSupported;
NvBool bInfoFrame;
} NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS;
/*
* NV0073_CTRL_CMD_STEREO_DONGLE_DEACTIVATE
*
* stereoDongleActivate wrapper / NV_STEREO_DONGLE_ACTIVATE_DATA_ACTIVE_NO
*
* If active count<=0 then no 3D app is running which indicates
* that we have really deactivated the stereo, updates sbios of 3D stereo state NOT ACTIVE.
*
* Parameters:
* [IN] subDeviceInstance - This parameter specifies the subdevice instance
* within the NV04_DISPLAY_COMMON parent device to which the operation
* should be directed. This parameter must specify a value between
* zero and the total number of subdevices within the parent device.
* This parameter should be set to zero for default behavior.
* [IN] head - head to be passed to stereoDongleActivate
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT - if (head > OBJ_MAX_HEADS)
* NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU
*/
#define NV0073_CTRL_CMD_STEREO_DONGLE_DEACTIVATE (0x731705U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS {
NvU32 subDeviceInstance;
NvU32 head;
} NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS;
/* _ctrl0073stereo_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073svp.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080.finn
//
#include "ctrl0080/ctrl0080bif.h"
#include "ctrl0080/ctrl0080gpu.h"
#include "ctrl0080/ctrl0080clk.h"
#include "ctrl0080/ctrl0080dma.h"
#include "ctrl0080/ctrl0080gr.h"
#include "ctrl0080/ctrl0080cipher.h"
#include "ctrl0080/ctrl0080fb.h"
#include "ctrl0080/ctrl0080fifo.h"
#include "ctrl0080/ctrl0080host.h"
#include "ctrl0080/ctrl0080perf.h"
#include "ctrl0080/ctrl0080msenc.h"
#include "ctrl0080/ctrl0080bsp.h"
#include "ctrl0080/ctrl0080rc.h"
#include "ctrl0080/ctrl0080nvjpg.h"
#include "ctrl0080/ctrl0080unix.h"
#include "ctrl0080/ctrl0080internal.h"

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV01_DEVICE_XX/NV03_DEVICE control commands and parameters */
#define NV0080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0080, NV0080_CTRL_##cat, idx)
/* GPU device command categories (6bits) */
#define NV0080_CTRL_RESERVED (0x00)
#define NV0080_CTRL_BIF (0x01)
#define NV0080_CTRL_GPU (0x02)
#define NV0080_CTRL_CLK (0x10)
#define NV0080_CTRL_GR (0x11)
#define NV0080_CTRL_CIPHER (0x12)
#define NV0080_CTRL_FB (0x13)
#define NV0080_CTRL_HOST (0x14)
#define NV0080_CTRL_VIDEO (0x15)
#define NV0080_CTRL_FIFO (0x17)
#define NV0080_CTRL_DMA (0x18)
#define NV0080_CTRL_PERF (0x19)
#define NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED (0x99) /* finn: Evaluated from "(NV0080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV0080_CTRL_MSENC (0x1B)
#define NV0080_CTRL_BSP (0x1C)
#define NV0080_CTRL_RC (0x1D)
#define NV0080_CTRL_OS_UNIX (0x1E)
#define NV0080_CTRL_NVJPG (0x1F)
#define NV0080_CTRL_INTERNAL (0x20)
#define NV0080_CTRL_NVLINK (0x21)
/*
* NV0080_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_CMD_NULL (0x800000) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */
/* _ctrl0080base_h_ */
/* extract device cap setting from specified category-specific caps table */
#define NV0080_CTRL_GET_CAP(cat,tbl,c) \
NV0080_CTRL_##cat##_GET_CAP(tbl, NV0080_CTRL_##cat##_CAPS_##c)

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/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080bif.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/*
* NV0080_CTRL_CMD_BIF_RESET
*
* This command initiates the specified reset type on the GPU.
*
* flags
* Specifies various arguments to the reset operation.
*
* Supported fields include:
*
* NV0080_CTRL_BIF_RESET_FLAGS_TYPE
* When set to _SW_RESET, a SW (fullchip) reset is performed. When set
* to _SBR, a secondary-bus reset is performed. When set to
* _FUNDAMENTAL, a fundamental reset is performed.
*
* NOTE: _FUNDAMENTAL is not yet supported.
*
* Possible status return values are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_BIF_RESET (0x800102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_BIF_RESET_PARAMS {
NvU32 flags;
} NV0080_CTRL_BIF_RESET_PARAMS;
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 2:0
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET (0x00000001)
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR (0x00000002)
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL (0x00000003)
/*
* NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR
*
* baseDmaSysmemAddr
* This parameter represents the base DMA address for sysmem which will be
* added to all DMA accesses issued by GPU. Currently GPUs do not support 64-bit physical address,
* hence if sysmem is greater than max GPU supported physical address width, this address
* will be non-zero
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_OBJECT_PARENT
*/
#define NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR (0x800103) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS {
NV_DECLARE_ALIGNED(NvU64 baseDmaSysmemAddr, 8);
} NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS;
/*
* NV0080_CTRL_BIF_SET_ASPM_FEATURE
*
* aspmFeatureSupported
* ASPM feature override by client
*
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE (0x800104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS {
NvU32 aspmFeatureSupported;
} NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS;
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S 0:0
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED 0x000000001
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED 0x000000000
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1 1:1
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED 0x000000001
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED 0x000000000
/* _ctrl0080bif_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080bsp.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE bit stream processor control commands and parameters */
/*
* NV0080_CTRL_CMD_BSP_GET_CAPS
*
* This command returns the set of BSP capabilities for the device
* in the form of an array of unsigned bytes. BSP capabilities
* include supported features and required workarounds for the decoder
* within the device, each represented by a byte offset into the
* table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_BSP_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the BSP caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
* instanceId
* This parameter specifies the instance Id of NVDEC for which
* cap bits are requested.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_BSP_GET_CAPS (0x801c01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BSP_INTERFACE_ID << 8) | NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_BSP_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
NvU32 instanceId;
} NV0080_CTRL_BSP_GET_CAPS_PARAMS;
/*
* Size in bytes of bsp caps table. This value should be one greater
* than the largest byte_index value above.
*/
#define NV0080_CTRL_BSP_CAPS_TBL_SIZE 8
/*
* NV0080_CTRL_CMD_BSP_GET_CAPS_V2
*
* This command returns the set of BSP capabilities for the device
* in the form of an array of unsigned bytes. BSP capabilities
* include supported features and required workarounds for the decoder
* within the device, each represented by a byte offset into the
* table and a bit position within that byte.
* (The V2 version flattens the capsTbl array pointer).
*
* capsTbl
* This parameter is an array of unsigned bytes where the BSP caps bits
* will be transferred by the RM.
* instanceId
* This parameter specifies the instance Id of NVDEC for which
* cap bits are requested.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_BSP_GET_CAPS_V2 (0x801c02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BSP_INTERFACE_ID << 8) | NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID" */
#define NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 {
NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE];
NvU32 instanceId;
} NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2;
/* _ctrl0080bsp_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080cipher.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080clk.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080dma.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE dma control commands and parameters */
/*
* NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK
*
* This parameter returns the parameters specific to a PTE as follows:
* pageSize
* GET: This parameter returns the page size of the PTE information
* being returned. If 0, then this pteBlock[] array entry is
* invalid or not used. (pteBlock[0] is always used.)
* SET: This parameter specifies the page size of the PTE information
* to be set. If 0, then this pteBlock[] array entry is invalid
* or not used. (pteBlock[0] is always used.)
* pteEntrySize
* GET: This parameter returns the size of the PTE in bytes for this GPU.
* SET: N/A
* comptagLine
* GET: This parameter returns the comptagline field of the corresponding PTE.
* SET: This parameter sets the comptagline field of the corresponding PTE.
* Incorrect values may lead to dire consequences.
* kind
* GET: This parameter returns the kind field of the corresponding PTE.
* SET: This parameter sets the kind field of the corresponding PTE.
* Incorrect values may lead to undesirable consequences.
* pteFlags
* This parameter returns various fields from the PTE, these are:
* FLAGS_VALID:
* GET: This flag returns the valid bit of the PTE.
* SET: This flag sets the valid bit of the PTE.
* FLAGS_ENCRYPTED:
* GET: This flag returns the encrypted bit of the PTE. Not all GPUs
* support encryption. If not supported, this flag will be set to
* NOT_SUPPORTED.
* SET: This flag sets the encrypted bit of the PTE.
* FLAGS_APERTURE:
* GET: This flag returns the aperture field of the PTE. See
* NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_FLAGS_APERTURE_* for values.
* SET: This flag sets the aperture field of the PTE. See
* NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_FLAGS_APERTURE_* for values.
* FLAGS_COMPTAGS:
* GET: This flag returns the comptags field of the PTE. (Not used on Fermi)
* SET: N/A
* FLAGS_GPU_CACHED:
* GET: This flag returns the GPU cacheable bit of the PTE. GPU caching of
* sysmem was added in iGT21a and Fermi. If not supported, this flag
* will be set to NOT_SUPPORTED.
* SET: N/A for specific chips, e.g., GF100
* FLAGS_SHADER_ACCESS:
* GET: This flag returns the shader access control of the PTE. This feature
* was introduced in Kepler. If not supported, this flag will be set to
* NOT_SUPPORTED.
* SET: N/A
*/
typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK {
NvU32 pageSize;
NV_DECLARE_ALIGNED(NvU64 pteEntrySize, 8);
NvU32 comptagLine;
NvU32 kind;
NvU32 pteFlags;
} NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK;
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID 0:0
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED 2:1
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED (0x00000002U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE 6:3
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY (0x00000002U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY (0x00000003U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS 10:7
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1 (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2 (0x00000002U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4 (0x00000004U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED 12:11
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED (0x00000002U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS 14:13
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY (0x00000002U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED (0x00000003U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY 15:15
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC 16:16
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING 17:17
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED 18:18
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE (0x00000001U)
/*
* NV0080_CTRL_DMA_GET_PTE_INFO
*
* This command queries PTE information for the specified GPU virtual address.
*
* gpuAddr
* This parameter specifies the GPU virtual address for which PTE
* information is to be returned.
* skipVASpaceInit
* This parameter specifies(true/false) whether the VA Space
* initialization should be skipped in this ctrl call.
* pteBlocks
* This parameter returns the page size-specific attributes of a PTE.
* Please see NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK.
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
* NV_ERR_GENERIC
*/
#define NV0080_CTRL_CMD_DMA_GET_PTE_INFO (0x801801U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS 4U
#define NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8);
NvU32 subDeviceId;
NvU8 skipVASpaceInit;
NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS], 8);
NvHandle hVASpace;
} NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS;
/*
* NV0080_CTRL_DMA_SET_PTE_INFO
*
* This command sets PTE information for the specified GPU virtual address.
* Usage of parameter and field definitions is identical to that of
* NV0080_CTRL_DMA_GET_PTE_INFO, with the following exception:
*
* - pteFlags field NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS is ignored,
* as this setting is specified via the kind specification.
* - pteEntrySize is ignored, as this setting is read-only in the GET case.
* - hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space.
*
*/
#define NV0080_CTRL_CMD_DMA_SET_PTE_INFO (0x80180aU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS 4U
#define NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8);
NvU32 subDeviceId;
NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS], 8);
NvHandle hVASpace;
} NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS;
#define NV0080_CTRL_CMD_DMA_FILL_PTE_MEM (0x801802U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS {
NvU32 pageCount;
struct {
NvHandle hClient;
NvHandle hDevice;
NvHandle hMemory;
NvU32 subDeviceId;
} hwResource;
struct {
NvU32 fbKind;
NvU32 sysKind;
NvU32 compTagStartOffset;
} comprInfo;
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8);
NV_DECLARE_ALIGNED(NvP64 pageArray, 8);
NV_DECLARE_ALIGNED(NvP64 pteMem, 8);
NvU32 pteMemPfn;
NvU32 pageSize;
NvU32 startPageIndex;
NvU32 flags;
NvHandle hSrcVASpace;
NvHandle hTgtVASpace;
NvU32 peerId;
} NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS;
/*
* NV0080_CTRL_DMA_FLUSH
*
* This command flushes the specified target unit
*
* targetUnit
* The unit to flush, either L2 cache or compression tag cache.
* This field is a logical OR of the individual fields such as
* L2 cache or compression tag cache. Also L2 invalidation for
* either SYSMEM/PEERMEM is triggered. But this invalidation is
* for FERMI.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*
* See Also:
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
* Flushes the entire GPU cache or a set of physical addresses (if the
* hardware supports it). Use this call if you want to flush a set of
* addresses or the entire GPU cache in unicast mode.
* NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE
* Flushes memory associated with a single allocation if the hardware
* supports it. Use this call if you want to flush a single allocation and
* you have a memory object describing the physical memory.
*/
#define NV0080_CTRL_CMD_DMA_FLUSH (0x801805U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0080_CTRL_DMA_FLUSH_PARAMS {
NvU32 targetUnit;
} NV0080_CTRL_DMA_FLUSH_PARAMS;
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2 0:0
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE (0x00000000U)
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE (0x00000001U)
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG 1:1
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE (0x00000000U)
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE (0x00000001U)
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB 2:2
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE (0x00000000U)
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE (0x00000001U)
// This is exclusively for Fermi
// The selection of non-zero valued bit-fields avoids the routing
// into the above cases and vice-versa
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE 4:3
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM (0x00000001U)
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM (0x00000002U)
/**
* NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS
*
* This command returns information about the VA caps on the GPU
*
* vaBitCount
* Returns number of bits in a virtual address
* pdeCoverageBitCount
* Returns number of VA bits covered in each PDE. One PDE covers
* 2^pdeCoverageBitCount bytes.
*
* bigPageSize
* Size of the big page
* compressionPageSize
* Size of region each compression tag covers
* dualPageTableSupported
* TRUE if one page table can map with both 4KB and big pages
*
* numPageTableFormats
* Returns the number of different page table sizes supported by the RM
* pageTableBigFormat
* pageTable4KFormat[]
* Returns size in bytes and number of VA bits covered by each page table
* format. Up to MAX_NUM_PAGE_TABLE_FORMATS can be returned. The most
* compact format will be pageTableSize[0] and the least compact format
* will be last.
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space.
* vaRangeLo
* Indicates the start of usable VA range.
*
* hugePageSize
* Size of the huge page if supported, 0 otherwise.
*
* vaSpaceId
* Virtual Address Space id assigned by RM.
* Only relevant on AMODEL.
*
* pageSize512MB
* Size of the 512MB page if supported, 0 otherwise.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS (0x801806U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID" */
typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT {
NvU32 pageTableSize;
NvU32 pageTableCoverage;
} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT;
#define NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS (16U)
#define NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS {
NvU32 vaBitCount;
NvU32 pdeCoverageBitCount;
NvU32 num4KPageTableFormats;
NvU32 bigPageSize;
NvU32 compressionPageSize;
NvU32 dualPageTableSupported;
NvU32 idealVRAMPageSize;
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTableBigFormat;
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTable4KFormat[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS];
NvHandle hVASpace;
NV_DECLARE_ALIGNED(NvU64 vaRangeLo, 8);
NvU32 hugePageSize;
NvU32 vaSpaceId;
NvU32 pageSize512MB;
} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS;
/*
* Adding a version define to allow clients to access valid
* parameters based on version.
*/
#define NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO 0x1U
/*
* NV0080_CTRL_DMA_GET_PDE_INFO
*
* This command queries PDE information for the specified GPU virtual address.
*
* gpuAddr
* This parameter specifies the GPU virtual address for which PDE
* information is to be returned.
* pdeVirtAddr
* This parameter returns the GPU virtual address of the PDE.
* pdeEntrySize
* This parameter returns the size of the PDE in bytes for this GPU.
* pdeAddrSpace
* This parameter returns the GPU address space of the PDE.
* pdeSize
* This parameter returns the fractional size of the page table(s) as
* actually set in the PDE, FULL, 1/2, 1/4 or 1/8. (This amount may
* differ from that derived from pdeVASpaceSize.) Intended for VERIF only.
* pteBlocks
* This parameter returns the page size-specific parameters as follows:
* ptePhysAddr
* This parameter returns the GPU physical address of the page table.
* pteCacheAttrib
* This parameter returns the caching attribute of the
* GPU physical address of the page table.
* pteEntrySize
* This parameter returns the size of the PTE in bytes for this GPU.
* pageSize
* This parameter returns the page size of the page table.
* If pageSize == 0, then this PTE block is not valid.
* pteAddrSpace
* This parameter returns the GPU address space of the page table.
* pdeVASpaceSize
* This parameter returns the size of the VA space addressable by
* the page table if fully used (i.e., if all PTEs marked VALID).
* pdbAddr
* This parameter returns the PDB address for the PDE.
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV0080_CTRL_CMD_DMA_GET_PDE_INFO (0x801809U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID" */
typedef struct NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK {
NV_DECLARE_ALIGNED(NvU64 ptePhysAddr, 8);
NvU32 pteCacheAttrib;
NvU32 pteEntrySize;
NvU32 pageSize;
NvU32 pteAddrSpace;
NvU32 pdeVASpaceSize;
NvU32 pdeFlags;
} NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK;
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY (0x00000000U)
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U)
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U)
#define NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS 4U
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8);
NV_DECLARE_ALIGNED(NvU64 pdeVirtAddr, 8);
NvU32 pdeEntrySize;
NvU32 pdeAddrSpace;
NvU32 pdeSize;
NvU32 subDeviceId;
NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS], 8);
NV_DECLARE_ALIGNED(NvU64 pdbAddr, 8);
NvHandle hVASpace;
} NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS;
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY (0x00000000U)
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U)
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U)
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL 1U
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF 2U
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER 3U
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH 4U
/*
* NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET
*
* This command invalidates PDB target setting in hardware.
* After execeution of this command PDB target would be in undefined state.
*
* Returns error if the PDB target can not be invalidate.
*
* This call is only supported on chips fermi and later chips.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET (0x80180bU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | 0xB" */
/*
* NV0080_CTRL_CMD_DMA_INVALIDATE_TLB
*
* This command invalidates the GPU TLB. This is intended to be used
* for RM clients that manage their own TLB consistency when updating
* page tables on their own, or with DEFER_TLB_INVALIDATION options
* to other RM APIs.
*
* hVASpace
* This parameter specifies the VASpace object whose MMU TLB entries
* needs to be invalidated, if the flag is set to NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE.
* Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace.
* Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC.
*
* flags
* This parameter can be used to specify any flags needed
* for the invlalidation request.
* NV0080_CTRL_DMA_INVALIDATE_TLB_ALL
* When set to TRUE this flag requests a global invalidate.
* When set to FALSE this flag requests a chip-specfic
* optimization to invalidate only the address space bound
* to the associated hDevice.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_TIMEOUT_RETRY
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_DMA_INVALIDATE_TLB (0x80180cU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS {
NvHandle hVASpace;
NvU32 flags;
} NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS;
#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL 0:0
#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE (0x00000001U)
/**
* NV0080_CTRL_CMD_DMA_GET_CAPS
*
* This command returns the set of DMA capabilities for the device
* in the form of an array of unsigned bytes. DMA capabilities
* include supported features and required workarounds for address
* translation system within the device, each represented by a byte
* offset into the table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_DMA_CAPS_TBL_SIZE.
*
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the framebuffer caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* 32BIT_POINTER_ENFORCED
* If this property is TRUE NVOS32 and NVOS46 calls with
* 32BIT_POINTER_DISABLED will return addresses above 4GB.
*
* SHADER_ACCESS_SUPPORTED
* If this property is set, the MMU in the system supports the independent
* access bits for the shader. This is accessed with the following fields:
* NVOS46_FLAGS_SHADER_ACCESS
* NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_FLAGS_SHADER_ACCESS
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_DMA_GET_CAPS (0x80180dU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID" */
/* size in bytes of fb caps table */
#define NV0080_CTRL_DMA_CAPS_TBL_SIZE 8U
#define NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV0080_CTRL_DMA_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NvU8 capsTbl[NV0080_CTRL_DMA_CAPS_TBL_SIZE];
} NV0080_CTRL_DMA_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0080_CTRL_DMA_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0080_CTRL_DMA_CAPS_32BIT_POINTER_ENFORCED 0:0x01
#define NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED 0:0x04
#define NV0080_CTRL_DMA_CAPS_SPARSE_VIRTUAL_SUPPORTED 0:0x08
#define NV0080_CTRL_DMA_CAPS_MULTIPLE_VA_SPACES_SUPPORTED 0:0x10
/*
* NV0080_CTRL_DMA_SET_VA_SPACE_SIZE
*
* Change the size of an existing VA space.
* NOTE: Currently this only supports growing the size, not shrinking.
*
* 1. Allocate new page directory able to map extended range.
* 2. Copy existing PDEs from old directory to new directory.
* 3. Initialize new PDEs to invalid.
* 4. Update instmem to point to new page directory.
* 5. Free old page directory.
*
* vaSpaceSize
* On input, the requested size of the VA space in bytes.
* On output, the actual resulting VA space size.
*
* The actual size will be greater than or equal to the requested size,
* unless NV0080_CTRL_DMA_GROW_VA_SPACE_SIZE_MAX is requested, which
* requests the maximum available.
*
* NOTE: Specific size requests (e.g. other than SIZE_MAX) must account
* for the VA hole at the beginning of the range which is used to
* distinguish NULL pointers. This region is not counted as part
* of the vaSpaceSize since it is not allocatable.
*
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space
* associated with the client/device pair.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INSUFFICIENT_RESOURCES
*/
#define NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE (0x80180eU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 vaSpaceSize, 8);
NvHandle hVASpace;
} NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS;
#define NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX (0xFFFFFFFFFFFFFFFFULL)
/*
* NV0080_CTRL_DMA_UPDATE_PDE_2
*
* This command updates a single PDE for the given (hClient, hDevice)
* with specific attributes.
* This command is only available on Windows and MODS platforms.
* This command can be called by kernel clients only.
*
* The VA range the PDE maps must be contained by a VA allocation marked with
* NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED.
* However if the MODS-only FORCE_OVERRIDE flag is set this restriction is relaxed.
*
* RM does not track the PDE's attributes in SW - this control simply stuffs
* the PDE in memory after translating and checking the parameters.
*
* Parameters are checked for relative consistency (e.g. valid domains),
* but it is the client's responsibility to provide correct page table
* addresses, e.g. global consistency is not checked.
*
* It is also the client's responsibility to flush/invalidate the MMU
* when appropriate, either by setting the _FLUSH_PDE_CACHE flag for this
* call or by flushing through other APIs.
* This control does not flush automatically to allow batches of calls
* to be made before a single flush.
*
* ptParams
* Page-size-specific parameters, as follows:
*
* physAddr
* Base address of physically contiguous memory of page table.
* Must be aligned sufficiently for the PDE address field.
* numEntries
* Deprecated and ignored.
* Use FLAGS_PDE_SIZE that applies to the tables for all page sizes.
* aperture
* Address space the base address applies to.
* Can be left as INVALID to ignore this page table size.
*
* pdeIndex
* The PDE index this update applies to.
* flags
* See NV0080_CTRL_DMA_UPDATE_PDE_FLAGS_*.
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space
* associated with the client/device pair.
* pPdeBuffer [out]
* Kernel pointer to 64 bit unsigned integer representing a Page Dir Entry
* that needs to be updated. It should point to memory as wide as the Page Dir
* Entry.
*
* If NULL, Page Dir Entry updates will go to the internally managed Page Dir.
* If not NULL, the updates will be written to this buffer.
*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_DMA_UPDATE_PDE_2 (0x80180fU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID" */
typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
NvU32 numEntries; // deprecated
NvU32 aperture;
} NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS;
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID (0x00000000U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY (0x00000001U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY (0x00000002U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY (0x00000003U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL 0U
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG 1U
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE 2U
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID (0xFU)
typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS {
NvU32 pdeIndex;
NvU32 flags;
NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS ptParams[NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE], 8);
NvHandle hVASpace;
NV_DECLARE_ALIGNED(NvP64 pPdeBuffer, 8); // NV_MMU_VER2_PDE__SIZE
NvU32 subDeviceId; // ID+1, 0 for BC
} NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS;
/*!
* If set a PDE cache flush (MMU invalidate) will be performed.
*/
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE 0:0
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE (0x00000001U)
/*!
* For verification purposes (MODS-only) this flag may be set to modify any PDE
* in the VA space (RM managed or externally managed).
* It is up to caller to restore any changes properly (or to expect faults).
*/
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE 1:1
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE (0x00000001U)
/*!
* Directly controls the PDE_SIZE field (size of the page tables pointed to by this PDE).
*/
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE 3:2
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL (0x00000000U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF (0x00000001U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER (0x00000002U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH (0x00000003U)
/*!
* Used to specify if the allocation is sparse. Applicable only in case of
* VA Space managed by OS, as in WDDM2.0
*/
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE 4:4
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE (0x00000001U)
/*
* NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE
* This interface will create a corresponding privileged
* kernel address space that will mirror user space allocations in this
* VASPACE.
* The user can either pass a FERMI_VASPACE_A handle or RM will use the
* vaspace associated with the client/device if hVaspace is passed as
* NULL.
* Once this property is set, the user will not be able to make allocations
* from the top most PDE of this address space.
*
* The user is expected to call this function as soon as he has created
* the device/Vaspace object. If the user has already made VA allocations
* in this vaspace then this call will return a failure
* (NV_ERR_INVALID_STATE).
* The Vaspace should have no VA allocations when this call is made.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE (0x801810U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS {
NvHandle hVASpace;
} NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS;
/*
* NV0080_CTRL_DMA_SET_DEFAULT_VASPACE
* This is a special control call provided for KMD to use.
* It will associate an allocated Address Space Object as the
* default address space of the device.
*
* This is added so that the USER can move to using address space objects when they
* want to specify the size of the big page size they want to use but still want
* to use the rest of the relevant RM apis without specifying the hVASpace.
*
* This call will succeed only if there is already no VASPACE associated with the
* device. This means the user will have to call this before he has made any allocations
* on this device/address space.
*
* The hVASpace that is passed in to be associated shoould belong to the parent device that
* this call is made for. This call will fail if we try to associate a VASpace belonging to
* some other client/device.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*
*/
#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE (0x801812U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID (0x12U)
typedef struct NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS {
NvHandle hVASpace;
} NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS;
/*!
* NV0080_CTRL_DMA_SET_PAGE_DIRECTORY
*
* Move an existing VA space to an externally-managed top-level page directory.
* The VA space must have been created in SHARED_MANAGEMENT mode.
* For lifecycle details, see NV_VASPACE_ALLOCATION_PARAMETERS documentation in nvos.h.
*
* RM will propagate the update to all channels using the VA space.
*
* NOTE: All channels using this VA space are expected to be idle and unscheduled prior
* to and during this control call - it is responsibility of caller to ensure this.
*
* physAddress
* Physical address of the new page directory within the aperture specified by flags.
* numEntries
* Number of entries in the new page directory.
* The backing phyical memory must be at least this size (multiplied by entry size).
* flags
* APERTURE
* Specifies which physical aperture the page directory resides.
* PRESERVE_PDES
* Deprecated - RM will always copy the RM-managed PDEs from the old page directory
* to the new page directory.
* ALL_CHANNELS
* If true, RM will update the instance blocks for all channels using
* the VAS and ignore the chId parameter.
* EXTEND_VASPACE
* If true, RM will use the client VA for client VA requests in VASPACE_SHARED_MANAGEMENT mode
* If false, RM will use the internal VA for client VA requests.
* IGNORE_CHANNEL_BUSY
* If true, RM will ignore the channel busy status during set page
* directory operation.
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space
* associated with the client/device pair.
* chId
* ID of the Channel to be updated.
* pasid
* PASID (Process Address Space IDentifier) of the process corresponding to
* the VA space. Ignored unless the VA space has ATS enabled.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_LIMIT
* NV_ERR_GENERIC
*/
#define NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (0x801813U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS {
NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
NvU32 numEntries;
NvU32 flags;
NvHandle hVASpace;
NvU32 chId;
NvU32 subDeviceId; // ID+1, 0 for BC
NvU32 pasid;
} NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS;
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE 1:0
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM (0x00000000U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH (0x00000001U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH (0x00000002U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES 2:2
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS 3:3
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY 4:4
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE 5:5
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE (0x00000001U)
/*!
* NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY
*
* Restore an existing VA space to an RM-managed top-level page directory.
* The VA space must have been created in SHARED_MANAGEMENT mode and
* previously relocated to an externally-managed page directory with
* NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (these two API are symmetric operations).
* For lifecycle details, see NV_VASPACE_ALLOCATION_PARAMETERS documentation in nvos.h.
*
* RM will propagate the update to all channels using the VA space.
*
* NOTE: All channels using this VA space are expected to be idle and unscheduled prior
* to and during this control call - it is responsibility of caller to ensure this.
*
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space
* associated with the client/device pair.
*/
#define NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY (0x801814U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID (0x14U)
typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS {
NvHandle hVASpace;
NvU32 subDeviceId; // ID+1, 0 for BC
} NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS;
/* _ctrl0080dma_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080fb.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE fb control commands and parameters */
/**
* NV0080_CTRL_CMD_FB_GET_CAPS
*
* This command returns the set of framebuffer capabilities for the device
* in the form of an array of unsigned bytes. Framebuffer capabilities
* include supported features and required workarounds for the framebuffer
* engine(s) within the device, each represented by a byte offset into the
* table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_FB_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the framebuffer caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_POINTER
*/
#define NV0080_CTRL_CMD_FB_GET_CAPS (0x801301) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_FB_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0080_CTRL_FB_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0080_CTRL_FB_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0080_CTRL_FB_CAPS_SUPPORT_RENDER_TO_SYSMEM 0:0x01
#define NV0080_CTRL_FB_CAPS_BLOCKLINEAR 0:0x02
#define NV0080_CTRL_FB_CAPS_SUPPORT_SCANOUT_FROM_SYSMEM 0:0x04
#define NV0080_CTRL_FB_CAPS_SUPPORT_CACHED_SYSMEM 0:0x08
#define NV0080_CTRL_FB_CAPS_SUPPORT_C24_COMPRESSION 0:0x10 // Deprecated
#define NV0080_CTRL_FB_CAPS_SUPPORT_SYSMEM_COMPRESSION 0:0x20
#define NV0080_CTRL_FB_CAPS_NISO_CFG0_BUG_534680 0:0x40 // Deprecated
#define NV0080_CTRL_FB_CAPS_ISO_FETCH_ALIGN_BUG_561630 0:0x80 // Deprecated
#define NV0080_CTRL_FB_CAPS_BLOCKLINEAR_GOBS_512 1:0x01
#define NV0080_CTRL_FB_CAPS_L2_TAG_BUG_632241 1:0x02
#define NV0080_CTRL_FB_CAPS_SINGLE_FB_UNIT 1:0x04 // Deprecated
#define NV0080_CTRL_FB_CAPS_CE_RMW_DISABLE_BUG_897745 1:0x08 // Deprecated
#define NV0080_CTRL_FB_CAPS_OS_OWNS_HEAP_NEED_ECC_SCRUB 1:0x10
#define NV0080_CTRL_FB_CAPS_ASYNC_CE_L2_BYPASS_SET 1:0x20 // Deprecated
#define NV0080_CTRL_FB_CAPS_DISABLE_TILED_CACHING_INVALIDATES_WITH_ECC_BUG_1521641 1:0x40
#define NV0080_CTRL_FB_CAPS_DISABLE_MSCG_WITH_VR_BUG_1681803 2:0x01
#define NV0080_CTRL_FB_CAPS_VIDMEM_ALLOCS_ARE_CLEARED 2:0x02
#define NV0080_CTRL_FB_CAPS_DISABLE_PLC_GLOBALLY 2:0x04
#define NV0080_CTRL_FB_CAPS_PLC_BUG_3046774 2:0x08
/* size in bytes of fb caps table */
#define NV0080_CTRL_FB_CAPS_TBL_SIZE 3
/*!
* NV0080_CTRL_CMD_FB_COMPBIT_STORE_GET_INFO
*
* This command returns compbit backing store-related information.
*
* size
* [out] Size of compbit store, in bytes
* address
* [out] Address of compbit store
* addressSpace
* [out] Address space of compbit store (corresponds to type NV_ADDRESS_SPACE in nvrm.h)
* maxCompbitLine
* [out] Maximum compbitline possible, determined based on size
* comptagsPerCacheLine
* [out] Number of compression tags per compression cache line, across all
* L2 slices.
* cacheLineSize
* [out] Size of compression cache line, across all L2 slices. (bytes)
* cacheLineSizePerSlice
* [out] Size of the compression cache line per slice (bytes)
* cacheLineFetchAlignment
* [out] Alignment used while fetching the compression cacheline range in FB.
* If start offset of compcacheline in FB is S and end offset is E, then
* the range to fetch to ensure entire compcacheline data is extracted is:
* (align_down(S) , align_up(E))
* This is needed in GM20X+ because of interleaving of data in Linear FB space.
* Example - In GM204 every other 1K FB chunk of data is offset by 16K.
* backingStoreBase
* [out] Address of start of Backing Store in linear FB Physical Addr space.
* This is the actual offset in FB which HW starts using as the Backing Store and
* in general will be different from the start of the region that driver allocates
* as the backing store. This address is expected to be 2K aligned.
* gobsPerComptagPerSlice
* [out] (Only on Pascal) Number of GOBS(512 bytes of surface PA) that correspond to one 64KB comptgaline, per slice.
* One GOB stores 1 byte of compression bits.
* 0 value means this field is not applicable for the current architecture.
* backingStoreCbcBase
* [out] 2KB aligned base address of CBC (post divide address)
* comptaglineAllocationPolicy
* [out] Policy used to allocate comptagline from CBC for the device
* privRegionStartOffset
* [out] Starting offset for any priv region allocated by clients. only used by MODS
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO (0x801306) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 Size, 8);
NV_DECLARE_ALIGNED(NvU64 Address, 8);
NvU32 AddressSpace;
NvU32 MaxCompbitLine;
NvU32 comptagsPerCacheLine;
NvU32 cacheLineSize;
NvU32 cacheLineSizePerSlice;
NvU32 cacheLineFetchAlignment;
NV_DECLARE_ALIGNED(NvU64 backingStoreBase, 8);
NvU32 gobsPerComptagPerSlice;
NvU32 backingStoreCbcBase;
NvU32 comptaglineAllocationPolicy;
NV_DECLARE_ALIGNED(NvU64 privRegionStartOffset, 8);
} NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS;
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN 0 // ADDR_UNKNOWN
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM 1 // ADDR_SYSMEM
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM 2 // ADDR_FBMEM
// Policy used to allocate comptaglines
/**
* Legacy mode allocates a comptagline for 64kb page. This mode will always allocate
* contiguous comptaglines from a ctag heap.
*/
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY 0
/**
* 1TO1 mode allocates a comptagline for 64kb page. This mode will calculate
* comptagline offset based on physical address. This mode will allocate
* contiguous comptaglines if the surface is contiguous and non-contiguous
* comptaglines for non-contiguous surfaces.
*/
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1 1
/**
* 1TO4_Heap mode allocates a comptagline for 256kb page granularity. This mode
* will allocate comptagline from a heap. This mode will align the surface allocations
* to 256kb before allocating comptaglines. The comptaglines allocated will always be
* contiguous here.
* TODO: For GA10x, this mode will support < 256kb surface allocations, by sharing
* a comptagline with at most 3 different 64Kb allocations. This will result in
* miixed-contiguity config where comptaglines will be allocated contiguously as well
* as non-contiguous when shared with other allocations.
*/
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4 2
/**
* Rawmode will transfer allocation of comptaglines to HW, where HW manages
* comptaglines based on physical offset. The comptaglines are cleared when SW
* issues physical/virtual scrub to the surface before reuse.
*/
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE 3
/**
* NV0080_CTRL_CMD_FB_GET_CAPS_V2
*
* This command returns the same set of framebuffer capabilities for the
* device as @ref NV0080_CTRL_CMD_FB_GET_CAPS. The difference is in the structure
* NV0080_CTRL_FB_GET_CAPS_V2_PARAMS, which contains a statically sized array,
* rather than a caps table pointer and a caps table size in
* NV0080_CTRL_FB_GET_CAPS_PARAMS.
*
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the framebuffer caps bits will be written by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_POINTER
*/
#define NV0080_CTRL_CMD_FB_GET_CAPS_V2 (0x801307) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0080_CTRL_FB_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_FB_CAPS_TBL_SIZE];
} NV0080_CTRL_FB_GET_CAPS_V2_PARAMS;
/* _ctrl0080fb_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080fifo.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE fifo control commands and parameters */
/**
* NV0080_CTRL_FIFO_GET_CAPS
*
* This command returns the set of FIFO engine capabilities for the device
* in the form of an array of unsigned bytes. FIFO capabilities
* include supported features and required workarounds for the FIFO
* engine(s) within the device, each represented by a byte offset into the
* table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_FIFO_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the framebuffer caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_GET_CAPS (0x801701) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_FIFO_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0080_CTRL_FIFO_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0080_CTRL_FIFO_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0080_CTRL_FIFO_CAPS_SUPPORT_SCHED_EVENT 0:0x01
#define NV0080_CTRL_FIFO_CAPS_SUPPORT_PCI_PB 0:0x02
#define NV0080_CTRL_FIFO_CAPS_SUPPORT_VID_PB 0:0x04
#define NV0080_CTRL_FIFO_CAPS_USERD_IN_SYSMEM 0:0x40
/* do not use pipelined PTE BLITs to update PTEs: call the RM */
#define NV0080_CTRL_FIFO_CAPS_NO_PIPELINED_PTE_BLIT 0:0x80
#define NV0080_CTRL_FIFO_CAPS_GPU_MAP_CHANNEL 1:0x01
#define NV0080_CTRL_FIFO_CAPS_BUFFEREDMODE_SCHEDULING 1:0x02 // Deprecated
#define NV0080_CTRL_FIFO_CAPS_WFI_BUG_898467 1:0x08 // Deprecated
#define NV0080_CTRL_FIFO_CAPS_HAS_HOST_LB_OVERFLOW_BUG_1667921 1:0x10
/*
* To indicate Volta subcontext support with multiple VA spaces in a TSG.
* We are not using "subcontext" tag for the property, since we also use
* subcontext to represent pre-VOlta SCG feature, which only allows a single
* VA space in a TSG.
*/
#define NV0080_CTRL_FIFO_CAPS_MULTI_VAS_PER_CHANGRP 1:0x20
#define NV0080_CTRL_FIFO_CAPS_SUPPORT_WDDM_INTERLEAVING 1:0x40
/* size in bytes of fifo caps table */
#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2
/*
* NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS
*
* This command enables the GPU to place various scheduling events in the
* off chip event buffer (with optional interrupt) for those GPUs that support
* it.
*
* record
* This parameter specifies a mask of event types to record.
* interrupt
* This parameter specifies a mask of event types for which to interrupt
* the CPU when the event occurs.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS (0x801703) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x3" */
typedef struct NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS {
NvU32 record;
NvU32 interrupt;
} NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS;
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX 0:0
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX 1:1
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST 2:2
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE 3:3
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT 4:4
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT 5:5
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD 6:6
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX 7:7
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI 8:8
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED 9:9
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC 10:10
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT 11:11
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL 11:0
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_ENABLE (0x00000fff)
/*
* NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS
*
* This command allows the caller to request that a set of channels
* be added to the runlist.
*
* fifoStartChannelListSize
* Size of the fifoStartChannelList. The units are in entries, not
* bytes.
* fifoStartChannelList
* This will be a list of NV0080_CTRL_FIFO_CHANNEL data structures,
* one for each channel that is to be started.
* channelHandle
* deprecated
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
/*
* hChannel
* This is the handle to the channel that is scheduled to be started.
*/
typedef struct NV0080_CTRL_FIFO_CHANNEL {
NvHandle hChannel;
} NV0080_CTRL_FIFO_CHANNEL;
#define NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS (0x801705) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS {
NvU32 fifoStartChannelListSize;
NvHandle channelHandle[8];
NV_DECLARE_ALIGNED(NvP64 fifoStartChannelList, 8);
} NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS;
#define NV0080_CTRL_FIFO_ENGINE_ID_GRAPHICS (0x00000000)
#define NV0080_CTRL_FIFO_ENGINE_ID_MPEG (0x00000001)
#define NV0080_CTRL_FIFO_ENGINE_ID_MOTION_ESTIMATION (0x00000002)
#define NV0080_CTRL_FIFO_ENGINE_ID_VIDEO (0x00000003)
#define NV0080_CTRL_FIFO_ENGINE_ID_BITSTREAM (0x00000004)
#define NV0080_CTRL_FIFO_ENGINE_ID_ENCRYPTION (0x00000005)
#define NV0080_CTRL_FIFO_ENGINE_ID_FGT (0x00000006)
/*
* NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES
*
* This command is used to provide the caller with the alignment and size
* of the context save region for an engine
*
* engineId
* This parameter is an input parameter specifying the engineId for which
* the alignment/size is requested.
* alignment
* This parameter is an output parameter which will be filled in with the
* minimum alignment requirement.
* size
* This parameter is an output parameter which will be filled in with the
* minimum size of the context save region for the engine.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES (0x801707) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID 4:0
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS (0x00000000)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD (0x00000001)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO (0x00000002)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG (0x00000003)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE (0x00000004)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY (0x00000005)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION (0x00000006)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS (0x00000007)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL (0x00000008)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM (0x00000009)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT (0x0000000a)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT (0x0000000b)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL (0x0000000c)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL (0x0000000d)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB (0x0000000e)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV (0x0000000f)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH (0x00000010)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB (0x00000011)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL (0x00000012)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB (0x00000013)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL (0x00000014)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL (0x00000015)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK (0x00000016)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT (0x00000017)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP (0x00000018)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT (0x00000019)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS {
NvU32 engineId;
NvU32 alignment;
NvU32 size;
} NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS;
/*
* NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS <Deprecated since Fermi+>
*
* This command allows the caller to group two sets of channels. A channel
* set includes one or more channels. After grouping, the grouped channel IDs
* are set to next to each other in the runlist. This command can be used
* several times to group more than two channels.
*
* Using a NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE after
* NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS is the general usage. A
* NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS after a
* NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE for a channel handle is not
* allowed.
*
* NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS defines the max channels in a
* group.
*
* hChannel1
* This parameter specifies the handle of the channel that belongs to the
* base set of channels.
* hChannel2
* This parameter specifies the handle of the channel that belongs to the
* additional set of channels.
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_CHANNEL
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS (0x801709) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x9" */
typedef struct NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM {
NvHandle hChannel1;
NvHandle hChannel2;
} NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM;
#define NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS (8)
/*
* NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE <Deprecated since Fermi+>
*
* This command allows the caller to divide the timeslice (DMA_TIMESLICE) of a
* channel between the channels in the group in which the channel resides.
* After applying this command, a timeslice divided channel (group) has a
* short timeslice and repeats more than once in the runlist. The total
* available execution time is not changed.
*
* Using this command after NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS is the
* general usage. A NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS after a
* NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE for a channel handle is not
* allowed.
*
* hChannel
* This parameter specifies the handle of the channel for the channel
* group to which the divided timeslice operation will apply.
* tsDivisor
* This parameter specifies the timeslice divisor value. This value
* should not exceed NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_CHANNEL
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INSUFFICIENT_RESOURCES
*/
#define NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE (0x80170b) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0xB" */
typedef struct NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM {
NvHandle hChannel;
NvU32 tsDivisor;
} NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM;
#define NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR (12)
/*
* NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST <Deprecated since Fermi+>
*
* This command preepmts the engine represented by the specified runlist.
*
* hRunlist
* This parameter specifies the per engine runlist handle. This
* parameter is being retained to maintain backwards compatibility
* with clients that have not transitioned over to using runlists
* on a per subdevice basis.
*
* engineID
* This parameter specifies the engine to be preempted. Engine defines
* can be found in cl2080.h.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST (0x80170c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0xC" */
typedef struct NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS {
NvHandle hRunlist;
NvU32 engineID;
} NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS;
/*
* NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST
*
* Takes a list of hChannels as input and returns the
* corresponding Channel IDs that they corresponding to
* on hw.
*
* numChannels
* Size of input hChannellist
* pChannelHandleList
* List of input channel handles
* pChannelList
* List of Channel ID's corresponding to the
* each entry in the hChannelList.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST (0x80170d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS {
NvU32 numChannels;
NV_DECLARE_ALIGNED(NvP64 pChannelHandleList, 8);
NV_DECLARE_ALIGNED(NvP64 pChannelList, 8);
} NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS;
/*
* NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE
*
* This control call is used to return the number of gp methods(gpsize) and push buffer methods(pbsize)
* allocated to each engine.
*
*engineID
* The engine ID which is an input
*
*gpEntries
* number of gp entries
*
*pbEntries
* number of pb entries (in units of 32B rows)
*
*/
#define NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE (0x80170e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS {
NvU32 engineID;
NvU32 gpEntries;
NvU32 pbEntries;
} NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS;
#define NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL (0xffffffff)
/*
* NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES
*
* This command allows internal properties of the channel
* to be modified even when the channel is active. Most of these properties
* are not meant to be modified during normal runs hence have been
* kept separate from channel alloc params. It is the
* responsibility of the underlying hal routine to make
* sure the channel properties are changed while the channel
* is *NOT* in a transient state.
*
* hChannel
* The handle to the channel.
*
* property
* The channel property to be modified.
* NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_xxx provides the entire list
* of properties.
*
* value
* The new value for the property.
* When property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS
* value = timeslice in microseconds
* desc: Used to change a channel's engine timeslice in microseconds
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS
* value = timeslice in microseconds
* desc: Used to change a channel's pbdma timeslice in microseconds
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE
* value is ignored
* desc: Disables a channel from being timesliced out from an engine.
* Other scheduling events like explicit yield, acquire failures will
* switch out the channel though.
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE
* value is ignored
* desc: Disables a channel from being timesliced out from its pbdma.
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET
* value is ignored
* desc: Override the channel's page directory pointer table with an
* erroneous aperture value. (TODO: make test calls NV_VERIF_FEATURES
* only)(VERIF ONLY)
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT
* value = engineID of engine that will have its context pointer reset.
* engineID defines can be found in cl2080.h
* (e.g., NV2080_ENGINE_TYPE_GRAPHICS)
* desc: Override the channel's engine context pointer with a non existent
* buffer forcing it to fault. (VERIF ONLY)
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT
* value = engineID of engine that will have its context pointer reset.
* engineID defines can be found in cl2080.h
* (e.g., NV2080_ENGINE_TYPE_GRAPHICS)
* desc: Override the channel's engine context pointer with a non existent
* buffer forcing it to fault. However the channel will not be preempted
* before having its channel state modified.(VERIF ONLY)
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP
* value is ignored
* desc: does not change any channel state exercises a full channel preempt/
* unbind/bind op. (VERIF ONLY)
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_CHANNEL
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES (0x80170f) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID (0xFU)
typedef struct NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS {
NvHandle hChannel;
NvU32 property;
NV_DECLARE_ALIGNED(NvU64 value, 8);
} NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS;
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS (0x00000000)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS (0x00000001)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE (0x00000002)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE (0x00000003)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET (0x00000004)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT (0x00000005)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP (0x00000007)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT (0x00000008)
/*
* NV0080_CTRL_CMD_FIFO_STOP_RUNLIST
*
* Stops all processing on the runlist for the given engine. This is only
* valid in per-engine round-robin scheduling mode.
*
* engineID
* This parameter specifies the engine to be stopped. Engine defines
* can be found in cl2080.h.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0080_CTRL_CMD_FIFO_STOP_RUNLIST (0x801711) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID (0x11U)
typedef struct NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS {
NvU32 engineID;
} NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS;
/*
* NV0080_CTRL_CMD_FIFO_START_RUNLIST
*
* Restarts a runlist previously stopped with NV0080_CTRL_CMD_FIFO_STOP_RUNLIST.
* This is only valid for per-engine round-robin mode.
*
* engineID
* This parameter specifies the engine to be started. Engine defines
* can be found in cl2080.h.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0080_CTRL_CMD_FIFO_START_RUNLIST (0x801712) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID (0x12U)
typedef struct NV0080_CTRL_FIFO_START_RUNLIST_PARAMS {
NvU32 engineID;
} NV0080_CTRL_FIFO_START_RUNLIST_PARAMS;
/**
* NV0080_CTRL_FIFO_GET_CAPS_V2
*
* This command returns the same set of FIFO engine capabilities for the device
* as @ref NV0080_CTRL_FIFO_GET_CAPS. The difference is in the structure
* NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS, which contains a statically sized array,
* rather than a caps table pointer and a caps table size in
* NV0080_CTRL_FIFO_GET_CAPS_PARAMS.
*
* capsTbl
* This parameter is an array of the client's caps table buffer.
* The framebuffer caps bits will be written by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 (0x801713) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_FIFO_CAPS_TBL_SIZE];
} NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS;
/**
* NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS
*
* @brief This command idles (deschedules and waits for pending work to complete) channels
* belonging to a particular device.
*
* numChannels
* Number of channels to idle
*
* hChannels
* Array of channel handles to idle
*
* flags
* NVOS30_FLAGS that control aspects of how the channel is idled
*
* timeout
* GPU timeout in microseconds, for each CHID Manager's idling operation
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_TIMEOUT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_LOCK_STATE
*/
#define NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS (0x801714) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS 4096
#define NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x14U)
typedef struct NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS {
NvU32 numChannels;
NvHandle hChannels[NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS];
NvU32 flags;
NvU32 timeout;
} NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS;
/* _ctrl0080fifo_h_ */

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src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080gpu.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
#include "nvlimits.h"
/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */
/*
* NV0080_CTRL_CMD_GPU_GET_CLASSLIST
*
* This command returns supported class information for the specified device.
* If the device is comprised of more than one GPU, the class list represents
* the set of supported classes common to all GPUs within the device.
*
* It has two modes:
*
* If the classList pointer is NULL, then this command returns the number
* of classes supported by the device in the numClasses field. The value
* should then be used by the client to allocate a classList buffer
* large enough to hold one 32bit value per numClasses entry.
*
* If the classList pointer is non-NULL, then this command returns the
* set of supported class numbers in the specified buffer.
*
* numClasses
* If classList is NULL, then this parameter will return the
* number of classes supported by the device. If classList is non-NULL,
* then this parameter indicates the number of entries in classList.
* classList
* This parameter specifies a pointer to the client's buffer into
* which the supported class numbers should be returned.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST (0x800201) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS {
NvU32 numClasses;
NV_DECLARE_ALIGNED(NvP64 classList, 8);
} NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS;
/**
* NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES
*
* This command returns the number of subdevices for the device.
*
* numSubDevices
* This parameter returns the number of subdevices within the device.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES (0x800280) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID (0x80U)
typedef struct NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS {
NvU32 numSubDevices;
} NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER
*
* This command returns the video link order of each subdevice id inside the
* device. This call can only be made after SLI is enabled. This call is
* intended for 3D clients to use to determine the vidlink order of the
* devices. The Display Output Parent will always be the first subdevice
* mask listed in the array. Note that this command should not be used in
* case of bridgeless SLI. The order of the subdevices returned by this
* command will not be correct in case of bridgeless SLI.
*
* ConnectionCount
* Each HW can provide 1 or 2 links between all GPUs in a device. This
* number tells how many links are available between GPUs. This data
* also represents the number of concurrent SLI heads that can run at
* the same time over this one device.
*
* Order
* This array returns the order of subdevices that are used through
* the vidlink for display output.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER (0x800281) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID (0x81U)
typedef struct NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS {
NvU32 ConnectionCount;
NvU32 Order[NV_MAX_SUBDEVICES];
} NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER
*
* This command sets display ownership within the device to the specified
* subdevice instance. The actual transfer of display ownership will take
* place at the next modeset.
*
* subDeviceInstance
* This member specifies the subdevice instance of the new display
* owner. The subdevice instance must be in the legal range
* indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER (0x800282) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x82U)
typedef struct NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS {
NvU32 subDeviceInstance;
} NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER
*
* This command returns the subdevice instance of the current display owner
* within the device.
*
* subDeviceInstance
* This member returns the subdevice instance of the current display
* owner. The subdevice instance will be in the legal range
* indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER (0x800283) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x83U)
typedef struct NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS {
NvU32 subDeviceInstance;
} NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_SET_VIDLINK
*
* This command enables or disables the VIDLINK of all subdevices in the
* current SLI configuration.
*
* enable
* Enables or disables the vidlink
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_GPU_SET_VIDLINK (0x800285) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID (0x85U)
typedef struct NV0080_CTRL_GPU_SET_VIDLINK_PARAMS {
NvU32 enable;
} NV0080_CTRL_GPU_SET_VIDLINK_PARAMS;
#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE (0x00000000)
#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE (0x00000001)
/* commands */
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS 0
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN 1
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP 2
/* status */
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON 0
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN 1
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED 2
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP 3
/*
* NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE
*
* This command is used to enable or disable the persistence of a GPU's
* software state when no clients exist. With persistent software state enabled
* the GPU's software state is not torn down when the last client exits, but is
* retained until either the kernel module unloads or persistent software state
* is disabled.
*
* newState
* This input parameter is used to enable or disable the persistence of the
* software state of all subdevices within the device.
* Possible values are:
* NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED
* NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE (0x800287) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */
/* Possible values of persistentSwState */
#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED (0x00000000)
#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED (0x00000001)
#define NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x87U)
typedef struct NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS {
NvU32 newState;
} NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE
*
* swStatePersistence
* This parameter returns a value indicating if persistent software
* state is currently enabled or not for the specified GPU. See the
* description of NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE.
* Possible values are:
* NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED
* NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE (0x800288) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x88U)
typedef struct NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS {
NvU32 swStatePersistence;
} NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS;
/**
* NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE
*
* This command returns a value indicating virtualization mode in
* which the GPU is running.
*
* virtualizationMode
* This parameter returns the virtualization mode of the device.
* Possible values are:
* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE
* This value indicates that there is no virtualization mode associated with the
* device (i.e. it's a baremetal GPU).
* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS
* This value indicates that the device is associated with the NMOS.
* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX
* This value indicates that the device is associated with VGX(guest GPU).
* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST
* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU
* This value indicates that the device is associated with vGPU(host GPU).
* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA
* This value indicates that the device is associated with vSGA(host GPU).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE (0x800289) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE (0x00000000)
#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS (0x00000001)
#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX (0x00000002)
#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST (0x00000003)
#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST
#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA (0x00000004)
#define NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS {
NvU32 virtualizationMode;
} NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE
*
* This command returns the setting information for sparse texture compute
* mode optimization on the associated GPU. This setting indicates how the
* large page size should be selected by the RM for the GPU.
*
* defaultSetting
* This field specifies what the OS default setting is for the associated
* GPU. See NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list
* of possible values.
* currentSetting
* This field specifies which optimization mode was applied when the
* driver was loaded. See
* NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of
* possible values.
* pendingSetting
* This field specifies which optimization mode will be applied on the
* next driver reload. See
* NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of
* possible values.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8CU)
typedef struct NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS {
NvU32 defaultSetting;
NvU32 currentSetting;
NvU32 pendingSetting;
} NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE
*
* This command sets the pending setting for sparse texture compute mode. This
* setting indicates how the large page size should be selected by the RM for
* the GPU on the next driver reload.
*
* setting
* This field specifies which use case the RM should optimize the large
* page size for on the next driver reload. Possible values for this
* field are:
* NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT
* This value indicates that the RM should use the default setting for
* the GPU's large page size. The default setting is reported by
* NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE.
* NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE
* This value indicates that the RM should select the GPU's large page
* size to optimize for compute use cases.
* NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE
* This value indicates that the RM should select the GPU's large page
* size to optimize for sparse texture use cases.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INSUFFICIENT_PERMISSIONS
*/
#define NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8DU)
typedef struct NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS {
NvU32 setting;
} NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS;
/* Possible sparse texture compute mode setting values */
#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT 0
#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE 1
#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE 2
/*
* NV0080_CTRL_CMD_GPU_GET_VGX_CAPS
*
* This command gets the VGX capability of the GPU depending on the status of
* the VGX hardware fuse.
*
* isVgx
* This field is set to NV_TRUE is VGX fuse is enabled for the GPU otherwise
* it is set to NV_FALSE.
*
* Possible status values returned are:
* NVOS_STATUS_SUCCESS
* NVOS_STATUS_ERROR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_GPU_GET_VGX_CAPS (0x80028e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID (0x8EU)
typedef struct NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS {
NvBool isVgx;
} NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS
*
* This command is used to query GPU SRIOV capabilities
* totalVFs
* Total number of virtual functions supported.
*
* firstVfOffset
* Offset of the first VF.
*
* vfFeatureMask
* Bitmask of features managed by the guest
*
* FirstVFBar0Address
* Address of BAR0 region of first VF.
*
* FirstVFBar1Address
* Address of BAR1 region of first VF.
*
* FirstVFBar2Address
* Address of BAR2 region of first VF.
*
* bar0Size
* Size of BAR0 region on VF.
*
* bar1Size
* Size of BAR1 region on VF.
*
* bar2Size
* Size of BAR2 region on VF.
*
* b64bitBar0
* If the VF BAR0 is 64-bit addressable.
*
* b64bitBar1
* If the VF BAR1 is 64-bit addressable.
*
* b64bitBar2
* If the VF BAR2 is 64-bit addressable.
*
* bSriovEnabled
* Flag for SR-IOV enabled or not.
*
* bSriovHeavyEnabled
* Flag for whether SR-IOV is enabled in standard or heavy mode.
*
* bEmulateVFBar0TlbInvalidationRegister
* Flag for whether VF's TLB Invalidate Register region needs emulation.
*
* bClientRmAllocatedCtxBuffer
* Flag for whether engine ctx buffer is managed by client RM.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS (0x800291) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID (0x91U)
typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
NvU32 totalVFs;
NvU32 firstVfOffset;
NvU32 vfFeatureMask;
NV_DECLARE_ALIGNED(NvU64 FirstVFBar0Address, 8);
NV_DECLARE_ALIGNED(NvU64 FirstVFBar1Address, 8);
NV_DECLARE_ALIGNED(NvU64 FirstVFBar2Address, 8);
NV_DECLARE_ALIGNED(NvU64 bar0Size, 8);
NV_DECLARE_ALIGNED(NvU64 bar1Size, 8);
NV_DECLARE_ALIGNED(NvU64 bar2Size, 8);
NvBool b64bitBar0;
NvBool b64bitBar1;
NvBool b64bitBar2;
NvBool bSriovEnabled;
NvBool bSriovHeavyEnabled;
NvBool bEmulateVFBar0TlbInvalidationRegister;
NvBool bClientRmAllocatedCtxBuffer;
} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS;
// Update this macro if new HW exceeds GPU Classlist MAX_SIZE
#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 116
#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID (0x92U)
typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS {
NvU32 numClasses; // __OUT__
NvU32 classList[NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE]; // __OUT__
} NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE
*
* Find a subdevice handle allocated under this device
*/
#define NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE (0x800293) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID" */
#define NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID (0x93U)
typedef struct NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM {
NvU32 subDeviceInst; // [in]
NvHandle hSubDevice; // [out]
} NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM;
/*
* NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS
*
* This command gets branding information for the device.
*
* brands
* Mask containing branding information. A bit in this
* mask is set if the GPU has particular branding.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO NVBIT(0)
#define NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS NVBIT(1)
#define NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN NVBIT(2)
#define NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS (0x800294) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID (0x94U)
typedef struct NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS {
NvU32 brands;
} NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS;
/*
* These are the per-VF BAR1 sizes that we support in MB.
* They are used with the NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE control call and
* should match the NV_XVE_BAR1_CONFIG_SIZE register defines.
*/
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M 64
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M 128
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M 256
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M 512
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G 1024
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G 2048
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G 4096
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G 8192
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G 16384
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G 32768
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G 65536
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G 131072
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G
#define NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID NV_U32_MAX
/*
* NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE
*
* @brief Resize BAR1 per-VF on the given GPU
* vfBar1SizeMB[in] size of per-VF BAR1 size in MB
* numVfs[out] number of VFs that can be created given the new BAR1 size
*/
#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE (0x800296) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID (0x96U)
typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS {
NvU32 vfBar1SizeMB;
NvU32 numVfs;
} NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS;
/* _ctrl0080gpu_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080gr.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
typedef struct NV0080_CTRL_GR_ROUTE_INFO {
NvU32 flags;
NV_DECLARE_ALIGNED(NvU64 route, 8);
} NV0080_CTRL_GR_ROUTE_INFO;
/* NV01_DEVICE_XX/NV03_DEVICE gr engine control commands and parameters */
/**
* NV0080_CTRL_CMD_GR_GET_CAPS
*
* This command returns the set of graphics capabilities for the device
* in the form of an array of unsigned bytes. Graphics capabilities
* include supported features and required workarounds for the graphics
* engine(s) within the device, each represented by a byte offset into the
* table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_GR_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the graphics caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*/
#define NV0080_CTRL_CMD_GR_GET_CAPS (0x801102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_GR_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0080_CTRL_GR_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0080_CTRL_GR_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/*
* Size in bytes of gr caps table. This value should be one greater
* than the largest byte_index value above.
*/
#define NV0080_CTRL_GR_CAPS_TBL_SIZE 23
/*
* NV0080_CTRL_CMD_GR_INFO
*
* This structure represents a single 32bit graphics engine value. Clients
* request a particular graphics engine value by specifying a unique bus
* information index.
*
* Legal graphics information index values are:
* NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS
* This index is used to request the number of clip IDs supported by
* the device.
* NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894
* This index is used to request the minimum number of attributes that
* need to be enabled to avoid bug 261894. A return value of 0
* indicates that there is no minimum and the bug is not present on this
* system.
*/
typedef struct NV0080_CTRL_GR_INFO {
NvU32 index;
NvU32 data;
} NV0080_CTRL_GR_INFO;
/* valid graphics info index values */
#define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS (0x00000000)
#define NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 (0x00000001)
#define NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK (0x00000002)
#define NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT (0x00000003)
#define NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT (0x00000004)
#define NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE (0x00000005)
#define NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT (0x00000006)
#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT (0x00000007)
#define NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR (0x00000008)
#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT (0x00000009)
#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT (0x0000000A)
#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT (0x0000000B)
#define NV0080_CTRL_GR_INFO_INDEX_SM_VERSION (0x0000000C)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM (0x0000000D)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP (0x0000000E)
#define NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES (0x0000000F)
#define NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES (0x00000010)
#define NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY (0x00000011)
#define NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY (0x00000012)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM (0x00000013)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS (0x00000014)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS (0x00000015)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS (0x00000016)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC (0x00000017)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS (0x00000018)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS (0x00000019)
#define NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED (0x0000001A)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS (0x0000001B)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC (0x0000001C)
#define NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT (0x0000001D)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES (0x0000001E)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS (0x0000001F)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC (0x00000020)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS (0x00000021)
#define NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT (0x00000022)
#define NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT (0x00000023)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS (0x00000024)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS (0x00000025)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES (0x00000026)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC (0x00000027)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP (0x00000028)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC (0x00000029)
#define NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC (0x0000002A)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP (0x0000002B)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT (0x0000002C)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT (0x0000002D)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT (0x0000002E)
/* When adding a new INDEX, please update MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
* reflects that.
*/
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000031)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x32) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
/*
* NV0080_CTRL_CMD_GR_GET_INFO
*
* This command returns graphics engine information for the associate GPU.
* Request to retrieve graphics information use a list of one or more
* NV0080_CTRL_GR_INFO structures.
*
* grInfoListSize
* This field specifies the number of entries on the caller's
* grInfoList.
* grInfoList
* This field specifies a pointer in the caller's address space
* to the buffer into which the bus information is to be returned.
* This buffer must be at least as big as grInfoListSize multiplied
* by the size of the NV0080_CTRL_GR_INFO structure.
*/
#define NV0080_CTRL_CMD_GR_GET_INFO (0x801104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0080_CTRL_GR_GET_INFO_PARAMS {
NvU32 grInfoListSize;
NV_DECLARE_ALIGNED(NvP64 grInfoList, 8);
} NV0080_CTRL_GR_GET_INFO_PARAMS;
/*
* NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE
* This command gets the current partition mode of a TSG context.
*
* NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE
* This command sets the partition mode of a TSG context.
*
* NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
* This structure defines the parameters used for TPC partitioning mode SET/GET commands
*
* hChannelGroup [IN]
* RM Handle to the TSG
*
* mode [IN/OUT]
* Partitioning mode enum value
* For the SET cmd, this is an input parameter
* For the GET cmd, this is an output parameter
*
* bEnableAllTpcs [IN]
* Flag to enable all TPCs by default
*
* grRouteInfo[IN]
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*
*/
#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */
#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */
/* Enum for listing TPC partitioning modes */
typedef enum NV0080_CTRL_GR_TPC_PARTITION_MODE {
NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = 0,
NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = 1,
NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = 2,
} NV0080_CTRL_GR_TPC_PARTITION_MODE;
typedef struct NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS {
NvHandle hChannelGroup; // [in]
NV0080_CTRL_GR_TPC_PARTITION_MODE mode; // [in/out]
NvBool bEnableAllTpcs; // [in/out]
NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); // [in]
} NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS;
/**
* NV0080_CTRL_CMD_GR_GET_CAPS_V2
*
* This command returns the same set of graphics capabilities for the device
* as @ref NV0080_CTRL_CMD_GR_GET_CAPS. The difference is in the structure
* NV0080_CTRL_GR_GET_INFO_V2_PARAMS, which contains a statically sized array,
* rather than a caps table pointer and a caps table size in
* NV0080_CTRL_GR_GET_INFO_PARAMS. Additionally,
* NV0080_CTRL_GR_GET_INFO_V2_PARAMS contains a parameter for specifying routing
* information, used for MIG.
*
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the graphics caps bits will be written by the RM.
* The caps table is an array of unsigned bytes.
*
* grRouteInfo
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*
* bCapsPopulated
* This parameter indicates that the capsTbl has been partially populated by
* previous calls to NV0080_CTRL_CMD_GR_GET_CAPS_V2 on other subdevices.
*/
#define NV0080_CTRL_CMD_GR_GET_CAPS_V2 (0x801109) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV0080_CTRL_GR_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE];
NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
NvBool bCapsPopulated;
} NV0080_CTRL_GR_GET_CAPS_V2_PARAMS;
#define NV0080_CTRL_CMD_GR_GET_INFO_V2 (0x801110) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV0080_CTRL_GR_GET_INFO_V2_PARAMS {
NvU32 grInfoListSize;
NV0080_CTRL_GR_INFO grInfoList[NV0080_CTRL_GR_INFO_MAX_SIZE];
NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
} NV0080_CTRL_GR_GET_INFO_V2_PARAMS;
/* _ctrl0080gr_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080host.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE host control commands and parameters */
/*
* NV0080_CTRL_CMD_HOST_GET_CAPS
*
* This command returns the set of host capabilities for the device
* in the form of an array of unsigned bytes. Host capabilities
* include supported features and required workarounds for the host-related
* engine(s) within the device, each represented by a byte offset into
* the table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_HOST_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the host caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_POINTER
*/
#define NV0080_CTRL_CMD_HOST_GET_CAPS (0x801401) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_HOST_INTERFACE_ID << 8) | NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_HOST_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0080_CTRL_HOST_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0080_CTRL_HOST_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0080_CTRL_HOST_CAPS_SEMA_ACQUIRE_BUG_105665 0:0x01
#define NV0080_CTRL_HOST_CAPS_DUP_CMPLT_BUG_126020 0:0x02
/*
* This bit indicates whether CPU mappings obtained with NvRmMapMemory() are
* coherent with the GPU. When this bit is _not_ set, all mappings are to the
* "raw" memory; i.e., they behave as it the NVOS33_FLAGS_MAPPING_DIRECT flag
* were used on a sysmem mapping.
*/
#define NV0080_CTRL_HOST_CAPS_GPU_COHERENT_MAPPING_SUPPORTED 0:0x04
#define NV0080_CTRL_HOST_CAPS_SYS_SEMA_DEADLOCK_BUG_148216 0:0x08
#define NV0080_CTRL_HOST_CAPS_SLOWSLI 0:0x10
#define NV0080_CTRL_HOST_CAPS_SEMA_READ_ONLY_BUG 0:0x20
#define NV0080_CTRL_HOST_CAPS_LARGE_NONCOH_UPSTR_WRITE_BUG_114871 0:0x40
#define NV0080_CTRL_HOST_CAPS_LARGE_UPSTREAM_WRITE_BUG_115115 0:0x80
#define NV0080_CTRL_HOST_CAPS_SEP_VIDMEM_PB_NOTIFIERS_BUG_83923 1:0x02
#define NV0080_CTRL_HOST_CAPS_P2P_4_WAY 1:0x08 // Deprecated
#define NV0080_CTRL_HOST_CAPS_P2P_8_WAY 1:0x10 // Deprecated
#define NV0080_CTRL_HOST_CAPS_P2P_DEADLOCK_BUG_203825 1:0x20 // Deprecated
#define NV0080_CTRL_HOST_CAPS_VIRTUAL_P2P 1:0x40
#define NV0080_CTRL_HOST_CAPS_BUG_254580 1:0x80
#define NV0080_CTRL_HOST_CAPS_COMPRESSED_BL_P2P_BUG_257072 2:0x02 // Deprecated
#define NV0080_CTRL_HOST_CAPS_CROSS_BLITS_BUG_270260 2:0x04 // Deprecated
/* unused 2:0x08 */
#define NV0080_CTRL_HOST_CAPS_MEM2MEM_BUG_365782 2:0x10
#define NV0080_CTRL_HOST_CAPS_CPU_WRITE_WAR_BUG_420495 2:0x20
#define NV0080_CTRL_HOST_CAPS_EXPLICIT_CACHE_FLUSH_REQD 2:0x40
#define NV0080_CTRL_HOST_CAPS_BAR1_READ_DEADLOCK_BUG_511418 2:0x80 // Deprecated
/* size in bytes of host caps table */
#define NV0080_CTRL_HOST_CAPS_TBL_SIZE 3
#define NV0080_CTRL_CMD_HOST_GET_CAPS_V2 (0x801402) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_HOST_INTERFACE_ID << 8) | NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_HOST_CAPS_TBL_SIZE];
} NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS;
/* _ctrl0080host_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080internal.finn
//
#include "nvlimits.h"
#include "ctrl0080gr.h"
#include "ctrl/ctrl0080/ctrl0080base.h"
#include "ctrl/ctrl0080/ctrl0080perf.h"
/*!
* @ref NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE
*/
#define NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE (0x802002) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID" */
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS {
NV_DECLARE_ALIGNED(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS params, 8);
} NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS;
/*!
* @ref NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE
*/
#define NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE (0x802003) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID" */
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS {
NV_DECLARE_ALIGNED(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS params, 8);
} NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS;
/*!
* @ref NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL
*/
#define NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL (0x802009) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID" */
/*!
* This command disables cuda limit activation at teardown of the client.
*/
#define NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x802004) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4" */
/*!
* @ref NV0080_CTRL_CMD_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL
*/
#define NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL (0x802007) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */
/*!
* @ref NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT
*/
#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS {
NvU8 powerDisconnectedGpuBus[NV_MAX_DEVICES];
NvU8 powerDisconnectedGpuCount;
} NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS;
/* ctrl0080internal_h */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080msenc.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE MSENC control commands and parameters */
/*
* NV0080_CTRL_CMD_MSENC_GET_CAPS
*
* This command returns the set of MSENC capabilities for the device
* in the form of an array of unsigned bytes. MSENC capabilities
* include supported features and required workarounds for the MSENC-related
* engine(s) within the device, each represented by a byte offset into
* the table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_MSENC_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the MSENC caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_MSENC_GET_CAPS (0x801b01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_MSENC_INTERFACE_ID << 8) | NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_MSENC_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0080_CTRL_MSENC_GET_CAPS_PARAMS;
/* size in bytes of MSENC caps table */
#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 4
/* _ctrl0080msenc_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE NVJPG control commands and parameters */
/*
* Size in bytes of NVJPG caps table. This value should be one greater
* than the largest byte_index value above.
*/
#define NV0080_CTRL_NVJPG_CAPS_TBL_SIZE 9
/*
* NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2
*
* This command returns the set of NVJPG capabilities for the device
* in the form of an array of unsigned bytes. NVJPG capabilities
* include supported features of the NVJPG engine(s) within the device,
* each represented by a byte offset into the table and a bit position within
* that byte.
*
* [out] capsTbl
* This caps table array is where the NVJPG caps bits will be transferred
* by the RM. The caps table is an array of unsigned bytes.
* instanceId
* This parameter specifies the instance Id of NVDEC for which
* cap bits are requested.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 (0x801f02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_NVJPG_INTERFACE_ID << 8) | NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE];
NvU32 instanceId;
} NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS;
/* _ctrl0080NVJPG_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080perf.finn
//
#define NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS {
NvBool bActivate;
} NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS;
#define NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS {
NvBool bCudaLimit;
} NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS;
/* _ctrl0080perf_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080rc.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */
/*
* NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK
*
* This command prevents RM from using callbacks when resetting a channel due
* to a page fault.
*
* Possible status return values are:
* NV_OK
*/
#define NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK (0x801d01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x1" */
/*
* NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK
*
* This command permits RM to use callbacks when resetting a channel due
* to a page fault.
*
* Possible status return values are:
* NV_OK
*/
#define NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK (0x801d02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x2" */
/* _ctrl0080rc_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080unix.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE UNIX-specific control commands and parameters */
/*
* NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH
*
* This command notifies RM to save or restore the current console state. It is
* intended to be called just before the display driver starts using the display
* engine, and after it has finished using it.
*
* cmd
* Indicates which operation should be performed.
*
* SAVE_VT_STATE
* Records the current state of the console, to be restored later.
* RESTORE_VT_STATE
* Restores the previously-saved console state.
*
* fbInfo
* Returns information about the system's framebuffer console, if one
* exists. If no console is present, all fields will be zero.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH (0x801e01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID" */
typedef struct NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO {
NvU32 subDeviceInstance;
NvU16 width;
NvU16 height;
NvU16 depth;
NvU16 pitch;
} NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO;
#define NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS {
NvU32 cmd; /* in */
NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO fbInfo; /* out */
} NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS;
/* Called when the display driver needs RM to save the console data,
* which will be used in RM based console restore */
#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE (0x00000001)
/* Called when the display driver needs RM to restore the console */
#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE (0x00000002)
/* Called when the display driver has restored the console -- RM doesn't
* need to do anything further, but needs to be informed to avoid turning the
* GPU off and thus destroying the console state. */
#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED (0x00000003)
#define NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO (0x801e02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS {
NvU32 subDeviceInstance; /* out */
NvU16 width; /* out */
NvU16 height; /* out */
NvU16 depth; /* out */
NvU16 pitch; /* out */
} NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS;
/* _ctrl0080unix_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0090.finn
//
// NV0080_CTRL_GR_TPC_PARTITION_MODE
#include "ctrl/ctrl0080/ctrl0080gr.h"
/*!
* This file defines control call interfaces for the KernelGraphicsContext
* objects Each channel running within a TSG contains a HW context represented
* by the above object(s). GR permits multiple channels to share a single
* context, and these APIs operate upon that context and may be issued from any
* TSG, channel, or context handle.
*/
/*
* NV0090_CTRL_CMD_NULL
*
* @brief This command does nothing.
*
* @return NV_OK
*/
#define NV0090_CTRL_CMD_NULL (0x900100) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x0" */
/*!
* NV0090_CTRL_CMD_SET_TPC_PARTITION_MODE
* NV0090_CTRL_CMD_GET_TPC_PARTITION_MODE
*
* @brief sets or gets the TPC partition mode for this context
*
* @param[in/out] mode Partitioning mode enum value
* @param[in/out] bEnableAllTpcs Flag to enable all TPCs by default
*
* @return NV_OK on success
* NV_ERR_OBJECT_NOT_FOUND if issued on non-GR ctx
*/
typedef struct NV0090_CTRL_TPC_PARTITION_MODE_PARAMS {
NV0080_CTRL_GR_TPC_PARTITION_MODE mode;
NvBool bEnableAllTpcs;
} NV0090_CTRL_TPC_PARTITION_MODE_PARAMS;
#define NV0090_CTRL_CMD_SET_TPC_PARTITION_MODE (0x900101) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x1" */
#define NV0090_CTRL_CMD_INTERNAL_SET_TPC_PARTITION_MODE (0x900102) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x2" */
#define NV0090_CTRL_CMD_GET_TPC_PARTITION_MODE (0x900103) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x3" */
#define NV0090_CTRL_CMD_INTERNAL_GET_TPC_PARTITION_MODE (0x900104) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x4" */
/**
* NV0090_CTRL_GET_MMU_DEBUG_MODE
*
* @brief retrieve the current MMU debug mode for the grctx according to the HW
*
* @param[out] bMode current MMU debug mode
*/
typedef struct NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS {
NvBool bMode;
} NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS;
#define NV0090_CTRL_CMD_GET_MMU_DEBUG_MODE (0x900105) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x5" */
#define NV0090_CTRL_CMD_INTERNAL_GET_MMU_DEBUG_MODE (0x900106) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x6" */
/**
* NV0090_CTRL_PROGRAM_VIDEMEM_PROMOTE
*
* @brief This control call is used to set the promotion policies to vidmem through
* per-TSG config
*
* If the request is for less bytes than the current PROMOTE setting, then
* the request is promoted. For example if the request size is for 32B and
* 64B promotion is turned on for that unit, then the request to FB will be
* for all the bytes to the 64B aligned address.
*
* @param[in] l1
* An input parameter which represents VIDMEM_L1_PROMOTE[17:16].
* @param[in] t1
* An input parameter which represents VIDMEM_T1_PROMOTE[19:18].
*
* @return NV_OK on success, or
* NV_ERR_INVALID_ARGUMENT or
* NV_ERR_INVALID_STATE
*/
typedef enum NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE {
NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = 0,
NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = 1,
NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = 2,
} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE;
typedef struct NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD {
NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE size;
} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD;
#define NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS {
NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD l1;
NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD t1;
} NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS;
#define NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE (0x900107) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x7" */
#define NV0090_CTRL_CMD_INTERNAL_PROGRAM_VIDMEM_PROMOTE (0x900108) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x8" */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl00f8.finn
//
#include "ctrl/ctrlxxxx.h"
#define NV00F8_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00f8, NV00F8_CTRL_##cat, idx)
/* NV00F8 command categories (6bits) */
#define NV00F8_CTRL_RESERVED (0x00U)
#define NV00F8_CTRL_FABRIC (0x01U)
/*
* NV00F8_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV00F8_CTRL_CMD_NULL (0xf80000U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NV00F8_CTRL_CMD_GET_INFO
*
* Queries memory allocation attributes.
*
* size [OUT]
* Size of the allocation.
*
* pageSize [OUT]
* Page size of the allocation.
*
* allocFlags [OUT]
* Flags passed during the allocation.
*/
#define NV00F8_CTRL_CMD_GET_INFO (0xf80101U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV00F8_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV00F8_CTRL_GET_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 pageSize;
NvU32 allocFlags;
} NV00F8_CTRL_GET_INFO_PARAMS;
/*
* NV00F8_CTRL_CMD_DESCRIBE
*
* Queries the physical attributes of the fabric memory allocation.
*
* offset [IN]
* Offset into memory allocation to query physical addresses for.
*
* totalPfns [OUT]
* Number of PFNs in memory allocation.
*
* pfnArray [OUT]
* Array of PFNs in memory allocation (2MB page size shifted).
*
* numPfns [OUT]
* Number of valid entries in pfnArray.
*
* Note: This ctrl call is only available for kerenl mode client in vGPU platforms.
*/
#define NV00F8_CTRL_CMD_DESCRIBE (0xf80102) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID" */
#define NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE 512
#define NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV00F8_CTRL_DESCRIBE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NV_DECLARE_ALIGNED(NvU64 totalPfns, 8);
NvU32 pfnArray[NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE];
NvU32 numPfns;
} NV00F8_CTRL_DESCRIBE_PARAMS;
/* _ctrl00f8_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080.finn
//
#include "ctrl/ctrlxxxx.h"
#include "ctrl2080/ctrl2080gpu.h"
#include "ctrl2080/ctrl2080fuse.h"
#include "ctrl2080/ctrl2080event.h"
#include "ctrl2080/ctrl2080tmr.h"
#include "ctrl2080/ctrl2080bios.h"
#include "ctrl2080/ctrl2080mc.h"
#include "ctrl2080/ctrl2080fifo.h"
#include "ctrl2080/ctrl2080fb.h"
#include "ctrl2080/ctrl2080gr.h"
#include "ctrl2080/ctrl2080bus.h"
#include "ctrl2080/ctrl2080thermal.h"
#include "ctrl2080/ctrl2080fan.h"
#include "ctrl2080/ctrl2080i2c.h"
#include "ctrl2080/ctrl2080internal.h"
#include "ctrl2080/ctrl2080spi.h"
#include "ctrl2080/ctrl2080gpio.h"
#include "ctrl2080/ctrl2080clk.h"
#include "ctrl2080/ctrl2080perf.h"
#include "ctrl2080/ctrl2080perf_cf.h"
#include "ctrl2080/ctrl2080rc.h"
#include "ctrl2080/ctrl2080dma.h"
#include "ctrl2080/ctrl2080dmabuf.h"
#include "ctrl2080/ctrl2080nvd.h"
#include "ctrl2080/ctrl2080boardobj.h"
#include "ctrl2080/ctrl2080pmgr.h"
#include "ctrl2080/ctrl2080power.h"
#include "ctrl2080/ctrl2080lpwr.h"
#include "ctrl2080/ctrl2080acr.h"
#include "ctrl2080/ctrl2080ce.h"
#include "ctrl2080/ctrl2080nvlink.h"
#include "ctrl2080/ctrl2080flcn.h"
#include "ctrl2080/ctrl2080volt.h"
#include "ctrl2080/ctrl2080ecc.h"
#include "ctrl2080/ctrl2080cipher.h"
#include "ctrl2080/ctrl2080fla.h"
#include "ctrl2080/ctrl2080gsp.h"
#include "ctrl2080/ctrl2080grmgr.h"
#include "ctrl2080/ctrl2080ucodefuzzer.h"
#include "ctrl2080/ctrl2080hshub.h"
/* include appropriate os-specific command header */
#include "ctrl2080/ctrl2080unix.h"

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/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080acr.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV20_SUBDEVICE_XX control commands and parameters */
#define NV2080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x2080, NV2080_CTRL_##cat, idx)
/* Subdevice command categories (6bits) */
#define NV2080_CTRL_RESERVED (0x00)
#define NV2080_CTRL_GPU (0x01)
#define NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED (0x81) /* finn: Evaluated from "(NV2080_CTRL_GPU | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_FUSE (0x02)
#define NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED (0x82) /* finn: Evaluated from "(NV2080_CTRL_FUSE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_EVENT (0x03)
#define NV2080_CTRL_TIMER (0x04)
#define NV2080_CTRL_THERMAL (0x05)
#define NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED (0xc5) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED (0x85) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_I2C (0x06)
#define NV2080_CTRL_EXTI2C (0x07)
#define NV2080_CTRL_BIOS (0x08)
#define NV2080_CTRL_CIPHER (0x09)
#define NV2080_CTRL_INTERNAL (0x0A)
#define NV2080_CTRL_CLK_LEGACY_PRIVILEGED (0xd0) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED (0x90) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_CLK (0x10)
#define NV2080_CTRL_FIFO (0x11)
#define NV2080_CTRL_GR (0x12)
#define NV2080_CTRL_FB (0x13)
#define NV2080_CTRL_MC (0x17)
#define NV2080_CTRL_BUS (0x18)
#define NV2080_CTRL_PERF_LEGACY_PRIVILEGED (0xe0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED (0xa0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_PERF (0x20)
#define NV2080_CTRL_NVIF (0x21)
#define NV2080_CTRL_RC (0x22)
#define NV2080_CTRL_GPIO (0x23)
#define NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED (0xa3) /* finn: Evaluated from "(NV2080_CTRL_GPIO | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_NVD (0x24)
#define NV2080_CTRL_DMA (0x25)
#define NV2080_CTRL_PMGR (0x26)
#define NV2080_CTRL_PMGR_LEGACY_PRIVILEGED (0xe6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED (0xa6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_POWER (0x27)
#define NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED (0xa7) /* finn: Evaluated from "(NV2080_CTRL_POWER | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_LPWR (0x28)
#define NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED (0xa8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_LPWR_LEGACY_PRIVILEGED (0xe8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV2080_CTRL_ACR (0x29)
#define NV2080_CTRL_CE (0x2A)
#define NV2080_CTRL_SPI (0x2B)
#define NV2080_CTRL_NVLINK (0x30)
#define NV2080_CTRL_FLCN (0x31)
#define NV2080_CTRL_VOLT (0x32)
#define NV2080_CTRL_VOLT_LEGACY_PRIVILEGED (0xf2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED (0xb2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_FAS (0x33)
#define NV2080_CTRL_ECC (0x34)
#define NV2080_CTRL_ECC_NON_PRIVILEGED (0xb4) /* finn: Evaluated from "(NV2080_CTRL_ECC | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_FLA (0x35)
#define NV2080_CTRL_GSP (0x36)
#define NV2080_CTRL_NNE (0x37)
#define NV2080_CTRL_GRMGR (0x38)
#define NV2080_CTRL_UCODE_FUZZER (0x39)
#define NV2080_CTRL_DMABUF (0x3A)
// per-OS categories start at highest category and work backwards
#define NV2080_CTRL_OS_WINDOWS (0x3F)
#define NV2080_CTRL_OS_MACOS (0x3E)
#define NV2080_CTRL_OS_UNIX (0x3D)
/*
* NV2080_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_NULL (0x20800000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */
/* _ctrl2080base_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080bios.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX bios-related control commands and parameters */
typedef struct NV2080_CTRL_BIOS_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_BIOS_INFO;
/* Maximum number of bios infos that can be queried at once */
#define NV2080_CTRL_BIOS_INFO_MAX_SIZE (0x0000000F)
#define NV2080_CTRL_BIOS_INFO_INDEX_REVISION (0x00000000)
#define NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION (0x00000001)
/*
* NV2080_CTRL_CMD_BIOS_GET_INFO
*
* This command returns bios information for the associated GPU.
* Requests to retrieve bios information use a list of one or more
* NV2080_CTRL_BIOS_INFO structures.
*
* biosInfoListSize
* This field specifies the number of entries on the caller's
* biosInfoList.
* biosInfoList
* This field specifies a pointer in the caller's address space
* to the buffer into which the bios information is to be returned.
* This buffer must be at least as big as biosInfoListSize multiplied
* by the size of the NV2080_CTRL_BIOS_INFO structure.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV2080_CTRL_CMD_BIOS_GET_INFO (0x20800802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | 0x2" */
typedef struct NV2080_CTRL_BIOS_GET_INFO_PARAMS {
NvU32 biosInfoListSize;
NV_DECLARE_ALIGNED(NvP64 biosInfoList, 8);
} NV2080_CTRL_BIOS_GET_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_BIOS_GET_INFO_V2
*
* This command returns bios information for the associated GPU.
* Requests to retrieve bios information use a list of one or more
* NV2080_CTRL_BIOS_INFO structures.
*
* biosInfoListSize
* This field specifies the number of entries on the caller's
* biosInfoList.
* biosInfoList
* Bios information to be returned.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV2080_CTRL_CMD_BIOS_GET_INFO_V2 (0x20800810) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS {
NvU32 biosInfoListSize;
NV2080_CTRL_BIOS_INFO biosInfoList[NV2080_CTRL_BIOS_INFO_MAX_SIZE];
} NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS;
/*
* NV2080_CTRL_CMD_BIOS_GET_SKU_INFO
*
* This command returns information about the current board SKU.
* NV_ERR_INVALID_OWNER will be returned if the call
* isn't made with the OS as the administrator.
*
* chipSKU
* This field returns the sku for the current chip.
* chipSKUMod
* This field returns the SKU modifier.
* project
* This field returns the Project (Board) number.
* projectSKU
* This field returns the Project (Board) SKU number.
* CDP
* This field returns the Collaborative Design Project Number.
* projectSKUMod
* This field returns the Project (Board) SKU Modifier.
* businessCycle
* This field returns the business cycle the board is associated with.
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_OWNER
*/
#define NV2080_CTRL_CMD_BIOS_GET_SKU_INFO (0x20800808) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID" */
/* maximum length of parameter strings */
#define NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS {
NvU32 BoardID;
char chipSKU[4];
char chipSKUMod[2];
char project[5];
char projectSKU[5];
char CDP[6];
char projectSKUMod[2];
NvU32 businessCycle;
} NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_BIOS_GET_POST_TIME
* This command is used to get the GPU POST time (in milliseconds).
* If the associated GPU is the master GPU this value will be recorded
* by the VBIOS and retrieved from the KDA buffer. If the associated
* GPU is a secondaryGPU then this value will reflect the devinit
* processing time.
*
* vbiosPostTime
* This parameter returns the vbios post time in msec.
*
* Possible return status values are
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME (0x20800809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS {
NV_DECLARE_ALIGNED(NvU64 vbiosPostTime, 8);
} NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS;
/*
* NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT
*
* This function is used to give out the UEFI version, UEFI image presence and
* Graphics Firmware Mode i.e. whether system is running in UEFI or not.
*
* version
* This parameter returns the UEFI version.
*
* flags
* This parameter indicates UEFI image presence and Graphics Firmware mode.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE
* This field returns UEFI presence value. Legal values for this
* field include:
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO
* This value indicates that UEFI image is not present.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES
* This value indicates that UEFI image is present.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER
* This value indicates that there is a dummy UEFI placeholder,
* which can later be updated with a valid UEFI image.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN
* This value indicates that UEFI image is hidden.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING
* This field indicates the UEFI running value. Legal values for
* this parameter include:
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE
* This value indicates that UEFI is not running.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE
* This value indicates that UEFI is running.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_READY
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT (0x2080080b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS {
NvU32 version;
NvU32 flags;
} NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS;
/* Legal values for flags parameter */
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE 1:0
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO (0x00000000)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES (0x00000001)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER (0x00000002)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN (0x00000003)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING 2:2
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE (0x00000000)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE (0x00000001)
/* _ctrl2080bios_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h"

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn
//
#include "nvtypes.h"

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/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080ce.finn
//
/* NV20_SUBDEVICE_XX ce control commands and parameters */
#include "ctrl2080common.h"
/*
* NV2080_CTRL_CMD_CE_GET_CAPS
*
* This command returns the set of CE capabilities for the device
* in the form of an array of unsigned bytes.
*
* ceEngineType
* This parameter specifies the copy engine type
* capsTblSize
* This parameter specifies the size in bytes of the caps table per CE.
* This value should be set to NV2080_CTRL_CE_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the CE caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_CE_GET_CAPS (0x20802a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID" */
/*
* Size in bytes of CE caps table. This value should be one greater
* than the largest byte_index value below.
*/
#define NV2080_CTRL_CE_CAPS_TBL_SIZE 2
#define NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_CE_GET_CAPS_PARAMS {
NvU32 ceEngineType;
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV2080_CTRL_CE_GET_CAPS_PARAMS;
#define NV2080_CTRL_CMD_CE_GET_CAPS_V2 (0x20802a03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
NvU32 ceEngineType;
NvU8 capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE];
} NV2080_CTRL_CE_GET_CAPS_V2_PARAMS;
/* extract cap bit setting from tbl */
#define NV2080_CTRL_CE_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV2080_CTRL_CE_CAPS_CE_GRCE 0:0x01
#define NV2080_CTRL_CE_CAPS_CE_SHARED 0:0x02
#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ 0:0x04
#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE 0:0x08
#define NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P 0:0x10
#define NV2080_CTRL_CE_CAPS_CE_SYSMEM 0:0x20
#define NV2080_CTRL_CE_CAPS_CE_P2P 0:0x40
#define NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED 0:0x80
#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 1:0x01
#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 1:0x02
/*
* NV2080_CTRL_CE_CAPS_CE_GRCE
* Set if the CE is synchronous with GR
*
* NV2080_CTRL_CE_CAPS_CE_SHARED
* Set if the CE shares physical CEs with any other CE
*
* NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ
* Set if the CE can give enhanced performance for SYSMEM reads over other CEs
*
* NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE
* Set if the CE can give enhanced performance for SYSMEM writes over other CEs
*
* NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P
* Set if the CE can be used for P2P transactions using NVLINK
* Once a CE is exposed for P2P over NVLINK, it will remain available for the life of RM
* PCE2LCE mapping may change based on the number of GPUs registered in RM however
*
* NV2080_CTRL_CE_CAPS_CE_SYSMEM
* Set if the CE can be used for SYSMEM transactions
*
* NV2080_CTRL_CE_CAPS_CE_P2P
* Set if the CE can be used for P2P transactions
*
* NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED
* Set if the CE supports BL copy size greater than 64K
*
* NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL
* Set if the CE supports non-pipelined Block linear
*
* NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL
* Set if the CE supports pipelined Block Linear
*/
/*
* NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK
*
* This command returns the mapping of PCE's for the given LCE
*
* ceEngineType
* This parameter specifies the copy engine type
* pceMask
* This parameter specifies a mask of PCEs that correspond
* to the LCE specified in ceEngineType
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS {
NvU32 ceEngineType;
NvU32 pceMask;
} NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS;
/*
* NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG
*
* This command sets the PCE2LCE configuration
*
* pceLceConfig[NV2080_CTRL_MAX_PCES]
* This parameter specifies the PCE-LCE mapping requested
* grceLceConfig[NV2080_CTRL_MAX_GRCES]
* This parameter specifies which LCE is the GRCE sharing with
* 0xF -> Does not share with any LCE
* 0-MAX_LCE -> Shares with the given LCE
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MAX_PCES 18
#define NV2080_CTRL_MAX_GRCES 2
#define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS {
NvU32 ceEngineType;
NvU32 pceLceMap[NV2080_CTRL_MAX_PCES];
NvU32 grceSharedLceMap[NV2080_CTRL_MAX_GRCES];
} NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS;
/*
* NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS
*
* This command updates the PCE-LCE mappings
*
* pPceLceMap [IN]
* This parameter tracks the array of PCE-LCE mappings.
*
* pGrceConfig [IN]
* This parameter tracks the array of GRCE configs.
* 0xF -> GRCE does not share with any LCE
* 0-MAX_LCE -> GRCE shares with the given LCE
*
* exposeCeMask [IN]
* This parameter specifies the mask of LCEs to export to the
* clients after the update.
*
* bUpdateNvlinkPceLce [IN]
* Whether PCE-LCE mappings need to be updated for nvlink topology.
* If this is NV_FALSE, RM would ignore the above values. However,
* PCE-LCE mappings will still be updated if there were any regkey
* overrides.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS {
NvU32 pceLceMap[NV2080_CTRL_MAX_PCES];
NvU32 grceConfig[NV2080_CTRL_MAX_GRCES];
NvU32 exposeCeMask;
NvBool bUpdateNvlinkPceLce;
} NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS;
#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS {
NvU32 stubbedCeMask;
} NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS;
/*
* NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS
*
* Query _CE_GRCE, _CE_SHARED, _CE_SUPPORTS_PIPELINED_BL, _CE_SUPPORTS_NONPIPELINED_BL bits of CE
* capabilities.
*
*/
#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0x7" */
#define NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS {
NvU32 size;
} NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS;
#define NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE (0x20802a08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASKS
*
* Get HSHUB and FBHUB PCE masks.
*
* [out] hshubPceMasks
* PCE mask for each HSHUB
* [out] fbhubPceMask
* FBHUB PCE mask
*/
#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK (0x20802a09) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_MAX_HSHUBS 5
#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS {
NvU32 hshubPceMasks[NV2080_CTRL_CE_MAX_HSHUBS];
NvU32 fbhubPceMask;
} NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS;
/*
* NV2080_CTRL_CMD_CE_GET_ALL_CAPS
*
* Query caps of all CEs.
*
* [out] capsTbl
* Array of CE caps in the order of CEs. The caps bits interpretation is the same as in
* NV2080_CTRL_CMD_CE_GET_CAPS.
* [out] present
* Bit mask indicating which CEs are usable by the client and have their caps indicated in capsTbl.
* If a CE is not marked present, its caps bits should be ignored.
* If client is subscribed to a MIG instance, only the CEs present in the instance are tagged as such.
*/
#define NV2080_CTRL_CMD_CE_GET_ALL_CAPS (0x20802a0a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID (0xaU)
typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS {
NvU8 capsTbl[NV2080_CTRL_MAX_PCES][NV2080_CTRL_CE_CAPS_TBL_SIZE];
NvU32 present;
} NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS;
#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0xb" */
/* _ctrl2080ce_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080cipher.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080clk.finn
//
/* _ctrl2080clk_h_ */
#include "nvfixedtypes.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobj.h"
#include "ctrl/ctrl2080/ctrl2080gpumon.h"
#include "ctrl/ctrl2080/ctrl2080clkavfs.h"
#include "ctrl/ctrl2080/ctrl2080volt.h"
#include "ctrl/ctrl2080/ctrl2080pmumon.h"

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/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobj.h"
#include "ctrl/ctrl2080/ctrl2080volt.h"

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/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2004 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080common.finn
//
#define NV2080_CTRL_CMD_MAX_HEADS 2

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080dma.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX dma control commands and parameters */
#include "ctrl2080common.h"
/*
* NV2080_CTRL_CMD_DMA_INVALIDATE_TLB
*
* This command invalidates the GPU TLB. This is intended to be used
* by RM clients that manage their own TLB consistency when updating
* page tables on their own, or with DEFER_TLB_INVALIDATION options
* to other RM APIs.
*
* hVASpace
* This parameter specifies the VASpace object whose MMU TLB entries needs to be invalidated.
* Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace.
* Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC.
*
* This call can be used with the NV50_DEFERRED_API_CLASS (class 0x5080).
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_TIMEOUT_RETRY
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_DMA_INVALIDATE_TLB (0x20802502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS {
NvHandle hClient; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
NvHandle hDevice; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
NvU32 engine; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
NvHandle hVASpace;
} NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS;
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS 0:0
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO 1:1
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY 2:2
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE 3:3
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB 4:4
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV 5:5
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG 6:6
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD 7:7
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION 8:8
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON 9:9
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS 10:10
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR 11:11
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE (0x00000001)
/*
* NV2080_CTRL_DMA_INFO
*
* This structure represents a single 32bit dma engine value. Clients
* request a particular DMA engine value by specifying a unique dma
* information index.
*
* Legal dma information index values are:
* NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
* This index can be used to request the system address size in bits.
*/
typedef struct NV2080_CTRL_DMA_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_DMA_INFO;
/* valid dma info index values */
#define NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE (0x000000000)
/* set INDEX_MAX to greatest possible index value */
#define NV2080_CTRL_DMA_INFO_INDEX_MAX NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
/*
* NV2080_CTRL_CMD_DMA_GET_INFO
*
* This command returns dma engine information for the associated GPU.
* Requests to retrieve dma information use an array of one or more
* NV2080_CTRL_DMA_INFO structures.
*
* dmaInfoTblSize
* This field specifies the number of valid entries in the dmaInfoList
* array. This value cannot exceed NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES.
* dmaInfoTbl
* This parameter contains the client's dma info table into
* which the dma info values will be transferred by the RM.
* The dma info table is an array of NV2080_CTRL_DMA_INFO structures.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_DMA_GET_INFO (0x20802503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID" */
/* maximum number of NV2080_CTRL_DMA_INFO entries per request */
#define NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES (256)
#define NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_DMA_GET_INFO_PARAMS {
NvU32 dmaInfoTblSize;
/*
* C form:
* NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES];
*/
NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES];
} NV2080_CTRL_DMA_GET_INFO_PARAMS;
typedef struct NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO {
/*!
* 64KB aligned address of source 64KB tile for comptag reswizzle.
*/
NvU32 srcAddr;
/*!
* 64KB aligned address of destination 64KB tile for comptag reswizzle.
*/
NvU32 dstAddr;
/*!
* Comptag index assigned to the 64K sized tile relative to
* the compcacheline. Absolute comptag index would be:
* startComptagIndex + relComptagIndex.
*/
NvU16 relComptagIndex;
} NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO;
// _ctrl2080dma_h_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn
//
/*
* NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD
*
* Exports RM vidmem handles to a dma-buf fd.
*
* The objects in the 'handles' array are exported to the fd as range:
* [index, index + numObjects).
*
* A dma-buf fd is created the first time this control call is called.
* The fd is an input parameter for subsequent calls to attach additional handles
* over NV2080_CTRL_DMABUF_MAX_HANDLES.
*
* fd
* A dma-buf file descriptor. If -1, a new FD will be created.
*
* totalObjects
* The total number of objects that the client wishes to export to the FD.
* This parameter will be honored only when the FD is getting created.
*
* numObjects
* The number of handles the user wishes to export in this call.
*
* index
* The index into the export fd at which to start exporting the handles in
* 'handles'. This index cannot overlap a previously used index.
*
* totalSize
* The total size of memory being exported in bytes, needed to create the dma-buf.
* This size includes the memory that will be exported in future export calls
* for this dma-buf.
*
* handles
* An array of {handle, offset, size} that describes the dma-buf.
* The offsets and sizes must be OS page-size aligned.
*
* Limitations:
* 1. This call only supports vidmem objects for now.
* 2. All memory handles should belong to the same GPU or the same GPU MIG instance.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_NO_MEMORY
* NV_ERR_OPERATING_SYSTEM
* NV_ERR_IN_USE
* NV_ERR_INVALID_OBJECT
* NV_ERR_INVALID_OBJECT_PARENT
*/
#define NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD (0x20803a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID << 8) | NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_DMABUF_MAX_HANDLES 128
typedef struct NV2080_CTRL_DMABUF_MEM_HANDLE_INFO {
NvHandle hMemory;
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
} NV2080_CTRL_DMABUF_MEM_HANDLE_INFO;
#define NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS {
NvS32 fd;
NvU32 totalObjects;
NvU32 numObjects;
NvU32 index;
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_DMABUF_MEM_HANDLE_INFO handles[NV2080_CTRL_DMABUF_MAX_HANDLES], 8);
} NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS;
// _ctrl2080dmabuf_h_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080ecc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#define NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS (0x20803400) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS
*
* sramLastClearedTimestamp [out]
* dramLastClearedTimestamp [out]
* unix-epoch based timestamp. These fields indicate when the error counters
* were last cleared by the user.
*
* sramErrorCounts [out]
* dramErrorCounts [out]
* Aggregate error counts for SRAM and DRAM
*/
#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U)
typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS {
NvU32 sramLastClearedTimestamp;
NvU32 dramLastClearedTimestamp;
NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotalCounts, 8);
NV_DECLARE_ALIGNED(NvU64 sramUncorrectedTotalCounts, 8);
NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotalCounts, 8);
NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotalCounts, 8);
} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS;
/* _ctrl2080ecc_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080event.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "nv_vgpu_types.h"
/* NV20_SUBDEVICE_XX event-related control commands and parameters */
/*
* NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* This command sets event notification state for the associated subdevice.
* This command requires that an instance of NV01_EVENT has been previously
* bound to the associated subdevice object.
*
* event
* This parameter specifies the type of event to which the specified
* action is to be applied. This parameter must specify a valid
* NV2080_NOTIFIERS value (see cl2080.h for more details) and should
* not exceed one less NV2080_NOTIFIERS_MAXCOUNT.
* action
* This parameter specifies the desired event notification action.
* Valid notification actions include:
* NV2080_CTRL_SET_EVENT_NOTIFICATION_DISABLE
* This action disables event notification for the specified
* event for the associated subdevice object.
* NV2080_CTRL_SET_EVENT_NOTIFICATION_SINGLE
* This action enables single-shot event notification for the
* specified event for the associated subdevice object.
* NV2080_CTRL_SET_EVENT_NOTIFICATION_REPEAT
* This action enables repeated event notification for the specified
* event for the associated system controller object.
* bNotifyState
* This boolean is used to indicate the current state of the notifier
* at the time of event registration. This is optional and its semantics
* needs to be agreed upon by the notifier and client using the notifier
* info32
* This is used to send 32-bit initial state info with the notifier at
* time of event registration
* info16
* This is used to send 16-bit initial state info with the notifier at
* time of event registration
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION (0x20800301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
NvU32 event;
NvU32 action;
NvBool bNotifyState;
NvU32 info32;
NvU16 info16;
} NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
/* XUSB/PPC D-state defines */
#define NV2080_EVENT_DSTATE_XUSB_D0 (0x00000000)
#define NV2080_EVENT_DSTATE_XUSB_D3 (0x00000003)
#define NV2080_EVENT_DSTATE_XUSB_INVALID (0xFFFFFFFF)
#define NV2080_EVENT_DSTATE_PPC_D0 (0x00000000)
#define NV2080_EVENT_DSTATE_PPC_D3 (0x00000003)
#define NV2080_EVENT_DSTATE_PPC_INVALID (0xFFFFFFFF)
// HDACODEC Decice DState, D3_COLD is only for verbose mapping, it cannot be logged
typedef enum NV2080_EVENT_HDACODEC_DSTATE {
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0 = 0,
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1 = 1,
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2 = 2,
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT = 3,
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD = 4,
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX = 5,
} NV2080_EVENT_HDACODEC_DSTATE;
/*
* NV2080_CTRL_CMD_EVENT_SET_TRIGGER
*
* This command triggers a software event for the associated subdevice.
* This command accepts no parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER (0x20800302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | 0x2" */
/*
* NV2080_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY
*
* hMemory
* This parameter specifies the handle of the memory object
* that identifies the memory address translation for this
* subdevice instance's notification(s). The beginning of the
* translation points to an array of notification data structures.
* The size of the translation must be at least large enough to hold the
* maximum number of notification data structures identified by
* the NV2080_MAX_NOTIFIERS value.
* Legal argument values must be instances of the following classes:
* NV01_NULL
* NV04_MEMORY
* When hMemory specifies the NV01_NULL_OBJECT value then any existing
* memory translation connection is cleared. There must not be any
* pending notifications when this command is issued.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x20800303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS {
NvHandle hMemory;
} NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS;
#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0
#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1
#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2
/*
* NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY
*
* hSemMemory
* This parameter specifies the handle of the memory object that
* identifies the semaphore memory associated with this subdevice
* event notification. Once this is set RM will generate an event
* only when there is a change in the semaphore value. It is
* expected that the semaphore memory value will be updated by
* the GPU indicating that there is an event pending. This
* command is used by VGX plugin to determine which virtual
* machine has generated a particular event.
*
* semOffset
* This parameter indicates the memory offset of the semaphore.
*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY (0x20800304) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS {
NvHandle hSemMemory;
NvU32 semOffset;
} NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI
*
* hSemMemory
* This parameter specifies the handle of the memory object that
* identifies the semaphore memory associated with this subdevice
* event notification. Once this is set RM will generate an event
* only when there is a change in the semaphore value. It is
* expected that the semaphore memory value will be updated by
* the GPU indicating that there is an event pending. This
* command is used by VGX plugin to determine which virtual
* machine has generated a particular event.
*
* guestMSIAddr
* This parameter indicates the guest allocated MSI address.
*
* guestMSIData
* This parameter indicates the MSI data set by the guest OS.
*
* vmIdType
* This parameter specifies the type of guest virtual machine identifier
*
* guestVmId
* This parameter specifies the guest virtual machine identifier
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI (0x20800305) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS {
NV_DECLARE_ALIGNED(NvU64 guestMSIAddr, 8);
NvU32 guestMSIData;
NvHandle hSemMemory;
NvBool isReset;
VM_ID_TYPE vmIdType;
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
} NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION
*
* hSemMemory
* This parameter specifies the handle of the memory object that
* identifies the semaphore memory associated with this subdevice
* event notification. Once this is set RM will generate an event
* only when there is a change in the semaphore value. It is
* expected that the semaphore memory value will be updated by
* the GPU indicating that there is an event pending. This
* command is used by VGX plugin to determine which virtual
* machine has generated a particular event.
*
* isSemaMemValidationEnabled
* This parameter used to enable/disable change in sema value check
* while generating an event.
*
* Possible status values returned are:
* NVOS_STATUS_SUCCESS
* NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE
* NVOS_STATUS_ERROR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION (0x20800306) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS {
NvHandle hSemMemory;
NvBool isSemaMemValidationEnabled;
} NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL
*
* hSemMemory
* This parameter specifies the handle of the memory object that
* identifies the semaphore memory associated with this subdevice
* event notification. Once this is set RM will generate an event
* only when there is a change in the semaphore value. It is
* expected that the semaphore memory value will be updated by
* the GPU indicating that there is an event pending. This
* command is used by VGX plugin to determine which virtual
* machine has generated a particular event.
*
* vmIdType
* This parameter specifies the type of guest virtual machine identifier
*
* guestVmId
* This parameter specifies the guest virtual machine identifier
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL (0x20800307) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS {
NvHandle hSemMemory;
VM_ID_TYPE vmIdType;
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
} NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO
*
* This command triggers a FIFO event for the associated subdevice.
*
* hEvent
* Handle of the event that should be notified. If zero, all
* non-stall interrupt events for this subdevice will be notified.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO (0x20800308) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS {
NvHandle hEvent;
} NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF_FOR_UID
*
* This command is used to create a video bind-point to an event buffer that
* is filtered by UID.
*
* hEventBuffer[IN]
* The event buffer to bind to
*
* recordSize[IN]
* The size of the FECS record in bytes
*
* levelOfDetail[IN]
* One of NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_:
* FULL: Report all CtxSw events
* SIMPLE: Report engine start and engine end events only
* CUSTOM: Report events in the eventFilter field
* NOTE: RM may override the level-of-detail depending on the caller
*
* eventFilter[IN]
* Bitmask of events to report if levelOfDetail is CUSTOM
*
* bAllUsers[IN]
* Only report video data for the current user if false, for all users if true
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF (0x20800309) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD {
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL = 0,
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE = 1,
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM = 2,
} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD;
#define NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS {
NvHandle hEventBuffer;
NvU32 recordSize;
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD levelOfDetail;
NvU32 eventFilter;
NvBool bAllUsers;
} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS;
/* _ctrl2080event_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fan.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fifo.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*
* NV2080_CTRL_CMD_SET_GPFIFO
*
* This command set the GPFIFO offset and number of entries for a channel
* after it has been allocated. The channel must be idle and not pending,
* otherwise ERROR_IN_USE will be returned.
*
* hChannel
* The handle to the channel.
* base
* The base of the GPFIFO in the channel ctxdma.
* numEntries
* The number of entries in the GPFIFO.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_CHANNEL
* NV_ERR_STATE_IN_USE
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV2080_CTRL_CMD_SET_GPFIFO (0x20801102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_CMD_SET_GPFIFO_PARAMS {
NvHandle hChannel;
NV_DECLARE_ALIGNED(NvU64 base, 8);
NvU32 numEntries;
} NV2080_CTRL_CMD_SET_GPFIFO_PARAMS;
/*
* NV2080_CTRL_FIFO_BIND_CHANNEL
*
* This structure is used to describe a channel that is to have
* it's bindable engines bound to those of other channels.
*
* hClient
* This structure member contains the handle of the client object
* that owns the channel object specified by hChannel.
*
* hChannel
* This structure member contains the channel handle of the channel
* object.
*/
typedef struct NV2080_CTRL_FIFO_BIND_CHANNEL {
NvHandle hClient;
NvHandle hChannel;
} NV2080_CTRL_FIFO_BIND_CHANNEL;
/*
* NV2080_CTRL_CMD_FIFO_BIND_ENGINES
*
* This control call is now deprecated.
* This command can be used to bind different video engines on G8X from separate
* channels together for operations such as idling. The set of bindable engines
* includes the NV2080_ENGINE_TYPE_BSP, NV2080_ENGINE_TYPE_VP and
* NV2080_ENGINE_TYPE_PPP engines.
*
* bindChannelCount
* This parameter specifies the number of channels to bind together. This
* parameter cannot exceed NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS.
*
* bindChannels
* The parameter specifies the array of channels to bind together. The first
* bindChannelCount entries are used in the bind channel operation.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_CHANNEL
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS (16)
#define NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS {
NvU32 bindChannelCount;
NV2080_CTRL_FIFO_BIND_CHANNEL bindChannels[NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS];
} NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS;
#define NV2080_CTRL_CMD_FIFO_BIND_ENGINES (0x20801103) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES
*
* This command is used for a client to setup specialized custom operational
* properties that may be specific to an environment, or properties that
* should be set generally but are not for reasons of backward compatibility
* with previous chip generations
*
* flags
* This field specifies the operational properties to be applied
*
* Possible return status values returned are
* NV_OK
* NV_ERR_INVALID_CHANNEL
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES (0x20801104) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS {
NvU32 flags;
} NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS;
#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE 0:0
#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE (0x00000000)
#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE (0x00000001)
/*
* NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT
*
* This command returns the maximum number of physical channels available for
* allocation on the current GPU. This may be less than or equal to the total
* number of channels supported by the current hardware.
*
* physChannelCount
* This output parameter contains the maximum physical channel count.
*
* physChannelCountInUse
* This output parameter contains the number of physical channels in use
*
* Possible return status values returned are
* NV_OK
*
*/
#define NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT (0x20801108) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS {
NvU32 physChannelCount;
NvU32 physChannelCountInUse;
} NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS;
/*
* NV2080_CTRL_FIFO_INFO
*
* This structure represents a single 32bit fifo engine value. Clients
* request a particular FIFO engine value by specifying a unique fifo
* information index.
*
* Legal fifo information index values are:
* NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL
* This index can be used to request the amount of instance space
* in kilobytes reserved by the fifo engine.
* NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS
* This index can be used to query the maximum number of channel groups
* that can be allocated on the GPU.
* NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP
* This index can be used to query the maximum number of channels that can
* be allocated in a single channel group.
* NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP
* This index can be used to query the maximum number of subcontext that can
* be allocated in a single channel group.
* NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET
* This index can be used to query the starting offset of the RM
* pre-allocated USERD range in BAR1. This index query is honored only
* on Legacy-vGPU host RM.
* NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE
* This index can be used to query the default timeslice value
* (microseconds) used for a channel or channel group.
* NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE
* This index can be used to query the number of channel groups that are
* already allocated on the GPU.
* NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED
* This index can be used to check if per runlist channel ram is supported, and
* to query the supported number of channels per runlist.
* NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE
* This index can be used to get max channel groups supported per engine/runlist.
* NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE
* This index can be used too get channel groups currently in use per engine/runlist.
*
*/
typedef struct NV2080_CTRL_FIFO_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_FIFO_INFO;
/* valid fifo info index values */
#define NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL (0x000000000)
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS (0x000000001)
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP (0x000000002)
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP (0x000000003)
#define NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET (0x000000004)
#define NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE (0x000000005)
#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE (0x000000006)
#define NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED (0x000000007)
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE (0x000000008)
#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE (0x000000009)
/* set INDEX_MAX to greatest possible index value */
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE
#define NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT (12)
/*
* NV2080_CTRL_CMD_FIFO_GET_INFO
*
* This command returns fifo engine information for the associated GPU.
* Requests to retrieve fifo information use an array of one or more
* NV2080_CTRL_FIFO_INFO structures.
*
* fifoInfoTblSize
* This field specifies the number of valid entries in the fifoInfoList
* array. This value cannot exceed NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES.
* fifoInfoTbl
* This parameter contains the client's fifo info table into
* which the fifo info values will be transferred by the RM.
* The fifo info table is an array of NV2080_CTRL_FIFO_INFO structures.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_GET_INFO (0x20801109) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID" */
/* maximum number of NV2080_CTRL_FIFO_INFO entries per request */
#define NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES (256)
#define NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_FIFO_GET_INFO_PARAMS {
NvU32 fifoInfoTblSize;
/*
* C form:
* NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES];
*/
NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES];
NvU32 engineType;
} NV2080_CTRL_FIFO_GET_INFO_PARAMS;
/*
* NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL
*
* This command removes the specified channel from the associated GPU's runlist
* and then initiates RC recovery. If the channel is active it will first be preempted.
* hChannel
* The handle to the channel to be preempted.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_CHANNEL
*/
#define NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL (0x2080110a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS {
NvHandle hChannel;
} NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS
*
* This command will disable or enable scheduling of channels described in the
* list provided. Whether or not the channels are also preempted off the GPU
* can be controlled by bOnlyDisableScheduling. By default channels are preempted
* off the GPU.
*
* bDisable
* This value determines whether to disable or
* enable the set of channels.
* numChannels
* The number of channels to be stopped.
* bOnlyDisableScheduling
* When false and bDisable=NV_TRUE,the call will ensure none of the listed
* channels are running in hardware and will not run until a call with
* bDisable=NV_FALSE is made. When true and bDisable=NV_TRUE, the control
* call will ensure that none of the listed channels can be scheduled on the
* GPU until a call with bDisable=NV_FALSE is made, but will not remove any
* of the listed channels from hardware if they are currently running. When
* bDisable=NV_FALSE this field is ignored.
* bRewindGpPut
* If a channel is being disabled and bRewindGpPut=NV_TRUE, the channel's RAMFC
* will be updated so that GP_PUT is reset to the value of GP_GET.
* hClientList
* An array of NvU32 listing the client handles
* hChannelList
* An array of NvU32 listing the channel handles
* to be stopped.
* pRunlistPreemptEvent
* KEVENT handle for Async HW runlist preemption (unused on preMaxwell)
* When NULL, will revert to synchronous preemption with spinloop
*
* Possible status values returned are:
* NV_OK
* NVOS_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS (0x2080110b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES (64)
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS {
NvBool bDisable;
NvU32 numChannels;
NvBool bOnlyDisableScheduling;
NvBool bRewindGpPut;
NV_DECLARE_ALIGNED(NvP64 pRunlistPreemptEvent, 8);
// C form: NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]
NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES];
// C form: NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]
NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES];
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS;
#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE (0x00000000)
#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE (0x00000001)
#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE (0x00000000)
#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE (0x00000001)
/*
* NV2080_CTRL_FIFO_MEM_INFO
*
* This structure describes the details of a block of memory. It consists
* of the following fields
*
* aperture
* One of the NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_* values
* base
* Physical base address of the memory
* size
* Size in bytes of the memory
*/
typedef struct NV2080_CTRL_FIFO_MEM_INFO {
NvU32 aperture;
NV_DECLARE_ALIGNED(NvU64 base, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
} NV2080_CTRL_FIFO_MEM_INFO;
/*
* NV2080_CTRL_FIFO_CHANNEL_MEM_INFO
*
* This structure describes the details of the instance memory, ramfc
* and method buffers a channel. It consists of the following fields
*
* inst
* Structure describing the details of instance memory
* ramfc
* Structure describing the details of ramfc
* methodBuf
* Array of structures describing the details of method buffers
* methodBufCount
* Number of method buffers(one per runqueue)
*/
// max runqueues
#define NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT 0x2
typedef struct NV2080_CTRL_FIFO_CHANNEL_MEM_INFO {
NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO inst, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO ramfc, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO methodBuf[NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT], 8);
NvU32 methodBufCount;
} NV2080_CTRL_FIFO_CHANNEL_MEM_INFO;
/*
* NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM
*
* This command returns the memory aperture, physical base address and the
* size of each of the instance memory, cache1 and ramfc of a channel.
*
* hChannel
* The handle to the channel for which the memory information is desired.
* chMemInfo
* A NV2080_CTRL_FIFO_CHANNEL_MEM_INFO structure
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_CHANNEL
*/
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO (0x2080110c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS {
NvHandle hChannel;
NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_CHANNEL_MEM_INFO chMemInfo, 8);
} NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS;
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID 0x00000000
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM 0x00000001
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH 0x00000002
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH 0x00000003
/*
* NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION
*
* This command determines the location (vidmem/sysmem)
* and attribute (cached/uncached/write combined) of memory where USERD is located.
*
* aperture
* One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_* values.
*
* attribute
* One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_* values.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_POINTER
*/
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION (0x2080110d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS {
NvU32 aperture;
NvU32 attribute;
} NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS;
// support for CPU coherent vidmem (VIDMEM_NVILINK_COH) is not yet available in RM
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM 0x00000000
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM 0x00000001
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED 0x00000000
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED 0X00000001
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED 0X00000002
/*
* NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE
*
* This command retrieves entries from the SW encoded GPU device info table
* from Host RM.
*
* Parameters:
*
* baseIndex [in]
* The starting index to read from the devinfo table. Must be a multiple of
* MAX_ENTRIES.
*
* entries [out]
* A buffer to store up to MAX_ENTRIES entries of the devinfo table.
*
* numEntries [out]
* Number of populated entries in the provided buffer.
*
* bMore [out]
* A boolean flag indicating whether more valid entries are available to be
* read. A value of NV_TRUE indicates that a further call to this control
* with baseIndex incremented by MAX_ENTRIES will yield further valid data.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE (0x20801112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES 256
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES 32
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES 16
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA 2
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN 16
/*
* NV2080_CTRL_FIFO_DEVICE_ENTRY
*
* This structure contains the engine, engine name and
* push buffers information of FIFO device entry. It consists of the following fields
*
* engineData
* Type of the engine
* pbdmaIds
* List of pbdma ids associated with engine
* pbdmaFaultIds
* List of pbdma fault ids associated with engine
* numPbdmas
* Number of pbdmas
* engineName
* Name of the engine
*/
typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY {
NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES];
NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
NvU32 numPbdmas;
char engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN];
} NV2080_CTRL_FIFO_DEVICE_ENTRY;
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x12U)
typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS {
NvU32 baseIndex;
NvU32 numEntries;
NvBool bMore;
// C form: NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];
NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];
} NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT
*
* This command clears the ENGINE or PBDMA FAULTED bit and reschedules the faulted channel
* by ringing channel's doorbell
*
* Parameters:
*
* engineType [in]
* The NV2080_ENGINE_TYPE of the engine to which the faulted
* channel is bound. This may be a logical id for guest RM in
* case of SMC.
*
* vChid [in]
* Virtual channel ID on which the fault occurred
*
* faultType [in]
* Whether fault was triggered by engine (_ENGINE_FAULTED) or PBDMA (_PBDMA_FAULTED)
* The value specified must be one of the NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_* values
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT (0x20801113) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE 0x00000001
#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA 0x00000002
#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS {
NvU32 engineType;
NvU32 vChid;
NvU32 faultType;
} NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY
*
* Allows clients to set the global scheduling policy for all runlists
* associated to the given subdevice.
*
* Currently, this is only supported for HW runlists.
*
* Since this is a global setting, only privileged clients will be allowed to
* set it. Regular clients will get NV_ERR_INSUFFICIENT_PERMISSIONS error.
*
* Once a certain scheduling policy is set, that policy cannot be changed to a
* different one unless all clients which set it have either restored the policy
* (using the corresponding restore flag) or died. Clients trying to set a
* policy while a different one is locked by another client will get a
* NV_ERR_INVALID_STATE error.
*
* The same client can set a scheduling policy and later change to another one
* only when no other clients have set the same policy. Such sequence will be
* equivalent to restoring the policy in between.
*
* For instance, the following sequence:
*
* 1. Set policy A
* 2. Set policy B
*
* is equivalent to:
*
* 1. Set policy A
* 2. Restore policy
* 3. Set policy B
*
* Parameters:
*
* flags
* This field specifies the operational properties to be applied:
*
* - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE
* Try to set the provided 'schedPolicy' scheduling policy. If the
* operation succeeds, other clients will be prevented from setting a
* different scheduling policy until all clients using it have either
* restored it or died.
*
* - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE
* Let the scheduler know the client no longer requires the current
* scheduling policy. This may or may not actually change the
* scheduling policy, depending on how many other clients are also
* using the current policy.
*
* The 'schedPolicy' parameter is ignored when this flag is set.
*
* schedPolicy
* One of:
*
* - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT
* Set the default scheduling policy and prevent other clients from
* changing it.
*
* - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED
* This scheduling policy will make channels to be scheduled according
* to their interleave level. See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL
* description for more details.
* - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM
* This scheduling policy will make channels to be scheduled according
* to their interleave level per WDDM policy.
* See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL description for more details.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY (0x20801115) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID" */
/* schedPolicy values */
#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT 0x0
#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED 0x1
#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM 0x2
/* SET_SCHED_POLICY flags */
#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE 0:0
#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE (0x00000000)
#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE (0x00000001)
#define NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID (0x15U)
typedef struct NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS {
NvU32 flags;
NvU32 schedPolicy;
} NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO
*
* This command updates the channel info params for an existing channel
*
* Can be a deferred Api. The control call can be used for migrating a
*
* channel to a new userd and gpfifo
*
* Parameters:
* [in] hClient - Client handle
* [in] hChannel - Channel handle
* [in] hUserdMemory - UserD handle
* [in] gpFifoEntries - Number of Gpfifo Entries
* [in] gpFifoOffset - Gpfifo Virtual Offset
* [in] userdOffset - UserD offset
*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO (0x20801116) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID (0x16U)
typedef struct NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS {
NvHandle hClient;
NvHandle hChannel;
NvHandle hUserdMemory;
NvU32 gpFifoEntries;
NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8);
NV_DECLARE_ALIGNED(NvU64 userdOffset, 8);
} NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS
*
* This command will disable or enable scheduling of all usermode channels.
*
* bDisable
* This value determines whether to disable or enable the usermode channels.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS (0x20801117) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID (0x17U)
typedef struct NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS {
NvBool bDisable;
} NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB
*
* When a VF subcontext is marked as a zombie, host RM points its PDB to a dummy
* page allocated by guest RM in GPA space. This command provides the parameters
* of the guest RMs memory descriptor to be able to create a corresponding
* memory descriptor on the host RM. Host RM uses this to program the PDB of a
* zombie subcontext.
*
* Parameters:
* Input parameters to describe the memory descriptor
* [in] base
* [in] size
* [in] addressSpace
* [in] cacheAttrib
*/
#define NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB (0x20801118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID (0x18U)
typedef struct NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS {
NV_DECLARE_ALIGNED(NvU64 base, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 addressSpace;
NvU32 cacheAttrib;
} NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS;
/* _ctrl2080fifo_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fla.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX FLA control commands and parameters */
#include "ctrl2080common.h"
/*
* NV2080_CTRL_CMD_FLA_RANGE
*
* This command is used to initialize/destroy FLA VAS for a GPU.This is intended
* to be used by RM clients that manages the FLA VASpace range. The mode of the
* command is decided based on the parameter passed by the client.
*
* base
* This parameter specifies the base of the FLA VAS that needs to be allocated
* for this GPU
*
* size
* This parameter specifies the size of the FLA VAS that needs to be allocated
* for this GPU
*
* mode
* This parameter specifies the functionality of the command.
* MODE_INITIALIZE
* Setting this mode, will initialize the FLA VASpace for the gpu with
* base and size passed as arguments. FLA VASpace will be owned by RM.
* if the client calls the command more than once before destroying
* the FLA VAS, then this command will verify the range exported before and
* return success if it matches. If FLA is not supported for the platform,
* will return NV_ERR_NOT_SUPPORTED.
* MODE_DESTROY (deprecated)
* This command is NOP.
* MODE_HOST_MANAGED_VAS_INITIALIZE
* This mode will initialize the FLA VASpace for the gpu with hVASpace
* handle in addition to base and size arguments. FLA VASpace will be initiated
* and owned by guest RM. Used only in virtualization platforms by internal clients.
* MODE_HOST_MANAGED_VAS_DESTROY
* This mode will destroy the FLA VAS associated with the device. It will destruct
* only the resources associated with host RM side. Used only in virtualization platforms
* by internal clients.
*
* hVASpace
* This paramete specifies the FLA VAspace that needs to be associated with
* device. This parameter takes effect only for internal client in virtualization
* platforms. For any other platform and external clients, this parameter has no effect.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_IN_USE
* NV_ERR_INVALID_OWNER
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FLA_RANGE (0x20803501) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_FLA_RANGE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 base, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 mode;
NvHandle hVASpace;
} NV2080_CTRL_FLA_RANGE_PARAMS;
#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE 0x00000000
#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE NVBIT(0)
#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY NVBIT(1)
#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE NVBIT(2)
#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY NVBIT(3)
/*
* NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK
*
* This command is used to (un)bind FLA Instance Memory Block(IMB) with MMU.
* This control call is created for vGPU platform, when a FLA VAS is created/destroyed
* by Guest RM. Guest RM doesn't have privilege to (un)bind the IMB with MMU, hence
* need to be RPC-ed to Host RM to (un)bind
* The mode of the command is decided based on the actionParam passed by the client.
*
* imbPhysAddr
* This parameter specifies the FLA Instance Memory Block PA to be programmed
* to MMU. IMB address should be 4k aligned. This parameter is needed only
* for ACTION_BIND.
*
* addrSpace
* This parameter specifies the address space of FLA Instance Memory Block. This
* parmater is needed only for ACTION_BIND.
* Available options are:
* NV2080_CTRL_FLA_ADDRSPACE_SYSMEM
* Clients need to use this address space if the IMB is located in sysmem
* NV2080_CTRL_FLA_ADDRSPACE_FBMEM
* Clients need to use this address space if the IMB is located in FB
*
* actionParam
* This parameter specifies the functionality of the command.
* NV2080_CTRL_FLA_ACTION_BIND
* Setting this type, will call busBindFla helper HAL
* NV2080_CTRL_FLA_ACTION_UNBIND
* Setting this type, will call busUnbindFla helper HAL
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INSUFFICIENT_PERMISSIONS
*/
typedef enum NV2080_CTRL_FLA_ADDRSPACE {
NV2080_CTRL_FLA_ADDRSPACE_SYSMEM = 0,
NV2080_CTRL_FLA_ADDRSPACE_FBMEM = 1,
} NV2080_CTRL_FLA_ADDRSPACE;
typedef enum NV2080_CTRL_FLA_ACTION {
NV2080_CTRL_FLA_ACTION_BIND = 0,
NV2080_CTRL_FLA_ACTION_UNBIND = 1,
} NV2080_CTRL_FLA_ACTION;
#define NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK (0x20803502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS {
NV_DECLARE_ALIGNED(NvU64 imbPhysAddr, 8);
NV2080_CTRL_FLA_ADDRSPACE addrSpace;
NV2080_CTRL_FLA_ACTION flaAction;
} NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS;
/*
* NV2080_CTRL_CMD_FLA_GET_RANGE
*
* This command is used to query the FLA base and size from plugin to return as static info to Guest RM.
*
* base
* This parameter returns the base address of FLA range registered to the subdevice.
* size
* This parameter returns the size of FLA range registered to the subdevice.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FLA_GET_RANGE (0x20803503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_FLA_GET_RANGE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 base, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
} NV2080_CTRL_FLA_GET_RANGE_PARAMS;
/*
* NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS
*
* This command returns the total size and the free size of the fabric vaspace.
* Note: This returns the information for the FABRIC_VASPACE_A class.
*
* totalSize[OUT]
* - Total fabric vaspace.
*
* freeSize [OUT]
* - Available fabric vaspace.
*
* Possible status values returned are:
*
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS (0x20803504) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
NV_DECLARE_ALIGNED(NvU64 freeSize, 8);
} NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS;
// _ctrl2080fla_h_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080flcn.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
//
// XAPICHK/XAPI_TEST breaks on including "nvmisc.h". Workaround: don't include
// the header in that case and just redefine the macros we need.
//
#include "nvmisc.h"
/*
* Obsolete Falcon ID type. Use NV2080_ENGINE_TYPE_ instead
*/
#define FALCON_ID_PMU (NV2080_ENGINE_TYPE_PMU)
#define FALCON_ID_DPU (NV2080_ENGINE_TYPE_DPU)
#define FALCON_ID_SEC2 (NV2080_ENGINE_TYPE_SEC2)
#define FALCON_ID_FBFLCN (NV2080_ENGINE_TYPE_FBFLCN)
/*
* NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE
*
* This command returns total heap size and free heap size of a falcon engine
*
* flcnID
* The falcon ID
*
* heapSize
* Total heap size in byte
*
* heapFree
* Total free heap size in byte
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_OBJECT
*/
#define NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE (0x20803101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS {
NvU32 flcnID;
NvU32 heapSize;
NvU32 heapFree;
} NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS;
/*!
* @defgroup NVOS_INST_EVT Instrumentation event types.
* @{
*/
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RECALIBRATE 0x00U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_TICK 0x01U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_YIELD 0x02U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_INT0 0x03U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_BLOCK 0x04U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_UNBLOCK 0x05U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HANDLER_BEGIN 0x06U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HANDLER_END 0x07U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_QUEUE_SEND 0x08U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_QUEUE_RECV 0x09U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RPC_BEGIN 0x0AU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RPC_END 0x0BU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_SKIPPED 0x0CU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EXEC_PROFILE_BEGIN 0x0DU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EXEC_PROFILE_END 0x0EU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_LOAD_PROFILE_BEGIN 0x0FU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_LOAD_PROFILE_END 0x10U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_CODE_BEGIN 0x11U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_CODE_END 0x12U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_DATA_BEGIN 0x13U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_DATA_END 0x14U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_PROFILE_BEGIN 0x15U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_PROFILE_END 0x16U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_ODP_PROFILE_BEGIN 0x17U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_ODP_PROFILE_END 0x18U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_BEGIN 0x19U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_END 0x1AU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_2_BEGIN 0x1BU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_2_END 0x1CU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_3_BEGIN 0x1DU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_3_END 0x1EU
/*!@}*/
#define NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID 0xFFU
/*!
* Interrupts and exceptions both use the same event type. Set the first bit
* for exceptions to differentiate between the two.
*/
#define NV2080_CTRL_FLCN_NVOS_INST_IRQ_ID(_irqId) (_irqId)
#define NV2080_CTRL_FLCN_NVOS_INST_EXCI_ID(_exciId) (_exciId | (1 << 7))
/*!
* @defgroup NV_INSTRUMENTATION_EVENT_DATA Instrumentation event struct entry.
*
* This is a binary-packed representation of event type and additional data,
* including timing data and tracking IDs.
*
* @{
*/
/*!
* Below DRF needs constants assigned to start and end so it can be represented in FINN properly
* This is because FINN v1 will not have the ability to represent DRF's and bit fields yet
*/
#define NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_EXTENT (31)
#define NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_BASE (27)
#define NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE \
(NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_EXTENT) : \
(NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_BASE)
#define NV_INSTRUMENTATION_EVENT_DATA_TASK_ID 26:19
#define NV_INSTRUMENTATION_EVENT_DATA_EXTRA 26:19
#define NV_INSTRUMENTATION_EVENT_DATA_TIME_DELTA 18:0
#define NV_INSTRUMENTATION_EVENT_DATA_TIME_ABS 26:0
/*!@}*/
/*!
* The maximum number of event types, calculated from the number of bits in the
* event structure.
*/
#define NV2080_CTRL_FLCN_NVOS_INST_NUM_EVT_TYPES (0x20U) /* finn: Evaluated from "(1 << (NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_EXTENT - NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_BASE + 1))" */
/*!
* The number of bytes required in the event mask to contain all event types.
*/
#define NV2080_CTRL_FLCN_NVOS_INST_MASK_SIZE_BYTES (0x4U) /* finn: Evaluated from "(NV2080_CTRL_FLCN_NVOS_INST_NUM_EVT_TYPES / 8)" */
/*!
* Instrumentation event bitfield structure. Exact structure depends on the
* first five bits, which represent event type.
*
* For most event types, the structure is:
* - 5 bits of event type
* - 8 bits of ID
* - 19 bits of delta time (time since last event). If we've missed some
* events, it's the amount of time since the last event that was not
* skipped. If this time would overflow, a recalibration event is inserted
* instead (see below).
*
* The main exception is the recalibration event, which has no ID/delta time
* fields and instead has a 27-bit absolute timestamp. This event is used
* when the gap between two events is greater than the maximum 20-bit integer.
*
* All timestamps are represented in increments of 32ns
* (the finest possible timer resolution).
*/
typedef struct NVOS_INSTRUMENTATION_EVENT {
/*!
* Field containing the event type and data.
*
* Bitmask of @ref NV_INSTRUMENTATION_EVENT_DATA.
*/
NvU32 data;
} NVOS_INSTRUMENTATION_EVENT;
typedef struct NVOS_INSTRUMENTATION_EVENT *PNVOS_INSTRUMENTATION_EVENT;
/*
* NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_MAP/UNMAP
*
* Params for both RmCtrls are the same (out for _MAP, in for _UNMAP)
*/
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_MAP (0x20803112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x12" */
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_UNMAP (0x20803113) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x13" */
typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
//! The beginning of the instrumentation buffer, mapped to user memory.
NV_DECLARE_ALIGNED(NvP64 begin, 8);
// Priv pointer for memory mapping.
NV_DECLARE_ALIGNED(NvP64 pPriv, 8);
// The size of the user-mapped instrumentation buffer.
NV_DECLARE_ALIGNED(NvU64 size, 8);
} NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET_INFO
*
* Get static information about FLCN instrumentation.
*/
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET_INFO (0x20803114) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS_MESSAGE_ID (0x14U)
typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
//! Whether or not instrumentation is enabled
NvBool bEnabled;
/*!
* Whether we use PTIMER (resolution 32ns) or the 30us timer tick (NV_TRUE
* is PTIMER).
*/
NvBool bIsTimerPrecise;
} NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET/SET_CONTROL
*
* Get/set the event bitmask.
*/
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET_CONTROL (0x20803115) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x15" */
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_SET_CONTROL (0x20803116) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x16" */
typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
/*!
* The bitmask of which event types to log. An event type corresponding to
* a bit with a zero will be ignored at the log site, which prevents it
* from filling up the resident buffer in the PMU. In general, set this to
* only log the event types you actually want to use.
* Refer to NVOS_BM_* in nvos_utility.h for usage.
*/
NvU8 mask[4];
} NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_RECALIBRATE
*
* Send a recalibrate event to the intstrumentation.
*/
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_RECALIBRATE (0x20803117) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS_MESSAGE_ID (0x17U)
typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
} NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH
*
* Get the egine arch i.e FALCON, RISCV etc given the NV2080_ENGINE_TYPE_*.
*
*/
#define NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH (0x20803118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID (0x18U)
typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
//! The engine architecture - FALCON or RISC-V
NvU32 engineArch;
} NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS;
/*!
* @defgroup Engine Arch types
* @{
*/
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT 0x0
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON 0x1
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV 0x2
/*!@}*/
/* ----------------------- uStreamer (INST v2) ------------------------------ */
/*!
* @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT uStreamer event fields.
*
* This is a binary-packed representation of uStreamer events. There are
* three main types of entry: Head, Payload, and Tail. COMM here is used
* when a field is shared among multiple event types.
*
* @{
*/
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_FLAG 31:31
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_HEAD 30:30
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_VARIABLE 29:29
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EXTEND 28:28
/*!
* Below DRF's need constants assigned to start and end so they can be represented in FINN properly
* This is because FINN v1 will not have the ability to represent DRF's and bit fields yet.
*/
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT (27)
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE (20)
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID \
(NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT) : \
(NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE)
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT (28)
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE (24)
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT \
(NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT) : \
(NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE)
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_LENGTH 19:8
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOAD 7:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT 23:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_HEAD_TIME 29:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_DATA_PAYLOAD 30:0
/*!@}*/
/*!
* @defgroup NV2080_CTRL_FLCN_USTREAMER_FEATURE
*
* This defines all the features currently supported by uStreamer. For a new
* usecase of uStreamer, a feature should be defined here describing the usecase.
* This value should be unique for each queue.
*
* @{
*/
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT 0U
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON 1U
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT 2U
/*!@}*/
/*!
* @defgroup NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY
*
* This defines the DRF used for ustreamer queue policy
*
* @{
*/
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH 0:0
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED 0U
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED 1U
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH 1:1
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED 0U
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED 1U
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH 2:2
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED 0U
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED 1U
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_THRESHOLD 31:8
/*!@}*/
/*!
* The maximum number of compact event types, calculated from the number of bits
* in the event structure.
*/
#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT (0x20U) /* finn: Evaluated from "(1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE + 1))" */
/*!
* The maximum number of event types, calculated from the number of bits in the
* event structure.
*/
#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES (0x120U) /* finn: Evaluated from "((1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE + 1)) + NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT)" */
/*!
* The number of bytes required in the event mask to contain all event types.
*/
#define NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES (0x24U) /* finn: Evaluated from "((NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES + 7) / 8)" */
/*!
* uStreamer Event Filter type, stored as a bitmask.
*/
typedef struct NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER {
NvU8 mask[NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES];
} NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER;
/*!
* NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO
* Get queue info for mapping / unmapping
*/
#define NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO (0x20803120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
//!
// The page size of the requested queue in bytes.
//
NvU32 pageSize;
//! Offset of the queue buffer in FB.
NV_DECLARE_ALIGNED(NvUPtr offset, 8);
//!
// The size of the user-mapped instrumentation buffer. Measured in bytes.
//
NvU32 size;
//!
// The feature ID of the queue.
//
NvU8 queueFeatureId;
} NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET/SET
*
* Get/set the event bitmask for the default queue.
*/
#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x22" */
#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x23" */
typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
/*!
* The bitmask of which event types to log. An event type corresponding to
* a bit with a zero will be ignored at the log site, which prevents it
* from filling up the resident buffer in the PMU. In general, set this to
* only log the event types you actually want to use.
* Refer to NVOS_BM_* in nvos_utility.h for usage.
*/
NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER eventFilter;
//! The queueId of the queue whose eventFilter we want to interact with
NvU8 queueId;
} NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO
*
* This command provides the attributes of the falcon engine context buffer
*
* hUserClient [IN]
* This parameter specifies the client handle that owns this channel.
* hChannel [IN]
* This parameter specifies the channel or channel group (TSG) handle
* alignment
* Specifies the alignment requirement for each context buffer
* size
* Aligned size of context buffer
* bufferHandle
* Opaque pointer to memdesc. Used by kernel clients for tracking purpose only.
* pageCount
* allocation size in the form of pageCount
* physAddr
* Physical address of the buffer first page
* aperture
* allocation aperture. Could be SYSMEM, VIDMEM, UNKNOWN
* kind
* PTE kind of this allocation.
* pageSize
* Page size of the buffer.
* bIsContigous
* States if physical allocation for this buffer is contiguous. PageSize will
* have no meaning if this flag is set.
* bDeviceDescendant
* TRUE if the allocation is a constructed under a Device or Subdevice.
* uuid
* SHA1 UUID of the Device or Subdevice. Valid when bDeviceDescendant is TRUE.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO (0x20803124) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID (0x24U)
typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS {
NvHandle hUserClient;
NvHandle hChannel;
NV_DECLARE_ALIGNED(NvU64 alignment, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NV_DECLARE_ALIGNED(NvP64 bufferHandle, 8);
NV_DECLARE_ALIGNED(NvU64 pageCount, 8);
NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
NvU32 aperture;
NvU32 kind;
NvU32 pageSize;
NvBool bIsContigous;
NvBool bDeviceDescendant;
NvU8 uuid[16];
} NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS;
// Aperture flags
#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN
#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM
#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM
/*
* NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE
*
* This command provides the size of the falcon engine context buffer
*
* hChannel [IN]
* This parameter specifies the channel or channel group (TSG) handle
* totalBufferSize [OUT]
* This parameter returns the total context buffers size.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE (0x20803125) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x25U)
typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS {
NvHandle hChannel;
NV_DECLARE_ALIGNED(NvU64 totalBufferSize, 8);
} NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS;
/* _ctrl2080flcn_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fuse.finn
//
/* _ctrl2080fuse_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gpio.finn
//
/* _ctrl2080gpio_h_ */
#include "ctrl/ctrl2080/ctrl2080base.h"

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/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*!
* This structure represents base class of GPU monitoring sample.
*/
typedef struct NV2080_CTRL_GPUMON_SAMPLE {
/*!
* Timestamps in nano-seconds.
*/
NV_DECLARE_ALIGNED(NvU64 timeStamp, 8);
} NV2080_CTRL_GPUMON_SAMPLE;
/*!
* This structure represents base GPU monitoring sample.
*/
typedef struct NV2080_CTRL_GPUMON_SAMPLES {
/*!
* Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference.
*/
NvU8 type;
/*!
* Size of the buffer, this should be
* bufSize == NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_*
* sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE).
*/
NvU32 bufSize;
/*!
* Number of samples in ring buffer.
*/
NvU32 count;
/*!
* tracks the offset of the tail in the circular queue array pSamples.
*/
NvU32 tracker;
/*!
* Pointer to a circular queue based on array of NV2080_CTRL_GPUMON_SAMPLE
* or its derived types structs with size == bufSize.
*
* @note This circular queue wraps around after 10 seconds of sampling,
* and it is clients' responsibility to query within this time frame in
* order to avoid losing samples.
* @note With one exception, this queue contains last 10 seconds of samples
* with tracker poiniting to oldest entry and entry before tracker as the
* newest entry. Exception is when queue is not full (i.e. tracker is
* pointing to a zeroed out entry), in that case valid entries are between 0
* and tracker.
* @note Clients can store tracker from previous query in order to provide
* samples since last read.
*/
NV_DECLARE_ALIGNED(NvP64 pSamples, 8);
} NV2080_CTRL_GPUMON_SAMPLES;
/*!
* Enumeration of GPU monitoring sample types.
*/
#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS 0x00000001
#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL 0x00000002
/*!
* Macro for invalid PID.
*/
#define NV2080_GPUMON_PID_INVALID ((NvU32)(~0))

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX grmgr control commands and parameters */
//
// NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO
//
// This control call works as a batched query interface where we
// have multiple different queries that can be passed in
// and RM will return the associated data and status type
// If there is any error in NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS,
// we will immediately fail the call.
// However, if there is an error in the query-specific calls, we will
// log the error and march on.
//
// NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS
// numQueries[IN]
// - Specifies the number of valid queries that the caller will be passing in
//
// Possible status values returned are:
// NV_OK
// NV_ERR_INVALID_ARGUMENT
// NV_ERR_INVALID_STATE
//
#define NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO (0x20803801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID << 8) | NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID" */
// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO
#define NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES 96
//
// Preference is to keep max.size of union at 24 bytes (i.e. 6 32-bit members)
// so that the size of entire query struct is maintained at 32 bytes, to ensure
// that overall params struct does not exceed 4kB
//
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE 32
#define NV2080_CTRL_GRMGR_MAX_SMC_IDS 8
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS
* gpcCount[OUT]
* - No. of logical/local GPCs which client can use to create the
* logical/local mask respectively
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS {
NvU32 gpcCount; // param[out] - logical/local GPC mask
} NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS
* gpcId[IN]
* - Logical/local GPC ID
* chipletGpcMap[OUT]
* - Returns chiplet GPC ID for legacy case and device monitoring client
* - Returns local GPC ID (== input gpcId) for SMC client
* - Does not support DM attribution case
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS {
NvU32 gpcId; // param[in] - logical/local GPC ID
NvU32 chipletGpcMap; // param[out] - chiplet GPC ID
} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS
* gpcId[IN]
* - Logical/local GPC ID
* tpcMask[OUT]
* - Returns physical TPC mask for legacy, DM client and SMC cases
* - Does not support DM attribution case
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS {
NvU32 gpcId; // param[in] - logical/local GPC ID
NvU32 tpcMask; // param[out] - physical TPC mask
} NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS
* gpcId[IN]
* - Logical/local GPC ID
* ppcMask[OUT]
* - Returns physical PPC mask for legacy, DM client and SMC cases
* - Does not support DM attribution case
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS {
NvU32 gpcId; // param[in] - logical/local GPC ID
NvU32 ppcMask; // param[out] - physical PPC mask
} NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS;
/*!
* !!! DEPRECATED - This query will return NV_ERR_NOT_SUPPORTED since deleting
* it would break driver compatibility !!!
*
* NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS
* swizzId[IN]
* - Swizz ID of partition
* - A DM client with an invalid swizz ID, will fail this call
* - This parameter is not compulsory for an SMC client; the subscription
* itself will do the necessary validation.
* gpcId[IN]
* - Logical/local GPC ID
* chipletGpcMap[OUT]
* - Returns chiplet GPC ID for legacy case and device monitoring client
* - Returns local GPC ID (== input gpcId) for SMC client
* - Does not support non-attribution case for DM client
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS {
NvU32 swizzId; // param[in] - swizz ID of partition
NvU32 gpcId; // param[in] - logical/local GPC ID
NvU32 chipletGpcMap; // param[out] - chiplet GPC ID
} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS
* gpcId[IN]
* - Logical/local GPC ID
* ropMask[OUT]
* - Returns physical ROP mask for legacy, DM client
* - Returns logical ROP mask for SMC
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS {
NvU32 gpcId; // param[in] - logical/local GPC ID
NvU32 ropMask; // param[out] - physical ROP mask
} NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS
* chipletSyspipeMask [OUT]
* - Mask of chiplet SMC-IDs for DM client attribution case
* - Mask of local SMC-IDs for SMC client
* - Legacy case returns 1 GR
* - Does not support attribution case for DM client
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS {
NvU32 chipletSyspipeMask; // param[out] - Mask of chiplet SMC IDs
} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS
* swizzId[IN]
* - Swizz ID of partition
* - A DM client with an invalid swizz ID, will fail this call
* physSyspipeId[GRMGR_MAX_SMC_IDS] [OUT]
* - Physical SMC-IDs mapped to partition local idx for DM client attribution case
* - Does not support non-attribution case for DM client, SMC clients, legacy case
* physSyspipeIdCount[OUT]
* - Valid count of physSmcIds which has been populated in above array.
* - Failure case will return 0
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS {
NvU16 swizzId; // param[in] - swizz ID of partition
NvU16 physSyspipeIdCount; // param[out] - Count of physSmcIds in above array
NvU8 physSyspipeId[NV2080_CTRL_GRMGR_MAX_SMC_IDS]; // param[out] - physical/local SMC IDs
} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS
* swizzId[IN]
* - Swizz ID of partition
* - Mandatory parameter
* - A DM client with an invalid swizz ID, will fail this call
* grIdx[IN]
* - Local grIdx for a partition
* - Mandatory parameter
* gpcEnMask[OUT]
* - Logical enabled GPC mask associated with requested grIdx of the partition i.e swizzid->engineId->gpcMask
* - These Ids should be used as input further
* - Does not support non-attribution case for DM client, SMC clients, legacy case
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS {
NvU32 swizzId; // param[in] - swizz ID of partition
NvU32 grIdx; // param[in] - partition local GR ID
NvU32 gpcEnMask; // param[out] - logical enabled GPC mask
} NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID
* syspipeId[OUT]
* - Partition-local GR idx for client subscribed to exec partition
* - Does not support legacy case, DM client, or SMC client subscribed only to partition
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS {
NvU32 syspipeId; // param[out] - partition-local Gr idx
} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS;
/*!
* queryType[IN]
* - Use queryType defines to specify what information is being requested
* status[OUT]
* - Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS {
NvU16 queryType;
NvU8 reserved[2]; // To keep the struct aligned for now and available for future use (if needed)
NvU32 status;
union {
NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS gpcCountData;
NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS chipletGpcMapData;
NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS tpcMaskData;
NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS ppcMaskData;
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS partitionGpcMapData;
NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS syspipeMaskData;
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS partitionChipletSyspipeData;
NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS dmGpcMaskData;
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS partitionSyspipeIdData;
NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS ropMaskData;
} queryData;
} NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS;
#define NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS {
NvU16 numQueries;
NvU8 reserved[6]; // To keep the struct aligned for now and available for future use (if needed)
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS queries[NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES];
} NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS;
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID 0
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT 1
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP 2
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK 3
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK 4
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP 5 /* deprecated */
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK 6
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS 7
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK 8
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID 9
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK 10
/* _ctrl2080grmgr_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gsp.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX GSP control commands and parameters */
/*
* NV2080_CTRL_CMD_GSP_GET_FEATURES
*
* This command is used to determine which GSP features are
* supported on this GPU.
*
* gspFeatures
* Bit mask that specifies GSP features supported.
* bValid
* If this field is set to NV_TRUE, then above bit mask is
* considered valid. Otherwise, bit mask should be ignored
* as invalid. bValid will be set to NV_TRUE when RM is a
* GSP client with GPU support offloaded to GSP firmware.
* bDefaultGspRmGpu
* If this field is set to NV_TRUE, it indicates that the
* underlying GPU has GSP-RM enabled by default. If set to NV_FALSE,
* it indicates that the GPU has GSP-RM disabled by default.
* firmwareVersion
* This field contains the buffer into which the firmware build version
* should be returned, if GPU is offloaded. Otherwise, the buffer
* will remain untouched.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_GSP_GET_FEATURES (0x20803601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID" */
#define NV2080_GSP_MAX_BUILD_VERSION_LENGTH (0x0000040)
#define NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS {
NvU32 gspFeatures;
NvBool bValid;
NvBool bDefaultGspRmGpu;
NvU8 firmwareVersion[NV2080_GSP_MAX_BUILD_VERSION_LENGTH];
} NV2080_CTRL_GSP_GET_FEATURES_PARAMS;
/* Valid feature values */
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED 0:0
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000)
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001)
// _ctrl2080gsp_h_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080hshub.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*
* NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK
*
* This command get active HSHUB masks.
*
* hshubNcisocMask
* NCISOC enabled active HSHUBs
* hshubNvlMask
* NVLINK capable active HSHUBs.
*/
#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS {
NvU32 hshubNcisocMask;
NvU32 hshubNvlMask;
} NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS;
#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK (0x20804101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID" */
/* _ctrl2080hshub_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080i2c.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX i2c-related control commands and parameters */
/*
* NV2080_CTRL_I2C_VERSION
*
* NV2080_CTRL_I2C_VERSION_0_0:
* This return state specifies that support is only available
* for single subAddr reads.
*
*/
#define NV2080_CTRL_I2C_VERSION_0 0x00
/* maximum number of i2c entries support */
#define NV2080_CTRL_I2C_MAX_ENTRIES 256
#define NV2080_CTRL_I2C_MAX_REG_LEN 8
#define NV2080_CTRL_I2C_MAX_ADDR_ENTRIES 20
/*
* NV2080_CTRL_I2C_FLAGS
*
* NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC:
* This option specified that non-compliant i2c for SI1930UC is required
*
* NV2080_CTRL_I2C_FLAGS_PRIVILEGE
* This option specified that the i2c access is privileged
*
* NV2080_CTRL_I2C_FLAGS_PX3540
* This option specified that the i2c device -PX3540/3544- is accessed
*/
#define NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC (0x00000001)
#define NV2080_CTRL_I2C_FLAGS_PRIVILEGE (0x00000002)
#define NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED (0x00000004)
#define NV2080_CTRL_I2C_FLAGS_PX3540 (0x00000010)
#define NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED (0x00000008)
/*
* NV2080_CTRL_CMD_I2C_READ_BUFFER
*
* This command allocates video memory for a particular subset of microcode.
*
* version
* This field is returned to the client and indicates the current
* supported I2C controls available.
*
* port
* This field must be specified by the client to indicate which port/bus
* in which i2c access is desired.
*
* flags
* This field is specified by the client to request additional options
* as provided by NV2080_CTRL_I2C_FLAGS.
*
* inputCount
* This field specifies the total # of elements contained in inputBuffer
*
* inputBuffer
* This should contain the chipaddr as the first element, followed by
* the each subAddress in which to access the first element of data
* Eg. <chipAddr> <subAddr1> ... <subAddrX>
* In general, client will only have 2 elements <chipAddr> <subAddr>
*
* outputCount
* This field specifies how many registers from the start register index.
* The maximum values allow are NV2080_CTRL_I2C_MAX_ENTRIES.
*
* outputBuffer
* This buffer is returned to the client with the data read from
* the start register index.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_STATE_IN_USE
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*
*/
#define NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_I2C_READ_BUFFER_PARAMS {
NvU32 version;
NvU32 port;
NvU32 flags;
NvU32 inputCount;
// C form: NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
NvU32 outputCount;
// C form: NvU8 outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
NvU8 outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
} NV2080_CTRL_I2C_READ_BUFFER_PARAMS;
#define NV2080_CTRL_CMD_I2C_READ_BUFFER (0x20800601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_I2C_WRITE_BUFFER
*
* This command allocates video memory for a particular subset of microcode.
*
* version
* This field is returned to the client and indicates the current
* supported I2C controls available.
*
* port
* This field must be specified by the client to indicate which port/bus
* in which i2c access is desired.
*
* flags
* This field is specified by the client to request additional options.
* NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC:
* - Specifies that non-compliant i2c access for SI1930UC is required
*
* inputCount
* This field specifies the total # of elements contained in inputBuffer
*
* inputBuffer
* This should contain the chipaddr as the first element, followed by
* the each subAddress in which to access the first element of data,
* and finally the data to be programmed.
* Eg. <chipAddr> <subAddr1> ... <subAddrX> <data1> ... <dataX>
* In general, client will have 2 elements + data to be programmed.
* <chipAddr> <subAddr> <data1> ... <dataX>
*
* encrClientID
* This field is specified by client, which is used to uniquely access
* the client's encryption context
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_STATE_IN_USE
* NV_ERR_INVALID_STATE
*
*/
#define NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS {
NvU32 version;
NvU32 port;
NvU32 flags;
NvU32 inputCount;
// C form: NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
NvU32 encrClientID;
} NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS;
#define NV2080_CTRL_CMD_I2C_WRITE_BUFFER (0x20800602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_I2C_READ_REG
*
* This command allocates video memory for a particular subset of microcode.
*
* version
* This field is returned to the client and indicates the current
* supported I2C controls available.
*
* port
* This field must be specified by the client to indicate which port/bus
* in which i2c access is desired.
*
* flags
* This field is specified by the client to request additional options.
* NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC:
* - Specifies that non-compliant i2c access for SI1930UC is required
* addr
* This field is specified by the client to target address.
* reg
* This field is specified by the client to target register address.
*
* bufsize
* This field specifies the total bytes # of register size
*
* buffer
* when used for read, it used as buffer that store returned register content
* when used for write, It include data that will be written.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_STATE_IN_USE
* NV_ERR_INVALID_STATE
*
*/
typedef struct NV2080_CTRL_I2C_RW_REG_PARAMS {
NvU32 version;
NvU32 port;
NvU32 flags;
NvU32 addr;
NvU8 reg;
NvU8 bufsize;
// C form: NvU8 buffer[NV2080_CTRL_I2C_MAX_ENTRIES - 1];
NvU8 buffer[(NV2080_CTRL_I2C_MAX_ENTRIES - 1)];
} NV2080_CTRL_I2C_RW_REG_PARAMS;
// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name
typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS;
#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x3" */
#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x4" */
/*
* NV006F_CTRL_CMD_SYSTEM_I2C_ACCESS
*
* This command allows Clients to read and write data using the I2C ports
*
* token [IN]
* This used in i2cAcquirePort
*
* cmd [IN]
* The I2CAccess command
*
* port [IN]
* The port ID of the concerned display
*
* flags [IN]
* The I2CAccess Flags such ack,start,stop
*
* data [OUT/IN]
* Data that needs to be pass or read out
*
* dataBuffSize [IN]
* Size of the data buffer.
*
* speed [IN]
* Speed of transaction.
*
* status [OUT]
* The I2CAccess Status returned
*
* encrClientID [IN]
* This field is specified by client, which is used to uniquely access
* the client's encryption context
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV2080_CTRL_I2C_ACCESS_PARAMS {
NvU32 token;
NvU32 cmd;
NvU32 port;
NvU32 flags;
NV_DECLARE_ALIGNED(NvP64 data, 8);
NvU32 status;
NvU32 dataBuffSize;
NvU32 speed;
NvU32 encrClientID;
} NV2080_CTRL_I2C_ACCESS_PARAMS;
// commands
#define NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE 0x1
#define NV2080_CTRL_I2C_ACCESS_CMD_RELEASE 0x2
#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE 0x3
#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE 0x4
#define NV2080_CTRL_I2C_ACCESS_CMD_NULL 0x5
#define NV2080_CTRL_I2C_ACCESS_CMD_RESET 0x6
#define NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT 0x11
#define NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE 0x12
#define NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE 0x13
#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER 0x14
#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER 0x15
#define NV2080_CTRL_I2C_ACCESS_CMD_START 0x17
#define NV2080_CTRL_I2C_ACCESS_CMD_STOP 0x18
#define NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE 0x20
// flags
#define NV2080_CTRL_I2C_ACCESS_FLAG_START 0x1
#define NV2080_CTRL_I2C_ACCESS_FLAG_STOP 0x2
#define NV2080_CTRL_I2C_ACCESS_FLAG_ACK 0x4
#define NV2080_CTRL_I2C_ACCESS_FLAG_RAB 0x8
#define NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS 0x10
#define NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE 0x20
#define NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED 0x40
#define NV2080_CTRL_I2C_ACCESS_FLAG_RESTART 0x80
#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT 0x100
#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT 0x200
#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT 0x400
#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT 0x800
#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT 0x1000
// port
#define NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC 0x0
#define NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY 0x1
#define NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY 0x2
#define NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY 0x3
#define NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY 0x4
// Alternate numeric port designators
#define NV2080_CTRL_I2C_ACCESS_PORT_1 0x1
#define NV2080_CTRL_I2C_ACCESS_PORT_2 0x2
#define NV2080_CTRL_I2C_ACCESS_PORT_3 0x3
#define NV2080_CTRL_I2C_ACCESS_PORT_4 0x4
#define NV2080_CTRL_I2C_ACCESS_PORT_5 0x5
#define NV2080_CTRL_I2C_ACCESS_PORT_6 0x6
#define NV2080_CTRL_I2C_ACCESS_PORT_7 0x7
#define NV2080_CTRL_I2C_ACCESS_PORT_8 0x8
#define NV2080_CTRL_I2C_ACCESS_PORT_9 0x9
#define NV2080_CTRL_I2C_ACCESS_PORT_10 0x10
// Total ports count
#define NV2080_CTRL_I2C_ACCESS_NUM_PORTS NV2080_CTRL_I2C_ACCESS_PORT_10
// status
#define NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS 0x0
#define NV2080_CTRL_I2C_ACCESS_STATUS_ERROR 0x1
#define NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR 0x2
#define NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY 0x3
#define NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND 0x4
#define NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING 0x5
#define NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE (0x20800620) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS {
NvU32 head;
NvU32 authType;
NvU32 status;
} NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS;
/* _ctrl2080i2c_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080illum.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn
//
// _ctrl2080lpwr_h_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080mc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX mc control commands and parameters */
/**
* NV2080_CTRL_CMD_MC_GET_ARCH_INFO
*
* This command returns chip architecture information from the
* master control engine in the specified GPU.
*
* architecture
* This parameter specifies the architecture level for the GPU.
* implementation
* This parameter specifies the implementation of the architecture
* for the GPU.
* revision
* This parameter specifies the revision of the mask used to produce
* the GPU.
* subRevision
* This parameter specific the sub revision of the GPU. Value is one of
* NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_MC_GET_ARCH_INFO (0x20801701) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
NvU32 architecture;
NvU32 implementation;
NvU32 revision;
NvU8 subRevision;
} NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS;
/* valid architecture values */
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X (0xE0000023)
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 (0x00000160)
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170)
/* valid ARCHITECTURE_T23X implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 (0x00000004)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D (0x00000005)
/* valid ARCHITECTURE_TU10x implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102 (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104 (0x00000004)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106 (0x00000006)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116 (0x00000008)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117 (0x00000007)
/* valid ARCHITECTURE_GA10x implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102 (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103 (0x00000003)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104 (0x00000004)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106 (0x00000006)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107 (0x00000007)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B (0x0000000B)
/* Valid Chip sub revisions */
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P (0x00000001)
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R (0x00000003)
/*
* NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS
*
* This command instructs the RM to service interrupts for the specified
* engine(s).
*
* engines
* This parameter specifies which engines should have their interrupts
* serviced.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS (0x20801702) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_ENGINE_ID_GRAPHICS 0x00000001
#define NV2080_CTRL_MC_ENGINE_ID_ALL 0xFFFFFFFF
#define NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS {
NvU32 engines;
} NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS;
/*
* NV2080_CTRL_CMD_MC_GET_MANUFACTURER
*
* This command returns the GPU manufacturer information for the associated
* subdevice.
*
* manufacturer
* This parameter returns the manufacturer value for the GPU.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_MC_GET_MANUFACTURER (0x20801703) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS {
NvU32 manufacturer;
} NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS;
/*
* NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS
*
* This command is used to allow clients to query whether hostclk slowdown is
* disabled.
*
* bDisabled
* This parameter will hold the status of hostclk slowdown
*
* Possible status values returned are:
* NV_OK
*
*/
#define NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS (0x20801708) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS {
NvBool bDisabled;
} NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS
*
* This command is used to allow clients to disable/enable hostclk slowdown.
*
* bDisable
* When this parameter is set to TRUE, RM should disable hostclk slowdown.
* If it is set to FALSE, RM will attempt to enable hostclk slowdown, but
* in this case, slowdown is NOT guaranteed to be enabled since there may
* be other reason (like regkey) preventing slowdown.
*
* Possible status values returned are:
* NV_OK
*
*/
#define NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS (0x20801709) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS {
NvBool bDisable;
} NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP
*
* This call will setup RM to either service or ignore the
* repayable fault interrupt.
* This is a privileged call that can only be called by the UVM driver
* when it will take ownership of the repalayable fault interrupt.
*
* Possible status values returned are:
* NVOS_STATUS_SUCCESS
* NVOS_STATUS_ERROR_INVALID_ARGUMENT
* NVOS_STATUS_ERROR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP (0x2080170c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS {
NvBool bOwnedByRm;
} NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS;
/*
* NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS
*
* This command gets the notification interrupt vectors device for all VGPU engines from Host RM.
*
* Parameters:
*
* entries [out]
* A buffer to store up to MAX_ENGINES entries of type
* NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY.
*
* numEntries [out]
* Number of populated entries in the provided buffer.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS (0x2080170d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES 256
typedef struct NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY {
NvU32 nv2080EngineType;
NvU32 notificationIntrVector;
} NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY;
#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS {
NvU32 numEntries;
NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY entries[NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES];
} NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS;
/*
* NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE
*
* This command gets the static interrupts needed by VGPU from Host RM.
*
* Parameters:
*
* entries [out]
* A buffer to store up to MAX_ENGINES entries of type
* NV2080_CTRL_MC_STATIC_INTR_ENTRY.
*
* numEntries [out]
* Number of populated entries in the provided buffer.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE (0x2080170e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX 32
// Interface defines for static MC_ENGINE_IDX defines
#define NV2080_INTR_TYPE_NULL (0x00000000)
#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT (0x00000001)
#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR (0x00000002)
#define NV2080_INTR_TYPE_INFO_FAULT (0x00000003)
#define NV2080_INTR_TYPE_REPLAYABLE_FAULT (0x00000004)
#define NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR (0x00000005)
#define NV2080_INTR_TYPE_ACCESS_CNTR (0x00000006)
#define NV2080_INTR_TYPE_TMR (0x00000007)
#define NV2080_INTR_TYPE_CPU_DOORBELL (0x00000008)
#define NV2080_INTR_TYPE_GR0_FECS_LOG (0x00000009)
#define NV2080_INTR_TYPE_GR1_FECS_LOG (0x0000000A)
#define NV2080_INTR_TYPE_GR2_FECS_LOG (0x0000000B)
#define NV2080_INTR_TYPE_GR3_FECS_LOG (0x0000000C)
#define NV2080_INTR_TYPE_GR4_FECS_LOG (0x0000000D)
#define NV2080_INTR_TYPE_GR5_FECS_LOG (0x0000000E)
#define NV2080_INTR_TYPE_GR6_FECS_LOG (0x0000000F)
#define NV2080_INTR_TYPE_GR7_FECS_LOG (0x00000010)
typedef struct NV2080_CTRL_MC_STATIC_INTR_ENTRY {
NvU32 nv2080IntrType;
NvU32 pmcIntrMask;
NvU32 intrVectorStall;
NvU32 intrVectorNonStall;
} NV2080_CTRL_MC_STATIC_INTR_ENTRY;
#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS {
NvU32 numEntries;
NV2080_CTRL_MC_STATIC_INTR_ENTRY entries[NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX];
} NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS;
/* _ctrl2080mc_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080nvd.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrlxxxx.h"
/*
* NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE
*
* This command gets the expected dump size of a particular GPU dump component.
* Note that events that occur between this command and a later
* NV2080_CTRL_CMD_NVD_GET_DUMP command could alter the size of
* the buffer required.
*
* component
* One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to estimate
* the size of.
* size
* This parameter returns the expected size.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT if component is invalid.
*
*/
#define NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE (0x20802401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS {
NvU32 component;
NvU32 size;
} NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS;
/*
* NV2080_CTRL_CMD_NVD_GET_DUMP
*
* This command gets a dump of a particular GPU dump component. If triggers
* is non-zero, the command waits for the trigger to occur
* before it returns.
*
* pBuffer
* This parameter points to the buffer for the data.
* component
* One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to select
* for dumping.
* size
* On entry, this parameter specifies the maximum length for
* the returned data. On exit, it specifies the number of bytes
* returned.
*
* Possible status values returned are:
* NV_OK
* NVOS_ERROR_INVALID_ARGUMENT if component is invalid.
* NVOS_ERROR_INVALID_ADDRESS if pBuffer is invalid
* NVOS_ERROR_INVALID_???? if the buffer was too small
*
*
*/
#define NV2080_CTRL_CMD_NVD_GET_DUMP (0x20802402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_NVD_GET_DUMP_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pBuffer, 8);
NvU32 component;
NvU32 size;
} NV2080_CTRL_NVD_GET_DUMP_PARAMS;
/*
* NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL
*
* This command returns the contents of the Journal used by NOCAT, and
* optionally clears the data
*
* clear:
* [IN] indicates if should the data be cleared after reporting
*
* JournalRecords :
* [OUT] an array of Journal records reported.
*
* outstandingAssertCount:
* [OUT] number of asserts that remain to be reported on.
*
* reportedAssertCount:
* [OUT] the number of asserts contained in the report
*
* asserts:
* [OUT] an array of up to NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS assert reports
*/
#define NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL (0x20802409) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID" */
#define NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER 1024
#define NV2080_NOCAT_JOURNAL_MAX_STR_LEN 65
#define NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS 10
#define NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS 32
// structure to hold clock details.
typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS {
NvS32 userMinOffset;
NvS32 userMaxOffset;
NvU32 factoryMinOffset;
NvU32 factoryMaxOffset;
NvU32 lastActiveClock;
NvU32 lastActiveVolt;
NvU32 lastActivePoint;
NvU32 kappa;
} NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS;
// structure to hold clock configuration & state.
typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG {
NvU32 pstateVer;
NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS gpcOverclock;
NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS mclkOverclock;
NvBool bUserOverclocked;
NvBool bFactoryOverclocked;
} NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG;
// structure to hold the GPU context at the time of the report.
typedef struct NV2080_NOCAT_JOURNAL_GPU_STATE {
NvBool bValid;
NvU32 strap;
NvU16 deviceId;
NvU16 vendorId;
NvU16 subsystemVendor;
NvU16 subsystemId;
NvU16 revision;
NvU16 type;
NvU32 vbiosVersion;
NvBool bOptimus;
NvBool bMsHybrid;
NvBool bFullPower;
NvU32 vbiosOemVersion;
NvU16 memoryType;
NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU8 vbiosProject[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvBool bInFullchipReset;
NvBool bInSecBusReset;
NvBool bInGc6Reset;
NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG overclockCfg;
} NV2080_NOCAT_JOURNAL_GPU_STATE;
#define NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN 0
#define NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK 1
#define NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE 2
#define NV2080_NOCAT_JOURNAL_REC_TYPE_TDR 3
#define NV2080_NOCAT_JOURNAL_REC_TYPE_RC 4
#define NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT 5
#define NV2080_NOCAT_JOURNAL_REC_TYPE_ANY 6
// this should be relative to the highest type value
#define NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT (0x7) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REC_TYPE_ANY + 1" */
typedef struct NV2080_NOCAT_JOURNAL_ENTRY {
NvU8 recType;
NvU32 bugcheck;
NvU32 tdrBucketId;
NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 subsystem;
NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
NvU32 diagBufferLen;
NvU8 diagBuffer[NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER];
NvU8 faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 mmuFaultType;
NvU32 mmuErrorSrc;
NvU8 tdrReason[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
} NV2080_NOCAT_JOURNAL_ENTRY;
typedef struct NV2080_NOCAT_JOURNAL_RECORD {
NvU32 GPUTag;
NV_DECLARE_ALIGNED(NvU64 loadAddress, 8);
NV_DECLARE_ALIGNED(NvU64 timeStamp, 8);
NV_DECLARE_ALIGNED(NvU64 stateMask, 8);
NV2080_NOCAT_JOURNAL_GPU_STATE nocatGpuState;
NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_ENTRY nocatJournalEntry, 8);
} NV2080_NOCAT_JOURNAL_RECORD;
// NOCAT activity counter indexes
// collection activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX 0
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 1
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 2
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 3
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 4
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_DROPPED_IDX 5
// reporting activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 6
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 7
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 8
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MISSED_IDX 9
// update activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 10
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 11
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 12
// general errors
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 13
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 14
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 15
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX 16
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 17
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CACHE_UPDATE_IDX 18
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX 19
// this should be relative to the highest counter index
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT (0x14) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX + 1" */
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY 0:0
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES 1
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO 0
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS 1:1
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES 1
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO 0
#define NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
NvU32 flags;
NvU32 nocatRecordCount;
NvU32 nocatOutstandingRecordCount;
NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_RECORD journalRecords[NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS], 8);
NvU32 activityCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT];
NvU8 reserved[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
} NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS;
/*
* NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA
*
* This command reports the TDR data collected by KMD to be added to the
* nocat record
*
* dataType:
* [IN] specifies the type of data provided.
* targetRecordType
* [IN] specifies record type the data is intended for.
* nocatJournalData
* [IN] specifies the data to be added.
*/
#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */
// data types & structures
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY 0
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD 2
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 3
#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0
#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1
#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP 2
#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET 3
#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4
#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5
#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6
#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7
typedef struct NV2080CtrlNocatJournalDataTdrReason {
NvU32 flags;
NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 subsystem;
NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
NvU32 reasonCode;
} NV2080CtrlNocatJournalDataTdrReason;
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR 0:0
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES 1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO 0
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER 1:1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO 0
typedef struct NV2080CtrlNocatJournalInsertRecord {
NvU32 flags;
NvU8 recType;
NvU32 bugcheck;
NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 subsystem;
NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
NvU8 faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 tdrReason;
} NV2080CtrlNocatJournalInsertRecord;
#define NV2080_CTRL_NOCAT_TAG_CLEAR 0:0
#define NV2080_CTRL_NOCAT_TAG_CLEAR_YES 1
#define NV2080_CTRL_NOCAT_TAG_CLEAR_NO 0
typedef struct NV2080CtrlNocatJournalSetTag {
NvU32 flags;
NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
} NV2080CtrlNocatJournalSetTag;
#define NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS {
NvU32 dataType;
NvU32 targetRecordType;
union {
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8);
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord insertData, 8);
NV2080CtrlNocatJournalSetTag tagData;
} nocatJournalData;
} NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS;
/* _ctr2080nvd_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080perf.finn
//
#include "nvfixedtypes.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
#define NV_SUBPROC_NAME_MAX_LENGTH 100
#include "nvmisc.h"
#include "ctrl/ctrl2080/ctrl2080clk.h"
#include "ctrl/ctrl2080/ctrl2080gpumon.h"
#include "ctrl/ctrl2080/ctrl2080volt.h"
#include "ctrl/ctrl2080/ctrl2080vfe.h"
#include "ctrl/ctrl2080/ctrl2080pmumon.h"
#include "ctrl/ctrl0080/ctrl0080perf.h"
//
// XAPICHK/XAPI_TEST chokes on the "static NVINLINE" defines in nvmisc.h.
// However, we don't need any of those definitions for those tests (XAPICHK is a
// syntactical check, not a functional test). So, instead, just #define out the
// macros referenced below.
//
/*
* NV2080_CTRL_CMD_PERF_BOOST
*
* This command can be used to boost P-State up one level or to the highest for a limited
* duration for the associated subdevice. Boosts from different clients are being tracked
* independently. Note that there are other factors that can limit P-States so the resulting
* P-State may differ from expectation.
*
* flags
* This parameter specifies the actual command. _CLEAR is to clear existing boost.
* _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost
* to the highest P-State.
* duration
* This parameter specifies the duration of the boost in seconds. This has to be less
* than NV2080_CTRL_PERF_BOOST_DURATION_MAX.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD 1:0
#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR (0x00000000)
#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL (0x00000001)
#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX (0x00000002)
#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA 4:4
#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO (0x00000000)
#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES (0x00000001)
#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC 5:5
#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO (0x00000000)
#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES (0x00000001)
#define NV2080_CTRL_PERF_BOOST_DURATION_MAX 3600 //The duration can be specified up to 1 hour
#define NV2080_CTRL_PERF_BOOST_DURATION_INFINITE 0xffffffff // If set this way, the boost will last until cleared.
#define NV2080_CTRL_CMD_PERF_BOOST (0x2080200a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV2080_CTRL_PERF_BOOST_PARAMS {
NvU32 flags;
NvU32 duration;
} NV2080_CTRL_PERF_BOOST_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW
*
* This command reserves HW Performance Monitoring capabilities for exclusive
* use by the requester. If the HW Performance Monitoring capabilities are
* currently in use then NVOS_STATUS_ERROR_STATE_IN_USE is returned.
*
* bAcquire
* When set to TRUE this parameter indicates that the client wants to
* acquire the Performance Monitoring capabilities on the subdevice.
* When set to FALSE this parameter releases the Performance Monitoring
* capabilities on the subdevice.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_ERROR_STATE_IN_USE
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW (0x20802093) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID (0x93U)
typedef struct NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS {
NvBool bAcquire;
} NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS;
/*!
* Enumeration of the RATED_TDP arbitration clients which make requests to force
* enable/disable VF points above the RATED_TDP point.
*
* These clients are sorted in descending priority - the RM will arbitrate
* between all clients in order of priority, taking as output the first client
* whose input action != @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT.
*/
typedef enum NV2080_CTRL_PERF_RATED_TDP_CLIENT {
/*!
* Internal RM client corresponding to the RM's internal state and features.
* The RM client will either allow default behavior (@ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT) or will limit to RATED_TDP
* (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) when no power
* controllers are active.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = 0,
/*!
* This Client is specifically for Bug 1785342 where we need to limit the TDP
* to Min value on boot. And clear the Max TDP limit.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = 1,
/*!
* Global client request. This client is expected to be used by a global
* switch functionality in an end-user tool, such as EVGA Precision, to
* either force enabling boost above RATED_TDP (@ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED) or to force limiting to
* RATED_TDP (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) across the
* board, regardless of any app-profie settings.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = 2,
/*!
* Operating system request. This client is expected to be used by the
* operating system to set @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK
* for performance profiling.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = 3,
/*!
* App profile client requests. This client is expected to be used by the
* app-profile settings to either default to whatever was requested by
* higher-priority clients (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT)
* or to limit to RATED_TDP (@ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) for apps which have shown
* bad behavior when boosting.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = 4,
/*!
* Number of supported clients.
*
* @Note MUST ALWAYS BE LAST!
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = 5,
} NV2080_CTRL_PERF_RATED_TDP_CLIENT;
/*!
* Enumeration RATED_TDP actions - these are the requested actions clients can
* make to change the behavior of the RATED_TDP functionality.
*/
typedef enum NV2080_CTRL_PERF_RATED_TDP_ACTION {
/*!
* The default action - meaning no explicit request from the client other
* than to take the default behavior (allowing boosting above RATED_TDP) or
* any explicit actions from lower priority clients.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = 0,
/*!
* Force allow boosting above RATED_TDP - this action explicitly requests
* boosting above RATED_TDP, preventing lower priority clients to limit to
* RATED_TDP.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = 1,
/*!
* Force to limit above RATED_TDP - this action explicitly requests to limit
* to RATED_TDP. This is the opposite of the default behavior to allow
* boosting above RATED_TDP. Clients specify this action when they
* explicitly need boost to be disabled (e.g. eliminating perf variation,
* special apps which exhibit bad behavior, etc.).
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = 2,
/*!
* Lock to RATED_TDP - this action requests the clocks to be fixed at the
* RATED_TDP. Used for achieving stable clocks required for profiling.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = 3,
/*!
* Lock to Min TDP - This requests min to be fixed at RATED_TDP but allow
* boosting for max
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = 4,
} NV2080_CTRL_PERF_RATED_TDP_ACTION;
/*!
* Structure describing dynamic state of the RATED_TDP feature.
*/
#define NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID (0x6DU)
typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS {
/*!
* Structure of internal RM state - these values are used to determine the
* behavior of NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM per the RM's @ref
* perfPwrRatedTdpLimitRegisterClientActive() interface.
*/
struct {
/*!
* [out] - Mask of active client controllers (@ref
* PERF_PWR_RATED_TDP_CLIENT) which are currently regulating TDP. When
* this mask is zero, NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
*/
NvU32 clientActiveMask;
/*!
* [out] - Boolean indicating that user has requested locking to
* RATED_TDP vPstate via corresponding regkey
* NV_REG_STR_RM_PERF_RATED_TDP_LIMIT. When the boolean value is true,
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
*/
NvU8 bRegkeyLimitRatedTdp;
} rm;
/*!
* [out] - Arbitrated output action of all client requests (@ref inputs).
* This is the current state of the RATED_TDP feature. Will only be @ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED or @ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION output;
/*!
* [out] - Array of input client request actions, indexed via @ref
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_<xyz>. RM will arbitrate between these
* requests, choosing the highest priority request != @ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS];
} NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS;
/*!
* NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL
*
* This command retrieves the current requested RATED_TDP action corresponding
* to the specified client.
*
* See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of
* parameters.
*
* Possible status values returned are
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6E" */
/*!
* NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL
*
* This command sets the requested RATED_TDP action corresponding to the
* specified client. @Note, however, that this command is unable to set @ref
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM.
*
* See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of
* parameters.
*
* Possible status values returned are
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6F" */
/*!
* Structure containing the requested action for a RATED_TDP client (@ref
* NV2080_CTRL_PERF_RATED_TDP_CLIENT).
*/
typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS {
/*!
* [in] - Specified client for request.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT client;
/*!
* [in/out] - Client's requested action.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION input;
} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS;
/*!
* This struct represents the GPU monitoring perfmon sample for an engine.
*/
typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE {
/*!
* Percentage during the sample that the engine remains busy. This
* is in units of pct*100.
*/
NvU32 util;
/*!
* Scaling factor to convert utilization from full GPU to per vGPU.
*/
NvU32 vgpuScale;
/*!
* Process ID of the process that was active on the engine when the
* sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID
* will be returned.
*/
NvU32 procId;
/*!
* Process ID of the process in the vGPU VM that was active on the engine when
* the sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID
* will be returned.
*/
NvU32 subProcessID;
/*!
* Process name of the process in the vGPU VM that was active on the engine when
* the sample was taken. If no process is active then NULL will be returned.
*/
char subProcessName[NV_SUBPROC_NAME_MAX_LENGTH];
} NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE;
/*!
* This struct represents the GPU monitoring perfmon sample.
*/
typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE {
/*!
* Base GPU monitoring sample.
*/
NV_DECLARE_ALIGNED(NV2080_CTRL_GPUMON_SAMPLE base, 8);
/*!
* FB bandwidth utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb;
/*!
* GR utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr;
/*!
* NV ENCODER utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc;
/*!
* NV DECODER utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec;
} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE;
/*!
* This struct represents the GPU monitoring samples of perfmon values that
* client wants the access to.
*/
#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID (0x83U)
typedef NV2080_CTRL_GPUMON_SAMPLES NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM;
/*!
* Number of GPU monitoring sample in their respective buffers.
*/
#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 100
#define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE \
NV_SIZEOF32(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \
NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL
/*!
* NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2
*
* This command returns perfmon gpu monitoring utilization samples.
* This command is not supported with SMC enabled.
*
* See NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_V2 for documentation
* on the parameters.
*
* Possible status values returned are
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*
* Note this is the same as NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES
* but without the embedded pointer.
*
*/
#define NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 (0x20802096) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID" */
/*!
* This structure represents the GPU monitoring samples of utilization values that
* the client wants access to.
*/
#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID (0x96U)
typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS {
/*!
* Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference.
*/
NvU8 type;
/*!
* Size of the buffer, this should be
* bufSize == NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_*
* sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE).
*/
NvU32 bufSize;
/*!
* Number of samples in ring buffer.
*/
NvU32 count;
/*!
* tracks the offset of the tail in the circular queue array pSamples.
*/
NvU32 tracker;
/*!
* A circular queue with size == bufSize.
*
* @note This circular queue wraps around after 10 seconds of sampling,
* and it is clients' responsibility to query within this time frame in
* order to avoid losing samples.
* @note With one exception, this queue contains last 10 seconds of samples
* with tracker poiniting to oldest entry and entry before tracker as the
* newest entry. Exception is when queue is not full (i.e. tracker is
* pointing to a zeroed out entry), in that case valid entries are between 0
* and tracker.
* @note Clients can store tracker from previous query in order to provide
* samples since last read.
*/
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL], 8);
} NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_GPU_IS_IDLE
*
* This command notifies RM to make p state switching aggressive by setting
* required limiting factors to speed up GC6 Entry initiation.
*
* prevPstate [out]
* This parameter will contain the pstate before the switch was initiated
*
* Possible status return values are:
* NV_OK : If P State Switch is successful
* NV_INVALID_STATE : If unable to access P State structure
* NVOS_STATUS_ERROR : If P State Switch is unsuccessful
*/
#define NV2080_CTRL_CMD_PERF_GPU_IS_IDLE (0x20802089) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS {
NvU32 prevPstate;
NvU32 action;
} NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS;
#define NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE (0x00000001)
#define NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE (0x00000002)
/*
* NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY
*
* This command is for the KMD Aggressive P-state feature.
*
* bGpuIsIdle [in]
* When true, applies cap to lowest P-state/GPCCLK. When false, releases cap.
* idleTimeUs [in]
* The amount of time (in microseconds) the GPU was idle since previous
* call, part of the GPU utilization data from KMD.
* busyTimeUs [in]
* The amount of time (in microseconds) the GPU was not idle since
* previous call, part of the GPU utilization data from KMD.
*
* Possible status return values are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY (0x2080208f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID (0x8FU)
typedef struct NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS {
NvBool bGpuIsIdle;
NvBool bRestoreToMax;
NV_DECLARE_ALIGNED(NvU64 idleTimeUs, 8);
NV_DECLARE_ALIGNED(NvU64 busyTimeUs, 8);
} NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS;
/* _ctrl2080perf_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn
//
/* _ctrl2080perf_cf_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080power.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080rc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*
* NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM
*
* This command returns data read from the specified virtual memory address for
* the associated subdevice.
*
* hChannel
* This parameter specifies the channel object handle from which the virtual
* memory range applies.
* virtAddress
* This parameter specifies the GPU base virtual memory address from which data should
* be read. The amount of data read is specified by the bufferSize parameter.
* bufferPtr
* This parameter specifies the buffer address in the caller's address space into which
* the data is to be returned. The address must be aligned on an 8-byte boundary.
* The buffer must be at least as big as the value specified bufferSize parameter (in bytes).
* bufferSize
* This parameter specifies the size of the buffer referenced by the bufferPtr parameter.
* This parameter also indicates the total number of bytes to be returned.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_XLATE
*/
#define NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS {
NvHandle hChannel;
NV_DECLARE_ALIGNED(NvU64 virtAddress, 8);
NV_DECLARE_ALIGNED(NvP64 bufferPtr, 8);
NvU32 bufferSize;
} NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS;
#define NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM (0x20802204) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_RC_GET_ERROR_COUNT
*
* This command returns the number of RC errors.
*
* errorCount
* Number of RC errors.
*
* Note: If SMC is enabled, mig/monitor capability must be acquired to query
* aggregate information. Otherwise, the control call returns
* NV_ERR_INSUFFICIENT_PERMISSIONS.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INSUFFICIENT_PERMISSIONS.
*/
#define NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS {
NvU32 errorCount;
} NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS;
#define NV2080_CTRL_CMD_RC_GET_ERROR_COUNT (0x20802205) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE (0x2000) /* finn: Evaluated from "(8 * 1024)" */
#define NV2080_CTRL_CMD_RC_GET_ERROR (0x20802206) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x6" */
/*
* NV2080_CTRL_CMD_RC_GET_ERROR_V2
*
* This command returns an error element in the RC error list.
*
* whichBuffer
* Which Error to return (0 is oldest)
* outputRecordSize
* Output Size of Buffer -- Zero if error record doesn't exist
* recordBuffer
* buffer
*
* Note: If SMC is enabled, mig/monitor capability must be acquired to query
* aggregate information. Otherwise, the control call returns
* NV_ERR_INSUFFICIENT_PERMISSIONS.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INSUFFICIENT_PERMISSIONS.
*
*/
#define NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV2080_CTRL_RC_GET_ERROR_V2_PARAMS {
NvU32 whichBuffer; // [IN] - which error to return (0 is oldest)
NvU32 outputRecordSize; // [OUT]
NvU8 recordBuffer[NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE];
} NV2080_CTRL_RC_GET_ERROR_V2_PARAMS;
#define NV2080_CTRL_CMD_RC_GET_ERROR_V2 (0x20802213) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY
*
* This command cleans error history.
*
* This command has no input parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY (0x20802207) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x7" */
/*
* NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO
*
* This command returns information about the RC watchdog.
*
* watchdogStatusFlags
* This output parameter is a combination of one or more of the following:
*
* NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE
* This is the value of watchdogStatusFlags if no flags are set.
*
* NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED
* This means that the watchdog is disabled.
*
* NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING
* This means that the watchdog is running.
*
* NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED
* This means that the watchdog has been initialized.
*
* A typical result would be either "running and initialized", or
* "disabled". However, "initialized, but not running, and not disabled"
* is also quite reasonable (if the computer is hibernating, for example).
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS {
NvU32 watchdogStatusFlags;
} NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS;
#define NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO (0x20802209) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID" */
/* valid values for watchdogStatusFlags */
#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE (0x00000000)
#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED (0x00000001)
#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING (0x00000002)
#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED (0x00000004)
/*
* NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG
*
* This command disables the RC watchdog, if possible.
* If, however, another RM client has already explicitly (via NV2080 call) enabled
* the RC watchdog, then this method returns NV_ERR_STATE_IN_USE.
*
* This command, if successful, will prevent other clients from enabling the
* watchdog until the calling RM client releases its request with
* NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS or frees its NV20_SUBDEVICE.
*
* See NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG for disabling the watchdog
* without preventing other clients from enabling it.
*
* Possible status return values are:
* NV_OK
* NV_ERR_STATE_IN_USE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG (0x2080220a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xA" */
/*
* NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG
*
* This command enables the RC watchdog, if possible.
* If, however, another RM client has already explicitly (via NV2080 call) disabled
* the RC watchdog, then this method returns NV_ERR_STATE_IN_USE.
*
* Possible status return values are:
* NV_OK
* NV_ERR_STATE_IN_USE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG (0x2080220b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xB" */
/*
* NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS
*
* This command releases all of the RM client's outstanding requests to enable
* or disable the watchdog.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS (0x2080220c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xC" */
/*
* NV2080_CTRL_CMD_SET_RC_RECOVERY/NV2080_CTRL_CMD_GET_RC_RECOVERY
*
* This command disables/enables RC recovery.
*
* rcEnable
* NV2080_CTRL_CMD_SET_RC_RECOVERY_DISABLED
* Disable robust channel recovery.
*
* NV2080_CTRL_CMD_SET_RC_RECOVERY_ENABLED
* Enable robust channel recovery with default breakpoint handling.
*
* Possible status return values are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
typedef struct NV2080_CTRL_CMD_RC_RECOVERY_PARAMS {
NvU32 rcEnable;
} NV2080_CTRL_CMD_RC_RECOVERY_PARAMS;
#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xD" */
#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xE" */
/* valid values for rcEnable */
#define NV2080_CTRL_CMD_RC_RECOVERY_DISABLED (0x00000000)
#define NV2080_CTRL_CMD_RC_RECOVERY_ENABLED (0x00000001)
/*
* NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE
*
* This command can be used to set TDR timeout state.
*
* It can be used to indicate that a timeout has occurred and that a GPU
* reset will start. It can also be used to indicate that the reset has
* completed along with the corresponding complition status.
*
* cmd
* This parameter is used to indicate the stage of the TDR recovery
* process. Legal values for this parameter are:
* NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN
* This value indicates that TDR recovery is about to begin.
* NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END
* This value indicates that TDR recovery has completed.
*
* status
* This parameter is valid when the cmd parameter is set to
* NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END. It is used
* to specify the completion status of the TDR recovery. Legal
* values for this parameter include:
* NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL
* This value indicates the recovery failed.
* NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS
* This value indicates the recovery succeeded.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_COMMAND
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE (0x2080220f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID (0xFU)
typedef struct NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS {
NvU32 cmd;
NvS32 status;
} NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS;
/* valid cmd values */
#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN (0x00000000)
#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END (0x00000001)
/* valid status values */
#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS (0x00000000)
#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL (0x00000001)
/*
* NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG
*
* This command disables the RC watchdog, similarly to how
* NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG does. However, unlike that command, this
* command will not prevent another RM client from explicitly enabling the RC
* watchdog with NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG.
*
* Possible status return values are:
* NV_OK
* NV_ERR_STATE_IN_USE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG (0x20802210) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x10" */
/*
* NV2080_CTRL_CMD_GET_RC_INFO/NV2080_CTRL_CMD_SET_RC_INFO
*
* This command can be used to set robust channel parameters.
*
* rcMode
* NV2080_CTRL_CMD_SET_RC_INFO_MODE_DISABLE
* Disable robust channel operation.
*
* NV2080_CTRL_CMD_SET_RC_INFO_MODE_ENABLE
* Enable robust channel operation.
*
* rcBreak
* NV2080_CTRL_CMD_SET_RC_INFO_BREAK_DISABLE
* Disable breakpoint handling during robust channel operation.
*
* NV2080_CTRL_CMD_SET_RC_INFO_BREAK_ENABLE
* Enable breakpoint handling during robust channel operation.
*
* Possible status return values are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
typedef struct NV2080_CTRL_CMD_RC_INFO_PARAMS {
NvU32 rcMode;
NvU32 rcBreak;
} NV2080_CTRL_CMD_RC_INFO_PARAMS;
#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x11" */
#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x12" */
/* valid rcMode values */
#define NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE (0x00000000)
#define NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE (0x00000001)
/* valid rcBreak values */
#define NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE (0x00000000)
#define NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE (0x00000001)
/* _ctrl2080rc_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080spi.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080thermal.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080tmr.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_TIMER related control commands and parameters */
/*
* NV2080_CTRL_CMD_TIMER_SCHEDULE
*
* This command schedules a GPU timer event to fire at the specified time interval.
* Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and
* NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags
*
* time_nsec
* This parameter specifies the time in nanoseconds at which the GPU timer
* event is to fire.
* flags
* This parameter determines the interpretation of the value specified by
* the time_nsec parameter:
* NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS
* This flag indicates that time_nsec is in absolute time.
* NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL
* This flag indicates that time_nsec is in relative time.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_TIMER_SCHEDULE (0x20800401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 time_nsec, 8);
NvU32 flags;
} NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS;
/* valid flag values */
#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME 0:0
#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS (0x00000000)
#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL (0x00000001)
/*
* NV2080_CTRL_CMD_TIMER_CANCEL
*
* This command cancels any pending timer events initiated with the
* NV2080_CTRL_CMD_TIMER_SCHEDULE command.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_TIMER_CANCEL (0x20800402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | 0x2" */
/*
* NV2080_CTRL_CMD_TIMER_GET_TIME
*
* This command returns the current GPU timer value. The current time is
* expressed in elapsed nanoseconds since 00:00 GMT, January 1, 1970
* (zero hour) with a resolution of 32 nanoseconds.
*
* Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and
* NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_TIMER_GET_TIME (0x20800403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_TIMER_GET_TIME_PARAMS {
NV_DECLARE_ALIGNED(NvU64 time_nsec, 8);
} NV2080_CTRL_TIMER_GET_TIME_PARAMS;
/*
* NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET
*
* The command returns the offset of the timer registers, so that clients may
* map them directly.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET (0x20800404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS {
NvU32 tmr_offset;
} NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS;
/*
* NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE
*
* This structure describes the information obtained with
* NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO command.
*
* gpuTime
* GPU time is the value of GPU global timer (PTIMER) with a resolution
* of 32 nano seconds.
* cpuTime
* CPU time. Resolution of the cpu time depends on its source. Refer to
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_* for more information.
*/
typedef struct NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE {
NV_DECLARE_ALIGNED(NvU64 cpuTime, 8);
NV_DECLARE_ALIGNED(NvU64 gpuTime, 8);
} NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE;
/*
* NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO
*
* This command returns correlation information between GPU time and CPU time
* for a given CPU clock type.
*
* cpuClkId
* This parameter specifies the source of the CPU clock. Legal values for
* this parameter include:
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME
* This clock id will provide real time in microseconds since
* 00:00:00 UTC on January 1, 1970.
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API
* This clock id will provide time stamp that is constant-rate, high
* precision using platform API that is also available in the user mode.
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC
* This clock id will provide time stamp using CPU's time stamp counter.
*
* sampleCount
* This field specifies the number of clock samples to be taken.
* This value cannot exceed NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES.
*
* samples
* This field returns an array of requested samples. Refer to
* NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE to get details about each entry
* in the array.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO (0x20800406) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES 16
#define NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS {
NvU8 cpuClkId;
NvU8 sampleCount;
NV_DECLARE_ALIGNED(NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE samples[NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES], 8);
} NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS;
/* Legal cpuClkId values */
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME (0x00000001)
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC (0x00000002)
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API (0x00000003)
/*!
* NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ
*
* This command changes the frequency at which Graphics Engine time stamp is
* updated. Frequency can either be set to max or restored to default.
* Clients can independently use this call to increase the timer frequency
* as a global reference count is maintained for requests to Max frequency.
* Client is assured that the system stays in this state till the requested
* client releases the state or is killed. Timer frequency will automatically
* be restored to default when there is no pending request to increase.
*
* Note that recursive requests for the same state from the same client
* are considered invalid.
*
* bSetMaxFreq
* Set to NV_TRUE if GR tick frequency needs to be set to Max.
*
* See @ref NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS for
* documentation of parameters.
*
* Possible status values returned are
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_STATE_IN_USE
* NV_ERR_INVALID_OPERATION
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */
/*!
* This struct contains bSetMaxFreq flag.
*/
#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS {
NvBool bSetMaxFreq;
} NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS;
/* _ctrl2080tmr_h_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080ucodefuzzer.finn
//

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080unix.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX OS control commands and parameters */
/*
* NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT
*
* This command increases or decreases the value of the per-GPU GC6 blocker
* refCount used by Linux kernel clients to prevent the GPU from entering GC6.
*
* When the refCount is non-zero, the GPU cannot enter GC6. When the refCount
* transitions from zero to non-zero as a result of this command, the GPU will
* automatically come out of GC6.
*
* action Whether to increment or decrement the value of the refCount.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT (0x20803d01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS {
NvU32 action;
} NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS;
// Possible values for action
#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC (0x00000001)
#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC (0x00000002)
/*
* NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF
*
* RM by default allows GCOFF but when the X driver disallows to enter in GCOFF
* then this rmcontrol sets flag as NV_FALSE and if it allows to enter in GCOFF
* then the flag is set as NV_TRUE.
*
* action Whether to allow or disallow the user mode clients to enter in GCOFF.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF (0x20803d02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS {
NvU32 action;
} NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS;
// Possible values for action
#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW (0x00000001)
#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW (0x00000002)
/*
* NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER
*
* GPU can have integrated HDA (High Definition Audio) controller which
* can be in active or suspended state during dynamic power management.
* This command will perform HDA controller wakeup (if bEnter is false) or
* suspend (if bEnter is true).
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER (0x20803d03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS {
NvBool bEnter;
} NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS;
/*
* NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS
*
* Initialize cyclestats HWPM support in the kernel. This will set up a callback
* event for the channel indicated by hNotifierResource. This callback will execute
* perf register read / write commands enqueued in the shared buffer indicated by
* hNotifyDataMemory. Only one client may use HWPM functionality at a time.
*
* Additionally, if perfmonIdCount is greater than zero, mode-e HWPM streaming into
* the buffer indicated by hSnapshotMemory will be initialized (but not turned on).
* Data will be copied into the provided buffer every 10ms, or whenever a
* NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER command is issued.
*/
#define NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS (0x20803d04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS {
NvHandle hNotifierResource;
NvU32 notifyDataSize;
NvHandle hNotifyDataMemory;
NvU32 perfmonIdCount;
NvU32 snapshotBufferSize;
NvHandle hSnapshotMemory;
} NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS;
/*
* NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER
*
* Immediately copies any pending mode-e HWPM data into the previously
* installed snapshot buffer instead of waiting for the timer.
*/
#define NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER (0x20803d05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x5" */
/*
* NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER
*
* Stop the timer responsible for copying mode-e HWPM data to the snapshot buffer.
* The snapshot buffer must not be freed by the client before this command is issued.
*/
#define NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER (0x20803d06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x6" */
/*
* NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS
*
* This command will be used by clients to check if the GPU video memory will
* be persistent during system suspend/resume cycle.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS (0x20803d07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS {
NvBool bVidmemPersistent;
} NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS
*
* This command will be used by clients to set restore TGP flag which will
* help to restore TGP limits when clients are destroyed.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS (0x20803d08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS {
NvBool bUpdateTGP;
} NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS;
/* _ctrl2080unix_h_ */

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