NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-03-04 20:59:50 +00:00
Code Issues Packages Projects Releases Wiki Activity

515.43.04

Browse Source
This commit is contained in:
Andy Ritger
2022-05-09 13:18:59 -07:00
commit 1739a20efc
2519 changed files with 1060036 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

76
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h Normal file
View File

@@ -0,0 +1,76 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV01_DEVICE_XX/NV03_DEVICE control commands and parameters */
#define NV0080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0080, NV0080_CTRL_##cat, idx)
/* GPU device command categories (6bits) */
#define NV0080_CTRL_RESERVED (0x00)
#define NV0080_CTRL_BIF (0x01)
#define NV0080_CTRL_GPU (0x02)
#define NV0080_CTRL_CLK (0x10)
#define NV0080_CTRL_GR (0x11)
#define NV0080_CTRL_CIPHER (0x12)
#define NV0080_CTRL_FB (0x13)
#define NV0080_CTRL_HOST (0x14)
#define NV0080_CTRL_VIDEO (0x15)
#define NV0080_CTRL_FIFO (0x17)
#define NV0080_CTRL_DMA (0x18)
#define NV0080_CTRL_PERF (0x19)
#define NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED (0x99) /* finn: Evaluated from "(NV0080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV0080_CTRL_MSENC (0x1B)
#define NV0080_CTRL_BSP (0x1C)
#define NV0080_CTRL_RC (0x1D)
#define NV0080_CTRL_OS_UNIX (0x1E)
#define NV0080_CTRL_NVJPG (0x1F)
#define NV0080_CTRL_INTERNAL (0x20)
#define NV0080_CTRL_NVLINK (0x21)
/*
* NV0080_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_CMD_NULL (0x800000) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */
/* _ctrl0080base_h_ */
/* extract device cap setting from specified category-specific caps table */
#define NV0080_CTRL_GET_CAP(cat,tbl,c) \
NV0080_CTRL_##cat##_GET_CAP(tbl, NV0080_CTRL_##cat##_CAPS_##c)

121
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h Normal file
View File

@@ -0,0 +1,121 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080bif.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/*
* NV0080_CTRL_CMD_BIF_RESET
*
* This command initiates the specified reset type on the GPU.
*
* flags
* Specifies various arguments to the reset operation.
*
* Supported fields include:
*
* NV0080_CTRL_BIF_RESET_FLAGS_TYPE
* When set to _SW_RESET, a SW (fullchip) reset is performed. When set
* to _SBR, a secondary-bus reset is performed. When set to
* _FUNDAMENTAL, a fundamental reset is performed.
*
* NOTE: _FUNDAMENTAL is not yet supported.
*
* Possible status return values are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_BIF_RESET (0x800102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_BIF_RESET_PARAMS {
NvU32 flags;
} NV0080_CTRL_BIF_RESET_PARAMS;
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 2:0
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET (0x00000001)
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR (0x00000002)
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL (0x00000003)
/*
* NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR
*
* baseDmaSysmemAddr
* This parameter represents the base DMA address for sysmem which will be
* added to all DMA accesses issued by GPU. Currently GPUs do not support 64-bit physical address,
* hence if sysmem is greater than max GPU supported physical address width, this address
* will be non-zero
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_OBJECT_PARENT
*/
#define NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR (0x800103) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS {
NV_DECLARE_ALIGNED(NvU64 baseDmaSysmemAddr, 8);
} NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS;
/*
* NV0080_CTRL_BIF_SET_ASPM_FEATURE
*
* aspmFeatureSupported
* ASPM feature override by client
*
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE (0x800104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS {
NvU32 aspmFeatureSupported;
} NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS;
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S 0:0
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED 0x000000001
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED 0x000000000
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1 1:1
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED 0x000000001
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED 0x000000000
/* _ctrl0080bif_h_ */

114
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h Normal file
View File

@@ -0,0 +1,114 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080bsp.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE bit stream processor control commands and parameters */
/*
* NV0080_CTRL_CMD_BSP_GET_CAPS
*
* This command returns the set of BSP capabilities for the device
* in the form of an array of unsigned bytes. BSP capabilities
* include supported features and required workarounds for the decoder
* within the device, each represented by a byte offset into the
* table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_BSP_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the BSP caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
* instanceId
* This parameter specifies the instance Id of NVDEC for which
* cap bits are requested.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_BSP_GET_CAPS (0x801c01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BSP_INTERFACE_ID << 8) | NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_BSP_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
NvU32 instanceId;
} NV0080_CTRL_BSP_GET_CAPS_PARAMS;
/*
* Size in bytes of bsp caps table. This value should be one greater
* than the largest byte_index value above.
*/
#define NV0080_CTRL_BSP_CAPS_TBL_SIZE 8
/*
* NV0080_CTRL_CMD_BSP_GET_CAPS_V2
*
* This command returns the set of BSP capabilities for the device
* in the form of an array of unsigned bytes. BSP capabilities
* include supported features and required workarounds for the decoder
* within the device, each represented by a byte offset into the
* table and a bit position within that byte.
* (The V2 version flattens the capsTbl array pointer).
*
* capsTbl
* This parameter is an array of unsigned bytes where the BSP caps bits
* will be transferred by the RM.
* instanceId
* This parameter specifies the instance Id of NVDEC for which
* cap bits are requested.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_BSP_GET_CAPS_V2 (0x801c02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BSP_INTERFACE_ID << 8) | NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID" */
#define NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 {
NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE];
NvU32 instanceId;
} NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2;
/* _ctrl0080bsp_h_ */

32
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080cipher.finn
//

32
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080clk.finn
//

911
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h Normal file
View File

@@ -0,0 +1,911 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080dma.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE dma control commands and parameters */
/*
* NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK
*
* This parameter returns the parameters specific to a PTE as follows:
* pageSize
* GET: This parameter returns the page size of the PTE information
* being returned. If 0, then this pteBlock[] array entry is
* invalid or not used. (pteBlock[0] is always used.)
* SET: This parameter specifies the page size of the PTE information
* to be set. If 0, then this pteBlock[] array entry is invalid
* or not used. (pteBlock[0] is always used.)
* pteEntrySize
* GET: This parameter returns the size of the PTE in bytes for this GPU.
* SET: N/A
* comptagLine
* GET: This parameter returns the comptagline field of the corresponding PTE.
* SET: This parameter sets the comptagline field of the corresponding PTE.
* Incorrect values may lead to dire consequences.
* kind
* GET: This parameter returns the kind field of the corresponding PTE.
* SET: This parameter sets the kind field of the corresponding PTE.
* Incorrect values may lead to undesirable consequences.
* pteFlags
* This parameter returns various fields from the PTE, these are:
* FLAGS_VALID:
* GET: This flag returns the valid bit of the PTE.
* SET: This flag sets the valid bit of the PTE.
* FLAGS_ENCRYPTED:
* GET: This flag returns the encrypted bit of the PTE. Not all GPUs
* support encryption. If not supported, this flag will be set to
* NOT_SUPPORTED.
* SET: This flag sets the encrypted bit of the PTE.
* FLAGS_APERTURE:
* GET: This flag returns the aperture field of the PTE. See
* NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_FLAGS_APERTURE_* for values.
* SET: This flag sets the aperture field of the PTE. See
* NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_FLAGS_APERTURE_* for values.
* FLAGS_COMPTAGS:
* GET: This flag returns the comptags field of the PTE. (Not used on Fermi)
* SET: N/A
* FLAGS_GPU_CACHED:
* GET: This flag returns the GPU cacheable bit of the PTE. GPU caching of
* sysmem was added in iGT21a and Fermi. If not supported, this flag
* will be set to NOT_SUPPORTED.
* SET: N/A for specific chips, e.g., GF100
* FLAGS_SHADER_ACCESS:
* GET: This flag returns the shader access control of the PTE. This feature
* was introduced in Kepler. If not supported, this flag will be set to
* NOT_SUPPORTED.
* SET: N/A
*/
typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK {
NvU32 pageSize;
NV_DECLARE_ALIGNED(NvU64 pteEntrySize, 8);
NvU32 comptagLine;
NvU32 kind;
NvU32 pteFlags;
} NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK;
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID 0:0
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED 2:1
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED (0x00000002U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE 6:3
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY (0x00000002U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY (0x00000003U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS 10:7
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1 (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2 (0x00000002U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4 (0x00000004U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED 12:11
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED (0x00000002U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS 14:13
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY (0x00000002U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED (0x00000003U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY 15:15
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC 16:16
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING 17:17
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE (0x00000001U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED 18:18
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE (0x00000001U)
/*
* NV0080_CTRL_DMA_GET_PTE_INFO
*
* This command queries PTE information for the specified GPU virtual address.
*
* gpuAddr
* This parameter specifies the GPU virtual address for which PTE
* information is to be returned.
* skipVASpaceInit
* This parameter specifies(true/false) whether the VA Space
* initialization should be skipped in this ctrl call.
* pteBlocks
* This parameter returns the page size-specific attributes of a PTE.
* Please see NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK.
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
* NV_ERR_GENERIC
*/
#define NV0080_CTRL_CMD_DMA_GET_PTE_INFO (0x801801U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS 4U
#define NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8);
NvU32 subDeviceId;
NvU8 skipVASpaceInit;
NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS], 8);
NvHandle hVASpace;
} NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS;
/*
* NV0080_CTRL_DMA_SET_PTE_INFO
*
* This command sets PTE information for the specified GPU virtual address.
* Usage of parameter and field definitions is identical to that of
* NV0080_CTRL_DMA_GET_PTE_INFO, with the following exception:
*
* - pteFlags field NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS is ignored,
* as this setting is specified via the kind specification.
* - pteEntrySize is ignored, as this setting is read-only in the GET case.
* - hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space.
*
*/
#define NV0080_CTRL_CMD_DMA_SET_PTE_INFO (0x80180aU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS 4U
#define NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8);
NvU32 subDeviceId;
NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS], 8);
NvHandle hVASpace;
} NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS;
#define NV0080_CTRL_CMD_DMA_FILL_PTE_MEM (0x801802U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS {
NvU32 pageCount;
struct {
NvHandle hClient;
NvHandle hDevice;
NvHandle hMemory;
NvU32 subDeviceId;
} hwResource;
struct {
NvU32 fbKind;
NvU32 sysKind;
NvU32 compTagStartOffset;
} comprInfo;
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8);
NV_DECLARE_ALIGNED(NvP64 pageArray, 8);
NV_DECLARE_ALIGNED(NvP64 pteMem, 8);
NvU32 pteMemPfn;
NvU32 pageSize;
NvU32 startPageIndex;
NvU32 flags;
NvHandle hSrcVASpace;
NvHandle hTgtVASpace;
NvU32 peerId;
} NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS;
/*
* NV0080_CTRL_DMA_FLUSH
*
* This command flushes the specified target unit
*
* targetUnit
* The unit to flush, either L2 cache or compression tag cache.
* This field is a logical OR of the individual fields such as
* L2 cache or compression tag cache. Also L2 invalidation for
* either SYSMEM/PEERMEM is triggered. But this invalidation is
* for FERMI.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*
* See Also:
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
* Flushes the entire GPU cache or a set of physical addresses (if the
* hardware supports it). Use this call if you want to flush a set of
* addresses or the entire GPU cache in unicast mode.
* NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE
* Flushes memory associated with a single allocation if the hardware
* supports it. Use this call if you want to flush a single allocation and
* you have a memory object describing the physical memory.
*/
#define NV0080_CTRL_CMD_DMA_FLUSH (0x801805U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0080_CTRL_DMA_FLUSH_PARAMS {
NvU32 targetUnit;
} NV0080_CTRL_DMA_FLUSH_PARAMS;
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2 0:0
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE (0x00000000U)
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE (0x00000001U)
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG 1:1
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE (0x00000000U)
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE (0x00000001U)
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB 2:2
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE (0x00000000U)
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE (0x00000001U)
// This is exclusively for Fermi
// The selection of non-zero valued bit-fields avoids the routing
// into the above cases and vice-versa
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE 4:3
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM (0x00000001U)
#define NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM (0x00000002U)
/**
* NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS
*
* This command returns information about the VA caps on the GPU
*
* vaBitCount
* Returns number of bits in a virtual address
* pdeCoverageBitCount
* Returns number of VA bits covered in each PDE. One PDE covers
* 2^pdeCoverageBitCount bytes.
*
* bigPageSize
* Size of the big page
* compressionPageSize
* Size of region each compression tag covers
* dualPageTableSupported
* TRUE if one page table can map with both 4KB and big pages
*
* numPageTableFormats
* Returns the number of different page table sizes supported by the RM
* pageTableBigFormat
* pageTable4KFormat[]
* Returns size in bytes and number of VA bits covered by each page table
* format. Up to MAX_NUM_PAGE_TABLE_FORMATS can be returned. The most
* compact format will be pageTableSize[0] and the least compact format
* will be last.
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space.
* vaRangeLo
* Indicates the start of usable VA range.
*
* hugePageSize
* Size of the huge page if supported, 0 otherwise.
*
* vaSpaceId
* Virtual Address Space id assigned by RM.
* Only relevant on AMODEL.
*
* pageSize512MB
* Size of the 512MB page if supported, 0 otherwise.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS (0x801806U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID" */
typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT {
NvU32 pageTableSize;
NvU32 pageTableCoverage;
} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT;
#define NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS (16U)
#define NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS {
NvU32 vaBitCount;
NvU32 pdeCoverageBitCount;
NvU32 num4KPageTableFormats;
NvU32 bigPageSize;
NvU32 compressionPageSize;
NvU32 dualPageTableSupported;
NvU32 idealVRAMPageSize;
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTableBigFormat;
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTable4KFormat[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS];
NvHandle hVASpace;
NV_DECLARE_ALIGNED(NvU64 vaRangeLo, 8);
NvU32 hugePageSize;
NvU32 vaSpaceId;
NvU32 pageSize512MB;
} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS;
/*
* Adding a version define to allow clients to access valid
* parameters based on version.
*/
#define NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO 0x1U
/*
* NV0080_CTRL_DMA_GET_PDE_INFO
*
* This command queries PDE information for the specified GPU virtual address.
*
* gpuAddr
* This parameter specifies the GPU virtual address for which PDE
* information is to be returned.
* pdeVirtAddr
* This parameter returns the GPU virtual address of the PDE.
* pdeEntrySize
* This parameter returns the size of the PDE in bytes for this GPU.
* pdeAddrSpace
* This parameter returns the GPU address space of the PDE.
* pdeSize
* This parameter returns the fractional size of the page table(s) as
* actually set in the PDE, FULL, 1/2, 1/4 or 1/8. (This amount may
* differ from that derived from pdeVASpaceSize.) Intended for VERIF only.
* pteBlocks
* This parameter returns the page size-specific parameters as follows:
* ptePhysAddr
* This parameter returns the GPU physical address of the page table.
* pteCacheAttrib
* This parameter returns the caching attribute of the
* GPU physical address of the page table.
* pteEntrySize
* This parameter returns the size of the PTE in bytes for this GPU.
* pageSize
* This parameter returns the page size of the page table.
* If pageSize == 0, then this PTE block is not valid.
* pteAddrSpace
* This parameter returns the GPU address space of the page table.
* pdeVASpaceSize
* This parameter returns the size of the VA space addressable by
* the page table if fully used (i.e., if all PTEs marked VALID).
* pdbAddr
* This parameter returns the PDB address for the PDE.
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV0080_CTRL_CMD_DMA_GET_PDE_INFO (0x801809U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID" */
typedef struct NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK {
NV_DECLARE_ALIGNED(NvU64 ptePhysAddr, 8);
NvU32 pteCacheAttrib;
NvU32 pteEntrySize;
NvU32 pageSize;
NvU32 pteAddrSpace;
NvU32 pdeVASpaceSize;
NvU32 pdeFlags;
} NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK;
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY (0x00000000U)
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U)
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U)
#define NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS 4U
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 gpuAddr, 8);
NV_DECLARE_ALIGNED(NvU64 pdeVirtAddr, 8);
NvU32 pdeEntrySize;
NvU32 pdeAddrSpace;
NvU32 pdeSize;
NvU32 subDeviceId;
NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK pteBlocks[NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS], 8);
NV_DECLARE_ALIGNED(NvU64 pdbAddr, 8);
NvHandle hVASpace;
} NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS;
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY (0x00000000U)
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U)
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U)
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL 1U
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF 2U
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER 3U
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH 4U
/*
* NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET
*
* This command invalidates PDB target setting in hardware.
* After execeution of this command PDB target would be in undefined state.
*
* Returns error if the PDB target can not be invalidate.
*
* This call is only supported on chips fermi and later chips.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET (0x80180bU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | 0xB" */
/*
* NV0080_CTRL_CMD_DMA_INVALIDATE_TLB
*
* This command invalidates the GPU TLB. This is intended to be used
* for RM clients that manage their own TLB consistency when updating
* page tables on their own, or with DEFER_TLB_INVALIDATION options
* to other RM APIs.
*
* hVASpace
* This parameter specifies the VASpace object whose MMU TLB entries
* needs to be invalidated, if the flag is set to NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE.
* Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace.
* Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC.
*
* flags
* This parameter can be used to specify any flags needed
* for the invlalidation request.
* NV0080_CTRL_DMA_INVALIDATE_TLB_ALL
* When set to TRUE this flag requests a global invalidate.
* When set to FALSE this flag requests a chip-specfic
* optimization to invalidate only the address space bound
* to the associated hDevice.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_TIMEOUT_RETRY
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_DMA_INVALIDATE_TLB (0x80180cU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS {
NvHandle hVASpace;
NvU32 flags;
} NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS;
#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL 0:0
#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE (0x00000001U)
/**
* NV0080_CTRL_CMD_DMA_GET_CAPS
*
* This command returns the set of DMA capabilities for the device
* in the form of an array of unsigned bytes. DMA capabilities
* include supported features and required workarounds for address
* translation system within the device, each represented by a byte
* offset into the table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_DMA_CAPS_TBL_SIZE.
*
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the framebuffer caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* 32BIT_POINTER_ENFORCED
* If this property is TRUE NVOS32 and NVOS46 calls with
* 32BIT_POINTER_DISABLED will return addresses above 4GB.
*
* SHADER_ACCESS_SUPPORTED
* If this property is set, the MMU in the system supports the independent
* access bits for the shader. This is accessed with the following fields:
* NVOS46_FLAGS_SHADER_ACCESS
* NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_FLAGS_SHADER_ACCESS
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_DMA_GET_CAPS (0x80180dU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID" */
/* size in bytes of fb caps table */
#define NV0080_CTRL_DMA_CAPS_TBL_SIZE 8U
#define NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV0080_CTRL_DMA_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NvU8 capsTbl[NV0080_CTRL_DMA_CAPS_TBL_SIZE];
} NV0080_CTRL_DMA_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0080_CTRL_DMA_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0080_CTRL_DMA_CAPS_32BIT_POINTER_ENFORCED 0:0x01
#define NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED 0:0x04
#define NV0080_CTRL_DMA_CAPS_SPARSE_VIRTUAL_SUPPORTED 0:0x08
#define NV0080_CTRL_DMA_CAPS_MULTIPLE_VA_SPACES_SUPPORTED 0:0x10
/*
* NV0080_CTRL_DMA_SET_VA_SPACE_SIZE
*
* Change the size of an existing VA space.
* NOTE: Currently this only supports growing the size, not shrinking.
*
* 1. Allocate new page directory able to map extended range.
* 2. Copy existing PDEs from old directory to new directory.
* 3. Initialize new PDEs to invalid.
* 4. Update instmem to point to new page directory.
* 5. Free old page directory.
*
* vaSpaceSize
* On input, the requested size of the VA space in bytes.
* On output, the actual resulting VA space size.
*
* The actual size will be greater than or equal to the requested size,
* unless NV0080_CTRL_DMA_GROW_VA_SPACE_SIZE_MAX is requested, which
* requests the maximum available.
*
* NOTE: Specific size requests (e.g. other than SIZE_MAX) must account
* for the VA hole at the beginning of the range which is used to
* distinguish NULL pointers. This region is not counted as part
* of the vaSpaceSize since it is not allocatable.
*
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space
* associated with the client/device pair.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INSUFFICIENT_RESOURCES
*/
#define NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE (0x80180eU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 vaSpaceSize, 8);
NvHandle hVASpace;
} NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS;
#define NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX (0xFFFFFFFFFFFFFFFFULL)
/*
* NV0080_CTRL_DMA_UPDATE_PDE_2
*
* This command updates a single PDE for the given (hClient, hDevice)
* with specific attributes.
* This command is only available on Windows and MODS platforms.
* This command can be called by kernel clients only.
*
* The VA range the PDE maps must be contained by a VA allocation marked with
* NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED.
* However if the MODS-only FORCE_OVERRIDE flag is set this restriction is relaxed.
*
* RM does not track the PDE's attributes in SW - this control simply stuffs
* the PDE in memory after translating and checking the parameters.
*
* Parameters are checked for relative consistency (e.g. valid domains),
* but it is the client's responsibility to provide correct page table
* addresses, e.g. global consistency is not checked.
*
* It is also the client's responsibility to flush/invalidate the MMU
* when appropriate, either by setting the _FLUSH_PDE_CACHE flag for this
* call or by flushing through other APIs.
* This control does not flush automatically to allow batches of calls
* to be made before a single flush.
*
* ptParams
* Page-size-specific parameters, as follows:
*
* physAddr
* Base address of physically contiguous memory of page table.
* Must be aligned sufficiently for the PDE address field.
* numEntries
* Deprecated and ignored.
* Use FLAGS_PDE_SIZE that applies to the tables for all page sizes.
* aperture
* Address space the base address applies to.
* Can be left as INVALID to ignore this page table size.
*
* pdeIndex
* The PDE index this update applies to.
* flags
* See NV0080_CTRL_DMA_UPDATE_PDE_FLAGS_*.
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space
* associated with the client/device pair.
* pPdeBuffer [out]
* Kernel pointer to 64 bit unsigned integer representing a Page Dir Entry
* that needs to be updated. It should point to memory as wide as the Page Dir
* Entry.
*
* If NULL, Page Dir Entry updates will go to the internally managed Page Dir.
* If not NULL, the updates will be written to this buffer.
*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_DMA_UPDATE_PDE_2 (0x80180fU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID" */
typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
NvU32 numEntries; // deprecated
NvU32 aperture;
} NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS;
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID (0x00000000U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY (0x00000001U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY (0x00000002U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY (0x00000003U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL 0U
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG 1U
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE 2U
#define NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID (0xFU)
typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS {
NvU32 pdeIndex;
NvU32 flags;
NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS ptParams[NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE], 8);
NvHandle hVASpace;
NV_DECLARE_ALIGNED(NvP64 pPdeBuffer, 8); // NV_MMU_VER2_PDE__SIZE
NvU32 subDeviceId; // ID+1, 0 for BC
} NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS;
/*!
* If set a PDE cache flush (MMU invalidate) will be performed.
*/
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE 0:0
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE (0x00000001U)
/*!
* For verification purposes (MODS-only) this flag may be set to modify any PDE
* in the VA space (RM managed or externally managed).
* It is up to caller to restore any changes properly (or to expect faults).
*/
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE 1:1
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE (0x00000001U)
/*!
* Directly controls the PDE_SIZE field (size of the page tables pointed to by this PDE).
*/
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE 3:2
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL (0x00000000U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF (0x00000001U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER (0x00000002U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH (0x00000003U)
/*!
* Used to specify if the allocation is sparse. Applicable only in case of
* VA Space managed by OS, as in WDDM2.0
*/
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE 4:4
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE (0x00000001U)
/*
* NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE
* This interface will create a corresponding privileged
* kernel address space that will mirror user space allocations in this
* VASPACE.
* The user can either pass a FERMI_VASPACE_A handle or RM will use the
* vaspace associated with the client/device if hVaspace is passed as
* NULL.
* Once this property is set, the user will not be able to make allocations
* from the top most PDE of this address space.
*
* The user is expected to call this function as soon as he has created
* the device/Vaspace object. If the user has already made VA allocations
* in this vaspace then this call will return a failure
* (NV_ERR_INVALID_STATE).
* The Vaspace should have no VA allocations when this call is made.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE (0x801810U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS {
NvHandle hVASpace;
} NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS;
/*
* NV0080_CTRL_DMA_SET_DEFAULT_VASPACE
* This is a special control call provided for KMD to use.
* It will associate an allocated Address Space Object as the
* default address space of the device.
*
* This is added so that the USER can move to using address space objects when they
* want to specify the size of the big page size they want to use but still want
* to use the rest of the relevant RM apis without specifying the hVASpace.
*
* This call will succeed only if there is already no VASPACE associated with the
* device. This means the user will have to call this before he has made any allocations
* on this device/address space.
*
* The hVASpace that is passed in to be associated shoould belong to the parent device that
* this call is made for. This call will fail if we try to associate a VASpace belonging to
* some other client/device.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*
*/
#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE (0x801812U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID (0x12U)
typedef struct NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS {
NvHandle hVASpace;
} NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS;
/*!
* NV0080_CTRL_DMA_SET_PAGE_DIRECTORY
*
* Move an existing VA space to an externally-managed top-level page directory.
* The VA space must have been created in SHARED_MANAGEMENT mode.
* For lifecycle details, see NV_VASPACE_ALLOCATION_PARAMETERS documentation in nvos.h.
*
* RM will propagate the update to all channels using the VA space.
*
* NOTE: All channels using this VA space are expected to be idle and unscheduled prior
* to and during this control call - it is responsibility of caller to ensure this.
*
* physAddress
* Physical address of the new page directory within the aperture specified by flags.
* numEntries
* Number of entries in the new page directory.
* The backing phyical memory must be at least this size (multiplied by entry size).
* flags
* APERTURE
* Specifies which physical aperture the page directory resides.
* PRESERVE_PDES
* Deprecated - RM will always copy the RM-managed PDEs from the old page directory
* to the new page directory.
* ALL_CHANNELS
* If true, RM will update the instance blocks for all channels using
* the VAS and ignore the chId parameter.
* EXTEND_VASPACE
* If true, RM will use the client VA for client VA requests in VASPACE_SHARED_MANAGEMENT mode
* If false, RM will use the internal VA for client VA requests.
* IGNORE_CHANNEL_BUSY
* If true, RM will ignore the channel busy status during set page
* directory operation.
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space
* associated with the client/device pair.
* chId
* ID of the Channel to be updated.
* pasid
* PASID (Process Address Space IDentifier) of the process corresponding to
* the VA space. Ignored unless the VA space has ATS enabled.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_LIMIT
* NV_ERR_GENERIC
*/
#define NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (0x801813U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS {
NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
NvU32 numEntries;
NvU32 flags;
NvHandle hVASpace;
NvU32 chId;
NvU32 subDeviceId; // ID+1, 0 for BC
NvU32 pasid;
} NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS;
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE 1:0
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM (0x00000000U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH (0x00000001U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH (0x00000002U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES 2:2
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS 3:3
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY 4:4
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE (0x00000001U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE 5:5
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE (0x00000000U)
#define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE (0x00000001U)
/*!
* NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY
*
* Restore an existing VA space to an RM-managed top-level page directory.
* The VA space must have been created in SHARED_MANAGEMENT mode and
* previously relocated to an externally-managed page directory with
* NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (these two API are symmetric operations).
* For lifecycle details, see NV_VASPACE_ALLOCATION_PARAMETERS documentation in nvos.h.
*
* RM will propagate the update to all channels using the VA space.
*
* NOTE: All channels using this VA space are expected to be idle and unscheduled prior
* to and during this control call - it is responsibility of caller to ensure this.
*
* hVASpace
* handle for the allocated VA space that this control call should operate
* on. If it's 0, it assumes to use the implicit allocated VA space
* associated with the client/device pair.
*/
#define NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY (0x801814U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID (0x14U)
typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS {
NvHandle hVASpace;
NvU32 subDeviceId; // ID+1, 0 for BC
} NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS;
/* _ctrl0080dma_h_ */

235
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h Normal file
View File

@@ -0,0 +1,235 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080fb.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE fb control commands and parameters */
/**
* NV0080_CTRL_CMD_FB_GET_CAPS
*
* This command returns the set of framebuffer capabilities for the device
* in the form of an array of unsigned bytes. Framebuffer capabilities
* include supported features and required workarounds for the framebuffer
* engine(s) within the device, each represented by a byte offset into the
* table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_FB_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the framebuffer caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_POINTER
*/
#define NV0080_CTRL_CMD_FB_GET_CAPS (0x801301) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_FB_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0080_CTRL_FB_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0080_CTRL_FB_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0080_CTRL_FB_CAPS_SUPPORT_RENDER_TO_SYSMEM 0:0x01
#define NV0080_CTRL_FB_CAPS_BLOCKLINEAR 0:0x02
#define NV0080_CTRL_FB_CAPS_SUPPORT_SCANOUT_FROM_SYSMEM 0:0x04
#define NV0080_CTRL_FB_CAPS_SUPPORT_CACHED_SYSMEM 0:0x08
#define NV0080_CTRL_FB_CAPS_SUPPORT_C24_COMPRESSION 0:0x10 // Deprecated
#define NV0080_CTRL_FB_CAPS_SUPPORT_SYSMEM_COMPRESSION 0:0x20
#define NV0080_CTRL_FB_CAPS_NISO_CFG0_BUG_534680 0:0x40 // Deprecated
#define NV0080_CTRL_FB_CAPS_ISO_FETCH_ALIGN_BUG_561630 0:0x80 // Deprecated
#define NV0080_CTRL_FB_CAPS_BLOCKLINEAR_GOBS_512 1:0x01
#define NV0080_CTRL_FB_CAPS_L2_TAG_BUG_632241 1:0x02
#define NV0080_CTRL_FB_CAPS_SINGLE_FB_UNIT 1:0x04 // Deprecated
#define NV0080_CTRL_FB_CAPS_CE_RMW_DISABLE_BUG_897745 1:0x08 // Deprecated
#define NV0080_CTRL_FB_CAPS_OS_OWNS_HEAP_NEED_ECC_SCRUB 1:0x10
#define NV0080_CTRL_FB_CAPS_ASYNC_CE_L2_BYPASS_SET 1:0x20 // Deprecated
#define NV0080_CTRL_FB_CAPS_DISABLE_TILED_CACHING_INVALIDATES_WITH_ECC_BUG_1521641 1:0x40
#define NV0080_CTRL_FB_CAPS_DISABLE_MSCG_WITH_VR_BUG_1681803 2:0x01
#define NV0080_CTRL_FB_CAPS_VIDMEM_ALLOCS_ARE_CLEARED 2:0x02
#define NV0080_CTRL_FB_CAPS_DISABLE_PLC_GLOBALLY 2:0x04
#define NV0080_CTRL_FB_CAPS_PLC_BUG_3046774 2:0x08
/* size in bytes of fb caps table */
#define NV0080_CTRL_FB_CAPS_TBL_SIZE 3
/*!
* NV0080_CTRL_CMD_FB_COMPBIT_STORE_GET_INFO
*
* This command returns compbit backing store-related information.
*
* size
* [out] Size of compbit store, in bytes
* address
* [out] Address of compbit store
* addressSpace
* [out] Address space of compbit store (corresponds to type NV_ADDRESS_SPACE in nvrm.h)
* maxCompbitLine
* [out] Maximum compbitline possible, determined based on size
* comptagsPerCacheLine
* [out] Number of compression tags per compression cache line, across all
* L2 slices.
* cacheLineSize
* [out] Size of compression cache line, across all L2 slices. (bytes)
* cacheLineSizePerSlice
* [out] Size of the compression cache line per slice (bytes)
* cacheLineFetchAlignment
* [out] Alignment used while fetching the compression cacheline range in FB.
* If start offset of compcacheline in FB is S and end offset is E, then
* the range to fetch to ensure entire compcacheline data is extracted is:
* (align_down(S) , align_up(E))
* This is needed in GM20X+ because of interleaving of data in Linear FB space.
* Example - In GM204 every other 1K FB chunk of data is offset by 16K.
* backingStoreBase
* [out] Address of start of Backing Store in linear FB Physical Addr space.
* This is the actual offset in FB which HW starts using as the Backing Store and
* in general will be different from the start of the region that driver allocates
* as the backing store. This address is expected to be 2K aligned.
* gobsPerComptagPerSlice
* [out] (Only on Pascal) Number of GOBS(512 bytes of surface PA) that correspond to one 64KB comptgaline, per slice.
* One GOB stores 1 byte of compression bits.
* 0 value means this field is not applicable for the current architecture.
* backingStoreCbcBase
* [out] 2KB aligned base address of CBC (post divide address)
* comptaglineAllocationPolicy
* [out] Policy used to allocate comptagline from CBC for the device
* privRegionStartOffset
* [out] Starting offset for any priv region allocated by clients. only used by MODS
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO (0x801306) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 Size, 8);
NV_DECLARE_ALIGNED(NvU64 Address, 8);
NvU32 AddressSpace;
NvU32 MaxCompbitLine;
NvU32 comptagsPerCacheLine;
NvU32 cacheLineSize;
NvU32 cacheLineSizePerSlice;
NvU32 cacheLineFetchAlignment;
NV_DECLARE_ALIGNED(NvU64 backingStoreBase, 8);
NvU32 gobsPerComptagPerSlice;
NvU32 backingStoreCbcBase;
NvU32 comptaglineAllocationPolicy;
NV_DECLARE_ALIGNED(NvU64 privRegionStartOffset, 8);
} NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS;
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN 0 // ADDR_UNKNOWN
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM 1 // ADDR_SYSMEM
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM 2 // ADDR_FBMEM
// Policy used to allocate comptaglines
/**
* Legacy mode allocates a comptagline for 64kb page. This mode will always allocate
* contiguous comptaglines from a ctag heap.
*/
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY 0
/**
* 1TO1 mode allocates a comptagline for 64kb page. This mode will calculate
* comptagline offset based on physical address. This mode will allocate
* contiguous comptaglines if the surface is contiguous and non-contiguous
* comptaglines for non-contiguous surfaces.
*/
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1 1
/**
* 1TO4_Heap mode allocates a comptagline for 256kb page granularity. This mode
* will allocate comptagline from a heap. This mode will align the surface allocations
* to 256kb before allocating comptaglines. The comptaglines allocated will always be
* contiguous here.
* TODO: For GA10x, this mode will support < 256kb surface allocations, by sharing
* a comptagline with at most 3 different 64Kb allocations. This will result in
* miixed-contiguity config where comptaglines will be allocated contiguously as well
* as non-contiguous when shared with other allocations.
*/
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4 2
/**
* Rawmode will transfer allocation of comptaglines to HW, where HW manages
* comptaglines based on physical offset. The comptaglines are cleared when SW
* issues physical/virtual scrub to the surface before reuse.
*/
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE 3
/**
* NV0080_CTRL_CMD_FB_GET_CAPS_V2
*
* This command returns the same set of framebuffer capabilities for the
* device as @ref NV0080_CTRL_CMD_FB_GET_CAPS. The difference is in the structure
* NV0080_CTRL_FB_GET_CAPS_V2_PARAMS, which contains a statically sized array,
* rather than a caps table pointer and a caps table size in
* NV0080_CTRL_FB_GET_CAPS_PARAMS.
*
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the framebuffer caps bits will be written by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_POINTER
*/
#define NV0080_CTRL_CMD_FB_GET_CAPS_V2 (0x801307) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0080_CTRL_FB_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_FB_CAPS_TBL_SIZE];
} NV0080_CTRL_FB_GET_CAPS_V2_PARAMS;
/* _ctrl0080fb_h_ */

645
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h Normal file
View File

@@ -0,0 +1,645 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080fifo.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE fifo control commands and parameters */
/**
* NV0080_CTRL_FIFO_GET_CAPS
*
* This command returns the set of FIFO engine capabilities for the device
* in the form of an array of unsigned bytes. FIFO capabilities
* include supported features and required workarounds for the FIFO
* engine(s) within the device, each represented by a byte offset into the
* table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_FIFO_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the framebuffer caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_GET_CAPS (0x801701) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_FIFO_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0080_CTRL_FIFO_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0080_CTRL_FIFO_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0080_CTRL_FIFO_CAPS_SUPPORT_SCHED_EVENT 0:0x01
#define NV0080_CTRL_FIFO_CAPS_SUPPORT_PCI_PB 0:0x02
#define NV0080_CTRL_FIFO_CAPS_SUPPORT_VID_PB 0:0x04
#define NV0080_CTRL_FIFO_CAPS_USERD_IN_SYSMEM 0:0x40
/* do not use pipelined PTE BLITs to update PTEs: call the RM */
#define NV0080_CTRL_FIFO_CAPS_NO_PIPELINED_PTE_BLIT 0:0x80
#define NV0080_CTRL_FIFO_CAPS_GPU_MAP_CHANNEL 1:0x01
#define NV0080_CTRL_FIFO_CAPS_BUFFEREDMODE_SCHEDULING 1:0x02 // Deprecated
#define NV0080_CTRL_FIFO_CAPS_WFI_BUG_898467 1:0x08 // Deprecated
#define NV0080_CTRL_FIFO_CAPS_HAS_HOST_LB_OVERFLOW_BUG_1667921 1:0x10
/*
* To indicate Volta subcontext support with multiple VA spaces in a TSG.
* We are not using "subcontext" tag for the property, since we also use
* subcontext to represent pre-VOlta SCG feature, which only allows a single
* VA space in a TSG.
*/
#define NV0080_CTRL_FIFO_CAPS_MULTI_VAS_PER_CHANGRP 1:0x20
#define NV0080_CTRL_FIFO_CAPS_SUPPORT_WDDM_INTERLEAVING 1:0x40
/* size in bytes of fifo caps table */
#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2
/*
* NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS
*
* This command enables the GPU to place various scheduling events in the
* off chip event buffer (with optional interrupt) for those GPUs that support
* it.
*
* record
* This parameter specifies a mask of event types to record.
* interrupt
* This parameter specifies a mask of event types for which to interrupt
* the CPU when the event occurs.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS (0x801703) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x3" */
typedef struct NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS {
NvU32 record;
NvU32 interrupt;
} NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS;
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX 0:0
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX 1:1
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST 2:2
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE 3:3
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT 4:4
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT 5:5
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD 6:6
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX 7:7
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI 8:8
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED 9:9
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC 10:10
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT 11:11
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL 11:0
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_ENABLE (0x00000fff)
/*
* NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS
*
* This command allows the caller to request that a set of channels
* be added to the runlist.
*
* fifoStartChannelListSize
* Size of the fifoStartChannelList. The units are in entries, not
* bytes.
* fifoStartChannelList
* This will be a list of NV0080_CTRL_FIFO_CHANNEL data structures,
* one for each channel that is to be started.
* channelHandle
* deprecated
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
/*
* hChannel
* This is the handle to the channel that is scheduled to be started.
*/
typedef struct NV0080_CTRL_FIFO_CHANNEL {
NvHandle hChannel;
} NV0080_CTRL_FIFO_CHANNEL;
#define NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS (0x801705) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS {
NvU32 fifoStartChannelListSize;
NvHandle channelHandle[8];
NV_DECLARE_ALIGNED(NvP64 fifoStartChannelList, 8);
} NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS;
#define NV0080_CTRL_FIFO_ENGINE_ID_GRAPHICS (0x00000000)
#define NV0080_CTRL_FIFO_ENGINE_ID_MPEG (0x00000001)
#define NV0080_CTRL_FIFO_ENGINE_ID_MOTION_ESTIMATION (0x00000002)
#define NV0080_CTRL_FIFO_ENGINE_ID_VIDEO (0x00000003)
#define NV0080_CTRL_FIFO_ENGINE_ID_BITSTREAM (0x00000004)
#define NV0080_CTRL_FIFO_ENGINE_ID_ENCRYPTION (0x00000005)
#define NV0080_CTRL_FIFO_ENGINE_ID_FGT (0x00000006)
/*
* NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES
*
* This command is used to provide the caller with the alignment and size
* of the context save region for an engine
*
* engineId
* This parameter is an input parameter specifying the engineId for which
* the alignment/size is requested.
* alignment
* This parameter is an output parameter which will be filled in with the
* minimum alignment requirement.
* size
* This parameter is an output parameter which will be filled in with the
* minimum size of the context save region for the engine.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES (0x801707) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID 4:0
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS (0x00000000)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD (0x00000001)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO (0x00000002)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG (0x00000003)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE (0x00000004)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY (0x00000005)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION (0x00000006)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS (0x00000007)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL (0x00000008)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM (0x00000009)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT (0x0000000a)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT (0x0000000b)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL (0x0000000c)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL (0x0000000d)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB (0x0000000e)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV (0x0000000f)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH (0x00000010)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB (0x00000011)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL (0x00000012)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB (0x00000013)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL (0x00000014)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL (0x00000015)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK (0x00000016)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT (0x00000017)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP (0x00000018)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT (0x00000019)
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS {
NvU32 engineId;
NvU32 alignment;
NvU32 size;
} NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS;
/*
* NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS <Deprecated since Fermi+>
*
* This command allows the caller to group two sets of channels. A channel
* set includes one or more channels. After grouping, the grouped channel IDs
* are set to next to each other in the runlist. This command can be used
* several times to group more than two channels.
*
* Using a NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE after
* NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS is the general usage. A
* NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS after a
* NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE for a channel handle is not
* allowed.
*
* NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS defines the max channels in a
* group.
*
* hChannel1
* This parameter specifies the handle of the channel that belongs to the
* base set of channels.
* hChannel2
* This parameter specifies the handle of the channel that belongs to the
* additional set of channels.
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_CHANNEL
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS (0x801709) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x9" */
typedef struct NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM {
NvHandle hChannel1;
NvHandle hChannel2;
} NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM;
#define NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS (8)
/*
* NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE <Deprecated since Fermi+>
*
* This command allows the caller to divide the timeslice (DMA_TIMESLICE) of a
* channel between the channels in the group in which the channel resides.
* After applying this command, a timeslice divided channel (group) has a
* short timeslice and repeats more than once in the runlist. The total
* available execution time is not changed.
*
* Using this command after NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS is the
* general usage. A NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS after a
* NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE for a channel handle is not
* allowed.
*
* hChannel
* This parameter specifies the handle of the channel for the channel
* group to which the divided timeslice operation will apply.
* tsDivisor
* This parameter specifies the timeslice divisor value. This value
* should not exceed NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_CHANNEL
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INSUFFICIENT_RESOURCES
*/
#define NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE (0x80170b) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0xB" */
typedef struct NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM {
NvHandle hChannel;
NvU32 tsDivisor;
} NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM;
#define NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR (12)
/*
* NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST <Deprecated since Fermi+>
*
* This command preepmts the engine represented by the specified runlist.
*
* hRunlist
* This parameter specifies the per engine runlist handle. This
* parameter is being retained to maintain backwards compatibility
* with clients that have not transitioned over to using runlists
* on a per subdevice basis.
*
* engineID
* This parameter specifies the engine to be preempted. Engine defines
* can be found in cl2080.h.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST (0x80170c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0xC" */
typedef struct NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS {
NvHandle hRunlist;
NvU32 engineID;
} NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS;
/*
* NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST
*
* Takes a list of hChannels as input and returns the
* corresponding Channel IDs that they corresponding to
* on hw.
*
* numChannels
* Size of input hChannellist
* pChannelHandleList
* List of input channel handles
* pChannelList
* List of Channel ID's corresponding to the
* each entry in the hChannelList.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST (0x80170d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS {
NvU32 numChannels;
NV_DECLARE_ALIGNED(NvP64 pChannelHandleList, 8);
NV_DECLARE_ALIGNED(NvP64 pChannelList, 8);
} NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS;
/*
* NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE
*
* This control call is used to return the number of gp methods(gpsize) and push buffer methods(pbsize)
* allocated to each engine.
*
*engineID
* The engine ID which is an input
*
*gpEntries
* number of gp entries
*
*pbEntries
* number of pb entries (in units of 32B rows)
*
*/
#define NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE (0x80170e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS {
NvU32 engineID;
NvU32 gpEntries;
NvU32 pbEntries;
} NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS;
#define NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL (0xffffffff)
/*
* NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES
*
* This command allows internal properties of the channel
* to be modified even when the channel is active. Most of these properties
* are not meant to be modified during normal runs hence have been
* kept separate from channel alloc params. It is the
* responsibility of the underlying hal routine to make
* sure the channel properties are changed while the channel
* is *NOT* in a transient state.
*
* hChannel
* The handle to the channel.
*
* property
* The channel property to be modified.
* NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_xxx provides the entire list
* of properties.
*
* value
* The new value for the property.
* When property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS
* value = timeslice in microseconds
* desc: Used to change a channel's engine timeslice in microseconds
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS
* value = timeslice in microseconds
* desc: Used to change a channel's pbdma timeslice in microseconds
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE
* value is ignored
* desc: Disables a channel from being timesliced out from an engine.
* Other scheduling events like explicit yield, acquire failures will
* switch out the channel though.
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE
* value is ignored
* desc: Disables a channel from being timesliced out from its pbdma.
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET
* value is ignored
* desc: Override the channel's page directory pointer table with an
* erroneous aperture value. (TODO: make test calls NV_VERIF_FEATURES
* only)(VERIF ONLY)
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT
* value = engineID of engine that will have its context pointer reset.
* engineID defines can be found in cl2080.h
* (e.g., NV2080_ENGINE_TYPE_GRAPHICS)
* desc: Override the channel's engine context pointer with a non existent
* buffer forcing it to fault. (VERIF ONLY)
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT
* value = engineID of engine that will have its context pointer reset.
* engineID defines can be found in cl2080.h
* (e.g., NV2080_ENGINE_TYPE_GRAPHICS)
* desc: Override the channel's engine context pointer with a non existent
* buffer forcing it to fault. However the channel will not be preempted
* before having its channel state modified.(VERIF ONLY)
*
* property = NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP
* value is ignored
* desc: does not change any channel state exercises a full channel preempt/
* unbind/bind op. (VERIF ONLY)
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_CHANNEL
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES (0x80170f) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID (0xFU)
typedef struct NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS {
NvHandle hChannel;
NvU32 property;
NV_DECLARE_ALIGNED(NvU64 value, 8);
} NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS;
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS (0x00000000)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS (0x00000001)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE (0x00000002)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE (0x00000003)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET (0x00000004)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT (0x00000005)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP (0x00000007)
#define NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT (0x00000008)
/*
* NV0080_CTRL_CMD_FIFO_STOP_RUNLIST
*
* Stops all processing on the runlist for the given engine. This is only
* valid in per-engine round-robin scheduling mode.
*
* engineID
* This parameter specifies the engine to be stopped. Engine defines
* can be found in cl2080.h.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0080_CTRL_CMD_FIFO_STOP_RUNLIST (0x801711) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID (0x11U)
typedef struct NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS {
NvU32 engineID;
} NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS;
/*
* NV0080_CTRL_CMD_FIFO_START_RUNLIST
*
* Restarts a runlist previously stopped with NV0080_CTRL_CMD_FIFO_STOP_RUNLIST.
* This is only valid for per-engine round-robin mode.
*
* engineID
* This parameter specifies the engine to be started. Engine defines
* can be found in cl2080.h.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0080_CTRL_CMD_FIFO_START_RUNLIST (0x801712) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID (0x12U)
typedef struct NV0080_CTRL_FIFO_START_RUNLIST_PARAMS {
NvU32 engineID;
} NV0080_CTRL_FIFO_START_RUNLIST_PARAMS;
/**
* NV0080_CTRL_FIFO_GET_CAPS_V2
*
* This command returns the same set of FIFO engine capabilities for the device
* as @ref NV0080_CTRL_FIFO_GET_CAPS. The difference is in the structure
* NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS, which contains a statically sized array,
* rather than a caps table pointer and a caps table size in
* NV0080_CTRL_FIFO_GET_CAPS_PARAMS.
*
* capsTbl
* This parameter is an array of the client's caps table buffer.
* The framebuffer caps bits will be written by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 (0x801713) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_FIFO_CAPS_TBL_SIZE];
} NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS;
/**
* NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS
*
* @brief This command idles (deschedules and waits for pending work to complete) channels
* belonging to a particular device.
*
* numChannels
* Number of channels to idle
*
* hChannels
* Array of channel handles to idle
*
* flags
* NVOS30_FLAGS that control aspects of how the channel is idled
*
* timeout
* GPU timeout in microseconds, for each CHID Manager's idling operation
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_TIMEOUT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_LOCK_STATE
*/
#define NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS (0x801714) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS 4096
#define NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x14U)
typedef struct NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS {
NvU32 numChannels;
NvHandle hChannels[NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS];
NvU32 flags;
NvU32 timeout;
} NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS;
/* _ctrl0080fifo_h_ */

588
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h Normal file
View File

@@ -0,0 +1,588 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080gpu.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
#include "nvlimits.h"
/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */
/*
* NV0080_CTRL_CMD_GPU_GET_CLASSLIST
*
* This command returns supported class information for the specified device.
* If the device is comprised of more than one GPU, the class list represents
* the set of supported classes common to all GPUs within the device.
*
* It has two modes:
*
* If the classList pointer is NULL, then this command returns the number
* of classes supported by the device in the numClasses field. The value
* should then be used by the client to allocate a classList buffer
* large enough to hold one 32bit value per numClasses entry.
*
* If the classList pointer is non-NULL, then this command returns the
* set of supported class numbers in the specified buffer.
*
* numClasses
* If classList is NULL, then this parameter will return the
* number of classes supported by the device. If classList is non-NULL,
* then this parameter indicates the number of entries in classList.
* classList
* This parameter specifies a pointer to the client's buffer into
* which the supported class numbers should be returned.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST (0x800201) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS {
NvU32 numClasses;
NV_DECLARE_ALIGNED(NvP64 classList, 8);
} NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS;
/**
* NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES
*
* This command returns the number of subdevices for the device.
*
* numSubDevices
* This parameter returns the number of subdevices within the device.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES (0x800280) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID (0x80U)
typedef struct NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS {
NvU32 numSubDevices;
} NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER
*
* This command returns the video link order of each subdevice id inside the
* device. This call can only be made after SLI is enabled. This call is
* intended for 3D clients to use to determine the vidlink order of the
* devices. The Display Output Parent will always be the first subdevice
* mask listed in the array. Note that this command should not be used in
* case of bridgeless SLI. The order of the subdevices returned by this
* command will not be correct in case of bridgeless SLI.
*
* ConnectionCount
* Each HW can provide 1 or 2 links between all GPUs in a device. This
* number tells how many links are available between GPUs. This data
* also represents the number of concurrent SLI heads that can run at
* the same time over this one device.
*
* Order
* This array returns the order of subdevices that are used through
* the vidlink for display output.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER (0x800281) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID (0x81U)
typedef struct NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS {
NvU32 ConnectionCount;
NvU32 Order[NV_MAX_SUBDEVICES];
} NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER
*
* This command sets display ownership within the device to the specified
* subdevice instance. The actual transfer of display ownership will take
* place at the next modeset.
*
* subDeviceInstance
* This member specifies the subdevice instance of the new display
* owner. The subdevice instance must be in the legal range
* indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER (0x800282) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x82U)
typedef struct NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS {
NvU32 subDeviceInstance;
} NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER
*
* This command returns the subdevice instance of the current display owner
* within the device.
*
* subDeviceInstance
* This member returns the subdevice instance of the current display
* owner. The subdevice instance will be in the legal range
* indicated by the NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES command.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER (0x800283) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID (0x83U)
typedef struct NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS {
NvU32 subDeviceInstance;
} NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_SET_VIDLINK
*
* This command enables or disables the VIDLINK of all subdevices in the
* current SLI configuration.
*
* enable
* Enables or disables the vidlink
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_GPU_SET_VIDLINK (0x800285) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID (0x85U)
typedef struct NV0080_CTRL_GPU_SET_VIDLINK_PARAMS {
NvU32 enable;
} NV0080_CTRL_GPU_SET_VIDLINK_PARAMS;
#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE (0x00000000)
#define NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE (0x00000001)
/* commands */
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS 0
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN 1
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP 2
/* status */
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON 0
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN 1
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED 2
#define NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP 3
/*
* NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE
*
* This command is used to enable or disable the persistence of a GPU's
* software state when no clients exist. With persistent software state enabled
* the GPU's software state is not torn down when the last client exits, but is
* retained until either the kernel module unloads or persistent software state
* is disabled.
*
* newState
* This input parameter is used to enable or disable the persistence of the
* software state of all subdevices within the device.
* Possible values are:
* NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED
* NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE (0x800287) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */
/* Possible values of persistentSwState */
#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED (0x00000000)
#define NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED (0x00000001)
#define NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x87U)
typedef struct NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS {
NvU32 newState;
} NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE
*
* swStatePersistence
* This parameter returns a value indicating if persistent software
* state is currently enabled or not for the specified GPU. See the
* description of NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE.
* Possible values are:
* NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED
* NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE (0x800288) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID (0x88U)
typedef struct NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS {
NvU32 swStatePersistence;
} NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS;
/**
* NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE
*
* This command returns a value indicating virtualization mode in
* which the GPU is running.
*
* virtualizationMode
* This parameter returns the virtualization mode of the device.
* Possible values are:
* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE
* This value indicates that there is no virtualization mode associated with the
* device (i.e. it's a baremetal GPU).
* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS
* This value indicates that the device is associated with the NMOS.
* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX
* This value indicates that the device is associated with VGX(guest GPU).
* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST
* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU
* This value indicates that the device is associated with vGPU(host GPU).
* NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA
* This value indicates that the device is associated with vSGA(host GPU).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE (0x800289) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE (0x00000000)
#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS (0x00000001)
#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX (0x00000002)
#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST (0x00000003)
#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST
#define NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA (0x00000004)
#define NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS {
NvU32 virtualizationMode;
} NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE
*
* This command returns the setting information for sparse texture compute
* mode optimization on the associated GPU. This setting indicates how the
* large page size should be selected by the RM for the GPU.
*
* defaultSetting
* This field specifies what the OS default setting is for the associated
* GPU. See NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list
* of possible values.
* currentSetting
* This field specifies which optimization mode was applied when the
* driver was loaded. See
* NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of
* possible values.
* pendingSetting
* This field specifies which optimization mode will be applied on the
* next driver reload. See
* NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE for a list of
* possible values.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028c) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8CU)
typedef struct NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS {
NvU32 defaultSetting;
NvU32 currentSetting;
NvU32 pendingSetting;
} NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE
*
* This command sets the pending setting for sparse texture compute mode. This
* setting indicates how the large page size should be selected by the RM for
* the GPU on the next driver reload.
*
* setting
* This field specifies which use case the RM should optimize the large
* page size for on the next driver reload. Possible values for this
* field are:
* NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT
* This value indicates that the RM should use the default setting for
* the GPU's large page size. The default setting is reported by
* NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE.
* NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE
* This value indicates that the RM should select the GPU's large page
* size to optimize for compute use cases.
* NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE
* This value indicates that the RM should select the GPU's large page
* size to optimize for sparse texture use cases.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INSUFFICIENT_PERMISSIONS
*/
#define NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE (0x80028d) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID (0x8DU)
typedef struct NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS {
NvU32 setting;
} NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS;
/* Possible sparse texture compute mode setting values */
#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT 0
#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE 1
#define NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE 2
/*
* NV0080_CTRL_CMD_GPU_GET_VGX_CAPS
*
* This command gets the VGX capability of the GPU depending on the status of
* the VGX hardware fuse.
*
* isVgx
* This field is set to NV_TRUE is VGX fuse is enabled for the GPU otherwise
* it is set to NV_FALSE.
*
* Possible status values returned are:
* NVOS_STATUS_SUCCESS
* NVOS_STATUS_ERROR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_GPU_GET_VGX_CAPS (0x80028e) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID (0x8EU)
typedef struct NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS {
NvBool isVgx;
} NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS
*
* This command is used to query GPU SRIOV capabilities
* totalVFs
* Total number of virtual functions supported.
*
* firstVfOffset
* Offset of the first VF.
*
* vfFeatureMask
* Bitmask of features managed by the guest
*
* FirstVFBar0Address
* Address of BAR0 region of first VF.
*
* FirstVFBar1Address
* Address of BAR1 region of first VF.
*
* FirstVFBar2Address
* Address of BAR2 region of first VF.
*
* bar0Size
* Size of BAR0 region on VF.
*
* bar1Size
* Size of BAR1 region on VF.
*
* bar2Size
* Size of BAR2 region on VF.
*
* b64bitBar0
* If the VF BAR0 is 64-bit addressable.
*
* b64bitBar1
* If the VF BAR1 is 64-bit addressable.
*
* b64bitBar2
* If the VF BAR2 is 64-bit addressable.
*
* bSriovEnabled
* Flag for SR-IOV enabled or not.
*
* bSriovHeavyEnabled
* Flag for whether SR-IOV is enabled in standard or heavy mode.
*
* bEmulateVFBar0TlbInvalidationRegister
* Flag for whether VF's TLB Invalidate Register region needs emulation.
*
* bClientRmAllocatedCtxBuffer
* Flag for whether engine ctx buffer is managed by client RM.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS (0x800291) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID (0x91U)
typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
NvU32 totalVFs;
NvU32 firstVfOffset;
NvU32 vfFeatureMask;
NV_DECLARE_ALIGNED(NvU64 FirstVFBar0Address, 8);
NV_DECLARE_ALIGNED(NvU64 FirstVFBar1Address, 8);
NV_DECLARE_ALIGNED(NvU64 FirstVFBar2Address, 8);
NV_DECLARE_ALIGNED(NvU64 bar0Size, 8);
NV_DECLARE_ALIGNED(NvU64 bar1Size, 8);
NV_DECLARE_ALIGNED(NvU64 bar2Size, 8);
NvBool b64bitBar0;
NvBool b64bitBar1;
NvBool b64bitBar2;
NvBool bSriovEnabled;
NvBool bSriovHeavyEnabled;
NvBool bEmulateVFBar0TlbInvalidationRegister;
NvBool bClientRmAllocatedCtxBuffer;
} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS;
// Update this macro if new HW exceeds GPU Classlist MAX_SIZE
#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 116
#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID (0x92U)
typedef struct NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS {
NvU32 numClasses; // __OUT__
NvU32 classList[NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE]; // __OUT__
} NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS;
/*
* NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE
*
* Find a subdevice handle allocated under this device
*/
#define NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE (0x800293) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID" */
#define NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID (0x93U)
typedef struct NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM {
NvU32 subDeviceInst; // [in]
NvHandle hSubDevice; // [out]
} NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM;
/*
* NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS
*
* This command gets branding information for the device.
*
* brands
* Mask containing branding information. A bit in this
* mask is set if the GPU has particular branding.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO NVBIT(0)
#define NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS NVBIT(1)
#define NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN NVBIT(2)
#define NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS (0x800294) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID (0x94U)
typedef struct NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS {
NvU32 brands;
} NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS;
/*
* These are the per-VF BAR1 sizes that we support in MB.
* They are used with the NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE control call and
* should match the NV_XVE_BAR1_CONFIG_SIZE register defines.
*/
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M 64
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M 128
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M 256
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M 512
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G 1024
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G 2048
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G 4096
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G 8192
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G 16384
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G 32768
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G 65536
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G 131072
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M
#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G
#define NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID NV_U32_MAX
/*
* NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE
*
* @brief Resize BAR1 per-VF on the given GPU
* vfBar1SizeMB[in] size of per-VF BAR1 size in MB
* numVfs[out] number of VFs that can be created given the new BAR1 size
*/
#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE (0x800296) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID (0x96U)
typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS {
NvU32 vfBar1SizeMB;
NvU32 numVfs;
} NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS;
/* _ctrl0080gpu_h_ */

277
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h Normal file
View File

@@ -0,0 +1,277 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080gr.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
typedef struct NV0080_CTRL_GR_ROUTE_INFO {
NvU32 flags;
NV_DECLARE_ALIGNED(NvU64 route, 8);
} NV0080_CTRL_GR_ROUTE_INFO;
/* NV01_DEVICE_XX/NV03_DEVICE gr engine control commands and parameters */
/**
* NV0080_CTRL_CMD_GR_GET_CAPS
*
* This command returns the set of graphics capabilities for the device
* in the form of an array of unsigned bytes. Graphics capabilities
* include supported features and required workarounds for the graphics
* engine(s) within the device, each represented by a byte offset into the
* table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_GR_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the graphics caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*/
#define NV0080_CTRL_CMD_GR_GET_CAPS (0x801102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_GR_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0080_CTRL_GR_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0080_CTRL_GR_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/*
* Size in bytes of gr caps table. This value should be one greater
* than the largest byte_index value above.
*/
#define NV0080_CTRL_GR_CAPS_TBL_SIZE 23
/*
* NV0080_CTRL_CMD_GR_INFO
*
* This structure represents a single 32bit graphics engine value. Clients
* request a particular graphics engine value by specifying a unique bus
* information index.
*
* Legal graphics information index values are:
* NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS
* This index is used to request the number of clip IDs supported by
* the device.
* NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894
* This index is used to request the minimum number of attributes that
* need to be enabled to avoid bug 261894. A return value of 0
* indicates that there is no minimum and the bug is not present on this
* system.
*/
typedef struct NV0080_CTRL_GR_INFO {
NvU32 index;
NvU32 data;
} NV0080_CTRL_GR_INFO;
/* valid graphics info index values */
#define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS (0x00000000)
#define NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 (0x00000001)
#define NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK (0x00000002)
#define NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT (0x00000003)
#define NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT (0x00000004)
#define NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE (0x00000005)
#define NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT (0x00000006)
#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT (0x00000007)
#define NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR (0x00000008)
#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT (0x00000009)
#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT (0x0000000A)
#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT (0x0000000B)
#define NV0080_CTRL_GR_INFO_INDEX_SM_VERSION (0x0000000C)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM (0x0000000D)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP (0x0000000E)
#define NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES (0x0000000F)
#define NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES (0x00000010)
#define NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY (0x00000011)
#define NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY (0x00000012)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM (0x00000013)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS (0x00000014)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS (0x00000015)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS (0x00000016)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC (0x00000017)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS (0x00000018)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS (0x00000019)
#define NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED (0x0000001A)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS (0x0000001B)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC (0x0000001C)
#define NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT (0x0000001D)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES (0x0000001E)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS (0x0000001F)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC (0x00000020)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS (0x00000021)
#define NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT (0x00000022)
#define NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT (0x00000023)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS (0x00000024)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS (0x00000025)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES (0x00000026)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC (0x00000027)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP (0x00000028)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC (0x00000029)
#define NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC (0x0000002A)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP (0x0000002B)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT (0x0000002C)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT (0x0000002D)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT (0x0000002E)
/* When adding a new INDEX, please update MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
* reflects that.
*/
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000031)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x32) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
/*
* NV0080_CTRL_CMD_GR_GET_INFO
*
* This command returns graphics engine information for the associate GPU.
* Request to retrieve graphics information use a list of one or more
* NV0080_CTRL_GR_INFO structures.
*
* grInfoListSize
* This field specifies the number of entries on the caller's
* grInfoList.
* grInfoList
* This field specifies a pointer in the caller's address space
* to the buffer into which the bus information is to be returned.
* This buffer must be at least as big as grInfoListSize multiplied
* by the size of the NV0080_CTRL_GR_INFO structure.
*/
#define NV0080_CTRL_CMD_GR_GET_INFO (0x801104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0080_CTRL_GR_GET_INFO_PARAMS {
NvU32 grInfoListSize;
NV_DECLARE_ALIGNED(NvP64 grInfoList, 8);
} NV0080_CTRL_GR_GET_INFO_PARAMS;
/*
* NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE
* This command gets the current partition mode of a TSG context.
*
* NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE
* This command sets the partition mode of a TSG context.
*
* NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
* This structure defines the parameters used for TPC partitioning mode SET/GET commands
*
* hChannelGroup [IN]
* RM Handle to the TSG
*
* mode [IN/OUT]
* Partitioning mode enum value
* For the SET cmd, this is an input parameter
* For the GET cmd, this is an output parameter
*
* bEnableAllTpcs [IN]
* Flag to enable all TPCs by default
*
* grRouteInfo[IN]
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*
*/
#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */
#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */
/* Enum for listing TPC partitioning modes */
typedef enum NV0080_CTRL_GR_TPC_PARTITION_MODE {
NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = 0,
NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = 1,
NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = 2,
} NV0080_CTRL_GR_TPC_PARTITION_MODE;
typedef struct NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS {
NvHandle hChannelGroup; // [in]
NV0080_CTRL_GR_TPC_PARTITION_MODE mode; // [in/out]
NvBool bEnableAllTpcs; // [in/out]
NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); // [in]
} NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS;
/**
* NV0080_CTRL_CMD_GR_GET_CAPS_V2
*
* This command returns the same set of graphics capabilities for the device
* as @ref NV0080_CTRL_CMD_GR_GET_CAPS. The difference is in the structure
* NV0080_CTRL_GR_GET_INFO_V2_PARAMS, which contains a statically sized array,
* rather than a caps table pointer and a caps table size in
* NV0080_CTRL_GR_GET_INFO_PARAMS. Additionally,
* NV0080_CTRL_GR_GET_INFO_V2_PARAMS contains a parameter for specifying routing
* information, used for MIG.
*
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the graphics caps bits will be written by the RM.
* The caps table is an array of unsigned bytes.
*
* grRouteInfo
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*
* bCapsPopulated
* This parameter indicates that the capsTbl has been partially populated by
* previous calls to NV0080_CTRL_CMD_GR_GET_CAPS_V2 on other subdevices.
*/
#define NV0080_CTRL_CMD_GR_GET_CAPS_V2 (0x801109) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV0080_CTRL_GR_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE];
NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
NvBool bCapsPopulated;
} NV0080_CTRL_GR_GET_CAPS_V2_PARAMS;
#define NV0080_CTRL_CMD_GR_GET_INFO_V2 (0x801110) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV0080_CTRL_GR_GET_INFO_V2_PARAMS {
NvU32 grInfoListSize;
NV0080_CTRL_GR_INFO grInfoList[NV0080_CTRL_GR_INFO_MAX_SIZE];
NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
} NV0080_CTRL_GR_GET_INFO_V2_PARAMS;
/* _ctrl0080gr_h_ */

115
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h Normal file
View File

@@ -0,0 +1,115 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080host.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE host control commands and parameters */
/*
* NV0080_CTRL_CMD_HOST_GET_CAPS
*
* This command returns the set of host capabilities for the device
* in the form of an array of unsigned bytes. Host capabilities
* include supported features and required workarounds for the host-related
* engine(s) within the device, each represented by a byte offset into
* the table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_HOST_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the host caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_POINTER
*/
#define NV0080_CTRL_CMD_HOST_GET_CAPS (0x801401) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_HOST_INTERFACE_ID << 8) | NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_HOST_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0080_CTRL_HOST_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0080_CTRL_HOST_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0080_CTRL_HOST_CAPS_SEMA_ACQUIRE_BUG_105665 0:0x01
#define NV0080_CTRL_HOST_CAPS_DUP_CMPLT_BUG_126020 0:0x02
/*
* This bit indicates whether CPU mappings obtained with NvRmMapMemory() are
* coherent with the GPU. When this bit is _not_ set, all mappings are to the
* "raw" memory; i.e., they behave as it the NVOS33_FLAGS_MAPPING_DIRECT flag
* were used on a sysmem mapping.
*/
#define NV0080_CTRL_HOST_CAPS_GPU_COHERENT_MAPPING_SUPPORTED 0:0x04
#define NV0080_CTRL_HOST_CAPS_SYS_SEMA_DEADLOCK_BUG_148216 0:0x08
#define NV0080_CTRL_HOST_CAPS_SLOWSLI 0:0x10
#define NV0080_CTRL_HOST_CAPS_SEMA_READ_ONLY_BUG 0:0x20
#define NV0080_CTRL_HOST_CAPS_LARGE_NONCOH_UPSTR_WRITE_BUG_114871 0:0x40
#define NV0080_CTRL_HOST_CAPS_LARGE_UPSTREAM_WRITE_BUG_115115 0:0x80
#define NV0080_CTRL_HOST_CAPS_SEP_VIDMEM_PB_NOTIFIERS_BUG_83923 1:0x02
#define NV0080_CTRL_HOST_CAPS_P2P_4_WAY 1:0x08 // Deprecated
#define NV0080_CTRL_HOST_CAPS_P2P_8_WAY 1:0x10 // Deprecated
#define NV0080_CTRL_HOST_CAPS_P2P_DEADLOCK_BUG_203825 1:0x20 // Deprecated
#define NV0080_CTRL_HOST_CAPS_VIRTUAL_P2P 1:0x40
#define NV0080_CTRL_HOST_CAPS_BUG_254580 1:0x80
#define NV0080_CTRL_HOST_CAPS_COMPRESSED_BL_P2P_BUG_257072 2:0x02 // Deprecated
#define NV0080_CTRL_HOST_CAPS_CROSS_BLITS_BUG_270260 2:0x04 // Deprecated
/* unused 2:0x08 */
#define NV0080_CTRL_HOST_CAPS_MEM2MEM_BUG_365782 2:0x10
#define NV0080_CTRL_HOST_CAPS_CPU_WRITE_WAR_BUG_420495 2:0x20
#define NV0080_CTRL_HOST_CAPS_EXPLICIT_CACHE_FLUSH_REQD 2:0x40
#define NV0080_CTRL_HOST_CAPS_BAR1_READ_DEADLOCK_BUG_511418 2:0x80 // Deprecated
/* size in bytes of host caps table */
#define NV0080_CTRL_HOST_CAPS_TBL_SIZE 3
#define NV0080_CTRL_CMD_HOST_GET_CAPS_V2 (0x801402) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_HOST_INTERFACE_ID << 8) | NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_HOST_CAPS_TBL_SIZE];
} NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS;
/* _ctrl0080host_h_ */

106
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h Normal file
View File

@@ -0,0 +1,106 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080internal.finn
//
#include "nvlimits.h"
#include "ctrl0080gr.h"
#include "ctrl/ctrl0080/ctrl0080base.h"
#include "ctrl/ctrl0080/ctrl0080perf.h"
/*!
* @ref NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE
*/
#define NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE (0x802002) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID" */
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS {
NV_DECLARE_ALIGNED(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS params, 8);
} NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS;
/*!
* @ref NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE
*/
#define NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE (0x802003) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID" */
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS {
NV_DECLARE_ALIGNED(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS params, 8);
} NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS;
/*!
* @ref NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL
*/
#define NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL (0x802009) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID" */
/*!
* This command disables cuda limit activation at teardown of the client.
*/
#define NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x802004) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4" */
/*!
* @ref NV0080_CTRL_CMD_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL
*/
#define NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL (0x802007) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */
/*!
* @ref NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT
*/
#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS {
NvU8 powerDisconnectedGpuBus[NV_MAX_DEVICES];
NvU8 powerDisconnectedGpuCount;
} NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS;
/* ctrl0080internal_h */

76
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h Normal file
View File

@@ -0,0 +1,76 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080msenc.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE MSENC control commands and parameters */
/*
* NV0080_CTRL_CMD_MSENC_GET_CAPS
*
* This command returns the set of MSENC capabilities for the device
* in the form of an array of unsigned bytes. MSENC capabilities
* include supported features and required workarounds for the MSENC-related
* engine(s) within the device, each represented by a byte offset into
* the table and a bit position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0080_CTRL_MSENC_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the MSENC caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_MSENC_GET_CAPS (0x801b01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_MSENC_INTERFACE_ID << 8) | NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_MSENC_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0080_CTRL_MSENC_GET_CAPS_PARAMS;
/* size in bytes of MSENC caps table */
#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 4
/* _ctrl0080msenc_h_ */

78
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h Normal file
View File

@@ -0,0 +1,78 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE NVJPG control commands and parameters */
/*
* Size in bytes of NVJPG caps table. This value should be one greater
* than the largest byte_index value above.
*/
#define NV0080_CTRL_NVJPG_CAPS_TBL_SIZE 9
/*
* NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2
*
* This command returns the set of NVJPG capabilities for the device
* in the form of an array of unsigned bytes. NVJPG capabilities
* include supported features of the NVJPG engine(s) within the device,
* each represented by a byte offset into the table and a bit position within
* that byte.
*
* [out] capsTbl
* This caps table array is where the NVJPG caps bits will be transferred
* by the RM. The caps table is an array of unsigned bytes.
* instanceId
* This parameter specifies the instance Id of NVDEC for which
* cap bits are requested.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 (0x801f02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_NVJPG_INTERFACE_ID << 8) | NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE];
NvU32 instanceId;
} NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS;
/* _ctrl0080NVJPG_h_ */

50
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h Normal file
View File

@@ -0,0 +1,50 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080perf.finn
//
#define NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS {
NvBool bActivate;
} NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS;
#define NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS {
NvBool bCudaLimit;
} NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS;
/* _ctrl0080perf_h_ */

60
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h Normal file
View File

@@ -0,0 +1,60 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080rc.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */
/*
* NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK
*
* This command prevents RM from using callbacks when resetting a channel due
* to a page fault.
*
* Possible status return values are:
* NV_OK
*/
#define NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK (0x801d01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x1" */
/*
* NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK
*
* This command permits RM to use callbacks when resetting a channel due
* to a page fault.
*
* Possible status return values are:
* NV_OK
*/
#define NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK (0x801d02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x2" */
/* _ctrl0080rc_h_ */

107
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h Normal file
View File

@@ -0,0 +1,107 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080unix.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE UNIX-specific control commands and parameters */
/*
* NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH
*
* This command notifies RM to save or restore the current console state. It is
* intended to be called just before the display driver starts using the display
* engine, and after it has finished using it.
*
* cmd
* Indicates which operation should be performed.
*
* SAVE_VT_STATE
* Records the current state of the console, to be restored later.
* RESTORE_VT_STATE
* Restores the previously-saved console state.
*
* fbInfo
* Returns information about the system's framebuffer console, if one
* exists. If no console is present, all fields will be zero.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH (0x801e01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID" */
typedef struct NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO {
NvU32 subDeviceInstance;
NvU16 width;
NvU16 height;
NvU16 depth;
NvU16 pitch;
} NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO;
#define NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS {
NvU32 cmd; /* in */
NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO fbInfo; /* out */
} NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS;
/* Called when the display driver needs RM to save the console data,
* which will be used in RM based console restore */
#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE (0x00000001)
/* Called when the display driver needs RM to restore the console */
#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE (0x00000002)
/* Called when the display driver has restored the console -- RM doesn't
* need to do anything further, but needs to be informed to avoid turning the
* GPU off and thus destroying the console state. */
#define NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED (0x00000003)
#define NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO (0x801e02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS {
NvU32 subDeviceInstance; /* out */
NvU16 width; /* out */
NvU16 height; /* out */
NvU16 depth; /* out */
NvU16 pitch; /* out */
} NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS;
/* _ctrl0080unix_h_ */