NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-03-03 12:20:11 +00:00
Code Issues Packages Projects Releases Wiki Activity

515.43.04

Browse Source
This commit is contained in:
Andy Ritger
2022-05-09 13:18:59 -07:00
commit 1739a20efc
2519 changed files with 1060036 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080acr.finn
//

115
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h Normal file
View File

@@ -0,0 +1,115 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV20_SUBDEVICE_XX control commands and parameters */
#define NV2080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x2080, NV2080_CTRL_##cat, idx)
/* Subdevice command categories (6bits) */
#define NV2080_CTRL_RESERVED (0x00)
#define NV2080_CTRL_GPU (0x01)
#define NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED (0x81) /* finn: Evaluated from "(NV2080_CTRL_GPU | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_FUSE (0x02)
#define NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED (0x82) /* finn: Evaluated from "(NV2080_CTRL_FUSE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_EVENT (0x03)
#define NV2080_CTRL_TIMER (0x04)
#define NV2080_CTRL_THERMAL (0x05)
#define NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED (0xc5) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED (0x85) /* finn: Evaluated from "(NV2080_CTRL_THERMAL | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_I2C (0x06)
#define NV2080_CTRL_EXTI2C (0x07)
#define NV2080_CTRL_BIOS (0x08)
#define NV2080_CTRL_CIPHER (0x09)
#define NV2080_CTRL_INTERNAL (0x0A)
#define NV2080_CTRL_CLK_LEGACY_PRIVILEGED (0xd0) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED (0x90) /* finn: Evaluated from "(NV2080_CTRL_CLK | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_CLK (0x10)
#define NV2080_CTRL_FIFO (0x11)
#define NV2080_CTRL_GR (0x12)
#define NV2080_CTRL_FB (0x13)
#define NV2080_CTRL_MC (0x17)
#define NV2080_CTRL_BUS (0x18)
#define NV2080_CTRL_PERF_LEGACY_PRIVILEGED (0xe0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED (0xa0) /* finn: Evaluated from "(NV2080_CTRL_PERF | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_PERF (0x20)
#define NV2080_CTRL_NVIF (0x21)
#define NV2080_CTRL_RC (0x22)
#define NV2080_CTRL_GPIO (0x23)
#define NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED (0xa3) /* finn: Evaluated from "(NV2080_CTRL_GPIO | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_NVD (0x24)
#define NV2080_CTRL_DMA (0x25)
#define NV2080_CTRL_PMGR (0x26)
#define NV2080_CTRL_PMGR_LEGACY_PRIVILEGED (0xe6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED (0xa6) /* finn: Evaluated from "(NV2080_CTRL_PMGR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_POWER (0x27)
#define NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED (0xa7) /* finn: Evaluated from "(NV2080_CTRL_POWER | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_LPWR (0x28)
#define NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED (0xa8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_LPWR_LEGACY_PRIVILEGED (0xe8) /* finn: Evaluated from "(NV2080_CTRL_LPWR | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV2080_CTRL_ACR (0x29)
#define NV2080_CTRL_CE (0x2A)
#define NV2080_CTRL_SPI (0x2B)
#define NV2080_CTRL_NVLINK (0x30)
#define NV2080_CTRL_FLCN (0x31)
#define NV2080_CTRL_VOLT (0x32)
#define NV2080_CTRL_VOLT_LEGACY_PRIVILEGED (0xf2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED (0xb2) /* finn: Evaluated from "(NV2080_CTRL_VOLT | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_FAS (0x33)
#define NV2080_CTRL_ECC (0x34)
#define NV2080_CTRL_ECC_NON_PRIVILEGED (0xb4) /* finn: Evaluated from "(NV2080_CTRL_ECC | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_FLA (0x35)
#define NV2080_CTRL_GSP (0x36)
#define NV2080_CTRL_NNE (0x37)
#define NV2080_CTRL_GRMGR (0x38)
#define NV2080_CTRL_UCODE_FUZZER (0x39)
#define NV2080_CTRL_DMABUF (0x3A)
// per-OS categories start at highest category and work backwards
#define NV2080_CTRL_OS_WINDOWS (0x3F)
#define NV2080_CTRL_OS_MACOS (0x3E)
#define NV2080_CTRL_OS_UNIX (0x3D)
/*
* NV2080_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_NULL (0x20800000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID << 8) | 0x0" */
/* _ctrl2080base_h_ */

242
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h Normal file
View File

@@ -0,0 +1,242 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080bios.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX bios-related control commands and parameters */
typedef struct NV2080_CTRL_BIOS_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_BIOS_INFO;
/* Maximum number of bios infos that can be queried at once */
#define NV2080_CTRL_BIOS_INFO_MAX_SIZE (0x0000000F)
#define NV2080_CTRL_BIOS_INFO_INDEX_REVISION (0x00000000)
#define NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION (0x00000001)
/*
* NV2080_CTRL_CMD_BIOS_GET_INFO
*
* This command returns bios information for the associated GPU.
* Requests to retrieve bios information use a list of one or more
* NV2080_CTRL_BIOS_INFO structures.
*
* biosInfoListSize
* This field specifies the number of entries on the caller's
* biosInfoList.
* biosInfoList
* This field specifies a pointer in the caller's address space
* to the buffer into which the bios information is to be returned.
* This buffer must be at least as big as biosInfoListSize multiplied
* by the size of the NV2080_CTRL_BIOS_INFO structure.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV2080_CTRL_CMD_BIOS_GET_INFO (0x20800802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | 0x2" */
typedef struct NV2080_CTRL_BIOS_GET_INFO_PARAMS {
NvU32 biosInfoListSize;
NV_DECLARE_ALIGNED(NvP64 biosInfoList, 8);
} NV2080_CTRL_BIOS_GET_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_BIOS_GET_INFO_V2
*
* This command returns bios information for the associated GPU.
* Requests to retrieve bios information use a list of one or more
* NV2080_CTRL_BIOS_INFO structures.
*
* biosInfoListSize
* This field specifies the number of entries on the caller's
* biosInfoList.
* biosInfoList
* Bios information to be returned.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV2080_CTRL_CMD_BIOS_GET_INFO_V2 (0x20800810) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS {
NvU32 biosInfoListSize;
NV2080_CTRL_BIOS_INFO biosInfoList[NV2080_CTRL_BIOS_INFO_MAX_SIZE];
} NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS;
/*
* NV2080_CTRL_CMD_BIOS_GET_SKU_INFO
*
* This command returns information about the current board SKU.
* NV_ERR_INVALID_OWNER will be returned if the call
* isn't made with the OS as the administrator.
*
* chipSKU
* This field returns the sku for the current chip.
* chipSKUMod
* This field returns the SKU modifier.
* project
* This field returns the Project (Board) number.
* projectSKU
* This field returns the Project (Board) SKU number.
* CDP
* This field returns the Collaborative Design Project Number.
* projectSKUMod
* This field returns the Project (Board) SKU Modifier.
* businessCycle
* This field returns the business cycle the board is associated with.
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_OWNER
*/
#define NV2080_CTRL_CMD_BIOS_GET_SKU_INFO (0x20800808) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID" */
/* maximum length of parameter strings */
#define NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS {
NvU32 BoardID;
char chipSKU[4];
char chipSKUMod[2];
char project[5];
char projectSKU[5];
char CDP[6];
char projectSKUMod[2];
NvU32 businessCycle;
} NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_BIOS_GET_POST_TIME
* This command is used to get the GPU POST time (in milliseconds).
* If the associated GPU is the master GPU this value will be recorded
* by the VBIOS and retrieved from the KDA buffer. If the associated
* GPU is a secondaryGPU then this value will reflect the devinit
* processing time.
*
* vbiosPostTime
* This parameter returns the vbios post time in msec.
*
* Possible return status values are
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME (0x20800809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS {
NV_DECLARE_ALIGNED(NvU64 vbiosPostTime, 8);
} NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS;
/*
* NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT
*
* This function is used to give out the UEFI version, UEFI image presence and
* Graphics Firmware Mode i.e. whether system is running in UEFI or not.
*
* version
* This parameter returns the UEFI version.
*
* flags
* This parameter indicates UEFI image presence and Graphics Firmware mode.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE
* This field returns UEFI presence value. Legal values for this
* field include:
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO
* This value indicates that UEFI image is not present.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES
* This value indicates that UEFI image is present.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER
* This value indicates that there is a dummy UEFI placeholder,
* which can later be updated with a valid UEFI image.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN
* This value indicates that UEFI image is hidden.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING
* This field indicates the UEFI running value. Legal values for
* this parameter include:
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE
* This value indicates that UEFI is not running.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE
* This value indicates that UEFI is running.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_READY
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT (0x2080080b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS {
NvU32 version;
NvU32 flags;
} NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS;
/* Legal values for flags parameter */
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE 1:0
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO (0x00000000)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES (0x00000001)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER (0x00000002)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN (0x00000003)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING 2:2
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE (0x00000000)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE (0x00000001)
/* _ctrl2080bios_h_ */

35
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h"

34
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h Normal file
View File

@@ -0,0 +1,34 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn
//
#include "nvtypes.h"

1294
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h Normal file
View File

File diff suppressed because it is too large Load Diff

309
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h Normal file
View File

@@ -0,0 +1,309 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080ce.finn
//
/* NV20_SUBDEVICE_XX ce control commands and parameters */
#include "ctrl2080common.h"
/*
* NV2080_CTRL_CMD_CE_GET_CAPS
*
* This command returns the set of CE capabilities for the device
* in the form of an array of unsigned bytes.
*
* ceEngineType
* This parameter specifies the copy engine type
* capsTblSize
* This parameter specifies the size in bytes of the caps table per CE.
* This value should be set to NV2080_CTRL_CE_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the CE caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_CE_GET_CAPS (0x20802a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID" */
/*
* Size in bytes of CE caps table. This value should be one greater
* than the largest byte_index value below.
*/
#define NV2080_CTRL_CE_CAPS_TBL_SIZE 2
#define NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_CE_GET_CAPS_PARAMS {
NvU32 ceEngineType;
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV2080_CTRL_CE_GET_CAPS_PARAMS;
#define NV2080_CTRL_CMD_CE_GET_CAPS_V2 (0x20802a03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
NvU32 ceEngineType;
NvU8 capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE];
} NV2080_CTRL_CE_GET_CAPS_V2_PARAMS;
/* extract cap bit setting from tbl */
#define NV2080_CTRL_CE_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV2080_CTRL_CE_CAPS_CE_GRCE 0:0x01
#define NV2080_CTRL_CE_CAPS_CE_SHARED 0:0x02
#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ 0:0x04
#define NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE 0:0x08
#define NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P 0:0x10
#define NV2080_CTRL_CE_CAPS_CE_SYSMEM 0:0x20
#define NV2080_CTRL_CE_CAPS_CE_P2P 0:0x40
#define NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED 0:0x80
#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 1:0x01
#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 1:0x02
/*
* NV2080_CTRL_CE_CAPS_CE_GRCE
* Set if the CE is synchronous with GR
*
* NV2080_CTRL_CE_CAPS_CE_SHARED
* Set if the CE shares physical CEs with any other CE
*
* NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ
* Set if the CE can give enhanced performance for SYSMEM reads over other CEs
*
* NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE
* Set if the CE can give enhanced performance for SYSMEM writes over other CEs
*
* NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P
* Set if the CE can be used for P2P transactions using NVLINK
* Once a CE is exposed for P2P over NVLINK, it will remain available for the life of RM
* PCE2LCE mapping may change based on the number of GPUs registered in RM however
*
* NV2080_CTRL_CE_CAPS_CE_SYSMEM
* Set if the CE can be used for SYSMEM transactions
*
* NV2080_CTRL_CE_CAPS_CE_P2P
* Set if the CE can be used for P2P transactions
*
* NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED
* Set if the CE supports BL copy size greater than 64K
*
* NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL
* Set if the CE supports non-pipelined Block linear
*
* NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL
* Set if the CE supports pipelined Block Linear
*/
/*
* NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK
*
* This command returns the mapping of PCE's for the given LCE
*
* ceEngineType
* This parameter specifies the copy engine type
* pceMask
* This parameter specifies a mask of PCEs that correspond
* to the LCE specified in ceEngineType
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS {
NvU32 ceEngineType;
NvU32 pceMask;
} NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS;
/*
* NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG
*
* This command sets the PCE2LCE configuration
*
* pceLceConfig[NV2080_CTRL_MAX_PCES]
* This parameter specifies the PCE-LCE mapping requested
* grceLceConfig[NV2080_CTRL_MAX_GRCES]
* This parameter specifies which LCE is the GRCE sharing with
* 0xF -> Does not share with any LCE
* 0-MAX_LCE -> Shares with the given LCE
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MAX_PCES 18
#define NV2080_CTRL_MAX_GRCES 2
#define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS {
NvU32 ceEngineType;
NvU32 pceLceMap[NV2080_CTRL_MAX_PCES];
NvU32 grceSharedLceMap[NV2080_CTRL_MAX_GRCES];
} NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS;
/*
* NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS
*
* This command updates the PCE-LCE mappings
*
* pPceLceMap [IN]
* This parameter tracks the array of PCE-LCE mappings.
*
* pGrceConfig [IN]
* This parameter tracks the array of GRCE configs.
* 0xF -> GRCE does not share with any LCE
* 0-MAX_LCE -> GRCE shares with the given LCE
*
* exposeCeMask [IN]
* This parameter specifies the mask of LCEs to export to the
* clients after the update.
*
* bUpdateNvlinkPceLce [IN]
* Whether PCE-LCE mappings need to be updated for nvlink topology.
* If this is NV_FALSE, RM would ignore the above values. However,
* PCE-LCE mappings will still be updated if there were any regkey
* overrides.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS {
NvU32 pceLceMap[NV2080_CTRL_MAX_PCES];
NvU32 grceConfig[NV2080_CTRL_MAX_GRCES];
NvU32 exposeCeMask;
NvBool bUpdateNvlinkPceLce;
} NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS;
#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS {
NvU32 stubbedCeMask;
} NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS;
/*
* NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS
*
* Query _CE_GRCE, _CE_SHARED, _CE_SUPPORTS_PIPELINED_BL, _CE_SUPPORTS_NONPIPELINED_BL bits of CE
* capabilities.
*
*/
#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0x7" */
#define NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS {
NvU32 size;
} NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS;
#define NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE (0x20802a08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASKS
*
* Get HSHUB and FBHUB PCE masks.
*
* [out] hshubPceMasks
* PCE mask for each HSHUB
* [out] fbhubPceMask
* FBHUB PCE mask
*/
#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK (0x20802a09) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_MAX_HSHUBS 5
#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS {
NvU32 hshubPceMasks[NV2080_CTRL_CE_MAX_HSHUBS];
NvU32 fbhubPceMask;
} NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS;
/*
* NV2080_CTRL_CMD_CE_GET_ALL_CAPS
*
* Query caps of all CEs.
*
* [out] capsTbl
* Array of CE caps in the order of CEs. The caps bits interpretation is the same as in
* NV2080_CTRL_CMD_CE_GET_CAPS.
* [out] present
* Bit mask indicating which CEs are usable by the client and have their caps indicated in capsTbl.
* If a CE is not marked present, its caps bits should be ignored.
* If client is subscribed to a MIG instance, only the CEs present in the instance are tagged as such.
*/
#define NV2080_CTRL_CMD_CE_GET_ALL_CAPS (0x20802a0a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID (0xaU)
typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS {
NvU8 capsTbl[NV2080_CTRL_MAX_PCES][NV2080_CTRL_CE_CAPS_TBL_SIZE];
NvU32 present;
} NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS;
#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0xb" */
/* _ctrl2080ce_h_ */

32
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080cipher.finn
//

43
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h Normal file
View File

@@ -0,0 +1,43 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080clk.finn
//
/* _ctrl2080clk_h_ */
#include "nvfixedtypes.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobj.h"
#include "ctrl/ctrl2080/ctrl2080gpumon.h"
#include "ctrl/ctrl2080/ctrl2080clkavfs.h"
#include "ctrl/ctrl2080/ctrl2080volt.h"
#include "ctrl/ctrl2080/ctrl2080pmumon.h"

39
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h Normal file
View File

@@ -0,0 +1,39 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobj.h"
#include "ctrl/ctrl2080/ctrl2080volt.h"

34
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080common.h Normal file
View File

@@ -0,0 +1,34 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2004 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080common.finn
//
#define NV2080_CTRL_CMD_MAX_HEADS 2

188
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h Normal file
View File

@@ -0,0 +1,188 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080dma.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX dma control commands and parameters */
#include "ctrl2080common.h"
/*
* NV2080_CTRL_CMD_DMA_INVALIDATE_TLB
*
* This command invalidates the GPU TLB. This is intended to be used
* by RM clients that manage their own TLB consistency when updating
* page tables on their own, or with DEFER_TLB_INVALIDATION options
* to other RM APIs.
*
* hVASpace
* This parameter specifies the VASpace object whose MMU TLB entries needs to be invalidated.
* Specifying a GMMU VASpace object handle will invalidate the GMMU TLB for the particular VASpace.
* Specifying a SMMU VASpace object handle will flush the entire SMMU TLB & PTC.
*
* This call can be used with the NV50_DEFERRED_API_CLASS (class 0x5080).
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_TIMEOUT_RETRY
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_DMA_INVALIDATE_TLB (0x20802502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS {
NvHandle hClient; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
NvHandle hDevice; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
NvU32 engine; // Deprecated. Kept here for compactibility with chips_GB9-2-1-1
NvHandle hVASpace;
} NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS;
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS 0:0
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO 1:1
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY 2:2
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE 3:3
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB 4:4
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV 5:5
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG 6:6
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD 7:7
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION 8:8
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON 9:9
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS 10:10
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE (0x00000001)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR 11:11
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE (0x00000000)
#define NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE (0x00000001)
/*
* NV2080_CTRL_DMA_INFO
*
* This structure represents a single 32bit dma engine value. Clients
* request a particular DMA engine value by specifying a unique dma
* information index.
*
* Legal dma information index values are:
* NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
* This index can be used to request the system address size in bits.
*/
typedef struct NV2080_CTRL_DMA_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_DMA_INFO;
/* valid dma info index values */
#define NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE (0x000000000)
/* set INDEX_MAX to greatest possible index value */
#define NV2080_CTRL_DMA_INFO_INDEX_MAX NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
/*
* NV2080_CTRL_CMD_DMA_GET_INFO
*
* This command returns dma engine information for the associated GPU.
* Requests to retrieve dma information use an array of one or more
* NV2080_CTRL_DMA_INFO structures.
*
* dmaInfoTblSize
* This field specifies the number of valid entries in the dmaInfoList
* array. This value cannot exceed NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES.
* dmaInfoTbl
* This parameter contains the client's dma info table into
* which the dma info values will be transferred by the RM.
* The dma info table is an array of NV2080_CTRL_DMA_INFO structures.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_DMA_GET_INFO (0x20802503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMA_INTERFACE_ID << 8) | NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID" */
/* maximum number of NV2080_CTRL_DMA_INFO entries per request */
#define NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES (256)
#define NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_DMA_GET_INFO_PARAMS {
NvU32 dmaInfoTblSize;
/*
* C form:
* NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES];
*/
NV2080_CTRL_DMA_INFO dmaInfoTbl[NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES];
} NV2080_CTRL_DMA_GET_INFO_PARAMS;
typedef struct NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO {
/*!
* 64KB aligned address of source 64KB tile for comptag reswizzle.
*/
NvU32 srcAddr;
/*!
* 64KB aligned address of destination 64KB tile for comptag reswizzle.
*/
NvU32 dstAddr;
/*!
* Comptag index assigned to the 64K sized tile relative to
* the compcacheline. Absolute comptag index would be:
* startComptagIndex + relComptagIndex.
*/
NvU16 relComptagIndex;
} NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO;
// _ctrl2080dma_h_

105
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h Normal file
View File

@@ -0,0 +1,105 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn
//
/*
* NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD
*
* Exports RM vidmem handles to a dma-buf fd.
*
* The objects in the 'handles' array are exported to the fd as range:
* [index, index + numObjects).
*
* A dma-buf fd is created the first time this control call is called.
* The fd is an input parameter for subsequent calls to attach additional handles
* over NV2080_CTRL_DMABUF_MAX_HANDLES.
*
* fd
* A dma-buf file descriptor. If -1, a new FD will be created.
*
* totalObjects
* The total number of objects that the client wishes to export to the FD.
* This parameter will be honored only when the FD is getting created.
*
* numObjects
* The number of handles the user wishes to export in this call.
*
* index
* The index into the export fd at which to start exporting the handles in
* 'handles'. This index cannot overlap a previously used index.
*
* totalSize
* The total size of memory being exported in bytes, needed to create the dma-buf.
* This size includes the memory that will be exported in future export calls
* for this dma-buf.
*
* handles
* An array of {handle, offset, size} that describes the dma-buf.
* The offsets and sizes must be OS page-size aligned.
*
* Limitations:
* 1. This call only supports vidmem objects for now.
* 2. All memory handles should belong to the same GPU or the same GPU MIG instance.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_NO_MEMORY
* NV_ERR_OPERATING_SYSTEM
* NV_ERR_IN_USE
* NV_ERR_INVALID_OBJECT
* NV_ERR_INVALID_OBJECT_PARENT
*/
#define NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD (0x20803a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID << 8) | NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_DMABUF_MAX_HANDLES 128
typedef struct NV2080_CTRL_DMABUF_MEM_HANDLE_INFO {
NvHandle hMemory;
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
} NV2080_CTRL_DMABUF_MEM_HANDLE_INFO;
#define NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS {
NvS32 fd;
NvU32 totalObjects;
NvU32 numObjects;
NvU32 index;
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_DMABUF_MEM_HANDLE_INFO handles[NV2080_CTRL_DMABUF_MAX_HANDLES], 8);
} NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS;
// _ctrl2080dmabuf_h_

66
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h Normal file
View File

@@ -0,0 +1,66 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080ecc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#define NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS (0x20803400) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS
*
* sramLastClearedTimestamp [out]
* dramLastClearedTimestamp [out]
* unix-epoch based timestamp. These fields indicate when the error counters
* were last cleared by the user.
*
* sramErrorCounts [out]
* dramErrorCounts [out]
* Aggregate error counts for SRAM and DRAM
*/
#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U)
typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS {
NvU32 sramLastClearedTimestamp;
NvU32 dramLastClearedTimestamp;
NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotalCounts, 8);
NV_DECLARE_ALIGNED(NvU64 sramUncorrectedTotalCounts, 8);
NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotalCounts, 8);
NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotalCounts, 8);
} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS;
/* _ctrl2080ecc_h_ */

375
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h Normal file
View File

@@ -0,0 +1,375 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080event.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "nv_vgpu_types.h"
/* NV20_SUBDEVICE_XX event-related control commands and parameters */
/*
* NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* This command sets event notification state for the associated subdevice.
* This command requires that an instance of NV01_EVENT has been previously
* bound to the associated subdevice object.
*
* event
* This parameter specifies the type of event to which the specified
* action is to be applied. This parameter must specify a valid
* NV2080_NOTIFIERS value (see cl2080.h for more details) and should
* not exceed one less NV2080_NOTIFIERS_MAXCOUNT.
* action
* This parameter specifies the desired event notification action.
* Valid notification actions include:
* NV2080_CTRL_SET_EVENT_NOTIFICATION_DISABLE
* This action disables event notification for the specified
* event for the associated subdevice object.
* NV2080_CTRL_SET_EVENT_NOTIFICATION_SINGLE
* This action enables single-shot event notification for the
* specified event for the associated subdevice object.
* NV2080_CTRL_SET_EVENT_NOTIFICATION_REPEAT
* This action enables repeated event notification for the specified
* event for the associated system controller object.
* bNotifyState
* This boolean is used to indicate the current state of the notifier
* at the time of event registration. This is optional and its semantics
* needs to be agreed upon by the notifier and client using the notifier
* info32
* This is used to send 32-bit initial state info with the notifier at
* time of event registration
* info16
* This is used to send 16-bit initial state info with the notifier at
* time of event registration
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION (0x20800301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
NvU32 event;
NvU32 action;
NvBool bNotifyState;
NvU32 info32;
NvU16 info16;
} NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
/* XUSB/PPC D-state defines */
#define NV2080_EVENT_DSTATE_XUSB_D0 (0x00000000)
#define NV2080_EVENT_DSTATE_XUSB_D3 (0x00000003)
#define NV2080_EVENT_DSTATE_XUSB_INVALID (0xFFFFFFFF)
#define NV2080_EVENT_DSTATE_PPC_D0 (0x00000000)
#define NV2080_EVENT_DSTATE_PPC_D3 (0x00000003)
#define NV2080_EVENT_DSTATE_PPC_INVALID (0xFFFFFFFF)
// HDACODEC Decice DState, D3_COLD is only for verbose mapping, it cannot be logged
typedef enum NV2080_EVENT_HDACODEC_DSTATE {
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0 = 0,
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1 = 1,
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2 = 2,
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT = 3,
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD = 4,
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX = 5,
} NV2080_EVENT_HDACODEC_DSTATE;
/*
* NV2080_CTRL_CMD_EVENT_SET_TRIGGER
*
* This command triggers a software event for the associated subdevice.
* This command accepts no parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER (0x20800302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | 0x2" */
/*
* NV2080_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY
*
* hMemory
* This parameter specifies the handle of the memory object
* that identifies the memory address translation for this
* subdevice instance's notification(s). The beginning of the
* translation points to an array of notification data structures.
* The size of the translation must be at least large enough to hold the
* maximum number of notification data structures identified by
* the NV2080_MAX_NOTIFIERS value.
* Legal argument values must be instances of the following classes:
* NV01_NULL
* NV04_MEMORY
* When hMemory specifies the NV01_NULL_OBJECT value then any existing
* memory translation connection is cleared. There must not be any
* pending notifications when this command is issued.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x20800303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS {
NvHandle hMemory;
} NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS;
#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0
#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1
#define NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2
/*
* NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY
*
* hSemMemory
* This parameter specifies the handle of the memory object that
* identifies the semaphore memory associated with this subdevice
* event notification. Once this is set RM will generate an event
* only when there is a change in the semaphore value. It is
* expected that the semaphore memory value will be updated by
* the GPU indicating that there is an event pending. This
* command is used by VGX plugin to determine which virtual
* machine has generated a particular event.
*
* semOffset
* This parameter indicates the memory offset of the semaphore.
*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY (0x20800304) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS {
NvHandle hSemMemory;
NvU32 semOffset;
} NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI
*
* hSemMemory
* This parameter specifies the handle of the memory object that
* identifies the semaphore memory associated with this subdevice
* event notification. Once this is set RM will generate an event
* only when there is a change in the semaphore value. It is
* expected that the semaphore memory value will be updated by
* the GPU indicating that there is an event pending. This
* command is used by VGX plugin to determine which virtual
* machine has generated a particular event.
*
* guestMSIAddr
* This parameter indicates the guest allocated MSI address.
*
* guestMSIData
* This parameter indicates the MSI data set by the guest OS.
*
* vmIdType
* This parameter specifies the type of guest virtual machine identifier
*
* guestVmId
* This parameter specifies the guest virtual machine identifier
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI (0x20800305) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS {
NV_DECLARE_ALIGNED(NvU64 guestMSIAddr, 8);
NvU32 guestMSIData;
NvHandle hSemMemory;
NvBool isReset;
VM_ID_TYPE vmIdType;
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
} NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION
*
* hSemMemory
* This parameter specifies the handle of the memory object that
* identifies the semaphore memory associated with this subdevice
* event notification. Once this is set RM will generate an event
* only when there is a change in the semaphore value. It is
* expected that the semaphore memory value will be updated by
* the GPU indicating that there is an event pending. This
* command is used by VGX plugin to determine which virtual
* machine has generated a particular event.
*
* isSemaMemValidationEnabled
* This parameter used to enable/disable change in sema value check
* while generating an event.
*
* Possible status values returned are:
* NVOS_STATUS_SUCCESS
* NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE
* NVOS_STATUS_ERROR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION (0x20800306) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS {
NvHandle hSemMemory;
NvBool isSemaMemValidationEnabled;
} NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL
*
* hSemMemory
* This parameter specifies the handle of the memory object that
* identifies the semaphore memory associated with this subdevice
* event notification. Once this is set RM will generate an event
* only when there is a change in the semaphore value. It is
* expected that the semaphore memory value will be updated by
* the GPU indicating that there is an event pending. This
* command is used by VGX plugin to determine which virtual
* machine has generated a particular event.
*
* vmIdType
* This parameter specifies the type of guest virtual machine identifier
*
* guestVmId
* This parameter specifies the guest virtual machine identifier
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL (0x20800307) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS {
NvHandle hSemMemory;
VM_ID_TYPE vmIdType;
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
} NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO
*
* This command triggers a FIFO event for the associated subdevice.
*
* hEvent
* Handle of the event that should be notified. If zero, all
* non-stall interrupt events for this subdevice will be notified.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO (0x20800308) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS {
NvHandle hEvent;
} NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF_FOR_UID
*
* This command is used to create a video bind-point to an event buffer that
* is filtered by UID.
*
* hEventBuffer[IN]
* The event buffer to bind to
*
* recordSize[IN]
* The size of the FECS record in bytes
*
* levelOfDetail[IN]
* One of NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_:
* FULL: Report all CtxSw events
* SIMPLE: Report engine start and engine end events only
* CUSTOM: Report events in the eventFilter field
* NOTE: RM may override the level-of-detail depending on the caller
*
* eventFilter[IN]
* Bitmask of events to report if levelOfDetail is CUSTOM
*
* bAllUsers[IN]
* Only report video data for the current user if false, for all users if true
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF (0x20800309) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD {
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL = 0,
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE = 1,
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM = 2,
} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD;
#define NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS {
NvHandle hEventBuffer;
NvU32 recordSize;
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD levelOfDetail;
NvU32 eventFilter;
NvBool bAllUsers;
} NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS;
/* _ctrl2080event_h_ */

32
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fan.finn
//

2910
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h Normal file
View File

File diff suppressed because it is too large Load Diff

762
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h Normal file
View File

@@ -0,0 +1,762 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fifo.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*
* NV2080_CTRL_CMD_SET_GPFIFO
*
* This command set the GPFIFO offset and number of entries for a channel
* after it has been allocated. The channel must be idle and not pending,
* otherwise ERROR_IN_USE will be returned.
*
* hChannel
* The handle to the channel.
* base
* The base of the GPFIFO in the channel ctxdma.
* numEntries
* The number of entries in the GPFIFO.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_CHANNEL
* NV_ERR_STATE_IN_USE
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV2080_CTRL_CMD_SET_GPFIFO (0x20801102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_CMD_SET_GPFIFO_PARAMS {
NvHandle hChannel;
NV_DECLARE_ALIGNED(NvU64 base, 8);
NvU32 numEntries;
} NV2080_CTRL_CMD_SET_GPFIFO_PARAMS;
/*
* NV2080_CTRL_FIFO_BIND_CHANNEL
*
* This structure is used to describe a channel that is to have
* it's bindable engines bound to those of other channels.
*
* hClient
* This structure member contains the handle of the client object
* that owns the channel object specified by hChannel.
*
* hChannel
* This structure member contains the channel handle of the channel
* object.
*/
typedef struct NV2080_CTRL_FIFO_BIND_CHANNEL {
NvHandle hClient;
NvHandle hChannel;
} NV2080_CTRL_FIFO_BIND_CHANNEL;
/*
* NV2080_CTRL_CMD_FIFO_BIND_ENGINES
*
* This control call is now deprecated.
* This command can be used to bind different video engines on G8X from separate
* channels together for operations such as idling. The set of bindable engines
* includes the NV2080_ENGINE_TYPE_BSP, NV2080_ENGINE_TYPE_VP and
* NV2080_ENGINE_TYPE_PPP engines.
*
* bindChannelCount
* This parameter specifies the number of channels to bind together. This
* parameter cannot exceed NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS.
*
* bindChannels
* The parameter specifies the array of channels to bind together. The first
* bindChannelCount entries are used in the bind channel operation.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_CHANNEL
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS (16)
#define NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS {
NvU32 bindChannelCount;
NV2080_CTRL_FIFO_BIND_CHANNEL bindChannels[NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS];
} NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS;
#define NV2080_CTRL_CMD_FIFO_BIND_ENGINES (0x20801103) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES
*
* This command is used for a client to setup specialized custom operational
* properties that may be specific to an environment, or properties that
* should be set generally but are not for reasons of backward compatibility
* with previous chip generations
*
* flags
* This field specifies the operational properties to be applied
*
* Possible return status values returned are
* NV_OK
* NV_ERR_INVALID_CHANNEL
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES (0x20801104) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS {
NvU32 flags;
} NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS;
#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE 0:0
#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE (0x00000000)
#define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE (0x00000001)
/*
* NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT
*
* This command returns the maximum number of physical channels available for
* allocation on the current GPU. This may be less than or equal to the total
* number of channels supported by the current hardware.
*
* physChannelCount
* This output parameter contains the maximum physical channel count.
*
* physChannelCountInUse
* This output parameter contains the number of physical channels in use
*
* Possible return status values returned are
* NV_OK
*
*/
#define NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT (0x20801108) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS {
NvU32 physChannelCount;
NvU32 physChannelCountInUse;
} NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS;
/*
* NV2080_CTRL_FIFO_INFO
*
* This structure represents a single 32bit fifo engine value. Clients
* request a particular FIFO engine value by specifying a unique fifo
* information index.
*
* Legal fifo information index values are:
* NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL
* This index can be used to request the amount of instance space
* in kilobytes reserved by the fifo engine.
* NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS
* This index can be used to query the maximum number of channel groups
* that can be allocated on the GPU.
* NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP
* This index can be used to query the maximum number of channels that can
* be allocated in a single channel group.
* NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP
* This index can be used to query the maximum number of subcontext that can
* be allocated in a single channel group.
* NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET
* This index can be used to query the starting offset of the RM
* pre-allocated USERD range in BAR1. This index query is honored only
* on Legacy-vGPU host RM.
* NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE
* This index can be used to query the default timeslice value
* (microseconds) used for a channel or channel group.
* NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE
* This index can be used to query the number of channel groups that are
* already allocated on the GPU.
* NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED
* This index can be used to check if per runlist channel ram is supported, and
* to query the supported number of channels per runlist.
* NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE
* This index can be used to get max channel groups supported per engine/runlist.
* NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE
* This index can be used too get channel groups currently in use per engine/runlist.
*
*/
typedef struct NV2080_CTRL_FIFO_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_FIFO_INFO;
/* valid fifo info index values */
#define NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL (0x000000000)
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS (0x000000001)
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP (0x000000002)
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP (0x000000003)
#define NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET (0x000000004)
#define NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE (0x000000005)
#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE (0x000000006)
#define NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED (0x000000007)
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE (0x000000008)
#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE (0x000000009)
/* set INDEX_MAX to greatest possible index value */
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE
#define NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT (12)
/*
* NV2080_CTRL_CMD_FIFO_GET_INFO
*
* This command returns fifo engine information for the associated GPU.
* Requests to retrieve fifo information use an array of one or more
* NV2080_CTRL_FIFO_INFO structures.
*
* fifoInfoTblSize
* This field specifies the number of valid entries in the fifoInfoList
* array. This value cannot exceed NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES.
* fifoInfoTbl
* This parameter contains the client's fifo info table into
* which the fifo info values will be transferred by the RM.
* The fifo info table is an array of NV2080_CTRL_FIFO_INFO structures.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_GET_INFO (0x20801109) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID" */
/* maximum number of NV2080_CTRL_FIFO_INFO entries per request */
#define NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES (256)
#define NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_FIFO_GET_INFO_PARAMS {
NvU32 fifoInfoTblSize;
/*
* C form:
* NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES];
*/
NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES];
NvU32 engineType;
} NV2080_CTRL_FIFO_GET_INFO_PARAMS;
/*
* NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL
*
* This command removes the specified channel from the associated GPU's runlist
* and then initiates RC recovery. If the channel is active it will first be preempted.
* hChannel
* The handle to the channel to be preempted.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_CHANNEL
*/
#define NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL (0x2080110a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS {
NvHandle hChannel;
} NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS
*
* This command will disable or enable scheduling of channels described in the
* list provided. Whether or not the channels are also preempted off the GPU
* can be controlled by bOnlyDisableScheduling. By default channels are preempted
* off the GPU.
*
* bDisable
* This value determines whether to disable or
* enable the set of channels.
* numChannels
* The number of channels to be stopped.
* bOnlyDisableScheduling
* When false and bDisable=NV_TRUE,the call will ensure none of the listed
* channels are running in hardware and will not run until a call with
* bDisable=NV_FALSE is made. When true and bDisable=NV_TRUE, the control
* call will ensure that none of the listed channels can be scheduled on the
* GPU until a call with bDisable=NV_FALSE is made, but will not remove any
* of the listed channels from hardware if they are currently running. When
* bDisable=NV_FALSE this field is ignored.
* bRewindGpPut
* If a channel is being disabled and bRewindGpPut=NV_TRUE, the channel's RAMFC
* will be updated so that GP_PUT is reset to the value of GP_GET.
* hClientList
* An array of NvU32 listing the client handles
* hChannelList
* An array of NvU32 listing the channel handles
* to be stopped.
* pRunlistPreemptEvent
* KEVENT handle for Async HW runlist preemption (unused on preMaxwell)
* When NULL, will revert to synchronous preemption with spinloop
*
* Possible status values returned are:
* NV_OK
* NVOS_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS (0x2080110b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES (64)
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS {
NvBool bDisable;
NvU32 numChannels;
NvBool bOnlyDisableScheduling;
NvBool bRewindGpPut;
NV_DECLARE_ALIGNED(NvP64 pRunlistPreemptEvent, 8);
// C form: NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]
NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES];
// C form: NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]
NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES];
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS;
#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE (0x00000000)
#define NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE (0x00000001)
#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE (0x00000000)
#define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE (0x00000001)
/*
* NV2080_CTRL_FIFO_MEM_INFO
*
* This structure describes the details of a block of memory. It consists
* of the following fields
*
* aperture
* One of the NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_* values
* base
* Physical base address of the memory
* size
* Size in bytes of the memory
*/
typedef struct NV2080_CTRL_FIFO_MEM_INFO {
NvU32 aperture;
NV_DECLARE_ALIGNED(NvU64 base, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
} NV2080_CTRL_FIFO_MEM_INFO;
/*
* NV2080_CTRL_FIFO_CHANNEL_MEM_INFO
*
* This structure describes the details of the instance memory, ramfc
* and method buffers a channel. It consists of the following fields
*
* inst
* Structure describing the details of instance memory
* ramfc
* Structure describing the details of ramfc
* methodBuf
* Array of structures describing the details of method buffers
* methodBufCount
* Number of method buffers(one per runqueue)
*/
// max runqueues
#define NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT 0x2
typedef struct NV2080_CTRL_FIFO_CHANNEL_MEM_INFO {
NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO inst, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO ramfc, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO methodBuf[NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT], 8);
NvU32 methodBufCount;
} NV2080_CTRL_FIFO_CHANNEL_MEM_INFO;
/*
* NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM
*
* This command returns the memory aperture, physical base address and the
* size of each of the instance memory, cache1 and ramfc of a channel.
*
* hChannel
* The handle to the channel for which the memory information is desired.
* chMemInfo
* A NV2080_CTRL_FIFO_CHANNEL_MEM_INFO structure
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_CHANNEL
*/
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO (0x2080110c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS {
NvHandle hChannel;
NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_CHANNEL_MEM_INFO chMemInfo, 8);
} NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS;
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID 0x00000000
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM 0x00000001
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH 0x00000002
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH 0x00000003
/*
* NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION
*
* This command determines the location (vidmem/sysmem)
* and attribute (cached/uncached/write combined) of memory where USERD is located.
*
* aperture
* One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_* values.
*
* attribute
* One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_* values.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_POINTER
*/
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION (0x2080110d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS {
NvU32 aperture;
NvU32 attribute;
} NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS;
// support for CPU coherent vidmem (VIDMEM_NVILINK_COH) is not yet available in RM
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM 0x00000000
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM 0x00000001
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED 0x00000000
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED 0X00000001
#define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED 0X00000002
/*
* NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE
*
* This command retrieves entries from the SW encoded GPU device info table
* from Host RM.
*
* Parameters:
*
* baseIndex [in]
* The starting index to read from the devinfo table. Must be a multiple of
* MAX_ENTRIES.
*
* entries [out]
* A buffer to store up to MAX_ENTRIES entries of the devinfo table.
*
* numEntries [out]
* Number of populated entries in the provided buffer.
*
* bMore [out]
* A boolean flag indicating whether more valid entries are available to be
* read. A value of NV_TRUE indicates that a further call to this control
* with baseIndex incremented by MAX_ENTRIES will yield further valid data.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE (0x20801112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES 256
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES 32
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES 16
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA 2
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN 16
/*
* NV2080_CTRL_FIFO_DEVICE_ENTRY
*
* This structure contains the engine, engine name and
* push buffers information of FIFO device entry. It consists of the following fields
*
* engineData
* Type of the engine
* pbdmaIds
* List of pbdma ids associated with engine
* pbdmaFaultIds
* List of pbdma fault ids associated with engine
* numPbdmas
* Number of pbdmas
* engineName
* Name of the engine
*/
typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY {
NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES];
NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
NvU32 numPbdmas;
char engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN];
} NV2080_CTRL_FIFO_DEVICE_ENTRY;
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x12U)
typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS {
NvU32 baseIndex;
NvU32 numEntries;
NvBool bMore;
// C form: NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];
NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];
} NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT
*
* This command clears the ENGINE or PBDMA FAULTED bit and reschedules the faulted channel
* by ringing channel's doorbell
*
* Parameters:
*
* engineType [in]
* The NV2080_ENGINE_TYPE of the engine to which the faulted
* channel is bound. This may be a logical id for guest RM in
* case of SMC.
*
* vChid [in]
* Virtual channel ID on which the fault occurred
*
* faultType [in]
* Whether fault was triggered by engine (_ENGINE_FAULTED) or PBDMA (_PBDMA_FAULTED)
* The value specified must be one of the NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_* values
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT (0x20801113) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE 0x00000001
#define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA 0x00000002
#define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS {
NvU32 engineType;
NvU32 vChid;
NvU32 faultType;
} NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY
*
* Allows clients to set the global scheduling policy for all runlists
* associated to the given subdevice.
*
* Currently, this is only supported for HW runlists.
*
* Since this is a global setting, only privileged clients will be allowed to
* set it. Regular clients will get NV_ERR_INSUFFICIENT_PERMISSIONS error.
*
* Once a certain scheduling policy is set, that policy cannot be changed to a
* different one unless all clients which set it have either restored the policy
* (using the corresponding restore flag) or died. Clients trying to set a
* policy while a different one is locked by another client will get a
* NV_ERR_INVALID_STATE error.
*
* The same client can set a scheduling policy and later change to another one
* only when no other clients have set the same policy. Such sequence will be
* equivalent to restoring the policy in between.
*
* For instance, the following sequence:
*
* 1. Set policy A
* 2. Set policy B
*
* is equivalent to:
*
* 1. Set policy A
* 2. Restore policy
* 3. Set policy B
*
* Parameters:
*
* flags
* This field specifies the operational properties to be applied:
*
* - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE
* Try to set the provided 'schedPolicy' scheduling policy. If the
* operation succeeds, other clients will be prevented from setting a
* different scheduling policy until all clients using it have either
* restored it or died.
*
* - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE
* Let the scheduler know the client no longer requires the current
* scheduling policy. This may or may not actually change the
* scheduling policy, depending on how many other clients are also
* using the current policy.
*
* The 'schedPolicy' parameter is ignored when this flag is set.
*
* schedPolicy
* One of:
*
* - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT
* Set the default scheduling policy and prevent other clients from
* changing it.
*
* - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED
* This scheduling policy will make channels to be scheduled according
* to their interleave level. See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL
* description for more details.
* - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM
* This scheduling policy will make channels to be scheduled according
* to their interleave level per WDDM policy.
* See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL description for more details.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY (0x20801115) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID" */
/* schedPolicy values */
#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT 0x0
#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED 0x1
#define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM 0x2
/* SET_SCHED_POLICY flags */
#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE 0:0
#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE (0x00000000)
#define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE (0x00000001)
#define NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID (0x15U)
typedef struct NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS {
NvU32 flags;
NvU32 schedPolicy;
} NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO
*
* This command updates the channel info params for an existing channel
*
* Can be a deferred Api. The control call can be used for migrating a
*
* channel to a new userd and gpfifo
*
* Parameters:
* [in] hClient - Client handle
* [in] hChannel - Channel handle
* [in] hUserdMemory - UserD handle
* [in] gpFifoEntries - Number of Gpfifo Entries
* [in] gpFifoOffset - Gpfifo Virtual Offset
* [in] userdOffset - UserD offset
*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO (0x20801116) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID (0x16U)
typedef struct NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS {
NvHandle hClient;
NvHandle hChannel;
NvHandle hUserdMemory;
NvU32 gpFifoEntries;
NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8);
NV_DECLARE_ALIGNED(NvU64 userdOffset, 8);
} NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS
*
* This command will disable or enable scheduling of all usermode channels.
*
* bDisable
* This value determines whether to disable or enable the usermode channels.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS (0x20801117) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID (0x17U)
typedef struct NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS {
NvBool bDisable;
} NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB
*
* When a VF subcontext is marked as a zombie, host RM points its PDB to a dummy
* page allocated by guest RM in GPA space. This command provides the parameters
* of the guest RMs memory descriptor to be able to create a corresponding
* memory descriptor on the host RM. Host RM uses this to program the PDB of a
* zombie subcontext.
*
* Parameters:
* Input parameters to describe the memory descriptor
* [in] base
* [in] size
* [in] addressSpace
* [in] cacheAttrib
*/
#define NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB (0x20801118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID (0x18U)
typedef struct NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS {
NV_DECLARE_ALIGNED(NvU64 base, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 addressSpace;
NvU32 cacheAttrib;
} NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS;
/* _ctrl2080fifo_h_ */

213
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h Normal file
View File

@@ -0,0 +1,213 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fla.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX FLA control commands and parameters */
#include "ctrl2080common.h"
/*
* NV2080_CTRL_CMD_FLA_RANGE
*
* This command is used to initialize/destroy FLA VAS for a GPU.This is intended
* to be used by RM clients that manages the FLA VASpace range. The mode of the
* command is decided based on the parameter passed by the client.
*
* base
* This parameter specifies the base of the FLA VAS that needs to be allocated
* for this GPU
*
* size
* This parameter specifies the size of the FLA VAS that needs to be allocated
* for this GPU
*
* mode
* This parameter specifies the functionality of the command.
* MODE_INITIALIZE
* Setting this mode, will initialize the FLA VASpace for the gpu with
* base and size passed as arguments. FLA VASpace will be owned by RM.
* if the client calls the command more than once before destroying
* the FLA VAS, then this command will verify the range exported before and
* return success if it matches. If FLA is not supported for the platform,
* will return NV_ERR_NOT_SUPPORTED.
* MODE_DESTROY (deprecated)
* This command is NOP.
* MODE_HOST_MANAGED_VAS_INITIALIZE
* This mode will initialize the FLA VASpace for the gpu with hVASpace
* handle in addition to base and size arguments. FLA VASpace will be initiated
* and owned by guest RM. Used only in virtualization platforms by internal clients.
* MODE_HOST_MANAGED_VAS_DESTROY
* This mode will destroy the FLA VAS associated with the device. It will destruct
* only the resources associated with host RM side. Used only in virtualization platforms
* by internal clients.
*
* hVASpace
* This paramete specifies the FLA VAspace that needs to be associated with
* device. This parameter takes effect only for internal client in virtualization
* platforms. For any other platform and external clients, this parameter has no effect.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_IN_USE
* NV_ERR_INVALID_OWNER
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FLA_RANGE (0x20803501) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_FLA_RANGE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 base, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 mode;
NvHandle hVASpace;
} NV2080_CTRL_FLA_RANGE_PARAMS;
#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE 0x00000000
#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE NVBIT(0)
#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY NVBIT(1)
#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE NVBIT(2)
#define NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY NVBIT(3)
/*
* NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK
*
* This command is used to (un)bind FLA Instance Memory Block(IMB) with MMU.
* This control call is created for vGPU platform, when a FLA VAS is created/destroyed
* by Guest RM. Guest RM doesn't have privilege to (un)bind the IMB with MMU, hence
* need to be RPC-ed to Host RM to (un)bind
* The mode of the command is decided based on the actionParam passed by the client.
*
* imbPhysAddr
* This parameter specifies the FLA Instance Memory Block PA to be programmed
* to MMU. IMB address should be 4k aligned. This parameter is needed only
* for ACTION_BIND.
*
* addrSpace
* This parameter specifies the address space of FLA Instance Memory Block. This
* parmater is needed only for ACTION_BIND.
* Available options are:
* NV2080_CTRL_FLA_ADDRSPACE_SYSMEM
* Clients need to use this address space if the IMB is located in sysmem
* NV2080_CTRL_FLA_ADDRSPACE_FBMEM
* Clients need to use this address space if the IMB is located in FB
*
* actionParam
* This parameter specifies the functionality of the command.
* NV2080_CTRL_FLA_ACTION_BIND
* Setting this type, will call busBindFla helper HAL
* NV2080_CTRL_FLA_ACTION_UNBIND
* Setting this type, will call busUnbindFla helper HAL
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INSUFFICIENT_PERMISSIONS
*/
typedef enum NV2080_CTRL_FLA_ADDRSPACE {
NV2080_CTRL_FLA_ADDRSPACE_SYSMEM = 0,
NV2080_CTRL_FLA_ADDRSPACE_FBMEM = 1,
} NV2080_CTRL_FLA_ADDRSPACE;
typedef enum NV2080_CTRL_FLA_ACTION {
NV2080_CTRL_FLA_ACTION_BIND = 0,
NV2080_CTRL_FLA_ACTION_UNBIND = 1,
} NV2080_CTRL_FLA_ACTION;
#define NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK (0x20803502) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS {
NV_DECLARE_ALIGNED(NvU64 imbPhysAddr, 8);
NV2080_CTRL_FLA_ADDRSPACE addrSpace;
NV2080_CTRL_FLA_ACTION flaAction;
} NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS;
/*
* NV2080_CTRL_CMD_FLA_GET_RANGE
*
* This command is used to query the FLA base and size from plugin to return as static info to Guest RM.
*
* base
* This parameter returns the base address of FLA range registered to the subdevice.
* size
* This parameter returns the size of FLA range registered to the subdevice.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FLA_GET_RANGE (0x20803503) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_FLA_GET_RANGE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 base, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
} NV2080_CTRL_FLA_GET_RANGE_PARAMS;
/*
* NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS
*
* This command returns the total size and the free size of the fabric vaspace.
* Note: This returns the information for the FABRIC_VASPACE_A class.
*
* totalSize[OUT]
* - Total fabric vaspace.
*
* freeSize [OUT]
* - Available fabric vaspace.
*
* Possible status values returned are:
*
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS (0x20803504) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLA_INTERFACE_ID << 8) | NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
NV_DECLARE_ALIGNED(NvU64 freeSize, 8);
} NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS;
// _ctrl2080fla_h_

550
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h Normal file
View File

@@ -0,0 +1,550 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080flcn.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
//
// XAPICHK/XAPI_TEST breaks on including "nvmisc.h". Workaround: don't include
// the header in that case and just redefine the macros we need.
//
#include "nvmisc.h"
/*
* Obsolete Falcon ID type. Use NV2080_ENGINE_TYPE_ instead
*/
#define FALCON_ID_PMU (NV2080_ENGINE_TYPE_PMU)
#define FALCON_ID_DPU (NV2080_ENGINE_TYPE_DPU)
#define FALCON_ID_SEC2 (NV2080_ENGINE_TYPE_SEC2)
#define FALCON_ID_FBFLCN (NV2080_ENGINE_TYPE_FBFLCN)
/*
* NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE
*
* This command returns total heap size and free heap size of a falcon engine
*
* flcnID
* The falcon ID
*
* heapSize
* Total heap size in byte
*
* heapFree
* Total free heap size in byte
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_OBJECT
*/
#define NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE (0x20803101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS {
NvU32 flcnID;
NvU32 heapSize;
NvU32 heapFree;
} NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS;
/*!
* @defgroup NVOS_INST_EVT Instrumentation event types.
* @{
*/
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RECALIBRATE 0x00U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_TICK 0x01U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_YIELD 0x02U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_INT0 0x03U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_BLOCK 0x04U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_UNBLOCK 0x05U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HANDLER_BEGIN 0x06U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_HANDLER_END 0x07U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_QUEUE_SEND 0x08U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_QUEUE_RECV 0x09U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RPC_BEGIN 0x0AU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_RPC_END 0x0BU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_SKIPPED 0x0CU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EXEC_PROFILE_BEGIN 0x0DU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EXEC_PROFILE_END 0x0EU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_LOAD_PROFILE_BEGIN 0x0FU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_LOAD_PROFILE_END 0x10U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_CODE_BEGIN 0x11U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_CODE_END 0x12U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_DATA_BEGIN 0x13U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_ODP_DATA_END 0x14U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_PROFILE_BEGIN 0x15U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_PROFILE_END 0x16U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_ODP_PROFILE_BEGIN 0x17U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_DMA_ODP_PROFILE_END 0x18U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_BEGIN 0x19U
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_END 0x1AU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_2_BEGIN 0x1BU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_2_END 0x1CU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_3_BEGIN 0x1DU
#define NV2080_CTRL_FLCN_NVOS_INST_EVT_USER_CUSTOM_3_END 0x1EU
/*!@}*/
#define NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID 0xFFU
/*!
* Interrupts and exceptions both use the same event type. Set the first bit
* for exceptions to differentiate between the two.
*/
#define NV2080_CTRL_FLCN_NVOS_INST_IRQ_ID(_irqId) (_irqId)
#define NV2080_CTRL_FLCN_NVOS_INST_EXCI_ID(_exciId) (_exciId | (1 << 7))
/*!
* @defgroup NV_INSTRUMENTATION_EVENT_DATA Instrumentation event struct entry.
*
* This is a binary-packed representation of event type and additional data,
* including timing data and tracking IDs.
*
* @{
*/
/*!
* Below DRF needs constants assigned to start and end so it can be represented in FINN properly
* This is because FINN v1 will not have the ability to represent DRF's and bit fields yet
*/
#define NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_EXTENT (31)
#define NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_BASE (27)
#define NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE \
(NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_EXTENT) : \
(NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_BASE)
#define NV_INSTRUMENTATION_EVENT_DATA_TASK_ID 26:19
#define NV_INSTRUMENTATION_EVENT_DATA_EXTRA 26:19
#define NV_INSTRUMENTATION_EVENT_DATA_TIME_DELTA 18:0
#define NV_INSTRUMENTATION_EVENT_DATA_TIME_ABS 26:0
/*!@}*/
/*!
* The maximum number of event types, calculated from the number of bits in the
* event structure.
*/
#define NV2080_CTRL_FLCN_NVOS_INST_NUM_EVT_TYPES (0x20U) /* finn: Evaluated from "(1 << (NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_EXTENT - NV_INSTRUMENTATION_EVENT_DATA_EVENT_TYPE_DRF_BASE + 1))" */
/*!
* The number of bytes required in the event mask to contain all event types.
*/
#define NV2080_CTRL_FLCN_NVOS_INST_MASK_SIZE_BYTES (0x4U) /* finn: Evaluated from "(NV2080_CTRL_FLCN_NVOS_INST_NUM_EVT_TYPES / 8)" */
/*!
* Instrumentation event bitfield structure. Exact structure depends on the
* first five bits, which represent event type.
*
* For most event types, the structure is:
* - 5 bits of event type
* - 8 bits of ID
* - 19 bits of delta time (time since last event). If we've missed some
* events, it's the amount of time since the last event that was not
* skipped. If this time would overflow, a recalibration event is inserted
* instead (see below).
*
* The main exception is the recalibration event, which has no ID/delta time
* fields and instead has a 27-bit absolute timestamp. This event is used
* when the gap between two events is greater than the maximum 20-bit integer.
*
* All timestamps are represented in increments of 32ns
* (the finest possible timer resolution).
*/
typedef struct NVOS_INSTRUMENTATION_EVENT {
/*!
* Field containing the event type and data.
*
* Bitmask of @ref NV_INSTRUMENTATION_EVENT_DATA.
*/
NvU32 data;
} NVOS_INSTRUMENTATION_EVENT;
typedef struct NVOS_INSTRUMENTATION_EVENT *PNVOS_INSTRUMENTATION_EVENT;
/*
* NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_MAP/UNMAP
*
* Params for both RmCtrls are the same (out for _MAP, in for _UNMAP)
*/
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_MAP (0x20803112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x12" */
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_UNMAP (0x20803113) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x13" */
typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
//! The beginning of the instrumentation buffer, mapped to user memory.
NV_DECLARE_ALIGNED(NvP64 begin, 8);
// Priv pointer for memory mapping.
NV_DECLARE_ALIGNED(NvP64 pPriv, 8);
// The size of the user-mapped instrumentation buffer.
NV_DECLARE_ALIGNED(NvU64 size, 8);
} NV2080_CTRL_FLCN_INSTRUMENTATION_MAP_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET_INFO
*
* Get static information about FLCN instrumentation.
*/
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET_INFO (0x20803114) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS_MESSAGE_ID (0x14U)
typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
//! Whether or not instrumentation is enabled
NvBool bEnabled;
/*!
* Whether we use PTIMER (resolution 32ns) or the 30us timer tick (NV_TRUE
* is PTIMER).
*/
NvBool bIsTimerPrecise;
} NV2080_CTRL_FLCN_INSTRUMENTATION_GET_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET/SET_CONTROL
*
* Get/set the event bitmask.
*/
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_GET_CONTROL (0x20803115) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x15" */
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_SET_CONTROL (0x20803116) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x16" */
typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
/*!
* The bitmask of which event types to log. An event type corresponding to
* a bit with a zero will be ignored at the log site, which prevents it
* from filling up the resident buffer in the PMU. In general, set this to
* only log the event types you actually want to use.
* Refer to NVOS_BM_* in nvos_utility.h for usage.
*/
NvU8 mask[4];
} NV2080_CTRL_FLCN_INSTRUMENTATION_CONTROL_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_RECALIBRATE
*
* Send a recalibrate event to the intstrumentation.
*/
#define NV2080_CTRL_CMD_FLCN_INSTRUMENTATION_RECALIBRATE (0x20803117) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS_MESSAGE_ID (0x17U)
typedef struct NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
} NV2080_CTRL_FLCN_INSTRUMENTATION_RECALIBRATE_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH
*
* Get the egine arch i.e FALCON, RISCV etc given the NV2080_ENGINE_TYPE_*.
*
*/
#define NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH (0x20803118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID (0x18U)
typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
//! The engine architecture - FALCON or RISC-V
NvU32 engineArch;
} NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS;
/*!
* @defgroup Engine Arch types
* @{
*/
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT 0x0
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON 0x1
#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV 0x2
/*!@}*/
/* ----------------------- uStreamer (INST v2) ------------------------------ */
/*!
* @defgroup NV2080_CTRL_FLCN_USTREAMER_EVENT uStreamer event fields.
*
* This is a binary-packed representation of uStreamer events. There are
* three main types of entry: Head, Payload, and Tail. COMM here is used
* when a field is shared among multiple event types.
*
* @{
*/
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_FLAG 31:31
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_HEAD 30:30
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_VARIABLE 29:29
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EXTEND 28:28
/*!
* Below DRF's need constants assigned to start and end so they can be represented in FINN properly
* This is because FINN v1 will not have the ability to represent DRF's and bit fields yet.
*/
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT (27)
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE (20)
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID \
(NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT) : \
(NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE)
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT (28)
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE (24)
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT \
(NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT) : \
(NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE)
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_LENGTH 19:8
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOAD 7:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT 23:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_HEAD_TIME 29:0
#define NV2080_CTRL_FLCN_USTREAMER_EVENT_DATA_PAYLOAD 30:0
/*!@}*/
/*!
* @defgroup NV2080_CTRL_FLCN_USTREAMER_FEATURE
*
* This defines all the features currently supported by uStreamer. For a new
* usecase of uStreamer, a feature should be defined here describing the usecase.
* This value should be unique for each queue.
*
* @{
*/
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT 0U
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON 1U
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT 2U
/*!@}*/
/*!
* @defgroup NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY
*
* This defines the DRF used for ustreamer queue policy
*
* @{
*/
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH 0:0
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED 0U
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED 1U
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH 1:1
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED 0U
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED 1U
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH 2:2
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED 0U
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED 1U
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_THRESHOLD 31:8
/*!@}*/
/*!
* The maximum number of compact event types, calculated from the number of bits
* in the event structure.
*/
#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT (0x20U) /* finn: Evaluated from "(1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE + 1))" */
/*!
* The maximum number of event types, calculated from the number of bits in the
* event structure.
*/
#define NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES (0x120U) /* finn: Evaluated from "((1 << (NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT - NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE + 1)) + NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT)" */
/*!
* The number of bytes required in the event mask to contain all event types.
*/
#define NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES (0x24U) /* finn: Evaluated from "((NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES + 7) / 8)" */
/*!
* uStreamer Event Filter type, stored as a bitmask.
*/
typedef struct NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER {
NvU8 mask[NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES];
} NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER;
/*!
* NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO
* Get queue info for mapping / unmapping
*/
#define NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO (0x20803120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
//!
// The page size of the requested queue in bytes.
//
NvU32 pageSize;
//! Offset of the queue buffer in FB.
NV_DECLARE_ALIGNED(NvUPtr offset, 8);
//!
// The size of the user-mapped instrumentation buffer. Measured in bytes.
//
NvU32 size;
//!
// The feature ID of the queue.
//
NvU8 queueFeatureId;
} NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET/SET
*
* Get/set the event bitmask for the default queue.
*/
#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x22" */
#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x23" */
typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
NvU32 engine;
/*!
* The bitmask of which event types to log. An event type corresponding to
* a bit with a zero will be ignored at the log site, which prevents it
* from filling up the resident buffer in the PMU. In general, set this to
* only log the event types you actually want to use.
* Refer to NVOS_BM_* in nvos_utility.h for usage.
*/
NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER eventFilter;
//! The queueId of the queue whose eventFilter we want to interact with
NvU8 queueId;
} NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO
*
* This command provides the attributes of the falcon engine context buffer
*
* hUserClient [IN]
* This parameter specifies the client handle that owns this channel.
* hChannel [IN]
* This parameter specifies the channel or channel group (TSG) handle
* alignment
* Specifies the alignment requirement for each context buffer
* size
* Aligned size of context buffer
* bufferHandle
* Opaque pointer to memdesc. Used by kernel clients for tracking purpose only.
* pageCount
* allocation size in the form of pageCount
* physAddr
* Physical address of the buffer first page
* aperture
* allocation aperture. Could be SYSMEM, VIDMEM, UNKNOWN
* kind
* PTE kind of this allocation.
* pageSize
* Page size of the buffer.
* bIsContigous
* States if physical allocation for this buffer is contiguous. PageSize will
* have no meaning if this flag is set.
* bDeviceDescendant
* TRUE if the allocation is a constructed under a Device or Subdevice.
* uuid
* SHA1 UUID of the Device or Subdevice. Valid when bDeviceDescendant is TRUE.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO (0x20803124) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID (0x24U)
typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS {
NvHandle hUserClient;
NvHandle hChannel;
NV_DECLARE_ALIGNED(NvU64 alignment, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NV_DECLARE_ALIGNED(NvP64 bufferHandle, 8);
NV_DECLARE_ALIGNED(NvU64 pageCount, 8);
NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
NvU32 aperture;
NvU32 kind;
NvU32 pageSize;
NvBool bIsContigous;
NvBool bDeviceDescendant;
NvU8 uuid[16];
} NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS;
// Aperture flags
#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN
#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM
#define NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM
/*
* NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE
*
* This command provides the size of the falcon engine context buffer
*
* hChannel [IN]
* This parameter specifies the channel or channel group (TSG) handle
* totalBufferSize [OUT]
* This parameter returns the total context buffers size.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE (0x20803125) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x25U)
typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS {
NvHandle hChannel;
NV_DECLARE_ALIGNED(NvU64 totalBufferSize, 8);
} NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS;
/* _ctrl2080flcn_h_ */

35
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fuse.finn
//
/* _ctrl2080fuse_h_ */

38
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gpio.finn
//
/* _ctrl2080gpio_h_ */
#include "ctrl/ctrl2080/ctrl2080base.h"

3782
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h Normal file
View File

File diff suppressed because it is too large Load Diff

96
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h Normal file
View File

@@ -0,0 +1,96 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*!
* This structure represents base class of GPU monitoring sample.
*/
typedef struct NV2080_CTRL_GPUMON_SAMPLE {
/*!
* Timestamps in nano-seconds.
*/
NV_DECLARE_ALIGNED(NvU64 timeStamp, 8);
} NV2080_CTRL_GPUMON_SAMPLE;
/*!
* This structure represents base GPU monitoring sample.
*/
typedef struct NV2080_CTRL_GPUMON_SAMPLES {
/*!
* Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference.
*/
NvU8 type;
/*!
* Size of the buffer, this should be
* bufSize == NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_*
* sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE).
*/
NvU32 bufSize;
/*!
* Number of samples in ring buffer.
*/
NvU32 count;
/*!
* tracks the offset of the tail in the circular queue array pSamples.
*/
NvU32 tracker;
/*!
* Pointer to a circular queue based on array of NV2080_CTRL_GPUMON_SAMPLE
* or its derived types structs with size == bufSize.
*
* @note This circular queue wraps around after 10 seconds of sampling,
* and it is clients' responsibility to query within this time frame in
* order to avoid losing samples.
* @note With one exception, this queue contains last 10 seconds of samples
* with tracker poiniting to oldest entry and entry before tracker as the
* newest entry. Exception is when queue is not full (i.e. tracker is
* pointing to a zeroed out entry), in that case valid entries are between 0
* and tracker.
* @note Clients can store tracker from previous query in order to provide
* samples since last read.
*/
NV_DECLARE_ALIGNED(NvP64 pSamples, 8);
} NV2080_CTRL_GPUMON_SAMPLES;
/*!
* Enumeration of GPU monitoring sample types.
*/
#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS 0x00000001
#define NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL 0x00000002
/*!
* Macro for invalid PID.
*/
#define NV2080_GPUMON_PID_INVALID ((NvU32)(~0))

1789
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h Normal file
View File

File diff suppressed because it is too large Load Diff

266
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h Normal file
View File

@@ -0,0 +1,266 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX grmgr control commands and parameters */
//
// NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO
//
// This control call works as a batched query interface where we
// have multiple different queries that can be passed in
// and RM will return the associated data and status type
// If there is any error in NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS,
// we will immediately fail the call.
// However, if there is an error in the query-specific calls, we will
// log the error and march on.
//
// NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS
// numQueries[IN]
// - Specifies the number of valid queries that the caller will be passing in
//
// Possible status values returned are:
// NV_OK
// NV_ERR_INVALID_ARGUMENT
// NV_ERR_INVALID_STATE
//
#define NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO (0x20803801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID << 8) | NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID" */
// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO
#define NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES 96
//
// Preference is to keep max.size of union at 24 bytes (i.e. 6 32-bit members)
// so that the size of entire query struct is maintained at 32 bytes, to ensure
// that overall params struct does not exceed 4kB
//
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE 32
#define NV2080_CTRL_GRMGR_MAX_SMC_IDS 8
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS
* gpcCount[OUT]
* - No. of logical/local GPCs which client can use to create the
* logical/local mask respectively
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS {
NvU32 gpcCount; // param[out] - logical/local GPC mask
} NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS
* gpcId[IN]
* - Logical/local GPC ID
* chipletGpcMap[OUT]
* - Returns chiplet GPC ID for legacy case and device monitoring client
* - Returns local GPC ID (== input gpcId) for SMC client
* - Does not support DM attribution case
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS {
NvU32 gpcId; // param[in] - logical/local GPC ID
NvU32 chipletGpcMap; // param[out] - chiplet GPC ID
} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS
* gpcId[IN]
* - Logical/local GPC ID
* tpcMask[OUT]
* - Returns physical TPC mask for legacy, DM client and SMC cases
* - Does not support DM attribution case
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS {
NvU32 gpcId; // param[in] - logical/local GPC ID
NvU32 tpcMask; // param[out] - physical TPC mask
} NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS
* gpcId[IN]
* - Logical/local GPC ID
* ppcMask[OUT]
* - Returns physical PPC mask for legacy, DM client and SMC cases
* - Does not support DM attribution case
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS {
NvU32 gpcId; // param[in] - logical/local GPC ID
NvU32 ppcMask; // param[out] - physical PPC mask
} NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS;
/*!
* !!! DEPRECATED - This query will return NV_ERR_NOT_SUPPORTED since deleting
* it would break driver compatibility !!!
*
* NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS
* swizzId[IN]
* - Swizz ID of partition
* - A DM client with an invalid swizz ID, will fail this call
* - This parameter is not compulsory for an SMC client; the subscription
* itself will do the necessary validation.
* gpcId[IN]
* - Logical/local GPC ID
* chipletGpcMap[OUT]
* - Returns chiplet GPC ID for legacy case and device monitoring client
* - Returns local GPC ID (== input gpcId) for SMC client
* - Does not support non-attribution case for DM client
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS {
NvU32 swizzId; // param[in] - swizz ID of partition
NvU32 gpcId; // param[in] - logical/local GPC ID
NvU32 chipletGpcMap; // param[out] - chiplet GPC ID
} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS
* gpcId[IN]
* - Logical/local GPC ID
* ropMask[OUT]
* - Returns physical ROP mask for legacy, DM client
* - Returns logical ROP mask for SMC
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS {
NvU32 gpcId; // param[in] - logical/local GPC ID
NvU32 ropMask; // param[out] - physical ROP mask
} NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS
* chipletSyspipeMask [OUT]
* - Mask of chiplet SMC-IDs for DM client attribution case
* - Mask of local SMC-IDs for SMC client
* - Legacy case returns 1 GR
* - Does not support attribution case for DM client
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS {
NvU32 chipletSyspipeMask; // param[out] - Mask of chiplet SMC IDs
} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS
* swizzId[IN]
* - Swizz ID of partition
* - A DM client with an invalid swizz ID, will fail this call
* physSyspipeId[GRMGR_MAX_SMC_IDS] [OUT]
* - Physical SMC-IDs mapped to partition local idx for DM client attribution case
* - Does not support non-attribution case for DM client, SMC clients, legacy case
* physSyspipeIdCount[OUT]
* - Valid count of physSmcIds which has been populated in above array.
* - Failure case will return 0
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS {
NvU16 swizzId; // param[in] - swizz ID of partition
NvU16 physSyspipeIdCount; // param[out] - Count of physSmcIds in above array
NvU8 physSyspipeId[NV2080_CTRL_GRMGR_MAX_SMC_IDS]; // param[out] - physical/local SMC IDs
} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS
* swizzId[IN]
* - Swizz ID of partition
* - Mandatory parameter
* - A DM client with an invalid swizz ID, will fail this call
* grIdx[IN]
* - Local grIdx for a partition
* - Mandatory parameter
* gpcEnMask[OUT]
* - Logical enabled GPC mask associated with requested grIdx of the partition i.e swizzid->engineId->gpcMask
* - These Ids should be used as input further
* - Does not support non-attribution case for DM client, SMC clients, legacy case
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS {
NvU32 swizzId; // param[in] - swizz ID of partition
NvU32 grIdx; // param[in] - partition local GR ID
NvU32 gpcEnMask; // param[out] - logical enabled GPC mask
} NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS;
/*!
* NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID
* syspipeId[OUT]
* - Partition-local GR idx for client subscribed to exec partition
* - Does not support legacy case, DM client, or SMC client subscribed only to partition
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS {
NvU32 syspipeId; // param[out] - partition-local Gr idx
} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS;
/*!
* queryType[IN]
* - Use queryType defines to specify what information is being requested
* status[OUT]
* - Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS {
NvU16 queryType;
NvU8 reserved[2]; // To keep the struct aligned for now and available for future use (if needed)
NvU32 status;
union {
NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS gpcCountData;
NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS chipletGpcMapData;
NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS tpcMaskData;
NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS ppcMaskData;
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS partitionGpcMapData;
NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS syspipeMaskData;
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS partitionChipletSyspipeData;
NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS dmGpcMaskData;
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS partitionSyspipeIdData;
NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS ropMaskData;
} queryData;
} NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS;
#define NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS {
NvU16 numQueries;
NvU8 reserved[6]; // To keep the struct aligned for now and available for future use (if needed)
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS queries[NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES];
} NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS;
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID 0
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT 1
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP 2
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK 3
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK 4
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP 5 /* deprecated */
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK 6
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS 7
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK 8
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID 9
#define NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK 10
/* _ctrl2080grmgr_h_ */

85
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h Normal file
View File

@@ -0,0 +1,85 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gsp.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX GSP control commands and parameters */
/*
* NV2080_CTRL_CMD_GSP_GET_FEATURES
*
* This command is used to determine which GSP features are
* supported on this GPU.
*
* gspFeatures
* Bit mask that specifies GSP features supported.
* bValid
* If this field is set to NV_TRUE, then above bit mask is
* considered valid. Otherwise, bit mask should be ignored
* as invalid. bValid will be set to NV_TRUE when RM is a
* GSP client with GPU support offloaded to GSP firmware.
* bDefaultGspRmGpu
* If this field is set to NV_TRUE, it indicates that the
* underlying GPU has GSP-RM enabled by default. If set to NV_FALSE,
* it indicates that the GPU has GSP-RM disabled by default.
* firmwareVersion
* This field contains the buffer into which the firmware build version
* should be returned, if GPU is offloaded. Otherwise, the buffer
* will remain untouched.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_GSP_GET_FEATURES (0x20803601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID" */
#define NV2080_GSP_MAX_BUILD_VERSION_LENGTH (0x0000040)
#define NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS {
NvU32 gspFeatures;
NvBool bValid;
NvBool bDefaultGspRmGpu;
NvU8 firmwareVersion[NV2080_GSP_MAX_BUILD_VERSION_LENGTH];
} NV2080_CTRL_GSP_GET_FEATURES_PARAMS;
/* Valid feature values */
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED 0:0
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000)
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001)
// _ctrl2080gsp_h_

58
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h Normal file
View File

@@ -0,0 +1,58 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080hshub.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*
* NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK
*
* This command get active HSHUB masks.
*
* hshubNcisocMask
* NCISOC enabled active HSHUBs
* hshubNvlMask
* NVLINK capable active HSHUBs.
*/
#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS {
NvU32 hshubNcisocMask;
NvU32 hshubNvlMask;
} NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS;
#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK (0x20804101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID" */
/* _ctrl2080hshub_h_ */

368
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h Normal file
View File

@@ -0,0 +1,368 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080i2c.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX i2c-related control commands and parameters */
/*
* NV2080_CTRL_I2C_VERSION
*
* NV2080_CTRL_I2C_VERSION_0_0:
* This return state specifies that support is only available
* for single subAddr reads.
*
*/
#define NV2080_CTRL_I2C_VERSION_0 0x00
/* maximum number of i2c entries support */
#define NV2080_CTRL_I2C_MAX_ENTRIES 256
#define NV2080_CTRL_I2C_MAX_REG_LEN 8
#define NV2080_CTRL_I2C_MAX_ADDR_ENTRIES 20
/*
* NV2080_CTRL_I2C_FLAGS
*
* NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC:
* This option specified that non-compliant i2c for SI1930UC is required
*
* NV2080_CTRL_I2C_FLAGS_PRIVILEGE
* This option specified that the i2c access is privileged
*
* NV2080_CTRL_I2C_FLAGS_PX3540
* This option specified that the i2c device -PX3540/3544- is accessed
*/
#define NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC (0x00000001)
#define NV2080_CTRL_I2C_FLAGS_PRIVILEGE (0x00000002)
#define NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED (0x00000004)
#define NV2080_CTRL_I2C_FLAGS_PX3540 (0x00000010)
#define NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED (0x00000008)
/*
* NV2080_CTRL_CMD_I2C_READ_BUFFER
*
* This command allocates video memory for a particular subset of microcode.
*
* version
* This field is returned to the client and indicates the current
* supported I2C controls available.
*
* port
* This field must be specified by the client to indicate which port/bus
* in which i2c access is desired.
*
* flags
* This field is specified by the client to request additional options
* as provided by NV2080_CTRL_I2C_FLAGS.
*
* inputCount
* This field specifies the total # of elements contained in inputBuffer
*
* inputBuffer
* This should contain the chipaddr as the first element, followed by
* the each subAddress in which to access the first element of data
* Eg. <chipAddr> <subAddr1> ... <subAddrX>
* In general, client will only have 2 elements <chipAddr> <subAddr>
*
* outputCount
* This field specifies how many registers from the start register index.
* The maximum values allow are NV2080_CTRL_I2C_MAX_ENTRIES.
*
* outputBuffer
* This buffer is returned to the client with the data read from
* the start register index.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_STATE_IN_USE
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*
*/
#define NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_I2C_READ_BUFFER_PARAMS {
NvU32 version;
NvU32 port;
NvU32 flags;
NvU32 inputCount;
// C form: NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
NvU32 outputCount;
// C form: NvU8 outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
NvU8 outputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
} NV2080_CTRL_I2C_READ_BUFFER_PARAMS;
#define NV2080_CTRL_CMD_I2C_READ_BUFFER (0x20800601) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_I2C_WRITE_BUFFER
*
* This command allocates video memory for a particular subset of microcode.
*
* version
* This field is returned to the client and indicates the current
* supported I2C controls available.
*
* port
* This field must be specified by the client to indicate which port/bus
* in which i2c access is desired.
*
* flags
* This field is specified by the client to request additional options.
* NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC:
* - Specifies that non-compliant i2c access for SI1930UC is required
*
* inputCount
* This field specifies the total # of elements contained in inputBuffer
*
* inputBuffer
* This should contain the chipaddr as the first element, followed by
* the each subAddress in which to access the first element of data,
* and finally the data to be programmed.
* Eg. <chipAddr> <subAddr1> ... <subAddrX> <data1> ... <dataX>
* In general, client will have 2 elements + data to be programmed.
* <chipAddr> <subAddr> <data1> ... <dataX>
*
* encrClientID
* This field is specified by client, which is used to uniquely access
* the client's encryption context
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_STATE_IN_USE
* NV_ERR_INVALID_STATE
*
*/
#define NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS {
NvU32 version;
NvU32 port;
NvU32 flags;
NvU32 inputCount;
// C form: NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
NvU8 inputBuffer[NV2080_CTRL_I2C_MAX_ENTRIES];
NvU32 encrClientID;
} NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS;
#define NV2080_CTRL_CMD_I2C_WRITE_BUFFER (0x20800602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_I2C_READ_REG
*
* This command allocates video memory for a particular subset of microcode.
*
* version
* This field is returned to the client and indicates the current
* supported I2C controls available.
*
* port
* This field must be specified by the client to indicate which port/bus
* in which i2c access is desired.
*
* flags
* This field is specified by the client to request additional options.
* NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC:
* - Specifies that non-compliant i2c access for SI1930UC is required
* addr
* This field is specified by the client to target address.
* reg
* This field is specified by the client to target register address.
*
* bufsize
* This field specifies the total bytes # of register size
*
* buffer
* when used for read, it used as buffer that store returned register content
* when used for write, It include data that will be written.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_STATE_IN_USE
* NV_ERR_INVALID_STATE
*
*/
typedef struct NV2080_CTRL_I2C_RW_REG_PARAMS {
NvU32 version;
NvU32 port;
NvU32 flags;
NvU32 addr;
NvU8 reg;
NvU8 bufsize;
// C form: NvU8 buffer[NV2080_CTRL_I2C_MAX_ENTRIES - 1];
NvU8 buffer[(NV2080_CTRL_I2C_MAX_ENTRIES - 1)];
} NV2080_CTRL_I2C_RW_REG_PARAMS;
// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name
typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS;
#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x3" */
#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x4" */
/*
* NV006F_CTRL_CMD_SYSTEM_I2C_ACCESS
*
* This command allows Clients to read and write data using the I2C ports
*
* token [IN]
* This used in i2cAcquirePort
*
* cmd [IN]
* The I2CAccess command
*
* port [IN]
* The port ID of the concerned display
*
* flags [IN]
* The I2CAccess Flags such ack,start,stop
*
* data [OUT/IN]
* Data that needs to be pass or read out
*
* dataBuffSize [IN]
* Size of the data buffer.
*
* speed [IN]
* Speed of transaction.
*
* status [OUT]
* The I2CAccess Status returned
*
* encrClientID [IN]
* This field is specified by client, which is used to uniquely access
* the client's encryption context
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV2080_CTRL_I2C_ACCESS_PARAMS {
NvU32 token;
NvU32 cmd;
NvU32 port;
NvU32 flags;
NV_DECLARE_ALIGNED(NvP64 data, 8);
NvU32 status;
NvU32 dataBuffSize;
NvU32 speed;
NvU32 encrClientID;
} NV2080_CTRL_I2C_ACCESS_PARAMS;
// commands
#define NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE 0x1
#define NV2080_CTRL_I2C_ACCESS_CMD_RELEASE 0x2
#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE 0x3
#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE 0x4
#define NV2080_CTRL_I2C_ACCESS_CMD_NULL 0x5
#define NV2080_CTRL_I2C_ACCESS_CMD_RESET 0x6
#define NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT 0x11
#define NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE 0x12
#define NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE 0x13
#define NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER 0x14
#define NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER 0x15
#define NV2080_CTRL_I2C_ACCESS_CMD_START 0x17
#define NV2080_CTRL_I2C_ACCESS_CMD_STOP 0x18
#define NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE 0x20
// flags
#define NV2080_CTRL_I2C_ACCESS_FLAG_START 0x1
#define NV2080_CTRL_I2C_ACCESS_FLAG_STOP 0x2
#define NV2080_CTRL_I2C_ACCESS_FLAG_ACK 0x4
#define NV2080_CTRL_I2C_ACCESS_FLAG_RAB 0x8
#define NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS 0x10
#define NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE 0x20
#define NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED 0x40
#define NV2080_CTRL_I2C_ACCESS_FLAG_RESTART 0x80
#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT 0x100
#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT 0x200
#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT 0x400
#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT 0x800
#define NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT 0x1000
// port
#define NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC 0x0
#define NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY 0x1
#define NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY 0x2
#define NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY 0x3
#define NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY 0x4
// Alternate numeric port designators
#define NV2080_CTRL_I2C_ACCESS_PORT_1 0x1
#define NV2080_CTRL_I2C_ACCESS_PORT_2 0x2
#define NV2080_CTRL_I2C_ACCESS_PORT_3 0x3
#define NV2080_CTRL_I2C_ACCESS_PORT_4 0x4
#define NV2080_CTRL_I2C_ACCESS_PORT_5 0x5
#define NV2080_CTRL_I2C_ACCESS_PORT_6 0x6
#define NV2080_CTRL_I2C_ACCESS_PORT_7 0x7
#define NV2080_CTRL_I2C_ACCESS_PORT_8 0x8
#define NV2080_CTRL_I2C_ACCESS_PORT_9 0x9
#define NV2080_CTRL_I2C_ACCESS_PORT_10 0x10
// Total ports count
#define NV2080_CTRL_I2C_ACCESS_NUM_PORTS NV2080_CTRL_I2C_ACCESS_PORT_10
// status
#define NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS 0x0
#define NV2080_CTRL_I2C_ACCESS_STATUS_ERROR 0x1
#define NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR 0x2
#define NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY 0x3
#define NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND 0x4
#define NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING 0x5
#define NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE (0x20800620) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS {
NvU32 head;
NvU32 authType;
NvU32 status;
} NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS;
/* _ctrl2080i2c_h_ */

30
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080illum.finn
//

2211
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h Normal file
View File

File diff suppressed because it is too large Load Diff

37
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h Normal file
View File

@@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn
//
// _ctrl2080lpwr_h_

324
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h Normal file
View File

@@ -0,0 +1,324 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080mc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX mc control commands and parameters */
/**
* NV2080_CTRL_CMD_MC_GET_ARCH_INFO
*
* This command returns chip architecture information from the
* master control engine in the specified GPU.
*
* architecture
* This parameter specifies the architecture level for the GPU.
* implementation
* This parameter specifies the implementation of the architecture
* for the GPU.
* revision
* This parameter specifies the revision of the mask used to produce
* the GPU.
* subRevision
* This parameter specific the sub revision of the GPU. Value is one of
* NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_MC_GET_ARCH_INFO (0x20801701) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
NvU32 architecture;
NvU32 implementation;
NvU32 revision;
NvU8 subRevision;
} NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS;
/* valid architecture values */
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X (0xE0000023)
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 (0x00000160)
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170)
/* valid ARCHITECTURE_T23X implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 (0x00000004)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D (0x00000005)
/* valid ARCHITECTURE_TU10x implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102 (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104 (0x00000004)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106 (0x00000006)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116 (0x00000008)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117 (0x00000007)
/* valid ARCHITECTURE_GA10x implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102 (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103 (0x00000003)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104 (0x00000004)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106 (0x00000006)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107 (0x00000007)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B (0x0000000B)
/* Valid Chip sub revisions */
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P (0x00000001)
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R (0x00000003)
/*
* NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS
*
* This command instructs the RM to service interrupts for the specified
* engine(s).
*
* engines
* This parameter specifies which engines should have their interrupts
* serviced.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS (0x20801702) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_ENGINE_ID_GRAPHICS 0x00000001
#define NV2080_CTRL_MC_ENGINE_ID_ALL 0xFFFFFFFF
#define NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS {
NvU32 engines;
} NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS;
/*
* NV2080_CTRL_CMD_MC_GET_MANUFACTURER
*
* This command returns the GPU manufacturer information for the associated
* subdevice.
*
* manufacturer
* This parameter returns the manufacturer value for the GPU.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_MC_GET_MANUFACTURER (0x20801703) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS {
NvU32 manufacturer;
} NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS;
/*
* NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS
*
* This command is used to allow clients to query whether hostclk slowdown is
* disabled.
*
* bDisabled
* This parameter will hold the status of hostclk slowdown
*
* Possible status values returned are:
* NV_OK
*
*/
#define NV2080_CTRL_CMD_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS (0x20801708) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS {
NvBool bDisabled;
} NV2080_CTRL_MC_QUERY_HOSTCLK_SLOWDOWN_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS
*
* This command is used to allow clients to disable/enable hostclk slowdown.
*
* bDisable
* When this parameter is set to TRUE, RM should disable hostclk slowdown.
* If it is set to FALSE, RM will attempt to enable hostclk slowdown, but
* in this case, slowdown is NOT guaranteed to be enabled since there may
* be other reason (like regkey) preventing slowdown.
*
* Possible status values returned are:
* NV_OK
*
*/
#define NV2080_CTRL_CMD_MC_SET_HOSTCLK_SLOWDOWN_STATUS (0x20801709) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS {
NvBool bDisable;
} NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP
*
* This call will setup RM to either service or ignore the
* repayable fault interrupt.
* This is a privileged call that can only be called by the UVM driver
* when it will take ownership of the repalayable fault interrupt.
*
* Possible status values returned are:
* NVOS_STATUS_SUCCESS
* NVOS_STATUS_ERROR_INVALID_ARGUMENT
* NVOS_STATUS_ERROR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP (0x2080170c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS {
NvBool bOwnedByRm;
} NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS;
/*
* NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS
*
* This command gets the notification interrupt vectors device for all VGPU engines from Host RM.
*
* Parameters:
*
* entries [out]
* A buffer to store up to MAX_ENGINES entries of type
* NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY.
*
* numEntries [out]
* Number of populated entries in the provided buffer.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS (0x2080170d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES 256
typedef struct NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY {
NvU32 nv2080EngineType;
NvU32 notificationIntrVector;
} NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY;
#define NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS {
NvU32 numEntries;
NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY entries[NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES];
} NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS;
/*
* NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE
*
* This command gets the static interrupts needed by VGPU from Host RM.
*
* Parameters:
*
* entries [out]
* A buffer to store up to MAX_ENGINES entries of type
* NV2080_CTRL_MC_STATIC_INTR_ENTRY.
*
* numEntries [out]
* Number of populated entries in the provided buffer.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE (0x2080170e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID << 8) | NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX 32
// Interface defines for static MC_ENGINE_IDX defines
#define NV2080_INTR_TYPE_NULL (0x00000000)
#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT (0x00000001)
#define NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR (0x00000002)
#define NV2080_INTR_TYPE_INFO_FAULT (0x00000003)
#define NV2080_INTR_TYPE_REPLAYABLE_FAULT (0x00000004)
#define NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR (0x00000005)
#define NV2080_INTR_TYPE_ACCESS_CNTR (0x00000006)
#define NV2080_INTR_TYPE_TMR (0x00000007)
#define NV2080_INTR_TYPE_CPU_DOORBELL (0x00000008)
#define NV2080_INTR_TYPE_GR0_FECS_LOG (0x00000009)
#define NV2080_INTR_TYPE_GR1_FECS_LOG (0x0000000A)
#define NV2080_INTR_TYPE_GR2_FECS_LOG (0x0000000B)
#define NV2080_INTR_TYPE_GR3_FECS_LOG (0x0000000C)
#define NV2080_INTR_TYPE_GR4_FECS_LOG (0x0000000D)
#define NV2080_INTR_TYPE_GR5_FECS_LOG (0x0000000E)
#define NV2080_INTR_TYPE_GR6_FECS_LOG (0x0000000F)
#define NV2080_INTR_TYPE_GR7_FECS_LOG (0x00000010)
typedef struct NV2080_CTRL_MC_STATIC_INTR_ENTRY {
NvU32 nv2080IntrType;
NvU32 pmcIntrMask;
NvU32 intrVectorStall;
NvU32 intrVectorNonStall;
} NV2080_CTRL_MC_STATIC_INTR_ENTRY;
#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS {
NvU32 numEntries;
NV2080_CTRL_MC_STATIC_INTR_ENTRY entries[NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX];
} NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS;
/* _ctrl2080mc_h_ */

342
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h Normal file
View File

@@ -0,0 +1,342 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080nvd.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrlxxxx.h"
/*
* NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE
*
* This command gets the expected dump size of a particular GPU dump component.
* Note that events that occur between this command and a later
* NV2080_CTRL_CMD_NVD_GET_DUMP command could alter the size of
* the buffer required.
*
* component
* One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to estimate
* the size of.
* size
* This parameter returns the expected size.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT if component is invalid.
*
*/
#define NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE (0x20802401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS {
NvU32 component;
NvU32 size;
} NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS;
/*
* NV2080_CTRL_CMD_NVD_GET_DUMP
*
* This command gets a dump of a particular GPU dump component. If triggers
* is non-zero, the command waits for the trigger to occur
* before it returns.
*
* pBuffer
* This parameter points to the buffer for the data.
* component
* One of NVDUMP_COMPONENT < 0x400 defined in nvdump.h to select
* for dumping.
* size
* On entry, this parameter specifies the maximum length for
* the returned data. On exit, it specifies the number of bytes
* returned.
*
* Possible status values returned are:
* NV_OK
* NVOS_ERROR_INVALID_ARGUMENT if component is invalid.
* NVOS_ERROR_INVALID_ADDRESS if pBuffer is invalid
* NVOS_ERROR_INVALID_???? if the buffer was too small
*
*
*/
#define NV2080_CTRL_CMD_NVD_GET_DUMP (0x20802402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_NVD_GET_DUMP_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pBuffer, 8);
NvU32 component;
NvU32 size;
} NV2080_CTRL_NVD_GET_DUMP_PARAMS;
/*
* NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL
*
* This command returns the contents of the Journal used by NOCAT, and
* optionally clears the data
*
* clear:
* [IN] indicates if should the data be cleared after reporting
*
* JournalRecords :
* [OUT] an array of Journal records reported.
*
* outstandingAssertCount:
* [OUT] number of asserts that remain to be reported on.
*
* reportedAssertCount:
* [OUT] the number of asserts contained in the report
*
* asserts:
* [OUT] an array of up to NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS assert reports
*/
#define NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL (0x20802409) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID" */
#define NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER 1024
#define NV2080_NOCAT_JOURNAL_MAX_STR_LEN 65
#define NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS 10
#define NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS 32
// structure to hold clock details.
typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS {
NvS32 userMinOffset;
NvS32 userMaxOffset;
NvU32 factoryMinOffset;
NvU32 factoryMaxOffset;
NvU32 lastActiveClock;
NvU32 lastActiveVolt;
NvU32 lastActivePoint;
NvU32 kappa;
} NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS;
// structure to hold clock configuration & state.
typedef struct NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG {
NvU32 pstateVer;
NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS gpcOverclock;
NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS mclkOverclock;
NvBool bUserOverclocked;
NvBool bFactoryOverclocked;
} NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG;
// structure to hold the GPU context at the time of the report.
typedef struct NV2080_NOCAT_JOURNAL_GPU_STATE {
NvBool bValid;
NvU32 strap;
NvU16 deviceId;
NvU16 vendorId;
NvU16 subsystemVendor;
NvU16 subsystemId;
NvU16 revision;
NvU16 type;
NvU32 vbiosVersion;
NvBool bOptimus;
NvBool bMsHybrid;
NvBool bFullPower;
NvU32 vbiosOemVersion;
NvU16 memoryType;
NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU8 vbiosProject[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvBool bInFullchipReset;
NvBool bInSecBusReset;
NvBool bInGc6Reset;
NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG overclockCfg;
} NV2080_NOCAT_JOURNAL_GPU_STATE;
#define NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN 0
#define NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK 1
#define NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE 2
#define NV2080_NOCAT_JOURNAL_REC_TYPE_TDR 3
#define NV2080_NOCAT_JOURNAL_REC_TYPE_RC 4
#define NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT 5
#define NV2080_NOCAT_JOURNAL_REC_TYPE_ANY 6
// this should be relative to the highest type value
#define NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT (0x7) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REC_TYPE_ANY + 1" */
typedef struct NV2080_NOCAT_JOURNAL_ENTRY {
NvU8 recType;
NvU32 bugcheck;
NvU32 tdrBucketId;
NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 subsystem;
NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
NvU32 diagBufferLen;
NvU8 diagBuffer[NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER];
NvU8 faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 mmuFaultType;
NvU32 mmuErrorSrc;
NvU8 tdrReason[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
} NV2080_NOCAT_JOURNAL_ENTRY;
typedef struct NV2080_NOCAT_JOURNAL_RECORD {
NvU32 GPUTag;
NV_DECLARE_ALIGNED(NvU64 loadAddress, 8);
NV_DECLARE_ALIGNED(NvU64 timeStamp, 8);
NV_DECLARE_ALIGNED(NvU64 stateMask, 8);
NV2080_NOCAT_JOURNAL_GPU_STATE nocatGpuState;
NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_ENTRY nocatJournalEntry, 8);
} NV2080_NOCAT_JOURNAL_RECORD;
// NOCAT activity counter indexes
// collection activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX 0
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 1
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 2
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 3
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 4
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_DROPPED_IDX 5
// reporting activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 6
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 7
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 8
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MISSED_IDX 9
// update activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 10
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 11
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 12
// general errors
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 13
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 14
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 15
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX 16
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 17
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CACHE_UPDATE_IDX 18
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX 19
// this should be relative to the highest counter index
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT (0x14) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX + 1" */
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY 0:0
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES 1
#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO 0
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS 1:1
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES 1
#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO 0
#define NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
NvU32 flags;
NvU32 nocatRecordCount;
NvU32 nocatOutstandingRecordCount;
NV_DECLARE_ALIGNED(NV2080_NOCAT_JOURNAL_RECORD journalRecords[NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS], 8);
NvU32 activityCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT];
NvU8 reserved[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
} NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS;
/*
* NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA
*
* This command reports the TDR data collected by KMD to be added to the
* nocat record
*
* dataType:
* [IN] specifies the type of data provided.
* targetRecordType
* [IN] specifies record type the data is intended for.
* nocatJournalData
* [IN] specifies the data to be added.
*/
#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */
// data types & structures
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY 0
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD 2
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 3
#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0
#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1
#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP 2
#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET 3
#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4
#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5
#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6
#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7
typedef struct NV2080CtrlNocatJournalDataTdrReason {
NvU32 flags;
NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 subsystem;
NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
NvU32 reasonCode;
} NV2080CtrlNocatJournalDataTdrReason;
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR 0:0
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES 1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO 0
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER 1:1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1
#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO 0
typedef struct NV2080CtrlNocatJournalInsertRecord {
NvU32 flags;
NvU8 recType;
NvU32 bugcheck;
NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 subsystem;
NV_DECLARE_ALIGNED(NvU64 errorCode, 8);
NvU8 faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
NvU32 tdrReason;
} NV2080CtrlNocatJournalInsertRecord;
#define NV2080_CTRL_NOCAT_TAG_CLEAR 0:0
#define NV2080_CTRL_NOCAT_TAG_CLEAR_YES 1
#define NV2080_CTRL_NOCAT_TAG_CLEAR_NO 0
typedef struct NV2080CtrlNocatJournalSetTag {
NvU32 flags;
NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
} NV2080CtrlNocatJournalSetTag;
#define NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS {
NvU32 dataType;
NvU32 targetRecordType;
union {
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8);
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord insertData, 8);
NV2080CtrlNocatJournalSetTag tagData;
} nocatJournalData;
} NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS;
/* _ctr2080nvd_h_ */

2723
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h Normal file
View File

File diff suppressed because it is too large Load Diff

508
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h Normal file
View File

@@ -0,0 +1,508 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080perf.finn
//
#include "nvfixedtypes.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
#define NV_SUBPROC_NAME_MAX_LENGTH 100
#include "nvmisc.h"
#include "ctrl/ctrl2080/ctrl2080clk.h"
#include "ctrl/ctrl2080/ctrl2080gpumon.h"
#include "ctrl/ctrl2080/ctrl2080volt.h"
#include "ctrl/ctrl2080/ctrl2080vfe.h"
#include "ctrl/ctrl2080/ctrl2080pmumon.h"
#include "ctrl/ctrl0080/ctrl0080perf.h"
//
// XAPICHK/XAPI_TEST chokes on the "static NVINLINE" defines in nvmisc.h.
// However, we don't need any of those definitions for those tests (XAPICHK is a
// syntactical check, not a functional test). So, instead, just #define out the
// macros referenced below.
//
/*
* NV2080_CTRL_CMD_PERF_BOOST
*
* This command can be used to boost P-State up one level or to the highest for a limited
* duration for the associated subdevice. Boosts from different clients are being tracked
* independently. Note that there are other factors that can limit P-States so the resulting
* P-State may differ from expectation.
*
* flags
* This parameter specifies the actual command. _CLEAR is to clear existing boost.
* _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost
* to the highest P-State.
* duration
* This parameter specifies the duration of the boost in seconds. This has to be less
* than NV2080_CTRL_PERF_BOOST_DURATION_MAX.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD 1:0
#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR (0x00000000)
#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL (0x00000001)
#define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX (0x00000002)
#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA 4:4
#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO (0x00000000)
#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES (0x00000001)
#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC 5:5
#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO (0x00000000)
#define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES (0x00000001)
#define NV2080_CTRL_PERF_BOOST_DURATION_MAX 3600 //The duration can be specified up to 1 hour
#define NV2080_CTRL_PERF_BOOST_DURATION_INFINITE 0xffffffff // If set this way, the boost will last until cleared.
#define NV2080_CTRL_CMD_PERF_BOOST (0x2080200a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV2080_CTRL_PERF_BOOST_PARAMS {
NvU32 flags;
NvU32 duration;
} NV2080_CTRL_PERF_BOOST_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW
*
* This command reserves HW Performance Monitoring capabilities for exclusive
* use by the requester. If the HW Performance Monitoring capabilities are
* currently in use then NVOS_STATUS_ERROR_STATE_IN_USE is returned.
*
* bAcquire
* When set to TRUE this parameter indicates that the client wants to
* acquire the Performance Monitoring capabilities on the subdevice.
* When set to FALSE this parameter releases the Performance Monitoring
* capabilities on the subdevice.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_ERROR_STATE_IN_USE
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW (0x20802093) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID (0x93U)
typedef struct NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS {
NvBool bAcquire;
} NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS;
/*!
* Enumeration of the RATED_TDP arbitration clients which make requests to force
* enable/disable VF points above the RATED_TDP point.
*
* These clients are sorted in descending priority - the RM will arbitrate
* between all clients in order of priority, taking as output the first client
* whose input action != @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT.
*/
typedef enum NV2080_CTRL_PERF_RATED_TDP_CLIENT {
/*!
* Internal RM client corresponding to the RM's internal state and features.
* The RM client will either allow default behavior (@ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT) or will limit to RATED_TDP
* (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) when no power
* controllers are active.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = 0,
/*!
* This Client is specifically for Bug 1785342 where we need to limit the TDP
* to Min value on boot. And clear the Max TDP limit.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = 1,
/*!
* Global client request. This client is expected to be used by a global
* switch functionality in an end-user tool, such as EVGA Precision, to
* either force enabling boost above RATED_TDP (@ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED) or to force limiting to
* RATED_TDP (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) across the
* board, regardless of any app-profie settings.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = 2,
/*!
* Operating system request. This client is expected to be used by the
* operating system to set @ref NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK
* for performance profiling.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = 3,
/*!
* App profile client requests. This client is expected to be used by the
* app-profile settings to either default to whatever was requested by
* higher-priority clients (@ref NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT)
* or to limit to RATED_TDP (@ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT) for apps which have shown
* bad behavior when boosting.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = 4,
/*!
* Number of supported clients.
*
* @Note MUST ALWAYS BE LAST!
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = 5,
} NV2080_CTRL_PERF_RATED_TDP_CLIENT;
/*!
* Enumeration RATED_TDP actions - these are the requested actions clients can
* make to change the behavior of the RATED_TDP functionality.
*/
typedef enum NV2080_CTRL_PERF_RATED_TDP_ACTION {
/*!
* The default action - meaning no explicit request from the client other
* than to take the default behavior (allowing boosting above RATED_TDP) or
* any explicit actions from lower priority clients.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = 0,
/*!
* Force allow boosting above RATED_TDP - this action explicitly requests
* boosting above RATED_TDP, preventing lower priority clients to limit to
* RATED_TDP.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = 1,
/*!
* Force to limit above RATED_TDP - this action explicitly requests to limit
* to RATED_TDP. This is the opposite of the default behavior to allow
* boosting above RATED_TDP. Clients specify this action when they
* explicitly need boost to be disabled (e.g. eliminating perf variation,
* special apps which exhibit bad behavior, etc.).
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = 2,
/*!
* Lock to RATED_TDP - this action requests the clocks to be fixed at the
* RATED_TDP. Used for achieving stable clocks required for profiling.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = 3,
/*!
* Lock to Min TDP - This requests min to be fixed at RATED_TDP but allow
* boosting for max
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = 4,
} NV2080_CTRL_PERF_RATED_TDP_ACTION;
/*!
* Structure describing dynamic state of the RATED_TDP feature.
*/
#define NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID (0x6DU)
typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS {
/*!
* Structure of internal RM state - these values are used to determine the
* behavior of NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM per the RM's @ref
* perfPwrRatedTdpLimitRegisterClientActive() interface.
*/
struct {
/*!
* [out] - Mask of active client controllers (@ref
* PERF_PWR_RATED_TDP_CLIENT) which are currently regulating TDP. When
* this mask is zero, NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
*/
NvU32 clientActiveMask;
/*!
* [out] - Boolean indicating that user has requested locking to
* RATED_TDP vPstate via corresponding regkey
* NV_REG_STR_RM_PERF_RATED_TDP_LIMIT. When the boolean value is true,
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM will request
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
*/
NvU8 bRegkeyLimitRatedTdp;
} rm;
/*!
* [out] - Arbitrated output action of all client requests (@ref inputs).
* This is the current state of the RATED_TDP feature. Will only be @ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED or @ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION output;
/*!
* [out] - Array of input client request actions, indexed via @ref
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_<xyz>. RM will arbitrate between these
* requests, choosing the highest priority request != @ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS];
} NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS;
/*!
* NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL
*
* This command retrieves the current requested RATED_TDP action corresponding
* to the specified client.
*
* See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of
* parameters.
*
* Possible status values returned are
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6E" */
/*!
* NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL
*
* This command sets the requested RATED_TDP action corresponding to the
* specified client. @Note, however, that this command is unable to set @ref
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM.
*
* See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of
* parameters.
*
* Possible status values returned are
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6F" */
/*!
* Structure containing the requested action for a RATED_TDP client (@ref
* NV2080_CTRL_PERF_RATED_TDP_CLIENT).
*/
typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS {
/*!
* [in] - Specified client for request.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT client;
/*!
* [in/out] - Client's requested action.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION input;
} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS;
/*!
* This struct represents the GPU monitoring perfmon sample for an engine.
*/
typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE {
/*!
* Percentage during the sample that the engine remains busy. This
* is in units of pct*100.
*/
NvU32 util;
/*!
* Scaling factor to convert utilization from full GPU to per vGPU.
*/
NvU32 vgpuScale;
/*!
* Process ID of the process that was active on the engine when the
* sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID
* will be returned.
*/
NvU32 procId;
/*!
* Process ID of the process in the vGPU VM that was active on the engine when
* the sample was taken. If no process is active then NV2080_GPUMON_PID_INVALID
* will be returned.
*/
NvU32 subProcessID;
/*!
* Process name of the process in the vGPU VM that was active on the engine when
* the sample was taken. If no process is active then NULL will be returned.
*/
char subProcessName[NV_SUBPROC_NAME_MAX_LENGTH];
} NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE;
/*!
* This struct represents the GPU monitoring perfmon sample.
*/
typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE {
/*!
* Base GPU monitoring sample.
*/
NV_DECLARE_ALIGNED(NV2080_CTRL_GPUMON_SAMPLE base, 8);
/*!
* FB bandwidth utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb;
/*!
* GR utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr;
/*!
* NV ENCODER utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc;
/*!
* NV DECODER utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec;
} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE;
/*!
* This struct represents the GPU monitoring samples of perfmon values that
* client wants the access to.
*/
#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID (0x83U)
typedef NV2080_CTRL_GPUMON_SAMPLES NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM;
/*!
* Number of GPU monitoring sample in their respective buffers.
*/
#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 100
#define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE \
NV_SIZEOF32(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \
NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL
/*!
* NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2
*
* This command returns perfmon gpu monitoring utilization samples.
* This command is not supported with SMC enabled.
*
* See NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_V2 for documentation
* on the parameters.
*
* Possible status values returned are
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*
* Note this is the same as NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES
* but without the embedded pointer.
*
*/
#define NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 (0x20802096) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID" */
/*!
* This structure represents the GPU monitoring samples of utilization values that
* the client wants access to.
*/
#define NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID (0x96U)
typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS {
/*!
* Type of the sample, see NV2080_CTRL_GPUMON_SAMPLE_TYPE_* for reference.
*/
NvU8 type;
/*!
* Size of the buffer, this should be
* bufSize == NV2080_CTRL_*_GPUMON_SAMPLE_COUNT_*
* sizeof(derived type of NV2080_CTRL_GPUMON_SAMPLE).
*/
NvU32 bufSize;
/*!
* Number of samples in ring buffer.
*/
NvU32 count;
/*!
* tracks the offset of the tail in the circular queue array pSamples.
*/
NvU32 tracker;
/*!
* A circular queue with size == bufSize.
*
* @note This circular queue wraps around after 10 seconds of sampling,
* and it is clients' responsibility to query within this time frame in
* order to avoid losing samples.
* @note With one exception, this queue contains last 10 seconds of samples
* with tracker poiniting to oldest entry and entry before tracker as the
* newest entry. Exception is when queue is not full (i.e. tracker is
* pointing to a zeroed out entry), in that case valid entries are between 0
* and tracker.
* @note Clients can store tracker from previous query in order to provide
* samples since last read.
*/
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL], 8);
} NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS;
/*
* NV2080_CTRL_CMD_PERF_GPU_IS_IDLE
*
* This command notifies RM to make p state switching aggressive by setting
* required limiting factors to speed up GC6 Entry initiation.
*
* prevPstate [out]
* This parameter will contain the pstate before the switch was initiated
*
* Possible status return values are:
* NV_OK : If P State Switch is successful
* NV_INVALID_STATE : If unable to access P State structure
* NVOS_STATUS_ERROR : If P State Switch is unsuccessful
*/
#define NV2080_CTRL_CMD_PERF_GPU_IS_IDLE (0x20802089) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS {
NvU32 prevPstate;
NvU32 action;
} NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS;
#define NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE (0x00000001)
#define NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE (0x00000002)
/*
* NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY
*
* This command is for the KMD Aggressive P-state feature.
*
* bGpuIsIdle [in]
* When true, applies cap to lowest P-state/GPCCLK. When false, releases cap.
* idleTimeUs [in]
* The amount of time (in microseconds) the GPU was idle since previous
* call, part of the GPU utilization data from KMD.
* busyTimeUs [in]
* The amount of time (in microseconds) the GPU was not idle since
* previous call, part of the GPU utilization data from KMD.
*
* Possible status return values are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY (0x2080208f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID (0x8FU)
typedef struct NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS {
NvBool bGpuIsIdle;
NvBool bRestoreToMax;
NV_DECLARE_ALIGNED(NvU64 idleTimeUs, 8);
NV_DECLARE_ALIGNED(NvU64 busyTimeUs, 8);
} NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS;
/* _ctrl2080perf_h_ */

34
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h Normal file
View File

@@ -0,0 +1,34 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn
//
/* _ctrl2080perf_cf_h_ */

32
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn
//

32
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn
//

34
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h Normal file
View File

@@ -0,0 +1,34 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn
//

32
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080power.finn
//

371
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h Normal file
View File

@@ -0,0 +1,371 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080rc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*
* NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM
*
* This command returns data read from the specified virtual memory address for
* the associated subdevice.
*
* hChannel
* This parameter specifies the channel object handle from which the virtual
* memory range applies.
* virtAddress
* This parameter specifies the GPU base virtual memory address from which data should
* be read. The amount of data read is specified by the bufferSize parameter.
* bufferPtr
* This parameter specifies the buffer address in the caller's address space into which
* the data is to be returned. The address must be aligned on an 8-byte boundary.
* The buffer must be at least as big as the value specified bufferSize parameter (in bytes).
* bufferSize
* This parameter specifies the size of the buffer referenced by the bufferPtr parameter.
* This parameter also indicates the total number of bytes to be returned.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_XLATE
*/
#define NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS {
NvHandle hChannel;
NV_DECLARE_ALIGNED(NvU64 virtAddress, 8);
NV_DECLARE_ALIGNED(NvP64 bufferPtr, 8);
NvU32 bufferSize;
} NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS;
#define NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM (0x20802204) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_RC_GET_ERROR_COUNT
*
* This command returns the number of RC errors.
*
* errorCount
* Number of RC errors.
*
* Note: If SMC is enabled, mig/monitor capability must be acquired to query
* aggregate information. Otherwise, the control call returns
* NV_ERR_INSUFFICIENT_PERMISSIONS.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INSUFFICIENT_PERMISSIONS.
*/
#define NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS {
NvU32 errorCount;
} NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS;
#define NV2080_CTRL_CMD_RC_GET_ERROR_COUNT (0x20802205) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE (0x2000) /* finn: Evaluated from "(8 * 1024)" */
#define NV2080_CTRL_CMD_RC_GET_ERROR (0x20802206) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x6" */
/*
* NV2080_CTRL_CMD_RC_GET_ERROR_V2
*
* This command returns an error element in the RC error list.
*
* whichBuffer
* Which Error to return (0 is oldest)
* outputRecordSize
* Output Size of Buffer -- Zero if error record doesn't exist
* recordBuffer
* buffer
*
* Note: If SMC is enabled, mig/monitor capability must be acquired to query
* aggregate information. Otherwise, the control call returns
* NV_ERR_INSUFFICIENT_PERMISSIONS.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INSUFFICIENT_PERMISSIONS.
*
*/
#define NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV2080_CTRL_RC_GET_ERROR_V2_PARAMS {
NvU32 whichBuffer; // [IN] - which error to return (0 is oldest)
NvU32 outputRecordSize; // [OUT]
NvU8 recordBuffer[NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE];
} NV2080_CTRL_RC_GET_ERROR_V2_PARAMS;
#define NV2080_CTRL_CMD_RC_GET_ERROR_V2 (0x20802213) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY
*
* This command cleans error history.
*
* This command has no input parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY (0x20802207) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x7" */
/*
* NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO
*
* This command returns information about the RC watchdog.
*
* watchdogStatusFlags
* This output parameter is a combination of one or more of the following:
*
* NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE
* This is the value of watchdogStatusFlags if no flags are set.
*
* NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED
* This means that the watchdog is disabled.
*
* NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING
* This means that the watchdog is running.
*
* NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED
* This means that the watchdog has been initialized.
*
* A typical result would be either "running and initialized", or
* "disabled". However, "initialized, but not running, and not disabled"
* is also quite reasonable (if the computer is hibernating, for example).
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS {
NvU32 watchdogStatusFlags;
} NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS;
#define NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO (0x20802209) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID" */
/* valid values for watchdogStatusFlags */
#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE (0x00000000)
#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED (0x00000001)
#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING (0x00000002)
#define NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED (0x00000004)
/*
* NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG
*
* This command disables the RC watchdog, if possible.
* If, however, another RM client has already explicitly (via NV2080 call) enabled
* the RC watchdog, then this method returns NV_ERR_STATE_IN_USE.
*
* This command, if successful, will prevent other clients from enabling the
* watchdog until the calling RM client releases its request with
* NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS or frees its NV20_SUBDEVICE.
*
* See NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG for disabling the watchdog
* without preventing other clients from enabling it.
*
* Possible status return values are:
* NV_OK
* NV_ERR_STATE_IN_USE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG (0x2080220a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xA" */
/*
* NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG
*
* This command enables the RC watchdog, if possible.
* If, however, another RM client has already explicitly (via NV2080 call) disabled
* the RC watchdog, then this method returns NV_ERR_STATE_IN_USE.
*
* Possible status return values are:
* NV_OK
* NV_ERR_STATE_IN_USE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG (0x2080220b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xB" */
/*
* NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS
*
* This command releases all of the RM client's outstanding requests to enable
* or disable the watchdog.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS (0x2080220c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xC" */
/*
* NV2080_CTRL_CMD_SET_RC_RECOVERY/NV2080_CTRL_CMD_GET_RC_RECOVERY
*
* This command disables/enables RC recovery.
*
* rcEnable
* NV2080_CTRL_CMD_SET_RC_RECOVERY_DISABLED
* Disable robust channel recovery.
*
* NV2080_CTRL_CMD_SET_RC_RECOVERY_ENABLED
* Enable robust channel recovery with default breakpoint handling.
*
* Possible status return values are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
typedef struct NV2080_CTRL_CMD_RC_RECOVERY_PARAMS {
NvU32 rcEnable;
} NV2080_CTRL_CMD_RC_RECOVERY_PARAMS;
#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xD" */
#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xE" */
/* valid values for rcEnable */
#define NV2080_CTRL_CMD_RC_RECOVERY_DISABLED (0x00000000)
#define NV2080_CTRL_CMD_RC_RECOVERY_ENABLED (0x00000001)
/*
* NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE
*
* This command can be used to set TDR timeout state.
*
* It can be used to indicate that a timeout has occurred and that a GPU
* reset will start. It can also be used to indicate that the reset has
* completed along with the corresponding complition status.
*
* cmd
* This parameter is used to indicate the stage of the TDR recovery
* process. Legal values for this parameter are:
* NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN
* This value indicates that TDR recovery is about to begin.
* NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END
* This value indicates that TDR recovery has completed.
*
* status
* This parameter is valid when the cmd parameter is set to
* NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END. It is used
* to specify the completion status of the TDR recovery. Legal
* values for this parameter include:
* NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL
* This value indicates the recovery failed.
* NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS
* This value indicates the recovery succeeded.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_COMMAND
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE (0x2080220f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID (0xFU)
typedef struct NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS {
NvU32 cmd;
NvS32 status;
} NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS;
/* valid cmd values */
#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN (0x00000000)
#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END (0x00000001)
/* valid status values */
#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS (0x00000000)
#define NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL (0x00000001)
/*
* NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG
*
* This command disables the RC watchdog, similarly to how
* NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG does. However, unlike that command, this
* command will not prevent another RM client from explicitly enabling the RC
* watchdog with NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG.
*
* Possible status return values are:
* NV_OK
* NV_ERR_STATE_IN_USE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG (0x20802210) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x10" */
/*
* NV2080_CTRL_CMD_GET_RC_INFO/NV2080_CTRL_CMD_SET_RC_INFO
*
* This command can be used to set robust channel parameters.
*
* rcMode
* NV2080_CTRL_CMD_SET_RC_INFO_MODE_DISABLE
* Disable robust channel operation.
*
* NV2080_CTRL_CMD_SET_RC_INFO_MODE_ENABLE
* Enable robust channel operation.
*
* rcBreak
* NV2080_CTRL_CMD_SET_RC_INFO_BREAK_DISABLE
* Disable breakpoint handling during robust channel operation.
*
* NV2080_CTRL_CMD_SET_RC_INFO_BREAK_ENABLE
* Enable breakpoint handling during robust channel operation.
*
* Possible status return values are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
typedef struct NV2080_CTRL_CMD_RC_INFO_PARAMS {
NvU32 rcMode;
NvU32 rcBreak;
} NV2080_CTRL_CMD_RC_INFO_PARAMS;
#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x11" */
#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x12" */
/* valid rcMode values */
#define NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE (0x00000000)
#define NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE (0x00000001)
/* valid rcBreak values */
#define NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE (0x00000000)
#define NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE (0x00000001)
/* _ctrl2080rc_h_ */

32
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080spi.finn
//

30
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080thermal.finn
//

236
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h Normal file
View File

@@ -0,0 +1,236 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080tmr.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_TIMER related control commands and parameters */
/*
* NV2080_CTRL_CMD_TIMER_SCHEDULE
*
* This command schedules a GPU timer event to fire at the specified time interval.
* Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and
* NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags
*
* time_nsec
* This parameter specifies the time in nanoseconds at which the GPU timer
* event is to fire.
* flags
* This parameter determines the interpretation of the value specified by
* the time_nsec parameter:
* NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS
* This flag indicates that time_nsec is in absolute time.
* NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL
* This flag indicates that time_nsec is in relative time.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_TIMER_SCHEDULE (0x20800401) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 time_nsec, 8);
NvU32 flags;
} NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS;
/* valid flag values */
#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME 0:0
#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS (0x00000000)
#define NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL (0x00000001)
/*
* NV2080_CTRL_CMD_TIMER_CANCEL
*
* This command cancels any pending timer events initiated with the
* NV2080_CTRL_CMD_TIMER_SCHEDULE command.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_TIMER_CANCEL (0x20800402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | 0x2" */
/*
* NV2080_CTRL_CMD_TIMER_GET_TIME
*
* This command returns the current GPU timer value. The current time is
* expressed in elapsed nanoseconds since 00:00 GMT, January 1, 1970
* (zero hour) with a resolution of 32 nanoseconds.
*
* Can be called without API & GPU locks if NVOS54_FLAGS_IRQL_RAISED and
* NVOS54_FLAGS_LOCK_BYPASS are set in NVOS54_PARAMETERS.flags
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_TIMER_GET_TIME (0x20800403) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_TIMER_GET_TIME_PARAMS {
NV_DECLARE_ALIGNED(NvU64 time_nsec, 8);
} NV2080_CTRL_TIMER_GET_TIME_PARAMS;
/*
* NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET
*
* The command returns the offset of the timer registers, so that clients may
* map them directly.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET (0x20800404) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS {
NvU32 tmr_offset;
} NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS;
/*
* NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE
*
* This structure describes the information obtained with
* NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO command.
*
* gpuTime
* GPU time is the value of GPU global timer (PTIMER) with a resolution
* of 32 nano seconds.
* cpuTime
* CPU time. Resolution of the cpu time depends on its source. Refer to
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_* for more information.
*/
typedef struct NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE {
NV_DECLARE_ALIGNED(NvU64 cpuTime, 8);
NV_DECLARE_ALIGNED(NvU64 gpuTime, 8);
} NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE;
/*
* NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO
*
* This command returns correlation information between GPU time and CPU time
* for a given CPU clock type.
*
* cpuClkId
* This parameter specifies the source of the CPU clock. Legal values for
* this parameter include:
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME
* This clock id will provide real time in microseconds since
* 00:00:00 UTC on January 1, 1970.
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API
* This clock id will provide time stamp that is constant-rate, high
* precision using platform API that is also available in the user mode.
* NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC
* This clock id will provide time stamp using CPU's time stamp counter.
*
* sampleCount
* This field specifies the number of clock samples to be taken.
* This value cannot exceed NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES.
*
* samples
* This field returns an array of requested samples. Refer to
* NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE to get details about each entry
* in the array.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO (0x20800406) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES 16
#define NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS {
NvU8 cpuClkId;
NvU8 sampleCount;
NV_DECLARE_ALIGNED(NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE samples[NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES], 8);
} NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS;
/* Legal cpuClkId values */
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME (0x00000001)
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC (0x00000002)
#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API (0x00000003)
/*!
* NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ
*
* This command changes the frequency at which Graphics Engine time stamp is
* updated. Frequency can either be set to max or restored to default.
* Clients can independently use this call to increase the timer frequency
* as a global reference count is maintained for requests to Max frequency.
* Client is assured that the system stays in this state till the requested
* client releases the state or is killed. Timer frequency will automatically
* be restored to default when there is no pending request to increase.
*
* Note that recursive requests for the same state from the same client
* are considered invalid.
*
* bSetMaxFreq
* Set to NV_TRUE if GR tick frequency needs to be set to Max.
*
* See @ref NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS for
* documentation of parameters.
*
* Possible status values returned are
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_STATE_IN_USE
* NV_ERR_INVALID_OPERATION
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */
/*!
* This struct contains bSetMaxFreq flag.
*/
#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS {
NvBool bSetMaxFreq;
} NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS;
/* _ctrl2080tmr_h_ */

32
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080ucodefuzzer.finn
//

193
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h Normal file
View File

@@ -0,0 +1,193 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080unix.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/* NV20_SUBDEVICE_XX OS control commands and parameters */
/*
* NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT
*
* This command increases or decreases the value of the per-GPU GC6 blocker
* refCount used by Linux kernel clients to prevent the GPU from entering GC6.
*
* When the refCount is non-zero, the GPU cannot enter GC6. When the refCount
* transitions from zero to non-zero as a result of this command, the GPU will
* automatically come out of GC6.
*
* action Whether to increment or decrement the value of the refCount.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT (0x20803d01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS {
NvU32 action;
} NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS;
// Possible values for action
#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC (0x00000001)
#define NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC (0x00000002)
/*
* NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF
*
* RM by default allows GCOFF but when the X driver disallows to enter in GCOFF
* then this rmcontrol sets flag as NV_FALSE and if it allows to enter in GCOFF
* then the flag is set as NV_TRUE.
*
* action Whether to allow or disallow the user mode clients to enter in GCOFF.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF (0x20803d02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS {
NvU32 action;
} NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS;
// Possible values for action
#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW (0x00000001)
#define NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW (0x00000002)
/*
* NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER
*
* GPU can have integrated HDA (High Definition Audio) controller which
* can be in active or suspended state during dynamic power management.
* This command will perform HDA controller wakeup (if bEnter is false) or
* suspend (if bEnter is true).
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER (0x20803d03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS {
NvBool bEnter;
} NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS;
/*
* NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS
*
* Initialize cyclestats HWPM support in the kernel. This will set up a callback
* event for the channel indicated by hNotifierResource. This callback will execute
* perf register read / write commands enqueued in the shared buffer indicated by
* hNotifyDataMemory. Only one client may use HWPM functionality at a time.
*
* Additionally, if perfmonIdCount is greater than zero, mode-e HWPM streaming into
* the buffer indicated by hSnapshotMemory will be initialized (but not turned on).
* Data will be copied into the provided buffer every 10ms, or whenever a
* NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER command is issued.
*/
#define NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS (0x20803d04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS {
NvHandle hNotifierResource;
NvU32 notifyDataSize;
NvHandle hNotifyDataMemory;
NvU32 perfmonIdCount;
NvU32 snapshotBufferSize;
NvHandle hSnapshotMemory;
} NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS;
/*
* NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER
*
* Immediately copies any pending mode-e HWPM data into the previously
* installed snapshot buffer instead of waiting for the timer.
*/
#define NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER (0x20803d05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x5" */
/*
* NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER
*
* Stop the timer responsible for copying mode-e HWPM data to the snapshot buffer.
* The snapshot buffer must not be freed by the client before this command is issued.
*/
#define NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER (0x20803d06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | 0x6" */
/*
* NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS
*
* This command will be used by clients to check if the GPU video memory will
* be persistent during system suspend/resume cycle.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS (0x20803d07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS {
NvBool bVidmemPersistent;
} NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS
*
* This command will be used by clients to set restore TGP flag which will
* help to restore TGP limits when clients are destroyed.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS (0x20803d08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS {
NvBool bUpdateTGP;
} NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS;
/* _ctrl2080unix_h_ */

44
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h Normal file
View File

@@ -0,0 +1,44 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080vfe.finn
//
/* _ctrl2080vfe_h_ */
#include "nvfixedtypes.h"
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobj.h"
#include "ctrl/ctrl2080/ctrl2080bios.h"
/* --------------------------- Forward Defines ----------------------------- */
/* --------------------------- VFE Variable -------------------------------- */
/* --------------------------- VFE Equation -------------------------------- */

41
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h Normal file
View File

@@ -0,0 +1,41 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080volt.finn
//
/* _ctrl2080volt_h_ */
#include "ctrl/ctrl2080/ctrl2080base.h"
#include "ctrl/ctrl2080/ctrl2080boardobj.h"
#include "ctrl/ctrl2080/ctrl2080pmumon.h"