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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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515.43.04
This commit is contained in:
Andy Ritger
312
src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h
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312
src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <nvtypes.h>
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: ctrl/ctrl90f1.finn
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//
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#include "ctrl/ctrlxxxx.h"
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#include "mmu_fmt_types.h"
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#define GMMU_FMT_MAX_LEVELS 6
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/* Fermi+ GPU VASpace control commands and parameters */
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#define NV90F1_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90F1, NV90F1_CTRL_##cat, idx)
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/* Command categories (6bits) */
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#define NV90F1_CTRL_RESERVED (0x00)
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#define NV90F1_CTRL_VASPACE (0x01)
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/*!
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* Does nothing.
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*/
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#define NV90F1_CTRL_CMD_NULL (0x90f10000) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
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/*!
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* Get VAS GPU MMU format.
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*/
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#define NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT (0x90f10101) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID" */
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#define NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID (0x1U)
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typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS {
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/*!
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* [in] GPU sub-device handle - this API only supports unicast.
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* Pass 0 to use subDeviceId instead.
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*/
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NvHandle hSubDevice;
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/*!
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* [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
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*/
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NvU32 subDeviceId;
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/*!
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* [out] GMMU format struct. This is of RM-internal type "struct GMMU_FMT*"
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* which can only be accessed by kernel builds since this is a kernel
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* only API.
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*/
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NV_DECLARE_ALIGNED(NvP64 pFmt, 8);
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} NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS;
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/*!
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* Get VAS page level information.
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*/
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#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x2" */
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typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS {
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/*!
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* [in] GPU sub-device handle - this API only supports unicast.
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* Pass 0 to use subDeviceId instead.
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*/
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NvHandle hSubDevice;
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/*!
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* [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
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*/
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NvU32 subDeviceId;
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/*!
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* [in] GPU virtual address to query.
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*/
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NV_DECLARE_ALIGNED(NvU64 virtAddress, 8);
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/*!
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* [in] Page size to query.
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*/
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NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
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/*!
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* [out] Number of levels populated.
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*/
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NvU32 numLevels;
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/*!
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* [out] Per-level information.
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*/
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struct {
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/*!
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* Format of this level.
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*/
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NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8);
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/*!
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* Level/Sublevel Formats flattened
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*/
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NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8);
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NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8);
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/*!
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* Physical address of this page level instance.
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*/
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NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
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/*!
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* Aperture in which this page level instance resides.
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*/
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NvU32 aperture;
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/*!
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* Size in bytes allocated for this level instance.
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*/
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NV_DECLARE_ALIGNED(NvU64 size, 8);
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} levels[GMMU_FMT_MAX_LEVELS];
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} NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS;
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/*!
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* Reserve (allocate and bind) page directory/table entries up to
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* a given level of the MMU format. Also referred to as "lock-down".
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*
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* Each range that has been reserved must be released
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* eventually with @ref NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES.
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* A particular VA range and level (page size) combination may only be
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* locked down once at a given time, but each level is independent.
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*/
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#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */
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#define NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID (0x3U)
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typedef struct NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS {
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/*!
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* [in] GPU sub-device handle - this API only supports unicast.
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* Pass 0 to use subDeviceId instead.
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*/
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NvHandle hSubDevice;
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/*!
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* [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
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*/
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NvU32 subDeviceId;
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/*!
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* [in] Page size (VA coverage) of the level to reserve.
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* This need not be a leaf (page table) page size - it can be
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* the coverage of an arbitrary level (including root page directory).
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*/
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NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
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/*!
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* [in] First GPU virtual address of the range to reserve.
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* This must be aligned to pageSize.
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*/
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NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8);
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/*!
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* [in] Last GPU virtual address of the range to reserve.
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* This (+1) must be aligned to pageSize.
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*/
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NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8);
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} NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS;
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/*!
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* Release (unbind and free) page directory/table entries up to
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* a given level of the MMU format that has been reserved through a call to
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* @ref NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES. Also referred to as "unlock".
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*/
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#define NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES (0x90f10104) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID" */
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#define NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID (0x4U)
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typedef struct NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS {
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/*!
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* [in] GPU sub-device handle - this API only supports unicast.
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* Pass 0 to use subDeviceId instead.
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*/
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NvHandle hSubDevice;
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/*!
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* [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
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*/
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NvU32 subDeviceId;
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/*!
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* [in] Page size (VA coverage) of the level to release.
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* This need not be a leaf (page table) page size - it can be
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* the coverage of an arbitrary level (including root page directory).
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*/
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NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
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/*!
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* [in] First GPU virtual address of the range to release.
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* This must be aligned to pageSize.
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*/
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NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8);
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/*!
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* [in] Last GPU virtual address of the range to release.
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* This (+1) must be aligned to pageSize.
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*/
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NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8);
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} NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS;
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/*!
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* Get VAS page level information without kernel priviledge. This will internally call
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* NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO.
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*/
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#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x5" */
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/*!
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* Pin PDEs for a given VA range on the server RM and then mirror the client's page
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* directory/tables in the server.
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*
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* @ref
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*/
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#define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */
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#define NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID (0x6U)
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typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS {
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/*!
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* [in] GPU sub-device handle - this API only supports unicast.
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* Pass 0 to use subDeviceId instead.
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*/
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NvHandle hSubDevice;
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/*!
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* [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
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*/
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NvU32 subDeviceId;
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/*!
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* [in] Page size (VA coverage) of the level to reserve.
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* This need not be a leaf (page table) page size - it can be
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* the coverage of an arbitrary level (including root page directory).
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*/
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NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
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/*!
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* [in] First GPU virtual address of the range to reserve.
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* This must be aligned to pageSize.
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*/
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NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8);
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/*!
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* [in] Last GPU virtual address of the range to reserve.
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* This (+1) must be aligned to pageSize.
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*/
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NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8);
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/*!
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* [in] Number of PDE levels to copy.
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*/
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NvU32 numLevelsToCopy;
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/*!
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* [in] Per-level information.
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*/
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struct {
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/*!
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* Physical address of this page level instance.
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*/
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NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
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/*!
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* Size in bytes allocated for this level instance.
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*/
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NV_DECLARE_ALIGNED(NvU64 size, 8);
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/*!
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* Aperture in which this page level instance resides.
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*/
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NvU32 aperture;
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/*!
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* Page shift corresponding to the level
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*/
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NvU8 pageShift;
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} levels[GMMU_FMT_MAX_LEVELS];
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} NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS;
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/* _ctrl90f1_h_ */
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