mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-03-06 05:39:51 +00:00
515.43.04
This commit is contained in:
Andy Ritger
349
src/nvidia/generated/g_sdk-structures.h
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349
src/nvidia/generated/g_sdk-structures.h
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@@ -0,0 +1,349 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* WARNING: This is an autogenerated file. DO NOT EDIT.
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* This file is generated using below files:
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* template file: kernel/inc/vgpu/gt_sdk-structures.h
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* definition file: kernel/inc/vgpu/sdk-structures.def
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*/
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#ifdef SDK_STRUCTURES
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// These are copy of sdk structures, that will be used for the communication between the vmioplugin & guest RM.
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#include "vgpu/sdk-structures.h"
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typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00
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{
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NvU64 physAddress NV_ALIGN_BYTES(8);
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NvU32 numEntries;
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NvU32 flags;
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NvHandle hVASpace;
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NvU32 chId;
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NvU32 subDeviceId;
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} NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00;
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typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05
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{
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NvU64 physAddress NV_ALIGN_BYTES(8);
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NvU32 numEntries;
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NvU32 flags;
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NvHandle hVASpace;
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NvU32 chId;
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NvU32 subDeviceId;
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NvU32 pasid;
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} NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05;
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typedef NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05 NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v;
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typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v03_00
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{
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NvU64 physAddr NV_ALIGN_BYTES(8);
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NvU32 numEntries;
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NvU32 aperture;
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} NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v03_00;
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typedef NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v03_00 NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v;
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typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v03_00
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{
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NvU32 pdeIndex;
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NvU32 flags;
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NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v03_00 ptParams[NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE];
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NvHandle hVASpace;
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NvP64 pPdeBuffer NV_ALIGN_BYTES(8);
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NvU32 subDeviceId;
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} NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v03_00;
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typedef NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v03_00 NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v;
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typedef struct NVOS00_PARAMETERS_v03_00
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{
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NvHandle hRoot;
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NvHandle hObjectParent;
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NvHandle hObjectOld;
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NvV32 status;
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} NVOS00_PARAMETERS_v03_00;
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typedef NVOS00_PARAMETERS_v03_00 NVOS00_PARAMETERS_v;
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typedef struct NVOS46_PARAMETERS_v03_00
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{
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NvHandle hClient;
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NvHandle hDevice;
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NvHandle hDma;
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NvHandle hMemory;
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NvU64 offset NV_ALIGN_BYTES(8);
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NvU64 length NV_ALIGN_BYTES(8);
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NvV32 flags;
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NvU64 dmaOffset NV_ALIGN_BYTES(8);
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NvV32 status;
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} NVOS46_PARAMETERS_v03_00;
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typedef NVOS46_PARAMETERS_v03_00 NVOS46_PARAMETERS_v;
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typedef struct NVOS47_PARAMETERS_v03_00
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{
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NvHandle hClient;
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NvHandle hDevice;
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NvHandle hDma;
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NvHandle hMemory;
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NvV32 flags;
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NvU64 dmaOffset NV_ALIGN_BYTES(8);
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NvV32 status;
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} NVOS47_PARAMETERS_v03_00;
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typedef NVOS47_PARAMETERS_v03_00 NVOS47_PARAMETERS_v;
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typedef struct NVOS55_PARAMETERS_v03_00
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{
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NvHandle hClient;
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NvHandle hParent;
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NvHandle hObject;
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NvHandle hClientSrc;
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NvHandle hObjectSrc;
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NvU32 flags;
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NvU32 status;
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} NVOS55_PARAMETERS_v03_00;
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typedef NVOS55_PARAMETERS_v03_00 NVOS55_PARAMETERS_v;
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typedef struct NV2080_CTRL_GR_ROUTE_INFO_v12_01
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{
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NvU32 flags;
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NvU64 route NV_ALIGN_BYTES(8);
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} NV2080_CTRL_GR_ROUTE_INFO_v12_01;
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typedef NV2080_CTRL_GR_ROUTE_INFO_v12_01 NV2080_CTRL_GR_ROUTE_INFO_v;
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typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v03_00
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{
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NvHandle hClientTarget;
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NvHandle hChannelTarget;
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NvU32 reserved00[3];
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NvU32 regOpCount;
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NvP64 regOps NV_ALIGN_BYTES(8);
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} NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v03_00;
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typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01
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{
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NvHandle hClientTarget;
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NvHandle hChannelTarget;
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NvU32 reserved00[3];
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NvU32 regOpCount;
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NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo;
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NvP64 regOps NV_ALIGN_BYTES(8);
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} NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01;
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typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01 NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v;
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typedef struct NV2080_CTRL_GPU_REG_OP_v03_00
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{
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NvU8 regOp;
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NvU8 regType;
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NvU8 regStatus;
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NvU8 regQuad;
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NvU32 regGroupMask;
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NvU32 regSubGroupMask;
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NvU32 regOffset;
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NvU32 regValueHi;
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NvU32 regValueLo;
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NvU32 regAndNMaskHi;
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NvU32 regAndNMaskLo;
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} NV2080_CTRL_GPU_REG_OP_v03_00;
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typedef NV2080_CTRL_GPU_REG_OP_v03_00 NV2080_CTRL_GPU_REG_OP_v;
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typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01
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{
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NvU32 util;
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NvU32 procId;
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} NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01;
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typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00
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{
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NvU32 util;
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NvU32 procId;
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NvU32 subProcessID;
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} NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00;
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typedef NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v;
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typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v06_01
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{
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NvU64 timeStamp NV_ALIGN_BYTES(8);
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NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 fb;
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NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 gr;
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NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 nvenc;
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NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 nvdec;
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} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v06_01;
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typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v17_00
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{
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NvU64 timeStamp NV_ALIGN_BYTES(8);
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NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 fb;
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NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 gr;
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NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 nvenc;
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NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 nvdec;
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} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v17_00;
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typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E
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{
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NvU64 timeStamp NV_ALIGN_BYTES(8);
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NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 fb;
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NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 gr;
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NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 nvenc;
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NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 nvdec;
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} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E;
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typedef NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v;
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typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00
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{
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NvU8 type;
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NvU32 bufSize;
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NvU32 count;
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NvU32 tracker;
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NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v17_00 samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL];
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} NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00;
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typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E
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{
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NvU8 type;
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NvU32 bufSize;
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NvU32 count;
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NvU32 tracker;
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NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL];
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} NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E;
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typedef NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v;
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typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00
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{
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NvU32 flags;
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NvBool bBridgeless;
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NvU32 currLimits[NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM];
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} NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00;
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typedef NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v;
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typedef struct UpdateBarPde_v15_00
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{
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NV_RPC_UPDATE_PDE_BAR_TYPE barType;
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NvU64 entryValue NV_ALIGN_BYTES(8);
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NvU64 entryLevelShift NV_ALIGN_BYTES(8);
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} UpdateBarPde_v15_00;
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typedef UpdateBarPde_v15_00 UpdateBarPde_v;
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typedef struct gpu_exec_reg_ops_v03_00
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{
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NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v03_00 reg_op_params;
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NV2080_CTRL_GPU_REG_OP_v03_00 operations[];
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} gpu_exec_reg_ops_v03_00;
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typedef struct gpu_exec_reg_ops_v12_01
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{
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NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01 reg_op_params;
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NV2080_CTRL_GPU_REG_OP_v03_00 operations[];
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} gpu_exec_reg_ops_v12_01;
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typedef gpu_exec_reg_ops_v12_01 gpu_exec_reg_ops_v;
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typedef struct idle_channel_list_v03_00
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{
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NvU32 phClient;
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NvU32 phDevice;
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NvU32 phChannel;
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} idle_channel_list_v03_00;
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typedef idle_channel_list_v03_00 idle_channel_list_v;
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typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00
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{
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NvHandle hVASpace;
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NvU32 subDeviceId;
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} NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00;
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typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05
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{
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NvHandle hVASpace;
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NvU32 subDeviceId;
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} NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05;
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typedef NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v;
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typedef struct NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F
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{
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NvU32 regOpCount;
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NVB0CC_REGOPS_MODE mode;
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NvBool bPassed;
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NvBool bDirect;
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NV2080_CTRL_GPU_REG_OP_v03_00 regOps[NVB0CC_REGOPS_MAX_COUNT];
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} NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F;
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typedef NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v;
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typedef struct ATOMIC_OP_v1F_08
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{
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NvBool bSupported;
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NvU32 attributes;
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} ATOMIC_OP_v1F_08;
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typedef ATOMIC_OP_v1F_08 ATOMIC_OP_v;
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#endif
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#ifdef SDK_UNION_MEMBER_NAME_FUNCTIONS
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#endif
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#ifdef SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD
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#endif
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#ifdef SDK_ARRAY_LENGTH_FUNCTIONS
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// Array length functions for gpu_exec_reg_ops:
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static NV_STATUS get_array_length_gpu_exec_reg_ops_v03_00_operations(void *msg, NvS32 bytes_remaining, uint32_t* length)
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{
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gpu_exec_reg_ops_v03_00 *param = msg;
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if ((NvS32)(NV_OFFSETOF(gpu_exec_reg_ops_v03_00, reg_op_params.regOpCount) + sizeof(param->reg_op_params.regOpCount)) > bytes_remaining)
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return NV_ERR_BUFFER_TOO_SMALL;
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*length = param->reg_op_params.regOpCount;
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return NV_OK;
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}
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static NV_STATUS get_array_length_gpu_exec_reg_ops_v12_01_operations(void *msg, NvS32 bytes_remaining, uint32_t* length)
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{
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gpu_exec_reg_ops_v12_01 *param = msg;
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if ((NvS32)(NV_OFFSETOF(gpu_exec_reg_ops_v12_01, reg_op_params.regOpCount) + sizeof(param->reg_op_params.regOpCount)) > bytes_remaining)
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return NV_ERR_BUFFER_TOO_SMALL;
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*length = param->reg_op_params.regOpCount;
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return NV_OK;
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}
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#endif
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