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575.64.03

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This commit is contained in:
Bernhard Stoeckner
2025-07-01 19:29:04 +02:00
parent fade1f7b20
commit 1893c6c8fd
18 changed files with 101 additions and 66 deletions
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3
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -327,6 +327,9 @@ namespace DisplayPort
//
bool bForceHeadShutdownOnModeTransition;
// Set to true when we want to skip reset MST_EN before LT
bool bSkipResetMSTMBeforeLt;
bool bReportDeviceLostBeforeNew;
bool bDisableSSC;
bool bEnableFastLT;

1
src/common/displayport/inc/dp_edid.h
View File

@@ -173,6 +173,7 @@ namespace DisplayPort
bool bForceHeadShutdownOnModeTransition;
bool bSkipCableIdCheck;
bool bAllocateManualTimeslots;
bool bSkipResetMSTMBeforeLt;
}_WARFlags;
_WARFlags WARFlags;

34
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -2787,13 +2787,13 @@ bool ConnectorImpl::isHeadShutDownNeeded(Group * target, // Group
// In case of mode transition (DSC <-> non-DSC), if the link config is same as previous mode, we need to shut down the head
// since VBID[6] needs to be updated accordingly
//
if ((bForceHeadShutdownOnModeTransition &&
if ((bForceHeadShutdownOnModeTransition &&
((modesetInfo.bEnableDsc && targetImpl->lastModesetInfo.bEnableDsc) &&
(modesetInfo.bitsPerComponent != targetImpl->lastModesetInfo.bitsPerComponent))) ||
((lowestSelected.getTotalDataRate() == activeLinkConfig.getTotalDataRate()) &&
(modesetInfo.bEnableDsc != targetImpl->lastModesetInfo.bEnableDsc)))
((lowestSelected.getTotalDataRate() == activeLinkConfig.getTotalDataRate()) &&
(modesetInfo.bEnableDsc != targetImpl->lastModesetInfo.bEnableDsc)))
{
return true;
return true;
}
// For dual DP while changing link config, we need to shut
@@ -5358,9 +5358,9 @@ bool ConnectorImpl::getValidLowestLinkConfig
{
//
// If highest link rate is UHBR 128b132b and current selected config is 8b10b,
// FEC should not be enabled if DSC is not enabled since
// 1. This function will be called only for SST and that too when preferred
// link config is not set.
// FEC should not be enabled if DSC is not enabled since
// 1. This function will be called only for SST and that too when preferred
// link config is not set.
// 2. for SST and in 8b10b mode, FEC is enabled only when DSC is enabled
//
selectedConfig.enableFEC(false);
@@ -5655,8 +5655,9 @@ bool ConnectorImpl::validateLinkConfiguration(const LinkConfiguration & lConfig)
bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
LinkTrainingType trainType)
{
LinkTrainingType preferredTrainingType = trainType;
bool result = true;
LinkTrainingType preferredTrainingType = trainType;
bool result = true;
NvBool bSkipSettingStreamMode = false;
// Validate link config against caps
if (!force && !validateLinkConfiguration(lConfig))
@@ -5693,10 +5694,16 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
}
//
// Don't set the stream if we're shutting off the link
// or forcing the config
// Don't set the stream if we're:
// - forcing the config
// - Skipping LT and the flag to skip stream mode setting is true
// - shutting off the link
//
if (!force && lConfig.lanes != 0)
bSkipSettingStreamMode = force ||
(bSkipLt && this->bSkipResetMSTMBeforeLt) ||
(lConfig.lanes == 0);
if (!bSkipSettingStreamMode)
{
if (isLinkActive())
{
@@ -7009,6 +7016,8 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
{
bDelayAfterD3 = true;
}
// Do not reset MST_EN before LT for Sony SDM27Q10S in SST mode
this->bSkipResetMSTMBeforeLt = tmpEdid.WARFlags.bSkipResetMSTMBeforeLt;
// Panels use Legacy address range for interrupt reporting
if (tmpEdid.WARFlags.useLegacyAddress)
@@ -8294,6 +8303,7 @@ void ConnectorImpl::configInit()
bDP2XPreferNonDSCForLowPClk = false;
bDisableDscMaxBppLimit = false;
bForceHeadShutdownOnModeTransition = false;
bSkipResetMSTMBeforeLt = false;
}
bool ConnectorImpl::dpUpdateDscStream(Group *target, NvU32 dscBpp)

15
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -1,4 +1,4 @@
/*
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
@@ -615,12 +615,13 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
this->WARFlags.bSkipCableIdCheck = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Panel does not expose cable capability. Ignoring it. Bug 4968411");
}
else if(ProductID == 0x24b5 || ProductID == 0x32f2)
else if(ProductID == 0x24b5 || ProductID == 0x32f2 || ProductID == 0x27BC)
{
//
// Asus ROG PG248QP (0x24b5) Bug 5100062
// Asus ROG PG32UCDM (0x32f2) Bug 5088957
//
// Asus ROG PG27AQN (0x27BC) Bug 5300665
this->WARFlags.bForceHeadShutdown = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Force head shutdown.");
}
@@ -650,6 +651,14 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
DP_PRINTF(DP_NOTICE, "DP-WAR> VRT monitor does not work with GB20x when downspread is enabled. Disabling downspread.");
}
break;
case 0xD94D: // Sony
if (ProductID == 0x07EE) // Sony SDM27Q10S
{
this->WARFlags.bSkipResetMSTMBeforeLt = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Sony SDM27Q10S needs to skip reset MST_EN before LT");
}
break;
default:
break;
}

20
src/common/inc/nvBldVer.h
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@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r575_00
#define NV_BUILD_BRANCH r576_76
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r575_00
#define NV_PUBLIC_BRANCH r576_76
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r575/r575_00-212"
#define NV_BUILD_CHANGELIST_NUM (36105353)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r575/r576_76-213"
#define NV_BUILD_CHANGELIST_NUM (36163547)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r575/r575_00-212"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36105353)
#define NV_BUILD_NAME "rel/gpu_drv/r575/r576_76-213"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36163547)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r575_00-160"
#define NV_BUILD_CHANGELIST_NUM (36104828)
#define NV_BUILD_BRANCH_VERSION "r576_76-5"
#define NV_BUILD_CHANGELIST_NUM (36158686)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "576.76"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36104828)
#define NV_BUILD_NAME "576.88"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36158686)
#define NV_BUILD_BRANCH_BASE_VERSION R575
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "575.64"
#define NV_VERSION_STRING "575.64.03"
#else

5
src/nvidia/generated/g_chipset_nvoc.h
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@@ -306,7 +306,7 @@ struct OBJCL {
struct Object *__nvoc_pbase_Object; // obj super
struct OBJCL *__nvoc_pbase_OBJCL; // cl
// 36 PDB properties
// 37 PDB properties
NvBool PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE;
NvBool PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL;
NvBool PDB_PROP_CL_ASLM_SUPPORTS_NV_LINK_UPGRADE;
@@ -340,6 +340,7 @@ struct OBJCL {
NvBool PDB_PROP_CL_UNSUPPORTED_CHIPSET;
NvBool PDB_PROP_CL_IS_CHIPSET_IO_COHERENT;
NvBool PDB_PROP_CL_DISABLE_IOMAP_WC;
NvBool PDB_PROP_CL_WAR_AMD_5107271;
NvBool PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE;
NvBool PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR;
NvBool PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS;
@@ -390,6 +391,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJCL;
#endif //__nvoc_chipset_h_disabled
// Property macros
#define PDB_PROP_CL_WAR_AMD_5107271_BASE_CAST
#define PDB_PROP_CL_WAR_AMD_5107271_BASE_NAME PDB_PROP_CL_WAR_AMD_5107271
#define PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ_BASE_CAST
#define PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ_BASE_NAME PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ
#define PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE_BASE_CAST

3
src/nvidia/generated/g_nv_name_released.h
View File

@@ -5452,8 +5452,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2D39, 0x0000, 0x0000, "NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU" },
{ 0x2D58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },
{ 0x2D83, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050" },
{ 0x2D98, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050 Laptop GPU" },
{ 0x2DB8, 0x0000, 0x0000, "NVIDIA RTX PRO 1000 Blackwell Generation Laptop GPU" },
{ 0x2DB9, 0x0000, 0x0000, "NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU" },
{ 0x2DD8, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050 Laptop GPU" },
{ 0x2F04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070" },
{ 0x2F18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },
{ 0x2F38, 0x0000, 0x0000, "NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU" },

25
src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c
View File

@@ -49,6 +49,7 @@
#include "vgpu/rpc.h"
#include "vgpu/vgpu_events.h"
#include "nvdevid.h"
//
// statics
@@ -1428,15 +1429,37 @@ memmgrGetRsvdSizeForSr_GM107
MemoryManager *pMemoryManager
)
{
//
// Temporary WAR to override WDDM S/R buffer for specific skus
// Bug 5327051
//
static const NvU16 gb20x_devid[] = { 0x2B8C };
NvU32 pciDeviceID = DRF_VAL(_PCI, _DEVID, _DEVICE, pGpu->idInfo.PCIDeviceID);
NvBool overrideFbsrRsvdBufferSize = NV_FALSE;
for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(gb20x_devid); i++)
{
if (pciDeviceID == gb20x_devid[i])
{
overrideFbsrRsvdBufferSize = NV_TRUE;
break;
}
}
if (((pMemoryManager->Ram.fbTotalMemSizeMb >> 10) >= 31) || IS_GSP_CLIENT(pGpu))
{
//
// We need to reserve more memory for S/R if
// 1. FB size is > 32GB Bug Id: 2468357
// 1. FB size is >= 31GB Bug Id: 2468357
// 2. Or GSP is enabled Bug Id: 4312881
//
return 512 * 1024 * 1024;
}
else if (overrideFbsrRsvdBufferSize)
{
// Bug 5327051: WAR to override WDDM S/R buffer for specific skus
return 300 * 1024 * 1024;
}
else
{
return 256 * 1024 * 1024;

1
src/nvidia/src/kernel/platform/chipset/chipset.c
View File

@@ -811,6 +811,7 @@ void clSyncWithGsp_IMPL(OBJCL *pCl, GspSystemInfo *pGSI)
CL_SYNC_PDB(PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE);
CL_SYNC_PDB(PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR);
CL_SYNC_PDB(PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS);
CL_SYNC_PDB(PDB_PROP_CL_WAR_AMD_5107271);
#undef CL_SYNC_PDB

3
src/nvidia/src/kernel/platform/chipset/chipset_info.c
View File

@@ -1138,6 +1138,9 @@ AMD_X370_setupFunc
)
{
// WAR for bug 5107271 handling
pCl->setProperty(pCl, PDB_PROP_CL_WAR_AMD_5107271, NV_TRUE);
// Set ASPM L0S\L1 properties
_Set_ASPM_L0S_L1(pCl, NV_FALSE, NV_FALSE);