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575.64.03

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This commit is contained in:
Bernhard Stoeckner
2025-07-01 19:29:04 +02:00
parent fade1f7b20
commit 1893c6c8fd
18 changed files with 101 additions and 66 deletions
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5
src/nvidia/generated/g_chipset_nvoc.h
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@@ -306,7 +306,7 @@ struct OBJCL {
struct Object *__nvoc_pbase_Object; // obj super
struct OBJCL *__nvoc_pbase_OBJCL; // cl
// 36 PDB properties
// 37 PDB properties
NvBool PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE;
NvBool PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL;
NvBool PDB_PROP_CL_ASLM_SUPPORTS_NV_LINK_UPGRADE;
@@ -340,6 +340,7 @@ struct OBJCL {
NvBool PDB_PROP_CL_UNSUPPORTED_CHIPSET;
NvBool PDB_PROP_CL_IS_CHIPSET_IO_COHERENT;
NvBool PDB_PROP_CL_DISABLE_IOMAP_WC;
NvBool PDB_PROP_CL_WAR_AMD_5107271;
NvBool PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE;
NvBool PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR;
NvBool PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS;
@@ -390,6 +391,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJCL;
#endif //__nvoc_chipset_h_disabled
// Property macros
#define PDB_PROP_CL_WAR_AMD_5107271_BASE_CAST
#define PDB_PROP_CL_WAR_AMD_5107271_BASE_NAME PDB_PROP_CL_WAR_AMD_5107271
#define PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ_BASE_CAST
#define PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ_BASE_NAME PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ
#define PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE_BASE_CAST

3
src/nvidia/generated/g_nv_name_released.h
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@@ -5452,8 +5452,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2D39, 0x0000, 0x0000, "NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU" },
{ 0x2D58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },
{ 0x2D83, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050" },
{ 0x2D98, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050 Laptop GPU" },
{ 0x2DB8, 0x0000, 0x0000, "NVIDIA RTX PRO 1000 Blackwell Generation Laptop GPU" },
{ 0x2DB9, 0x0000, 0x0000, "NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU" },
{ 0x2DD8, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050 Laptop GPU" },
{ 0x2F04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070" },
{ 0x2F18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },
{ 0x2F38, 0x0000, 0x0000, "NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU" },

25
src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c
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@@ -49,6 +49,7 @@
#include "vgpu/rpc.h"
#include "vgpu/vgpu_events.h"
#include "nvdevid.h"
//
// statics
@@ -1428,15 +1429,37 @@ memmgrGetRsvdSizeForSr_GM107
MemoryManager *pMemoryManager
)
{
//
// Temporary WAR to override WDDM S/R buffer for specific skus
// Bug 5327051
//
static const NvU16 gb20x_devid[] = { 0x2B8C };
NvU32 pciDeviceID = DRF_VAL(_PCI, _DEVID, _DEVICE, pGpu->idInfo.PCIDeviceID);
NvBool overrideFbsrRsvdBufferSize = NV_FALSE;
for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(gb20x_devid); i++)
{
if (pciDeviceID == gb20x_devid[i])
{
overrideFbsrRsvdBufferSize = NV_TRUE;
break;
}
}
if (((pMemoryManager->Ram.fbTotalMemSizeMb >> 10) >= 31) || IS_GSP_CLIENT(pGpu))
{
//
// We need to reserve more memory for S/R if
// 1. FB size is > 32GB Bug Id: 2468357
// 1. FB size is >= 31GB Bug Id: 2468357
// 2. Or GSP is enabled Bug Id: 4312881
//
return 512 * 1024 * 1024;
}
else if (overrideFbsrRsvdBufferSize)
{
// Bug 5327051: WAR to override WDDM S/R buffer for specific skus
return 300 * 1024 * 1024;
}
else
{
return 256 * 1024 * 1024;

1
src/nvidia/src/kernel/platform/chipset/chipset.c
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@@ -811,6 +811,7 @@ void clSyncWithGsp_IMPL(OBJCL *pCl, GspSystemInfo *pGSI)
CL_SYNC_PDB(PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE);
CL_SYNC_PDB(PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR);
CL_SYNC_PDB(PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS);
CL_SYNC_PDB(PDB_PROP_CL_WAR_AMD_5107271);
#undef CL_SYNC_PDB

3
src/nvidia/src/kernel/platform/chipset/chipset_info.c
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@@ -1138,6 +1138,9 @@ AMD_X370_setupFunc
)
{
// WAR for bug 5107271 handling
pCl->setProperty(pCl, PDB_PROP_CL_WAR_AMD_5107271, NV_TRUE);
// Set ASPM L0S\L1 properties
_Set_ASPM_L0S_L1(pCl, NV_FALSE, NV_FALSE);