575.64.03

This commit is contained in:
Bernhard Stoeckner
2025-07-01 19:29:04 +02:00
parent fade1f7b20
commit 1893c6c8fd
18 changed files with 101 additions and 66 deletions

View File

@@ -1,7 +1,7 @@
# NVIDIA Linux Open GPU Kernel Module Source # NVIDIA Linux Open GPU Kernel Module Source
This is the source release of the NVIDIA Linux open GPU kernel modules, This is the source release of the NVIDIA Linux open GPU kernel modules,
version 575.64. version 575.64.03.
## How to Build ## How to Build
@@ -17,7 +17,7 @@ as root:
Note that the kernel modules built here must be used with GSP Note that the kernel modules built here must be used with GSP
firmware and user-space NVIDIA GPU driver components from a corresponding firmware and user-space NVIDIA GPU driver components from a corresponding
575.64 driver release. This can be achieved by installing 575.64.03 driver release. This can be achieved by installing
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
option. E.g., option. E.g.,
@@ -185,7 +185,7 @@ table below).
For details on feature support and limitations, see the NVIDIA GPU driver For details on feature support and limitations, see the NVIDIA GPU driver
end user README here: end user README here:
https://us.download.nvidia.com/XFree86/Linux-x86_64/575.64/README/kernel_open.html https://us.download.nvidia.com/XFree86/Linux-x86_64/575.64.03/README/kernel_open.html
For vGPU support, please refer to the README.vgpu packaged in the vGPU Host For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
Package for more details. Package for more details.
@@ -987,8 +987,11 @@ Subsystem Device ID.
| NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU | 2D39 | | NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU | 2D39 |
| NVIDIA GeForce RTX 5070 Laptop GPU | 2D58 | | NVIDIA GeForce RTX 5070 Laptop GPU | 2D58 |
| NVIDIA GeForce RTX 5060 Laptop GPU | 2D59 | | NVIDIA GeForce RTX 5060 Laptop GPU | 2D59 |
| NVIDIA GeForce RTX 5050 | 2D83 |
| NVIDIA GeForce RTX 5050 Laptop GPU | 2D98 |
| NVIDIA RTX PRO 1000 Blackwell Generation Laptop GPU | 2DB8 | | NVIDIA RTX PRO 1000 Blackwell Generation Laptop GPU | 2DB8 |
| NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU | 2DB9 | | NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU | 2DB9 |
| NVIDIA GeForce RTX 5050 Laptop GPU | 2DD8 |
| NVIDIA GeForce RTX 5070 | 2F04 | | NVIDIA GeForce RTX 5070 | 2F04 |
| NVIDIA GeForce RTX 5070 Ti Laptop GPU | 2F18 | | NVIDIA GeForce RTX 5070 Ti Laptop GPU | 2F18 |
| NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU | 2F38 | | NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU | 2F38 |

View File

@@ -79,7 +79,7 @@ ccflags-y += -I$(src)/common/inc
ccflags-y += -I$(src) ccflags-y += -I$(src)
ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
ccflags-y += -D__KERNEL__ -DMODULE -DNVRM ccflags-y += -D__KERNEL__ -DMODULE -DNVRM
ccflags-y += -DNV_VERSION_STRING=\"575.64\" ccflags-y += -DNV_VERSION_STRING=\"575.64.03\"
ifneq ($(SYSSRCHOST1X),) ifneq ($(SYSSRCHOST1X),)
ccflags-y += -I$(SYSSRCHOST1X) ccflags-y += -I$(SYSSRCHOST1X)

View File

@@ -4006,33 +4006,6 @@ compile_test() {
fi fi
;; ;;
dma_buf_has_dynamic_attachment)
#
# Determine if the function dma_buf_attachment_is_dynamic()
# is present.
#
# Added by commit: 15fd552d186c
# ("dma-buf: change DMA-buf locking convention v3") in v5.5 (2018-07-03)
#
echo "$CONFTEST_PREAMBLE
#include <linux/dma-buf.h>
bool conftest_dma_buf_attachment_is_dynamic(void) {
return dma_buf_attachment_is_dynamic(NULL);
}" > conftest$$.c
$CC $CFLAGS -c conftest$$.c > /dev/null 2>&1
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
echo "#define NV_DMA_BUF_HAS_DYNAMIC_ATTACHMENT" | append_conftest "functions"
rm -f conftest$$.o
return
else
echo "#undef NV_DMA_BUF_HAS_DYNAMIC_ATTACHMENT" | append_conftest "functions"
return
fi
;;
dma_buf_attachment_has_peer2peer) dma_buf_attachment_has_peer2peer)
# #
# Determine if peer2peer is present in struct dma_buf_attachment. # Determine if peer2peer is present in struct dma_buf_attachment.

View File

@@ -308,12 +308,13 @@ void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr,
NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu) NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu)
{ {
#if NV_IS_EXPORT_SYMBOL_GPL_iommu_dev_enable_feature
int ret; int ret;
ret = iommu_dev_enable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA); ret = iommu_dev_enable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA);
if (ret) if (ret)
return errno_to_nv_status(ret); return errno_to_nv_status(ret);
#endif
if (UVM_ATS_SMMU_WAR_REQUIRED()) if (UVM_ATS_SMMU_WAR_REQUIRED())
return uvm_ats_smmu_war_init(parent_gpu); return uvm_ats_smmu_war_init(parent_gpu);
else else
@@ -325,7 +326,9 @@ void uvm_ats_sva_remove_gpu(uvm_parent_gpu_t *parent_gpu)
if (UVM_ATS_SMMU_WAR_REQUIRED()) if (UVM_ATS_SMMU_WAR_REQUIRED())
uvm_ats_smmu_war_deinit(parent_gpu); uvm_ats_smmu_war_deinit(parent_gpu);
#if NV_IS_EXPORT_SYMBOL_GPL_iommu_dev_disable_feature
iommu_dev_disable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA); iommu_dev_disable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA);
#endif
} }
NV_STATUS uvm_ats_sva_bind_gpu(uvm_gpu_va_space_t *gpu_va_space) NV_STATUS uvm_ats_sva_bind_gpu(uvm_gpu_va_space_t *gpu_va_space)

View File

@@ -837,11 +837,10 @@ nv_dma_buf_map(
// PCIe mapping, importers must be able to handle peer MMIO resources // PCIe mapping, importers must be able to handle peer MMIO resources
// not backed by struct page. // not backed by struct page.
// //
#if defined(NV_DMA_BUF_HAS_DYNAMIC_ATTACHMENT) && \ #if defined(NV_DMA_BUF_ATTACHMENT_HAS_PEER2PEER)
defined(NV_DMA_BUF_ATTACHMENT_HAS_PEER2PEER)
if (((!priv->nv->coherent) || if (((!priv->nv->coherent) ||
(priv->mapping_type == NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE)) && (priv->mapping_type == NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE)) &&
dma_buf_attachment_is_dynamic(attachment) && (attachment->importer_ops != NULL) &&
!attachment->peer2peer) !attachment->peer2peer)
{ {
nv_printf(NV_DBG_ERRORS, nv_printf(NV_DBG_ERRORS,

View File

@@ -186,7 +186,6 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_ops_has_kmap
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_ops_has_kmap_atomic NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_ops_has_kmap_atomic
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_ops_has_map NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_ops_has_map
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_ops_has_map_atomic NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_ops_has_map_atomic
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_has_dynamic_attachment
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_attachment_has_peer2peer NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_attachment_has_peer2peer
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_set_mask_and_coherent NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_set_mask_and_coherent
NV_CONFTEST_FUNCTION_COMPILE_TESTS += devm_clk_bulk_get_all NV_CONFTEST_FUNCTION_COMPILE_TESTS += devm_clk_bulk_get_all
@@ -241,6 +240,8 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present___platform_driver_r
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_hrtimer_setup NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_hrtimer_setup
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_timer_delete_sync NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_timer_delete_sync
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl___vma_start_write NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl___vma_start_write
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_iommu_dev_enable_feature
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_iommu_dev_disable_feature
NV_CONFTEST_TYPE_COMPILE_TESTS += dma_ops NV_CONFTEST_TYPE_COMPILE_TESTS += dma_ops
NV_CONFTEST_TYPE_COMPILE_TESTS += swiotlb_dma_ops NV_CONFTEST_TYPE_COMPILE_TESTS += swiotlb_dma_ops

View File

@@ -327,6 +327,9 @@ namespace DisplayPort
// //
bool bForceHeadShutdownOnModeTransition; bool bForceHeadShutdownOnModeTransition;
// Set to true when we want to skip reset MST_EN before LT
bool bSkipResetMSTMBeforeLt;
bool bReportDeviceLostBeforeNew; bool bReportDeviceLostBeforeNew;
bool bDisableSSC; bool bDisableSSC;
bool bEnableFastLT; bool bEnableFastLT;

View File

@@ -173,6 +173,7 @@ namespace DisplayPort
bool bForceHeadShutdownOnModeTransition; bool bForceHeadShutdownOnModeTransition;
bool bSkipCableIdCheck; bool bSkipCableIdCheck;
bool bAllocateManualTimeslots; bool bAllocateManualTimeslots;
bool bSkipResetMSTMBeforeLt;
}_WARFlags; }_WARFlags;
_WARFlags WARFlags; _WARFlags WARFlags;

View File

@@ -2787,13 +2787,13 @@ bool ConnectorImpl::isHeadShutDownNeeded(Group * target, // Group
// In case of mode transition (DSC <-> non-DSC), if the link config is same as previous mode, we need to shut down the head // In case of mode transition (DSC <-> non-DSC), if the link config is same as previous mode, we need to shut down the head
// since VBID[6] needs to be updated accordingly // since VBID[6] needs to be updated accordingly
// //
if ((bForceHeadShutdownOnModeTransition && if ((bForceHeadShutdownOnModeTransition &&
((modesetInfo.bEnableDsc && targetImpl->lastModesetInfo.bEnableDsc) && ((modesetInfo.bEnableDsc && targetImpl->lastModesetInfo.bEnableDsc) &&
(modesetInfo.bitsPerComponent != targetImpl->lastModesetInfo.bitsPerComponent))) || (modesetInfo.bitsPerComponent != targetImpl->lastModesetInfo.bitsPerComponent))) ||
((lowestSelected.getTotalDataRate() == activeLinkConfig.getTotalDataRate()) && ((lowestSelected.getTotalDataRate() == activeLinkConfig.getTotalDataRate()) &&
(modesetInfo.bEnableDsc != targetImpl->lastModesetInfo.bEnableDsc))) (modesetInfo.bEnableDsc != targetImpl->lastModesetInfo.bEnableDsc)))
{ {
return true; return true;
} }
// For dual DP while changing link config, we need to shut // For dual DP while changing link config, we need to shut
@@ -5358,9 +5358,9 @@ bool ConnectorImpl::getValidLowestLinkConfig
{ {
// //
// If highest link rate is UHBR 128b132b and current selected config is 8b10b, // If highest link rate is UHBR 128b132b and current selected config is 8b10b,
// FEC should not be enabled if DSC is not enabled since // FEC should not be enabled if DSC is not enabled since
// 1. This function will be called only for SST and that too when preferred // 1. This function will be called only for SST and that too when preferred
// link config is not set. // link config is not set.
// 2. for SST and in 8b10b mode, FEC is enabled only when DSC is enabled // 2. for SST and in 8b10b mode, FEC is enabled only when DSC is enabled
// //
selectedConfig.enableFEC(false); selectedConfig.enableFEC(false);
@@ -5655,8 +5655,9 @@ bool ConnectorImpl::validateLinkConfiguration(const LinkConfiguration & lConfig)
bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force, bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
LinkTrainingType trainType) LinkTrainingType trainType)
{ {
LinkTrainingType preferredTrainingType = trainType; LinkTrainingType preferredTrainingType = trainType;
bool result = true; bool result = true;
NvBool bSkipSettingStreamMode = false;
// Validate link config against caps // Validate link config against caps
if (!force && !validateLinkConfiguration(lConfig)) if (!force && !validateLinkConfiguration(lConfig))
@@ -5693,10 +5694,16 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
} }
// //
// Don't set the stream if we're shutting off the link // Don't set the stream if we're:
// or forcing the config // - forcing the config
// - Skipping LT and the flag to skip stream mode setting is true
// - shutting off the link
// //
if (!force && lConfig.lanes != 0) bSkipSettingStreamMode = force ||
(bSkipLt && this->bSkipResetMSTMBeforeLt) ||
(lConfig.lanes == 0);
if (!bSkipSettingStreamMode)
{ {
if (isLinkActive()) if (isLinkActive())
{ {
@@ -7009,6 +7016,8 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
{ {
bDelayAfterD3 = true; bDelayAfterD3 = true;
} }
// Do not reset MST_EN before LT for Sony SDM27Q10S in SST mode
this->bSkipResetMSTMBeforeLt = tmpEdid.WARFlags.bSkipResetMSTMBeforeLt;
// Panels use Legacy address range for interrupt reporting // Panels use Legacy address range for interrupt reporting
if (tmpEdid.WARFlags.useLegacyAddress) if (tmpEdid.WARFlags.useLegacyAddress)
@@ -8294,6 +8303,7 @@ void ConnectorImpl::configInit()
bDP2XPreferNonDSCForLowPClk = false; bDP2XPreferNonDSCForLowPClk = false;
bDisableDscMaxBppLimit = false; bDisableDscMaxBppLimit = false;
bForceHeadShutdownOnModeTransition = false; bForceHeadShutdownOnModeTransition = false;
bSkipResetMSTMBeforeLt = false;
} }
bool ConnectorImpl::dpUpdateDscStream(Group *target, NvU32 dscBpp) bool ConnectorImpl::dpUpdateDscStream(Group *target, NvU32 dscBpp)

View File

@@ -1,4 +1,4 @@
/* /*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -615,12 +615,13 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
this->WARFlags.bSkipCableIdCheck = true; this->WARFlags.bSkipCableIdCheck = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Panel does not expose cable capability. Ignoring it. Bug 4968411"); DP_PRINTF(DP_NOTICE, "DP-WAR> Panel does not expose cable capability. Ignoring it. Bug 4968411");
} }
else if(ProductID == 0x24b5 || ProductID == 0x32f2) else if(ProductID == 0x24b5 || ProductID == 0x32f2 || ProductID == 0x27BC)
{ {
// //
// Asus ROG PG248QP (0x24b5) Bug 5100062 // Asus ROG PG248QP (0x24b5) Bug 5100062
// Asus ROG PG32UCDM (0x32f2) Bug 5088957 // Asus ROG PG32UCDM (0x32f2) Bug 5088957
// // Asus ROG PG27AQN (0x27BC) Bug 5300665
this->WARFlags.bForceHeadShutdown = true; this->WARFlags.bForceHeadShutdown = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Force head shutdown."); DP_PRINTF(DP_NOTICE, "DP-WAR> Force head shutdown.");
} }
@@ -650,6 +651,14 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
DP_PRINTF(DP_NOTICE, "DP-WAR> VRT monitor does not work with GB20x when downspread is enabled. Disabling downspread."); DP_PRINTF(DP_NOTICE, "DP-WAR> VRT monitor does not work with GB20x when downspread is enabled. Disabling downspread.");
} }
break; break;
case 0xD94D: // Sony
if (ProductID == 0x07EE) // Sony SDM27Q10S
{
this->WARFlags.bSkipResetMSTMBeforeLt = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Sony SDM27Q10S needs to skip reset MST_EN before LT");
}
break;
default: default:
break; break;
} }

View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without // and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script // corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH #ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r575_00 #define NV_BUILD_BRANCH r576_76
#endif #endif
#ifndef NV_PUBLIC_BRANCH #ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r575_00 #define NV_PUBLIC_BRANCH r576_76
#endif #endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r575/r575_00-212" #define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r575/r576_76-213"
#define NV_BUILD_CHANGELIST_NUM (36105353) #define NV_BUILD_CHANGELIST_NUM (36163547)
#define NV_BUILD_TYPE "Official" #define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r575/r575_00-212" #define NV_BUILD_NAME "rel/gpu_drv/r575/r576_76-213"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36105353) #define NV_LAST_OFFICIAL_CHANGELIST_NUM (36163547)
#else /* Windows builds */ #else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r575_00-160" #define NV_BUILD_BRANCH_VERSION "r576_76-5"
#define NV_BUILD_CHANGELIST_NUM (36104828) #define NV_BUILD_CHANGELIST_NUM (36158686)
#define NV_BUILD_TYPE "Official" #define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "576.76" #define NV_BUILD_NAME "576.88"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36104828) #define NV_LAST_OFFICIAL_CHANGELIST_NUM (36158686)
#define NV_BUILD_BRANCH_BASE_VERSION R575 #define NV_BUILD_BRANCH_BASE_VERSION R575
#endif #endif
// End buildmeister python edited section // End buildmeister python edited section

View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "575.64" #define NV_VERSION_STRING "575.64.03"
#else #else

View File

@@ -306,7 +306,7 @@ struct OBJCL {
struct Object *__nvoc_pbase_Object; // obj super struct Object *__nvoc_pbase_Object; // obj super
struct OBJCL *__nvoc_pbase_OBJCL; // cl struct OBJCL *__nvoc_pbase_OBJCL; // cl
// 36 PDB properties // 37 PDB properties
NvBool PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE; NvBool PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE;
NvBool PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL; NvBool PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL;
NvBool PDB_PROP_CL_ASLM_SUPPORTS_NV_LINK_UPGRADE; NvBool PDB_PROP_CL_ASLM_SUPPORTS_NV_LINK_UPGRADE;
@@ -340,6 +340,7 @@ struct OBJCL {
NvBool PDB_PROP_CL_UNSUPPORTED_CHIPSET; NvBool PDB_PROP_CL_UNSUPPORTED_CHIPSET;
NvBool PDB_PROP_CL_IS_CHIPSET_IO_COHERENT; NvBool PDB_PROP_CL_IS_CHIPSET_IO_COHERENT;
NvBool PDB_PROP_CL_DISABLE_IOMAP_WC; NvBool PDB_PROP_CL_DISABLE_IOMAP_WC;
NvBool PDB_PROP_CL_WAR_AMD_5107271;
NvBool PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE; NvBool PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE;
NvBool PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR; NvBool PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR;
NvBool PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS; NvBool PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS;
@@ -390,6 +391,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJCL;
#endif //__nvoc_chipset_h_disabled #endif //__nvoc_chipset_h_disabled
// Property macros // Property macros
#define PDB_PROP_CL_WAR_AMD_5107271_BASE_CAST
#define PDB_PROP_CL_WAR_AMD_5107271_BASE_NAME PDB_PROP_CL_WAR_AMD_5107271
#define PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ_BASE_CAST #define PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ_BASE_CAST
#define PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ_BASE_NAME PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ #define PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ_BASE_NAME PDB_PROP_CL_PCIE_CONFIG_SKIP_MCFG_READ
#define PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE_BASE_CAST #define PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE_BASE_CAST

View File

@@ -5452,8 +5452,11 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2D39, 0x0000, 0x0000, "NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU" }, { 0x2D39, 0x0000, 0x0000, "NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU" },
{ 0x2D58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" }, { 0x2D58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" }, { 0x2D59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },
{ 0x2D83, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050" },
{ 0x2D98, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050 Laptop GPU" },
{ 0x2DB8, 0x0000, 0x0000, "NVIDIA RTX PRO 1000 Blackwell Generation Laptop GPU" }, { 0x2DB8, 0x0000, 0x0000, "NVIDIA RTX PRO 1000 Blackwell Generation Laptop GPU" },
{ 0x2DB9, 0x0000, 0x0000, "NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU" }, { 0x2DB9, 0x0000, 0x0000, "NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU" },
{ 0x2DD8, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050 Laptop GPU" },
{ 0x2F04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070" }, { 0x2F04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070" },
{ 0x2F18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" }, { 0x2F18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },
{ 0x2F38, 0x0000, 0x0000, "NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU" }, { 0x2F38, 0x0000, 0x0000, "NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU" },

View File

@@ -49,6 +49,7 @@
#include "vgpu/rpc.h" #include "vgpu/rpc.h"
#include "vgpu/vgpu_events.h" #include "vgpu/vgpu_events.h"
#include "nvdevid.h"
// //
// statics // statics
@@ -1428,15 +1429,37 @@ memmgrGetRsvdSizeForSr_GM107
MemoryManager *pMemoryManager MemoryManager *pMemoryManager
) )
{ {
//
// Temporary WAR to override WDDM S/R buffer for specific skus
// Bug 5327051
//
static const NvU16 gb20x_devid[] = { 0x2B8C };
NvU32 pciDeviceID = DRF_VAL(_PCI, _DEVID, _DEVICE, pGpu->idInfo.PCIDeviceID);
NvBool overrideFbsrRsvdBufferSize = NV_FALSE;
for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(gb20x_devid); i++)
{
if (pciDeviceID == gb20x_devid[i])
{
overrideFbsrRsvdBufferSize = NV_TRUE;
break;
}
}
if (((pMemoryManager->Ram.fbTotalMemSizeMb >> 10) >= 31) || IS_GSP_CLIENT(pGpu)) if (((pMemoryManager->Ram.fbTotalMemSizeMb >> 10) >= 31) || IS_GSP_CLIENT(pGpu))
{ {
// //
// We need to reserve more memory for S/R if // We need to reserve more memory for S/R if
// 1. FB size is > 32GB Bug Id: 2468357 // 1. FB size is >= 31GB Bug Id: 2468357
// 2. Or GSP is enabled Bug Id: 4312881 // 2. Or GSP is enabled Bug Id: 4312881
// //
return 512 * 1024 * 1024; return 512 * 1024 * 1024;
} }
else if (overrideFbsrRsvdBufferSize)
{
// Bug 5327051: WAR to override WDDM S/R buffer for specific skus
return 300 * 1024 * 1024;
}
else else
{ {
return 256 * 1024 * 1024; return 256 * 1024 * 1024;

View File

@@ -811,6 +811,7 @@ void clSyncWithGsp_IMPL(OBJCL *pCl, GspSystemInfo *pGSI)
CL_SYNC_PDB(PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE); CL_SYNC_PDB(PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE);
CL_SYNC_PDB(PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR); CL_SYNC_PDB(PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR);
CL_SYNC_PDB(PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS); CL_SYNC_PDB(PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS);
CL_SYNC_PDB(PDB_PROP_CL_WAR_AMD_5107271);
#undef CL_SYNC_PDB #undef CL_SYNC_PDB

View File

@@ -1138,6 +1138,9 @@ AMD_X370_setupFunc
) )
{ {
// WAR for bug 5107271 handling
pCl->setProperty(pCl, PDB_PROP_CL_WAR_AMD_5107271, NV_TRUE);
// Set ASPM L0S\L1 properties // Set ASPM L0S\L1 properties
_Set_ASPM_L0S_L1(pCl, NV_FALSE, NV_FALSE); _Set_ASPM_L0S_L1(pCl, NV_FALSE, NV_FALSE);

View File

@@ -1,5 +1,5 @@
NVIDIA_VERSION = 575.64 NVIDIA_VERSION = 575.64.03
NVIDIA_NVID_VERSION = 575.64 NVIDIA_NVID_VERSION = 575.64.03
NVIDIA_NVID_EXTRA = NVIDIA_NVID_EXTRA =
# This file. # This file.