525.125.06

src/nvidia/arch/nvalloc/common/inc/nvcst.h

@@ -62,7 +62,6 @@ CHIPSET_SETUP_FUNC(Intel_A2D2_setupFunc)
 CHIPSET_SETUP_FUNC(Intel_A2C9_setupFunc)
 CHIPSET_SETUP_FUNC(Intel_A301_setupFunc)
 CHIPSET_SETUP_FUNC(Intel_0685_setupFunc)
-CHIPSET_SETUP_FUNC(Intel_IceLake_setupFunc)
 CHIPSET_SETUP_FUNC(Intel_4381_setupFunc)
 CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc)
 CHIPSET_SETUP_FUNC(Intel_7A04_setupFunc)
@@ -179,13 +178,13 @@ CSINFO chipsetInfo[] =
     {PCI_VENDOR_ID_INTEL,       0xA30D, CS_INTEL_A2C9,      "IntelH370",            Intel_A2C9_setupFunc},
     {PCI_VENDOR_ID_INTEL,       0xA301, CS_INTEL_A301,      "Intel-CannonLake",     Intel_A301_setupFunc},
     {PCI_VENDOR_ID_INTEL,       0x0685, CS_INTEL_0685,      "Intel-CometLake",      Intel_0685_setupFunc},
-    {PCI_VENDOR_ID_INTEL,       0xA1CB, CS_INTEL_C620,      "Intel-IceLake",        Intel_IceLake_setupFunc},
+    {PCI_VENDOR_ID_INTEL,       0xA1CB, CS_INTEL_C620,      "Intel-IceLake",        NULL},
 	{PCI_VENDOR_ID_INTEL,       0x4381, CS_INTEL_4381,      "Intel-RocketLake",     Intel_4381_setupFunc},
     {PCI_VENDOR_ID_INTEL,       0x4385, CS_INTEL_4381,      "Intel-RocketLake",     Intel_4381_setupFunc},
     {PCI_VENDOR_ID_INTEL,       0x7A82, CS_INTEL_7A82,      "Intel-AlderLake",      Intel_7A82_setupFunc},
     {PCI_VENDOR_ID_INTEL,       0x7A84, CS_INTEL_7A82,      "Intel-AlderLake",      Intel_7A82_setupFunc},
     {PCI_VENDOR_ID_INTEL,       0x1B81, CS_INTEL_1B81,      "Intel-SapphireRapids", NULL},
-    {PCI_VENDOR_ID_INTEL,       0x18DC, CS_INTEL_18DC,      "Intel-IceLake",        Intel_IceLake_setupFunc},
+    {PCI_VENDOR_ID_INTEL,       0x18DC, CS_INTEL_18DC,      "Intel-IceLake",        NULL},
     {PCI_VENDOR_ID_INTEL,       0x7A04, CS_INTEL_7A04,      "Intel-RaptorLake",     Intel_7A04_setupFunc},
 
     {PCI_VENDOR_ID_NVIDIA,      0x0FAE, CS_NVIDIA_T210,      "T210",      Nvidia_T210_setupFunc},

src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -142,6 +142,11 @@
 #define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SHUTDN              0x00000002
 #define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_HBM_SLOWDN          0x00000003
 #define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SW_SLOWDN           0x00000004
+#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_TARGET_TLIMIT       0x00000005
+#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_HW_SLOWDN_TLIMIT    0x00000006
+#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SHUTDN_TLIMIT       0x00000007
+#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_HBM_SLOWDN_TLIMIT   0x00000008
+#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SW_SLOWDN_TLIMIT    0x00000009
 #define NV_MSGBOX_CMD_ARG1_GET_MISC_ECC_ENABLED_STATE           0x00000000
 #define NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_RESET_REQUIRED          0x00000001
 #define NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_FLAGS_PAGE_0            0x00000000
@@ -623,7 +628,24 @@
 #define NV_MSGBOX_DATA_CAP_0_GPU_SYSCONTROL                                  18:18
 #define NV_MSGBOX_DATA_CAP_0_GPU_SYSCONTROL_NOT_AVAILABLE               0x00000000
 #define NV_MSGBOX_DATA_CAP_0_GPU_SYSCONTROL_AVAILABLE                   0x00000001
-#define NV_MSGBOX_DATA_CAP_0_THERMP_BITS                                     28:24  // Adjust when adding new bits
+#define NV_MSGBOX_DATA_CAP_0_THERMP_BITS                                     28:19  // Adjust when adding new bits
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_TLIMIT_BITS                         23:19  // Adjust when adding new bits
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_BITS                                28:24  // Adjust when adding new bits
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_TLIMIT                            19:19
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_TLIMIT_NOT_AVAILABLE         0x00000000
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_TLIMIT_AVAILABLE             0x00000001
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_TLIMIT                              20:20
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_TLIMIT_NOT_AVAILABLE           0x00000000
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_TLIMIT_AVAILABLE               0x00000001
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_TLIMIT                              21:21
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_TLIMIT_NOT_AVAILABLE           0x00000000
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_TLIMIT_AVAILABLE               0x00000001
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_TLIMIT                              22:22
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_TLIMIT_NOT_AVAILABLE           0x00000000
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_TLIMIT_AVAILABLE               0x00000001
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_TLIMIT                     23:23
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_TLIMIT_NOT_AVAILABLE  0x00000000
+#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_TLIMIT_AVAILABLE      0x00000001
 #define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC                            24:24
 #define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_NOT_AVAILABLE         0x00000000
 #define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_AVAILABLE             0x00000001
@@ -1070,16 +1092,14 @@
  * Response to
  * NV_MSGBOX_CMD_ARG1_GET_CLOCK_THROTTLE_REASON
  */
-#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON                                   31:0
-#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_NONE                        0x00000000
-#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_POWER_CAP                0x00000001
-#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_SLOWDOWN                 0x00000002
-#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SYNC_BOOST                  0x00000004
-#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN_TLIMIT  0x00000008
-#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN_TAVG    0x00000010
-#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN_TMEM    0x00000020
-#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_THERMAL_SLOWDOWN         0x00000040
-#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_POWER_BREAK_SLOWDOWN     0x00000080
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON                                  31:0
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_NONE                       0x00000000
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_POWER_CAP               0x00000001
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_SLOWDOWN                0x00000002
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_THERMAL_SLOWDOWN        0x00000004
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_POWER_BREAK_SLOWDOWN    0x00000008
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SYNC_BOOST                 0x00000010
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN        0x00000020
 
 /*
  * Number of Nvlink data outputs (dataOut, extData) for
@@ -1105,6 +1125,8 @@
 #define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_SAFE                   0x00000001
 #define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_ACTIVE                 0x00000002
 #define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_ERROR                  0x00000003
+#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_L1_LOW_POWER           0x00000004
+#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_NVLINK_DISABLED        0x00000005
 #define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_INVALID                0x000000ff
 
 /* Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_BANDWIDTH (in Mps) */

src/nvidia/arch/nvalloc/unix/include/nv-ioctl-nvlog.h

@@ -0,0 +1,43 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#if !defined(NV_IOCTL_NVLOG)
+#define NV_IOCTL_NVLOG
+
+#include <nvtypes.h>
+#include "ctrl/ctrl0000/ctrl0000nvd.h"
+
+typedef struct
+{
+    NvU32 ctrl; // in
+    NvU32 status; // out
+    union // in/out
+    {
+        NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS getNvlogInfo;
+        NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS getNvlogBufferInfo;
+        NV0000_CTRL_NVD_GET_NVLOG_PARAMS getNvlog;
+    } params;
+} NV_NVLOG_CTRL_PARAMS;
+
+#endif
+

src/nvidia/arch/nvalloc/unix/include/nv.h

@@ -495,6 +495,12 @@ struct nv_file_private_t
     nv_file_private_t *ctl_nvfp;
     void *ctl_nvfp_priv;
     NvU32 register_or_refcount;
+
+    //
+    // True if a client or an event was ever allocated on this fd.
+    // If false, RMAPI cleanup is skipped.
+    //
+    NvBool bCleanupRmapi;
 };
 
 // Forward define the gpu ops structures

src/nvidia/arch/nvalloc/unix/include/nv_escape.h

@@ -50,5 +50,6 @@
 #define NV_ESC_RM_EXPORT_OBJECT_TO_FD               0x5C
 #define NV_ESC_RM_IMPORT_OBJECT_FROM_FD             0x5D
 #define NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO        0x5E
+#define NV_ESC_RM_NVLOG_CTRL                        0x5F
 
 #endif // NV_ESCAPE_H_INCLUDED

src/nvidia/arch/nvalloc/unix/src/escape.c

@@ -46,6 +46,10 @@
 #include <class/cl003e.h> // NV01_MEMORY_SYSTEM
 #include <class/cl0071.h> // NV01_MEMORY_SYSTEM_OS_DESCRIPTOR
 
+#include "rmapi/client_resource.h"
+#include "nvlog/nvlog.h"
+#include <nv-ioctl-nvlog.h>
+
 #include <ctrl/ctrl00fd.h>
 
 #define NV_CTL_DEVICE_ONLY(nv)                 \
@@ -839,6 +843,40 @@ NV_STATUS RmIoctl(
             break;
         }
 
+        case NV_ESC_RM_NVLOG_CTRL:
+        {
+            NV_NVLOG_CTRL_PARAMS *pParams = data;
+
+            NV_CTL_DEVICE_ONLY(nv);
+
+            if (!osIsAdministrator())
+            {
+                rmStatus = NV_ERR_INSUFFICIENT_PERMISSIONS;
+                pParams->status = rmStatus;
+                goto done;
+            }
+
+            switch (pParams->ctrl)
+            {
+                // Do not use NVOC _DISPATCH here as it dereferences NULL RmClientResource*
+                case NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO:
+                    rmStatus = cliresCtrlCmdNvdGetNvlogInfo_IMPL(NULL, &pParams->params.getNvlogInfo);
+                    break;
+                case NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO:
+                    rmStatus = cliresCtrlCmdNvdGetNvlogBufferInfo_IMPL(NULL, &pParams->params.getNvlogBufferInfo);
+                    break;
+                case NV0000_CTRL_CMD_NVD_GET_NVLOG:
+                    rmStatus = cliresCtrlCmdNvdGetNvlog_IMPL(NULL, &pParams->params.getNvlog);
+                    break;
+                default:
+                    rmStatus = NV_ERR_NOT_SUPPORTED;
+                    break;
+            }
+
+            pParams->status = rmStatus;
+            goto done;
+        }
+
         case NV_ESC_REGISTER_FD:
         {
             nv_ioctl_register_fd_t *params = data;

src/nvidia/arch/nvalloc/unix/src/os.c

@@ -5247,3 +5247,11 @@ osDmabufIsSupported(void)
 {
     return os_dma_buf_enabled;
 }
+
+void osAllocatedRmClient(void *pOsInfo)
+{
+    nv_file_private_t* nvfp = (nv_file_private_t*)pOsInfo;
+
+    if (nvfp != NULL)
+        nvfp->bCleanupRmapi = NV_TRUE;
+}

src/nvidia/arch/nvalloc/unix/src/osapi.c

@@ -493,6 +493,8 @@ done:
         new_event->active   = NV_TRUE;
         new_event->refcount = 0;
 
+        nvfp->bCleanupRmapi = NV_TRUE;
+
         NV_PRINTF(LEVEL_INFO, "allocated OS event:\n");
         NV_PRINTF(LEVEL_INFO, "   hParent: 0x%x\n", hParent);
         NV_PRINTF(LEVEL_INFO, "   fd: %d\n", fd);
@@ -2457,16 +2459,29 @@ void NV_API_CALL rm_cleanup_file_private(
 {
     THREAD_STATE_NODE threadState;
     void      *fp;
-    RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL);
+    RM_API *pRmApi;
     RM_API_CONTEXT rmApiContext = {0};
     NvU32 i;
 
     NV_ENTER_RM_RUNTIME(sp,fp);
+
+    //
+    // Skip cleaning up this fd if:
+    // - no RMAPI clients and events were ever allocated on this fd
+    // - no RMAPI object handles were exported on this fd
+    // Access nvfp->handles without locking as fd cleanup is synchronised by the kernel
+    //
+    if (!nvfp->bCleanupRmapi && nvfp->handles == NULL)
+        goto done;
+
+    pRmApi = rmapiGetInterface(RMAPI_EXTERNAL);
     threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
     threadStateSetTimeoutOverride(&threadState, 10 * 1000);
 
-    if (rmapiPrologue(pRmApi, &rmApiContext) != NV_OK)
+    if (rmapiPrologue(pRmApi, &rmApiContext) != NV_OK) {
+        NV_EXIT_RM_RUNTIME(sp,fp);
         return;
+    }
 
     // LOCK: acquire API lock
     if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK)
@@ -2500,6 +2515,7 @@ void NV_API_CALL rm_cleanup_file_private(
     rmapiEpilogue(pRmApi, &rmApiContext);
     threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
 
+done:
     if (nvfp->ctl_nvfp != NULL)
     {
         nv_put_file_private(nvfp->ctl_nvfp_priv);

src/nvidia/arch/nvalloc/unix/src/osnvlink.c

@@ -95,6 +95,15 @@ static void NV_API_CALL osNvlinkFreeAltStack(nvidia_stack_t *sp)
 #endif
 }
 
+static NV_STATUS NV_API_CALL osNvlinkGetAltStack(nvidia_stack_t **sp)
+{
+    return osNvlinkAllocAltStack(sp);
+}
+static void NV_API_CALL osNvlinkPutAltStack(nvidia_stack_t *sp)
+{
+    osNvlinkFreeAltStack(sp);
+}
+
 static NvlStatus NV_API_CALL rm_nvlink_ops_add_link
 (
     struct nvlink_link *link
@@ -102,10 +111,9 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_add_link
 {
     void *fp;
     NvlStatus status;
-    KNVLINK_RM_LINK *pLink = link->link_info;
     nvidia_stack_t *sp;
 
-    if (NV_OK != osNvlinkAllocAltStack(&sp))
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
     {
         return NVL_ERR_GENERIC;
     }
@@ -116,14 +124,7 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_add_link
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
-    if (status == NVL_SUCCESS)
-    {
-        pLink->pOsInfo = sp;
-    }
-    else
-    {
-        osNvlinkFreeAltStack(sp);
-    }
+    osNvlinkPutAltStack(sp);
 
     return status;
 }
@@ -135,10 +136,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_remove_link
 {
     void *fp;
     NvlStatus status;
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
 
-    pLink->pOsInfo = NULL;
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -146,7 +149,7 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_remove_link
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
-    osNvlinkFreeAltStack(sp);
+    osNvlinkPutAltStack(sp);
 
     return status;
 }
@@ -159,8 +162,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_lock_link
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -170,6 +177,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_lock_link
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -180,8 +189,12 @@ static void NV_API_CALL rm_nvlink_ops_unlock_link
 {
     void *fp;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -190,6 +203,8 @@ static void NV_API_CALL rm_nvlink_ops_unlock_link
     threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
 
     NV_EXIT_RM_RUNTIME(sp, fp);
+
+    osNvlinkPutAltStack(sp);
 }
 
 static NvlStatus NV_API_CALL rm_nvlink_ops_queue_link_change
@@ -200,8 +215,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_queue_link_change
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link_change->master->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -211,6 +230,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_queue_link_change
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -224,8 +245,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_dl_link_mode
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -235,6 +260,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_dl_link_mode
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -247,8 +274,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_dl_link_mode
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -258,6 +289,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_dl_link_mode
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -271,8 +304,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_tl_link_mode
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -281,6 +318,7 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_tl_link_mode
     threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
 
     NV_EXIT_RM_RUNTIME(sp, fp);
+    osNvlinkPutAltStack(sp);
 
     return status;
 }
@@ -294,8 +332,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_tl_link_mode
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -305,6 +347,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_tl_link_mode
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -318,8 +362,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_tx_mode
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -329,6 +377,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_tx_mode
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -342,8 +392,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_tx_mode
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -353,6 +407,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_tx_mode
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -366,8 +422,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_rx_mode
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -377,6 +437,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_rx_mode
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -390,8 +452,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_rx_mode
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -401,6 +467,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_rx_mode
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -413,8 +481,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_rx_detect
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -424,6 +496,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_rx_detect
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -435,8 +509,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_rx_detect
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -446,6 +524,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_rx_detect
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -457,8 +537,12 @@ static void NV_API_CALL rm_nvlink_get_uphy_load
 {
     void *fp;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -467,6 +551,8 @@ static void NV_API_CALL rm_nvlink_get_uphy_load
     threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
 
     NV_EXIT_RM_RUNTIME(sp, fp);
+
+    osNvlinkPutAltStack(sp);
 }
 
 static NvlStatus NV_API_CALL rm_nvlink_ops_read_link_discovery_token
@@ -478,8 +564,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_read_link_discovery_token
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -489,6 +579,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_read_link_discovery_token
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -501,8 +593,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_write_link_discovery_token
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -512,6 +608,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_write_link_discovery_token
 
     NV_EXIT_RM_RUNTIME(sp, fp);
 
+    osNvlinkPutAltStack(sp);
+
     return status;
 }
 
@@ -522,8 +620,12 @@ static void NV_API_CALL rm_nvlink_ops_training_complete
 {
     void *fp;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK *pLink = link->link_info;
-    nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t *sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -532,6 +634,8 @@ static void NV_API_CALL rm_nvlink_ops_training_complete
     threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
 
     NV_EXIT_RM_RUNTIME(sp, fp);
+
+    osNvlinkPutAltStack(sp);
 }
 
 static NvlStatus NV_API_CALL rm_nvlink_ops_ali_training
@@ -542,8 +646,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_ali_training
     void *fp;
     NvlStatus status;
     THREAD_STATE_NODE threadState = {0};
-    KNVLINK_RM_LINK * pLink = link->link_info;
-    nvidia_stack_t * sp = (nvidia_stack_t *)pLink->pOsInfo;
+    nvidia_stack_t * sp;
+
+    if (osNvlinkGetAltStack(&sp) != NV_OK)
+    {
+        return NVL_ERR_GENERIC;
+    }
 
     NV_ENTER_RM_RUNTIME(sp, fp);
 
@@ -552,6 +660,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_ali_training
     threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
 
     NV_EXIT_RM_RUNTIME(sp, fp);
+
+    osNvlinkPutAltStack(sp);
     return status;
 }
 

src/nvidia/arch/nvalloc/unix/src/unix_intr.c

@@ -643,6 +643,7 @@ NV_STATUS rm_gpu_handle_mmu_faults(
     
     if (pGpu == NULL)
     {
+        NV_EXIT_RM_RUNTIME(sp,fp);
         return NV_ERR_OBJECT_NOT_FOUND;
     }