From 23e9e7621487fe632040a370249f690a456967dd Mon Sep 17 00:00:00 2001 From: Bernhard Stoeckner Date: Thu, 17 Apr 2025 17:48:53 +0200 Subject: [PATCH] 550.163.01 --- README.md | 7 +- kernel-open/Kbuild | 3 +- kernel-open/common/inc/nvmisc.h | 36 +++++ kernel-open/conftest.sh | 126 +++++++++++++++++- kernel-open/nvidia-drm/nvidia-drm-conftest.h | 4 + kernel-open/nvidia-drm/nvidia-drm-connector.c | 4 + kernel-open/nvidia-drm/nvidia-drm-drv.c | 6 +- kernel-open/nvidia-drm/nvidia-drm-sources.mk | 2 + .../nvidia-modeset/nvidia-modeset-linux.c | 5 + .../nvidia-modeset/nvidia-modeset.Kbuild | 1 + kernel-open/nvidia-uvm/uvm_conf_computing.c | 7 +- kernel-open/nvidia-uvm/uvm_linux.h | 2 +- kernel-open/nvidia-uvm/uvm_migrate.c | 44 +++--- kernel-open/nvidia-uvm/uvm_va_block.c | 2 +- kernel-open/nvidia/nv-mmap.c | 5 + kernel-open/nvidia/nv.c | 36 ++--- kernel-open/nvidia/nvidia.Kbuild | 3 + kernel-open/nvidia/os-mlock.c | 56 ++++++-- src/common/inc/nvBldVer.h | 20 +-- src/common/inc/nvUnixVersion.h | 2 +- src/common/inc/nvVer.h | 2 +- .../ada/ad102/dev_nv_pcfg_xve_regmap.h | 71 ++++++++++ .../nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h | 43 ++---- .../nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h | 25 ++++ .../sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h | 26 ++++ src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h | 2 +- src/common/sdk/nvidia/inc/nverror.h | 4 +- src/common/sdk/nvidia/inc/nvmisc.h | 36 +++++ .../nvalloc/common/inc/inforom/ifrstruct.h | 2 +- src/nvidia/arch/nvalloc/common/inc/nvpcie.h | 27 ++-- src/nvidia/generated/g_crashcat_report_nvoc.h | 14 +- src/nvidia/generated/g_gpu_nvoc.c | 13 +- src/nvidia/generated/g_gpu_nvoc.h | 4 + src/nvidia/generated/g_hal_stubs.h | 3 +- src/nvidia/generated/g_kern_bus_nvoc.h | 4 +- src/nvidia/generated/g_kernel_bif_nvoc.c | 4 + src/nvidia/generated/g_kernel_bif_nvoc.h | 2 + src/nvidia/generated/g_nv_name_released.h | 1 + src/nvidia/generated/g_rpc-message-header.h | 2 +- src/nvidia/generated/g_rpc-structures.h | 2 +- src/nvidia/generated/g_rpc_hal.h | 6 +- src/nvidia/generated/g_sdk-structures.h | 2 +- src/nvidia/generated/g_subdevice_nvoc.c | 87 +++++------- src/nvidia/generated/g_subdevice_nvoc.h | 8 -- src/nvidia/generated/rmconfig.h | 1 + src/nvidia/kernel/inc/vgpu/rpc_vgpu.h | 4 +- src/nvidia/kernel/vgpu/nv/rpc.c | 11 +- src/nvidia/kernel/vgpu/nv/vgpuctrl.c | 2 +- .../gpu/bif/arch/ada/kernel_bif_ad102.c | 61 ++++++++- src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c | 8 ++ src/nvidia/src/kernel/gpu/rc/kernel_rc.c | 22 ++- .../gpu/subdevice/subdevice_ctrl_gpu_kernel.c | 41 ++++++ .../gpu/subdevice/subdevice_ctrl_vgpu.c | 11 +- src/nvidia/src/kernel/mem_mgr/mem.c | 2 +- .../kernel/platform/chipset/chipset_pcie.c | 22 +-- .../virtualization/kernel_hostvgpudeviceapi.c | 8 +- .../src/libraries/crashcat/crashcat_report.c | 3 +- .../crashcat/v1/crashcat_report_v1.c | 103 +++++++------- .../v1/impl/crashcat_report_v1_generic.c | 2 +- .../v1/impl/crashcat_report_v1_libos2.c | 4 +- .../v1/impl/crashcat_report_v1_libos3.c | 4 +- version.mk | 2 +- 62 files changed, 780 insertions(+), 292 deletions(-) create mode 100644 src/common/inc/swref/published/ada/ad102/dev_nv_pcfg_xve_regmap.h diff --git a/README.md b/README.md index 07518d24f..28bdf1c45 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 550.144.03. +version 550.163.01. ## How to Build @@ -17,7 +17,7 @@ as root: Note that the kernel modules built here must be used with GSP firmware and user-space NVIDIA GPU driver components from a corresponding -550.144.03 driver release. This can be achieved by installing +550.163.01 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -188,7 +188,7 @@ encountered specific to them. For details on feature support and limitations, see the NVIDIA GPU driver end user README here: -https://us.download.nvidia.com/XFree86/Linux-x86_64/550.144.03/README/kernel_open.html +https://us.download.nvidia.com/XFree86/Linux-x86_64/550.163.01/README/kernel_open.html For vGPU support, please refer to the README.vgpu packaged in the vGPU Host Package for more details. @@ -933,4 +933,5 @@ Subsystem Device ID. | NVIDIA RTX 500 Ada Generation Laptop GPU | 28BB | | NVIDIA GeForce RTX 4060 Laptop GPU | 28E0 | | NVIDIA GeForce RTX 4050 Laptop GPU | 28E1 | +| NVIDIA GeForce RTX 3050 A Laptop GPU | 28E3 | | NVIDIA RTX 2000 Ada Generation Embedded GPU | 28F8 | diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index 71bb411b6..3a7c584bf 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -86,7 +86,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc EXTRA_CFLAGS += -I$(src) EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"550.144.03\" +EXTRA_CFLAGS += -DNV_VERSION_STRING=\"550.163.01\" ifneq ($(SYSSRCHOST1X),) EXTRA_CFLAGS += -I$(SYSSRCHOST1X) @@ -186,6 +186,7 @@ NV_CFLAGS_FROM_CONFTEST := $(shell $(NV_CONFTEST_CMD) build_cflags) NV_CONFTEST_CFLAGS = $(NV_CFLAGS_FROM_CONFTEST) $(EXTRA_CFLAGS) -fno-pie NV_CONFTEST_CFLAGS += $(call cc-disable-warning,pointer-sign) NV_CONFTEST_CFLAGS += $(call cc-option,-fshort-wchar,) +NV_CONFTEST_CFLAGS += $(call cc-option,-Werror=incompatible-pointer-types,) NV_CONFTEST_CFLAGS += -Wno-error NV_CONFTEST_COMPILE_TEST_HEADERS := $(obj)/conftest/macros.h diff --git a/kernel-open/common/inc/nvmisc.h b/kernel-open/common/inc/nvmisc.h index 6c47b6d3e..c8d5efe0a 100644 --- a/kernel-open/common/inc/nvmisc.h +++ b/kernel-open/common/inc/nvmisc.h @@ -694,6 +694,42 @@ nvPrevPow2_U64(const NvU64 x ) } \ } +// +// Bug 4851259: Newly added functions must be hidden from certain HS-signed +// ucode compilers to avoid signature mismatch. +// +#ifndef NVDEC_1_0 +/*! + * Returns the position of nth set bit in the given mask. + * + * Returns -1 if mask has fewer than n bits set. + * + * n is 0 indexed and has valid values 0..31 inclusive, so "zeroth" set bit is + * the first set LSB. + * + * Example, if mask = 0x000000F0u and n = 1, the return value will be 5. + * Example, if mask = 0x000000F0u and n = 4, the return value will be -1. + */ +static NV_FORCEINLINE NvS32 +nvGetNthSetBitIndex32(NvU32 mask, NvU32 n) +{ + NvU32 seenSetBitsCount = 0; + NvS32 index; + FOR_EACH_INDEX_IN_MASK(32, index, mask) + { + if (seenSetBitsCount == n) + { + return index; + } + ++seenSetBitsCount; + } + FOR_EACH_INDEX_IN_MASK_END; + + return -1; +} + +#endif // NVDEC_1_0 + // // Size to use when declaring variable-sized arrays // diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index d33e16d87..889cf6544 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -5321,6 +5321,45 @@ compile_test() { compile_check_conftest "$CODE" "NV_FOLLOW_PFN_PRESENT" "" "functions" ;; + + follow_pte_arg_vma) + # + # Determine if the first argument of follow_pte is + # mm_struct or vm_area_struct. + # + # The first argument was changed from mm_struct to vm_area_struct by + # commit 29ae7d96d166 ("mm: pass VMA instead of MM to follow_pte()") + # + CODE=" + #include + + typeof(follow_pte) conftest_follow_pte_has_vma_arg; + int conftest_follow_pte_has_vma_arg(struct vm_area_struct *vma, + unsigned long address, + pte_t **ptep, + spinlock_t **ptl) { + return 0; + }" + + compile_check_conftest "$CODE" "NV_FOLLOW_PTE_ARG1_VMA" "" "types" + ;; + + ptep_get) + # + # Determine if ptep_get() is present. + # + # ptep_get() was added by commit 481e980a7c19 + # ("mm: Allow arches to provide ptep_get()") + # + CODE=" + #include + void conftest_ptep_get(void) { + ptep_get(); + }" + + compile_check_conftest "$CODE" "NV_PTEP_GET_PRESENT" "" "functions" + ;; + drm_plane_atomic_check_has_atomic_state_arg) # # Determine if drm_plane_helper_funcs::atomic_check takes 'state' @@ -6269,6 +6308,32 @@ compile_test() { compile_check_conftest "$CODE" "NV_NUM_REGISTERED_FB_PRESENT" "" "types" ;; + acpi_video_register_backlight) + # + # Determine if acpi_video_register_backlight() function is present + # + # acpi_video_register_backlight was added by commit 3dbc80a3e4c55c + # (ACPI: video: Make backlight class device registration a separate + # step (v2)) for v6.0 (2022-09-02). + # Note: the include directive for in this conftest is + # necessary in order to support kernels between commit 0b9f7d93ca61 + # ("ACPI / i915: ignore firmware requests backlight change") for + # v3.16 (2014-07-07) and commit 3bd6bce369f5 ("ACPI / video: Port + # to new backlight interface selection API") for v4.2 (2015-07-16). + # Kernels within this range use the 'bool' type and the related + # 'false' value in without first including the + # definitions of that type and value. + # + CODE=" + #include + #include + void conftest_acpi_video_register_backlight(void) { + acpi_video_register_backlight(0); + }" + + compile_check_conftest "$CODE" "NV_ACPI_VIDEO_REGISTER_BACKLIGHT" "" "functions" + ;; + acpi_video_backlight_use_native) # # Determine if acpi_video_backlight_use_native() function is present @@ -6652,13 +6717,18 @@ compile_test() { # # Determine whether drm_client_setup is present. # - # Added by commit d07fdf922592 ("drm/fbdev-ttm: - # Convert to client-setup") in v6.13. + # Added by commit d07fdf922592 ("drm/fbdev-ttm: Convert to + # client-setup") in v6.13 in drm/drm_client_setup.h, but then moved + # to drm/clients/drm_client_setup.h by commit b86711c6d6e2 + # ("drm/client: Move public client header to clients/ subdirectory") + # in linux-next b86711c6d6e2. # CODE=" #include #if defined(NV_DRM_DRM_CLIENT_SETUP_H_PRESENT) #include + #elif defined(NV_DRM_CLIENTS_DRM_CLIENT_SETUP_H_PRESENT) + #include #endif void conftest_drm_client_setup(void) { drm_client_setup(); @@ -7038,6 +7108,58 @@ compile_test() { compile_check_conftest "$CODE" "NV_FOLIO_TEST_SWAPCACHE_PRESENT" "" "functions" ;; + + drm_driver_has_date) + # + # Determine if the 'drm_driver' structure has a 'date' field. + # + # Removed by commit cb2e1c2136f7 ("drm: remove driver date from + # struct drm_driver and all drivers") in linux-next, expected in + # v6.14. + # + CODE=" + #if defined(NV_DRM_DRMP_H_PRESENT) + #include + #endif + + #if defined(NV_DRM_DRM_DRV_H_PRESENT) + #include + #endif + + int conftest_drm_driver_has_date(void) { + return offsetof(struct drm_driver, date); + }" + + compile_check_conftest "$CODE" "NV_DRM_DRIVER_HAS_DATE" "" "types" + ;; + + drm_connector_helper_funcs_mode_valid_has_const_mode_arg) + # + # Determine if the 'mode' pointer argument is const in + # drm_connector_helper_funcs::mode_valid. + # + # The 'mode' pointer argument in + # drm_connector_helper_funcs::mode_valid was made const by commit + # 26d6fd81916e ("drm/connector: make mode_valid take a const struct + # drm_display_mode") in linux-next, expected in v6.15. + # + CODE=" + #if defined(NV_DRM_DRM_ATOMIC_HELPER_H_PRESENT) + #include + #endif + + static int conftest_drm_connector_mode_valid(struct drm_connector *connector, + const struct drm_display_mode *mode) { + return 0; + } + + const struct drm_connector_helper_funcs conftest_drm_connector_helper_funcs = { + .mode_valid = conftest_drm_connector_mode_valid, + };" + + compile_check_conftest "$CODE" "NV_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_HAS_CONST_MODE_ARG" "" "types" + ;; + # When adding a new conftest entry, please use the correct format for # specifying the relevant upstream Linux kernel commit. Please # avoid specifying -rc kernels, and only use SHAs that actually exist diff --git a/kernel-open/nvidia-drm/nvidia-drm-conftest.h b/kernel-open/nvidia-drm/nvidia-drm-conftest.h index 561e39cc5..54b2a99fe 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-conftest.h +++ b/kernel-open/nvidia-drm/nvidia-drm-conftest.h @@ -65,9 +65,13 @@ #if defined(NV_DRM_CLIENT_SETUP_PRESENT) && \ (defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PRESENT) || \ defined(NV_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES_PRESENT)) +// XXX remove dependency on DRM_TTM_HELPER by implementing nvidia-drm's own +// .fbdev_probe callback that uses NVKMS kapi +#if IS_ENABLED(CONFIG_DRM_TTM_HELPER) #define NV_DRM_FBDEV_AVAILABLE #define NV_DRM_CLIENT_AVAILABLE #endif +#endif /* * We can support color management if either drm_helper_crtc_enable_color_mgmt() diff --git a/kernel-open/nvidia-drm/nvidia-drm-connector.c b/kernel-open/nvidia-drm/nvidia-drm-connector.c index 4d2e11262..2fd4d96c3 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-connector.c +++ b/kernel-open/nvidia-drm/nvidia-drm-connector.c @@ -314,7 +314,11 @@ static int nv_drm_connector_get_modes(struct drm_connector *connector) } static int nv_drm_connector_mode_valid(struct drm_connector *connector, +#if defined(NV_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_HAS_CONST_MODE_ARG) + const struct drm_display_mode *mode) +#else struct drm_display_mode *mode) +#endif { struct drm_device *dev = connector->dev; struct nv_drm_device *nv_dev = to_nv_device(dev); diff --git a/kernel-open/nvidia-drm/nvidia-drm-drv.c b/kernel-open/nvidia-drm/nvidia-drm-drv.c index fdc9331fd..da2b70105 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-drv.c +++ b/kernel-open/nvidia-drm/nvidia-drm-drv.c @@ -1730,14 +1730,18 @@ static struct drm_driver nv_drm_driver = { .name = "nvidia-drm", .desc = "NVIDIA DRM driver", + +#if defined(NV_DRM_DRIVER_HAS_DATE) .date = "20160202", +#endif #if defined(NV_DRM_DRIVER_HAS_DEVICE_LIST) .device_list = LIST_HEAD_INIT(nv_drm_driver.device_list), #elif defined(NV_DRM_DRIVER_HAS_LEGACY_DEV_LIST) .legacy_dev_list = LIST_HEAD_INIT(nv_drm_driver.legacy_dev_list), #endif -#if defined(DRM_FBDEV_TTM_DRIVER_OPS) +// XXX implement nvidia-drm's own .fbdev_probe callback that uses NVKMS kapi directly +#if defined(NV_DRM_FBDEV_AVAILABLE) && defined(DRM_FBDEV_TTM_DRIVER_OPS) DRM_FBDEV_TTM_DRIVER_OPS, #endif }; diff --git a/kernel-open/nvidia-drm/nvidia-drm-sources.mk b/kernel-open/nvidia-drm/nvidia-drm-sources.mk index 8ab697345..1328ffd86 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-sources.mk +++ b/kernel-open/nvidia-drm/nvidia-drm-sources.mk @@ -134,4 +134,6 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffe NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_create_dp_colorspace_property_has_supported_colorspaces_arg NV_CONFTEST_TYPE_COMPILE_TESTS += drm_unlocked_ioctl_flag_present NV_CONFTEST_TYPE_COMPILE_TESTS += drm_output_poll_changed +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_date NV_CONFTEST_TYPE_COMPILE_TESTS += file_operations_fop_unsigned_offset_present +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_helper_funcs_mode_valid_has_const_mode_arg diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c index 39532ac42..4a2361aba 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c +++ b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c @@ -996,6 +996,11 @@ nvkms_register_backlight(NvU32 gpu_id, NvU32 display_id, void *drv_priv, #if defined(NV_ACPI_VIDEO_BACKLIGHT_USE_NATIVE) if (!acpi_video_backlight_use_native()) { +#if defined(NV_ACPI_VIDEO_REGISTER_BACKLIGHT) + nvkms_log(NVKMS_LOG_LEVEL_INFO, NVKMS_LOG_PREFIX, + "ACPI reported no NVIDIA native backlight available; attempting to use ACPI backlight."); + acpi_video_register_backlight(); +#endif return NULL; } #endif diff --git a/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild b/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild index 42cc187d1..63291c966 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild +++ b/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild @@ -102,3 +102,4 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += list_is_first NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_real_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += acpi_video_backlight_use_native +NV_CONFTEST_FUNCTION_COMPILE_TESTS += acpi_video_register_backlight diff --git a/kernel-open/nvidia-uvm/uvm_conf_computing.c b/kernel-open/nvidia-uvm/uvm_conf_computing.c index b2d165249..ba11e7b34 100644 --- a/kernel-open/nvidia-uvm/uvm_conf_computing.c +++ b/kernel-open/nvidia-uvm/uvm_conf_computing.c @@ -730,7 +730,12 @@ void uvm_conf_computing_disable_key_rotation(uvm_gpu_t *gpu) bool uvm_conf_computing_is_key_rotation_enabled(uvm_gpu_t *gpu) { - return gpu->channel_manager->conf_computing.key_rotation_enabled; + UVM_ASSERT(gpu); + + // If the channel_manager is not set, we're in channel manager destroy + // path after the pointer was NULL-ed. Chances are that other key rotation + // infrastructure is not available either. Disallow the key rotation. + return gpu->channel_manager && gpu->channel_manager->conf_computing.key_rotation_enabled; } bool uvm_conf_computing_is_key_rotation_enabled_in_pool(uvm_channel_pool_t *pool) diff --git a/kernel-open/nvidia-uvm/uvm_linux.h b/kernel-open/nvidia-uvm/uvm_linux.h index eaac371e9..4b28b5e60 100644 --- a/kernel-open/nvidia-uvm/uvm_linux.h +++ b/kernel-open/nvidia-uvm/uvm_linux.h @@ -226,7 +226,7 @@ static inline const struct cpumask *uvm_cpumask_of_node(int node) #define __GFP_NORETRY 0 #endif -#define NV_UVM_GFP_FLAGS (GFP_KERNEL) +#define NV_UVM_GFP_FLAGS (GFP_KERNEL | __GFP_NOMEMALLOC) #ifndef NV_ALIGN_DOWN #define NV_ALIGN_DOWN(v,g) ((v) & ~((g) - 1)) diff --git a/kernel-open/nvidia-uvm/uvm_migrate.c b/kernel-open/nvidia-uvm/uvm_migrate.c index 659523efd..dea41a684 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate.c +++ b/kernel-open/nvidia-uvm/uvm_migrate.c @@ -130,27 +130,12 @@ static NV_STATUS block_migrate_map_unmapped_pages(uvm_va_block_t *va_block, uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); NV_STATUS status = NV_OK; NV_STATUS tracker_status; + uvm_prot_t prot = UVM_PROT_READ_WRITE_ATOMIC; // Get the mask of unmapped pages because it will change after the // first map operation uvm_va_block_unmapped_pages_get(va_block, region, &va_block_context->caller_page_mask); - if (uvm_va_block_is_hmm(va_block) && !UVM_ID_IS_CPU(dest_id)) { - // Do not map pages that are already resident on the CPU. This is in - // order to avoid breaking system-wide atomic operations on HMM. HMM's - // implementation of system-side atomic operations involves restricting - // mappings to one processor (CPU or a GPU) at a time. If we were to - // grant a GPU a mapping to system memory, this gets into trouble - // because, on the CPU side, Linux can silently upgrade PTE permissions - // (move from read-only, to read-write, without any MMU notifiers - // firing), thus breaking the model by allowing simultaneous read-write - // access from two separate processors. To avoid that, just don't map - // such pages at all, when migrating. - uvm_page_mask_andnot(&va_block_context->caller_page_mask, - &va_block_context->caller_page_mask, - uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU, NUMA_NO_NODE)); - } - // Only map those pages that are not mapped anywhere else (likely due // to a first touch or a migration). We pass // UvmEventMapRemoteCauseInvalid since the destination processor of a @@ -166,6 +151,31 @@ static NV_STATUS block_migrate_map_unmapped_pages(uvm_va_block_t *va_block, if (status != NV_OK) goto out; + if (uvm_va_block_is_hmm(va_block) && UVM_ID_IS_CPU(dest_id)) { + uvm_processor_id_t id; + + // Do not atomically map pages that are resident on the CPU. This is in + // order to avoid breaking system-wide atomic operations on HMM. HMM's + // implementation of system-side atomic operations involves restricting + // mappings to one processor (CPU or a GPU) at a time. If we were to + // grant a GPU a mapping to system memory, this gets into trouble + // because, on the CPU side, Linux can silently upgrade PTE permissions + // (move from read-only, to read-write, without any MMU notifiers + // firing), thus breaking the model by allowing simultaneous read-write + // access from two separate processors. To avoid that, don't remote map + // such pages atomically, after migrating. + // Also note that HMM sets CPU mapping for resident pages so the mask + // of pages to be mapped needs to be recomputed without including the + // CPU mapping. + prot = UVM_PROT_READ_WRITE; + uvm_page_mask_region_fill(&va_block_context->caller_page_mask, region); + for_each_gpu_id_in_mask(id, &va_block->mapped) { + uvm_page_mask_andnot(&va_block_context->caller_page_mask, + &va_block_context->caller_page_mask, + uvm_va_block_map_mask_get(va_block, id)); + } + } + // Add mappings for AccessedBy processors // // No mappings within this call will operate on dest_id, so we don't @@ -176,7 +186,7 @@ static NV_STATUS block_migrate_map_unmapped_pages(uvm_va_block_t *va_block, dest_id, region, &va_block_context->caller_page_mask, - UVM_PROT_READ_WRITE_ATOMIC, + prot, NULL); out: diff --git a/kernel-open/nvidia-uvm/uvm_va_block.c b/kernel-open/nvidia-uvm/uvm_va_block.c index c4ed9dd8e..6b31a8aa3 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.c +++ b/kernel-open/nvidia-uvm/uvm_va_block.c @@ -1768,7 +1768,7 @@ static NV_STATUS block_alloc_cpu_chunk(uvm_va_block_t *block, if (status == NV_OK) break; - if (flags & UVM_CPU_CHUNK_ALLOC_FLAGS_STRICT) { + if ((flags & UVM_CPU_CHUNK_ALLOC_FLAGS_STRICT) && (num_possible_nodes() > 1)) { flags &= ~UVM_CPU_CHUNK_ALLOC_FLAGS_STRICT; numa_fallback = true; status = block_alloc_cpu_chunk_inject_error(block, alloc_size, flags, NUMA_NO_NODE, chunk); diff --git a/kernel-open/nvidia/nv-mmap.c b/kernel-open/nvidia/nv-mmap.c index 8fd449604..8e98c8175 100644 --- a/kernel-open/nvidia/nv-mmap.c +++ b/kernel-open/nvidia/nv-mmap.c @@ -143,6 +143,11 @@ nvidia_vma_access( return -EINVAL; } + if (write && !(mmap_context->prot & NV_PROTECT_WRITEABLE)) + { + return -EACCES; + } + offset = mmap_context->mmap_start; if (nv->flags & NV_FLAG_CONTROL) diff --git a/kernel-open/nvidia/nv.c b/kernel-open/nvidia/nv.c index 626f9cc46..e7ceaaf25 100644 --- a/kernel-open/nvidia/nv.c +++ b/kernel-open/nvidia/nv.c @@ -1628,8 +1628,6 @@ static void nv_init_mapping_revocation(nv_linux_state_t *nvl, nv_linux_file_private_t *nvlfp, struct inode *inode) { - down(&nvl->mmap_lock); - /* Set up struct address_space for use with unmap_mapping_range() */ address_space_init_once(&nvlfp->mapping); nvlfp->mapping.host = inode; @@ -1638,10 +1636,20 @@ static void nv_init_mapping_revocation(nv_linux_state_t *nvl, nvlfp->mapping.backing_dev_info = inode->i_mapping->backing_dev_info; #endif file->f_mapping = &nvlfp->mapping; +} - /* Add nvlfp to list of open files in nvl for mapping revocation */ +/* Adds nvlfp to list of open files for mapping revocation */ +static void nv_add_open_file(nv_linux_state_t *nvl, + nv_linux_file_private_t *nvlfp) +{ + nvlfp->nvptr = nvl; + + /* + * nvl->open_files and other mapping revocation members in nv_linux_state_t + * are protected by nvl->mmap_lock instead of nvl->ldata_lock. + */ + down(&nvl->mmap_lock); list_add(&nvlfp->entry, &nvl->open_files); - up(&nvl->mmap_lock); } @@ -1691,11 +1699,12 @@ static void nvidia_open_deferred(void *nvlfp_raw) */ down(&nvl->ldata_lock); rc = nv_open_device_for_nvlfp(NV_STATE_PTR(nvl), nvlfp->sp, nvlfp); - up(&nvl->ldata_lock); - /* Set nvptr only upon success (where nvl->usage_count is incremented) */ + /* Only add open file tracking where nvl->usage_count is incremented */ if (rc == 0) - nvlfp->nvptr = nvl; + nv_add_open_file(nvl, nvlfp); + + up(&nvl->ldata_lock); complete_all(&nvlfp->open_complete); } @@ -1814,6 +1823,7 @@ nvidia_open( } nv = NV_STATE_PTR(nvl); + nv_init_mapping_revocation(nvl, file, nvlfp, inode); if (nv_try_lock_foreground_open(file, nvl) == 0) { @@ -1824,11 +1834,11 @@ nvidia_open( rc = nv_open_device_for_nvlfp(nv, nvlfp->sp, nvlfp); - up(&nvl->ldata_lock); - - /* Set nvptr only upon success (where nvl->usage_count is incremented) */ + /* Only add open file tracking where nvl->usage_count is incremented */ if (rc == 0) - nvlfp->nvptr = nvl; + nv_add_open_file(nvl, nvlfp); + + up(&nvl->ldata_lock); complete_all(&nvlfp->open_complete); } @@ -1883,10 +1893,6 @@ failed: NV_SET_FILE_PRIVATE(file, NULL); } } - else - { - nv_init_mapping_revocation(nvl, file, nvlfp, inode); - } return rc; } diff --git a/kernel-open/nvidia/nvidia.Kbuild b/kernel-open/nvidia/nvidia.Kbuild index 5266bfadd..f72c62f46 100644 --- a/kernel-open/nvidia/nvidia.Kbuild +++ b/kernel-open/nvidia/nvidia.Kbuild @@ -161,6 +161,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += cc_attr_guest_sev_snp NV_CONFTEST_FUNCTION_COMPILE_TESTS += hv_get_isolation_type NV_CONFTEST_FUNCTION_COMPILE_TESTS += seq_read_iter NV_CONFTEST_FUNCTION_COMPILE_TESTS += follow_pfn +NV_CONFTEST_FUNCTION_COMPILE_TESTS += ptep_get NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_get NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_put_unlocked NV_CONFTEST_FUNCTION_COMPILE_TESTS += add_memory_driver_managed @@ -230,6 +231,8 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_memory_block_size_b NV_CONFTEST_SYMBOL_COMPILE_TESTS += crypto NV_CONFTEST_SYMBOL_COMPILE_TESTS += crypto_akcipher_verify NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_follow_pte +NV_CONFTEST_SYMBOL_COMPILE_TESTS += follow_pte_arg_vma +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_follow_pfnmap_start NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_pci_ats_supported NV_CONFTEST_SYMBOL_COMPILE_TESTS += ecc_digits_from_bytes diff --git a/kernel-open/nvidia/os-mlock.c b/kernel-open/nvidia/os-mlock.c index b0c32c1b4..6474a02bf 100644 --- a/kernel-open/nvidia/os-mlock.c +++ b/kernel-open/nvidia/os-mlock.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,14 +32,27 @@ #define NV_NUM_PIN_PAGES_PER_ITERATION 0x80000 #endif -static inline int nv_follow_pfn(struct vm_area_struct *vma, - unsigned long address, - unsigned long *pfn) +static inline int nv_follow_flavors(struct vm_area_struct *vma, + unsigned long address, + unsigned long *pfn) { -#if defined(NV_FOLLOW_PFN_PRESENT) - return follow_pfn(vma, address, pfn); -#else -#if NV_IS_EXPORT_SYMBOL_PRESENT_follow_pte +#if NV_IS_EXPORT_SYMBOL_PRESENT_follow_pfnmap_start + struct follow_pfnmap_args args = {}; + int rc; + + args.address = address; + args.vma = vma; + + rc = follow_pfnmap_start(&args); + if (rc) + return rc; + + *pfn = args.pfn; + + follow_pfnmap_end(&args); + + return 0; +#elif NV_IS_EXPORT_SYMBOL_PRESENT_follow_pte int status = 0; spinlock_t *ptl; pte_t *ptep; @@ -47,17 +60,40 @@ static inline int nv_follow_pfn(struct vm_area_struct *vma, if (!(vma->vm_flags & (VM_IO | VM_PFNMAP))) return status; + // + // The first argument of follow_pte() was changed from + // mm_struct to vm_area_struct in kernel 6.10. + // +#if defined(NV_FOLLOW_PTE_ARG1_VMA) status = follow_pte(vma, address, &ptep, &ptl); +#else + status = follow_pte(vma->vm_mm, address, &ptep, &ptl); +#endif if (status) return status; + +#if defined(NV_PTEP_GET_PRESENT) *pfn = pte_pfn(ptep_get(ptep)); +#else + *pfn = pte_pfn(READ_ONCE(*ptep)); +#endif // The lock is acquired inside follow_pte() pte_unmap_unlock(ptep, ptl); return 0; -#else // NV_IS_EXPORT_SYMBOL_PRESENT_follow_pte +#else return -1; -#endif // NV_IS_EXPORT_SYMBOL_PRESENT_follow_pte +#endif // NV_IS_EXPORT_SYMBOL_PRESENT_follow_pfnmap_start +} + +static inline int nv_follow_pfn(struct vm_area_struct *vma, + unsigned long address, + unsigned long *pfn) +{ +#if defined(NV_FOLLOW_PFN_PRESENT) + return follow_pfn(vma, address, pfn); +#else + return nv_follow_flavors(vma, address, pfn); #endif } diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h index eca406787..ea09d9653 100644 --- a/src/common/inc/nvBldVer.h +++ b/src/common/inc/nvBldVer.h @@ -36,25 +36,25 @@ // and then checked back in. You cannot make changes to these sections without // corresponding changes to the buildmeister script #ifndef NV_BUILD_BRANCH - #define NV_BUILD_BRANCH r553_54 + #define NV_BUILD_BRANCH r553_74 #endif #ifndef NV_PUBLIC_BRANCH - #define NV_PUBLIC_BRANCH r553_54 + #define NV_PUBLIC_BRANCH r553_74 #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r553_54-516" -#define NV_BUILD_CHANGELIST_NUM (35333542) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r553_74-609" +#define NV_BUILD_CHANGELIST_NUM (35802577) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r550/r553_54-516" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35333542) +#define NV_BUILD_NAME "rel/gpu_drv/r550/r553_74-609" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35802577) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "r553_54-2" -#define NV_BUILD_CHANGELIST_NUM (35311700) +#define NV_BUILD_BRANCH_VERSION "r553_74-1" +#define NV_BUILD_CHANGELIST_NUM (35802577) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "553.56" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35311700) +#define NV_BUILD_NAME "553.75" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35802577) #define NV_BUILD_BRANCH_BASE_VERSION R550 #endif // End buildmeister python edited section diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h index 6c938344d..b9bfbec12 100644 --- a/src/common/inc/nvUnixVersion.h +++ b/src/common/inc/nvUnixVersion.h @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "550.144.03" +#define NV_VERSION_STRING "550.163.01" #else diff --git a/src/common/inc/nvVer.h b/src/common/inc/nvVer.h index c8113d618..569f51ad3 100644 --- a/src/common/inc/nvVer.h +++ b/src/common/inc/nvVer.h @@ -3,7 +3,7 @@ #define NV_COMPANY_NAME_STRING_SHORT "NVIDIA" #define NV_COMPANY_NAME_STRING_FULL "NVIDIA Corporation" #define NV_COMPANY_NAME_STRING NV_COMPANY_NAME_STRING_FULL -#define NV_COPYRIGHT_YEAR "2024" +#define NV_COPYRIGHT_YEAR "2025" #define NV_COPYRIGHT "(C) " NV_COPYRIGHT_YEAR " NVIDIA Corporation. All rights reserved." // Please do not use the non-ascii copyright symbol for (C). #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ diff --git a/src/common/inc/swref/published/ada/ad102/dev_nv_pcfg_xve_regmap.h b/src/common/inc/swref/published/ada/ad102/dev_nv_pcfg_xve_regmap.h new file mode 100644 index 000000000..ac56cbce5 --- /dev/null +++ b/src/common/inc/swref/published/ada/ad102/dev_nv_pcfg_xve_regmap.h @@ -0,0 +1,71 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __dev_nv_pcfg_xve_regmap_h__ +#define __dev_nv_pcfg_xve_regmap_h__ + +#define NV_PCFG_XVE_REGISTER_MAP_START_OFFSET 0x00088000 + +/* + * _MAP has 1 bit set for each dword register. + * _COUNT has total number of set bits in _MAP. + */ +#define NV_PCFG_XVE_REGISTER_VALID_COUNT 474 +#define NV_PCFG_XVE_REGISTER_VALID_MAP { \ + /* 0x00088000 */ 0xFFF1FFFF, 0x101FFF9F, \ + /* 0x00088100 */ 0x3FFA3C7F, 0x00000000, \ + /* 0x00088200 */ 0x03F00000, 0x00000000, \ + /* 0x00088300 */ 0x00000000, 0x00000000, \ + /* 0x00088400 */ 0x8007FFC0, 0x3F3F5807, \ + /* 0x00088500 */ 0x000000BF, 0x00000000, \ + /* 0x00088600 */ 0x0140AA1F, 0x00000000, \ + /* 0x00088700 */ 0x00013FFF, 0x00000000, \ + /* 0x00088800 */ 0xFFEFDFD7, 0x1EDAFFFF, \ + /* 0x00088900 */ 0xFFFFFFFF, 0x006FFFFF, \ + /* 0x00088A00 */ 0xFF7FFFFF, 0x0007FFFF, \ + /* 0x00088B00 */ 0x00000000, 0xFFFFF000, \ + /* 0x00088C00 */ 0x0007BFE7, 0xFFC003FC, \ + /* 0x00088D00 */ 0xFFFFFFFF, 0x7C1F3FFF, \ + /* 0x00088E00 */ 0xFFFFFFFF, 0x00FFFFFF, \ + /* 0x00088F00 */ 0x00000000, 0xFF000000 } + +#define NV_PCFG_XVE_REGISTER_WR_COUNT 352 +#define NV_PCFG_XVE_REGISTER_WR_MAP { \ + /* 0x00088000 */ 0x3EF193FA, 0x1007C505, \ + /* 0x00088100 */ 0x3FFA0828, 0x00000000, \ + /* 0x00088200 */ 0x03200000, 0x00000000, \ + /* 0x00088300 */ 0x00000000, 0x00000000, \ + /* 0x00088400 */ 0x80007EC0, 0x3F075007, \ + /* 0x00088500 */ 0x000000BF, 0x00000000, \ + /* 0x00088600 */ 0x0140AA10, 0x00000000, \ + /* 0x00088700 */ 0x00013FFF, 0x00000000, \ + /* 0x00088800 */ 0x004C5FC3, 0x1C5AFFC0, \ + /* 0x00088900 */ 0xFFFC7804, 0x006FFFFF, \ + /* 0x00088A00 */ 0xFF7FFDFD, 0x00007FFF, \ + /* 0x00088B00 */ 0x00000000, 0xF8A54000, \ + /* 0x00088C00 */ 0x00003C01, 0x3FC003FC, \ + /* 0x00088D00 */ 0xFFFFFFFC, 0x701B2C3F, \ + /* 0x00088E00 */ 0xFFFFFFF8, 0x00FFBFFF, \ + /* 0x00088F00 */ 0x00000000, 0xFF000000 } + +#endif // {__dev_nv_pcfg_xve_regmap_h__} diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h index d8905557d..8f38b227c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,36 +39,9 @@ /* * NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS * - * sramLastClearedTimestamp [out] - * dramLastClearedTimestamp [out] - * unix-epoch based timestamp. These fields indicate when the error counters - * were last cleared by the user. - * - * sramErrorCounts [out] - * dramErrorCounts [out] - * Aggregate error counts for SRAM and DRAM - */ - -#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U) - -typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS { - NvU32 sramLastClearedTimestamp; - NvU32 dramLastClearedTimestamp; - - NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotalCounts, 8); - NV_DECLARE_ALIGNED(NvU64 sramUncorrectedTotalCounts, 8); - NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotalCounts, 8); - NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotalCounts, 8); -} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS; - -#define NV2080_CTRL_CMD_ECC_GET_ECI_COUNTERS (0x20803401U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID" */ - -/* - * NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS - * * sramParityUncorrectedUnique [out] * sramSecDedUncorrectedUnique [out] - * sramCorrectedTotal [out] + * sramCorrectedUnique [out] * dramUncorrectedTotal [out] * dramCorrectedTotal [out] * Aggregate error counts for SRAM and DRAM. @@ -88,12 +61,12 @@ typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS { * Boolean flag which is set if SRAM error threshold was exceeded */ -#define NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID (0x1U) +#define NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID (0x0U) -typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS { +typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS { NV_DECLARE_ALIGNED(NvU64 sramParityUncorrectedUnique, 8); NV_DECLARE_ALIGNED(NvU64 sramSecDedUncorrectedUnique, 8); - NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotal, 8); + NV_DECLARE_ALIGNED(NvU64 sramCorrectedUnique, 8); NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotal, 8); NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotal, 8); @@ -106,7 +79,7 @@ typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS { NV_DECLARE_ALIGNED(NvU64 sramBucketOther, 8); NvBool sramErrorThresholdExceeded; -} NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS; +} NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS; /* * NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS @@ -124,9 +97,9 @@ typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS { * dramUncTot [out]: * total uncorrectable DRAM error count */ -#define NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS (0x20803402U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS (0x20803401U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID (0x2U) +#define NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID (0x1U) typedef struct NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS { NV_DECLARE_ALIGNED(NvU64 sramCorUni, 8); diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h index e85c33924..d4c58a374 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h @@ -4300,6 +4300,31 @@ typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS { #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001afU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */ +/* + * NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK + * + * This command returns the TPC reconfig mask for a specific GPC + * + * gpc[IN] + * The GPC for which the TPC reconfig mask needs to be queried. + * The GPC should be specified as a logical index. + * + * tpcReconfigMask[OUT] + * Mask of reconfigurable TPCs in the specified GPC + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK (0x208001e7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID (0xe7U) + +typedef struct NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS { + NvU32 gpc; + NvU32 tpcReconfigMask; +} NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS; + typedef struct NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO { NvU32 engDesc; NvU32 ctxAttr; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h index e789e19af..03e344e9d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h @@ -1903,4 +1903,30 @@ typedef struct NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS { NvU32 numGfxTpc; } NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS; +/* + * NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK + * + * This command returns the TPC reconfig mask for a specific GPC + * + * gpc[IN] + * The GPC for which the TPC reconfig mask needs to be queried. + * The GPC should be specified as a logical index. + * + * tpcReconfigMask[OUT] + * Mask of reconfigurable TPCs in the specified GPC + * + * grRouteInfo[IN] + * This parameter specifies the routing information used to + * disambiguate the target GR engine. + */ +#define NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK (0x2080123bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID (0x3bU) + +typedef struct NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS { + NvU32 gpc; + NvU32 tpcReconfigMask; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS; + /* _ctrl2080gr_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h index f3ea79e77..337aa402c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/nverror.h b/src/common/sdk/nvidia/inc/nverror.h index aa0231f83..2adf548f1 100644 --- a/src/common/sdk/nvidia/inc/nverror.h +++ b/src/common/sdk/nvidia/inc/nverror.h @@ -125,7 +125,9 @@ #define ROBUST_CHANNEL_FAST_PATH_ERROR (141) #define GPU_INIT_ERROR (143) #define ROBUST_CHANNEL_KEY_ROTATION_ERROR (144) -#define ROBUST_CHANNEL_LAST_ERROR (ROBUST_CHANNEL_KEY_ROTATION_ERROR) +#define RESOURCE_RETIREMENT_EVENT (156) +#define RESOURCE_RETIREMENT_FAILURE (157) +#define ROBUST_CHANNEL_LAST_ERROR (RESOURCE_RETIREMENT_FAILURE) // Indexed CE reference diff --git a/src/common/sdk/nvidia/inc/nvmisc.h b/src/common/sdk/nvidia/inc/nvmisc.h index 6c47b6d3e..c8d5efe0a 100644 --- a/src/common/sdk/nvidia/inc/nvmisc.h +++ b/src/common/sdk/nvidia/inc/nvmisc.h @@ -694,6 +694,42 @@ nvPrevPow2_U64(const NvU64 x ) } \ } +// +// Bug 4851259: Newly added functions must be hidden from certain HS-signed +// ucode compilers to avoid signature mismatch. +// +#ifndef NVDEC_1_0 +/*! + * Returns the position of nth set bit in the given mask. + * + * Returns -1 if mask has fewer than n bits set. + * + * n is 0 indexed and has valid values 0..31 inclusive, so "zeroth" set bit is + * the first set LSB. + * + * Example, if mask = 0x000000F0u and n = 1, the return value will be 5. + * Example, if mask = 0x000000F0u and n = 4, the return value will be -1. + */ +static NV_FORCEINLINE NvS32 +nvGetNthSetBitIndex32(NvU32 mask, NvU32 n) +{ + NvU32 seenSetBitsCount = 0; + NvS32 index; + FOR_EACH_INDEX_IN_MASK(32, index, mask) + { + if (seenSetBitsCount == n) + { + return index; + } + ++seenSetBitsCount; + } + FOR_EACH_INDEX_IN_MASK_END; + + return -1; +} + +#endif // NVDEC_1_0 + // // Size to use when declaring variable-sized arrays // diff --git a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h index 2079cfa2f..395d6067c 100644 --- a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h +++ b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/arch/nvalloc/common/inc/nvpcie.h b/src/nvidia/arch/nvalloc/common/inc/nvpcie.h index f76f23b1d..fb72df42b 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvpcie.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvpcie.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2000-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2000-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -211,21 +211,18 @@ // to any specific hardware. // // -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0 0x000000C8 -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_ID 7:0 -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_NEXT 15:8 -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_LENGTH 23:16 -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_SIG_LO 31:24 -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1 0x000000CC -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_SIG_HI 15:0 -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_VERSION 18:16 -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_PEER_CLIQUE_ID 22:19 -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING 23:23 -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING_DEFAULT 0x00000000 -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING_DISABLE 0x00000001 -#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RSVD 31:24 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0 0x000000C8 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_ID 7:0 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_NEXT 15:8 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_LENGTH 23:16 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_SIG_LO 31:24 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1 0x000000CC +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_SIG_HI 15:0 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_VERSION 18:16 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_PEER_CLIQUE_ID 22:19 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RSVD 31:23 -#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250 +#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250 // Chipset-specific definitions. // Intel SantaRosa definitions diff --git a/src/nvidia/generated/g_crashcat_report_nvoc.h b/src/nvidia/generated/g_crashcat_report_nvoc.h index 88bdad6ff..ca7a05c74 100644 --- a/src/nvidia/generated/g_crashcat_report_nvoc.h +++ b/src/nvidia/generated/g_crashcat_report_nvoc.h @@ -36,6 +36,8 @@ extern "C" { #include "nv-crashcat.h" #include "nvoc/object.h" +#include "utils/nvprintf.h" +#include "nvlog/nvlog_printf.h" struct CrashCatEngine; @@ -396,12 +398,14 @@ const char *crashcatReportRiscvCauseToString(NvU64 xcause); #endif #define CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, fmt, ...) \ - crashcatEnginePrintf(pReport->pEngine, NV_FALSE, \ - CRASHCAT_LOG_PREFIX CRASHCAT_LOG_INDENT fmt, ##__VA_ARGS__) + portDbgPrintf(CRASHCAT_LOG_PREFIX CRASHCAT_LOG_INDENT fmt, ##__VA_ARGS__); \ + NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, \ + CRASHCAT_LOG_PREFIX CRASHCAT_LOG_INDENT fmt, ##__VA_ARGS__) + #define CRASHCAT_REPORT_LOG_DATA(pReport, fmt, ...) \ - crashcatEnginePrintf(pReport->pEngine, NV_FALSE, \ - CRASHCAT_LOG_PREFIX CRASHCAT_LOG_INDENT CRASHCAT_LOG_INDENT fmt, \ - ##__VA_ARGS__) + portDbgPrintf(CRASHCAT_LOG_PREFIX CRASHCAT_LOG_INDENT CRASHCAT_LOG_INDENT fmt, ##__VA_ARGS__); \ + NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, \ + CRASHCAT_LOG_PREFIX CRASHCAT_LOG_INDENT CRASHCAT_LOG_INDENT fmt, ##__VA_ARGS__) #endif // CRASHCAT_REPORT_H diff --git a/src/nvidia/generated/g_gpu_nvoc.c b/src/nvidia/generated/g_gpu_nvoc.c index 30e382db5..824715286 100644 --- a/src/nvidia/generated/g_gpu_nvoc.c +++ b/src/nvidia/generated/g_gpu_nvoc.c @@ -710,13 +710,20 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { } // Hal function -- gpuHandleSanityCheckRegReadError - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GH100; + pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_b3696a; } else { - pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GM107; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GH100; + } + else + { + pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GM107; + } } // Hal function -- gpuHandleSecFault diff --git a/src/nvidia/generated/g_gpu_nvoc.h b/src/nvidia/generated/g_gpu_nvoc.h index 997e3f8c9..7e3a139b4 100644 --- a/src/nvidia/generated/g_gpu_nvoc.h +++ b/src/nvidia/generated/g_gpu_nvoc.h @@ -2808,6 +2808,10 @@ static inline NV_STATUS gpuGetRegBaseOffset_DISPATCH(struct OBJGPU *pGpu, NvU32 return pGpu->__gpuGetRegBaseOffset__(pGpu, arg0, arg1); } +static inline void gpuHandleSanityCheckRegReadError_b3696a(struct OBJGPU *pGpu, NvU32 addr, NvU32 value) { + return; +} + void gpuHandleSanityCheckRegReadError_GM107(struct OBJGPU *pGpu, NvU32 addr, NvU32 value); void gpuHandleSanityCheckRegReadError_GH100(struct OBJGPU *pGpu, NvU32 addr, NvU32 value); diff --git a/src/nvidia/generated/g_hal_stubs.h b/src/nvidia/generated/g_hal_stubs.h index f2bed2161..3d36c07ea 100644 --- a/src/nvidia/generated/g_hal_stubs.h +++ b/src/nvidia/generated/g_hal_stubs.h @@ -1214,7 +1214,8 @@ NV_STATUS rpcCtrlGetZbcClearTable_STUB( NV_STATUS rpcCleanupSurface_STUB( POBJGPU pGpu, POBJRPC pRpc, - NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pArg3 + NvHandle arg3, + NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pArg4 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; diff --git a/src/nvidia/generated/g_kern_bus_nvoc.h b/src/nvidia/generated/g_kern_bus_nvoc.h index ca73ac599..062c27e11 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.h +++ b/src/nvidia/generated/g_kern_bus_nvoc.h @@ -53,8 +53,8 @@ extern "C" { // // Virtual BAR2 mapping info is shared by tesla and fermi code // -#if defined(NV_UNIX) && (defined(NVCPU_X86_64) || defined(NVCPU_AARCH64)) -// 64-bit Unix can support many more mappings than some other operating systems: +#if ((defined(NV_UNIX) && (defined(NVCPU_X86_64) || defined(NVCPU_AARCH64))) || (defined(NVCPU_X86_64) && defined(_WIN64))) +// 64-bit Unix and 64-bit Windows can support many more mappings than some other operating systems: #define BUS_BAR2_MAX_MAPPINGS 200 #else #define BUS_BAR2_MAX_MAPPINGS 50 diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.c b/src/nvidia/generated/g_kernel_bif_nvoc.c index d5409238a..4fc8efddc 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.c +++ b/src/nvidia/generated/g_kernel_bif_nvoc.c @@ -546,6 +546,10 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * { pThis->__kbifInitXveRegMap__ = &kbifInitXveRegMap_TU102; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kbifInitXveRegMap__ = &kbifInitXveRegMap_AD102; + } else { pThis->__kbifInitXveRegMap__ = &kbifInitXveRegMap_GA102; diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.h b/src/nvidia/generated/g_kernel_bif_nvoc.h index 1d75724f3..2f673b877 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.h +++ b/src/nvidia/generated/g_kernel_bif_nvoc.h @@ -794,6 +794,8 @@ NV_STATUS kbifInitXveRegMap_GA100(struct OBJGPU *pGpu, struct KernelBif *pKernel NV_STATUS kbifInitXveRegMap_GA102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU8 arg0); +NV_STATUS kbifInitXveRegMap_AD102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU8 arg0); + static inline NV_STATUS kbifInitXveRegMap_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU8 arg0) { return pKernelBif->__kbifInitXveRegMap__(pGpu, pKernelBif, arg0); } diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h index 08209e0c5..671423027 100644 --- a/src/nvidia/generated/g_nv_name_released.h +++ b/src/nvidia/generated/g_nv_name_released.h @@ -1080,6 +1080,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x28BB, 0x0000, 0x0000, "NVIDIA RTX 500 Ada Generation Laptop GPU" }, { 0x28E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" }, { 0x28E1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" }, + { 0x28E3, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 A Laptop GPU" }, { 0x28F8, 0x0000, 0x0000, "NVIDIA RTX 2000 Ada Generation Embedded GPU" }, { 0x13BD, 0x11cc, 0x10DE, "GRID M10-0B" }, { 0x13BD, 0x11cd, 0x10DE, "GRID M10-1B" }, diff --git a/src/nvidia/generated/g_rpc-message-header.h b/src/nvidia/generated/g_rpc-message-header.h index 414622628..f4ada16e4 100644 --- a/src/nvidia/generated/g_rpc-message-header.h +++ b/src/nvidia/generated/g_rpc-message-header.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/generated/g_rpc-structures.h b/src/nvidia/generated/g_rpc-structures.h index 88ddd89d5..ecca97cc0 100644 --- a/src/nvidia/generated/g_rpc-structures.h +++ b/src/nvidia/generated/g_rpc-structures.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/generated/g_rpc_hal.h b/src/nvidia/generated/g_rpc_hal.h index e4e8b3f37..b4fca5601 100644 --- a/src/nvidia/generated/g_rpc_hal.h +++ b/src/nvidia/generated/g_rpc_hal.h @@ -117,7 +117,7 @@ typedef NV_STATUS RpcCtrlGrSetCtxswPreemptionMode(POBJGPU, POBJRPC, NvHandl typedef NV_STATUS RpcCtrlB0ccExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); typedef NV_STATUS RpcCtrlGrmgrGetGrFsInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); typedef NV_STATUS RpcCtrlGetZbcClearTable(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); -typedef NV_STATUS RpcCleanupSurface(POBJGPU, POBJRPC, +typedef NV_STATUS RpcCleanupSurface(POBJGPU, POBJRPC, NvHandle, NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS*); typedef NV_STATUS RpcCtrlSetTimeslice(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); typedef NV_STATUS RpcCtrlGpuQueryEccStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); @@ -454,8 +454,8 @@ typedef struct RPC_HAL_IFACES { (_pRpc)->_hal.rpcCtrlGrmgrGetGrFsInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2) #define rpcCtrlGetZbcClearTable_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ (_pRpc)->_hal.rpcCtrlGetZbcClearTable(_pGpu, _pRpc, _arg0, _arg1, _pArg2) -#define rpcCleanupSurface_HAL(_pGpu, _pRpc, _pArg0) \ - (_pRpc)->_hal.rpcCleanupSurface(_pGpu, _pRpc, _pArg0) +#define rpcCleanupSurface_HAL(_pGpu, _pRpc, _arg0, _pArg1) \ + (_pRpc)->_hal.rpcCleanupSurface(_pGpu, _pRpc, _arg0, _pArg1) #define rpcCtrlSetTimeslice_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ (_pRpc)->_hal.rpcCtrlSetTimeslice(_pGpu, _pRpc, _arg0, _arg1, _pArg2) #define rpcCtrlGpuQueryEccStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ diff --git a/src/nvidia/generated/g_sdk-structures.h b/src/nvidia/generated/g_sdk-structures.h index b7f9403a2..0d7baacea 100644 --- a/src/nvidia/generated/g_sdk-structures.h +++ b/src/nvidia/generated/g_sdk-structures.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/generated/g_subdevice_nvoc.c b/src/nvidia/generated/g_subdevice_nvoc.c index 797e5bfb2..f0b7b37f3 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.c +++ b/src/nvidia/generated/g_subdevice_nvoc.c @@ -7890,34 +7890,19 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic { /* [510] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdEccGetEciCounters_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20803401u, - /*paramSize=*/ sizeof(NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdEccGetEciCounters" -#endif - }, - { /* [511] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdEccGetVolatileCounts_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*flags=*/ 0x210u, /*accessRight=*/0x0u, - /*methodId=*/ 0x20803402u, + /*methodId=*/ 0x20803401u, /*paramSize=*/ sizeof(NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdEccGetVolatileCounts" #endif }, - { /* [512] */ + { /* [511] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7932,7 +7917,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaRange" #endif }, - { /* [513] */ + { /* [512] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7947,7 +7932,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock" #endif }, - { /* [514] */ + { /* [513] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7962,7 +7947,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetRange" #endif }, - { /* [515] */ + { /* [514] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7977,7 +7962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats" #endif }, - { /* [516] */ + { /* [515] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x404a11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7992,7 +7977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetFeatures" #endif }, - { /* [517] */ + { /* [516] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8007,7 +7992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetRmHeapStats" #endif }, - { /* [518] */ + { /* [517] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8022,7 +8007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo" #endif }, - { /* [519] */ + { /* [518] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8037,7 +8022,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt" #endif }, - { /* [520] */ + { /* [519] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8052,7 +8037,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff" #endif }, - { /* [521] */ + { /* [520] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8067,7 +8052,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower" #endif }, - { /* [522] */ + { /* [521] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8082,7 +8067,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus" #endif }, - { /* [523] */ + { /* [522] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8097,7 +8082,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus" #endif }, - { /* [524] */ + { /* [523] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8112,7 +8097,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask" #endif }, - { /* [525] */ + { /* [524] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8127,7 +8112,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask" #endif }, - { /* [526] */ + { /* [525] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8142,7 +8127,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType" #endif }, - { /* [527] */ + { /* [526] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8157,7 +8142,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu" #endif }, - { /* [528] */ + { /* [527] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8172,7 +8157,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo" #endif }, - { /* [529] */ + { /* [528] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8187,7 +8172,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage" #endif }, - { /* [530] */ + { /* [529] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8202,7 +8187,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity" #endif }, - { /* [531] */ + { /* [530] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8217,7 +8202,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources" #endif }, - { /* [532] */ + { /* [531] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8232,7 +8217,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding" #endif }, - { /* [533] */ + { /* [532] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8247,7 +8232,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport" #endif }, - { /* [534] */ + { /* [533] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8262,7 +8247,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig" #endif }, - { /* [535] */ + { /* [534] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8277,7 +8262,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalFreeStates" #endif }, - { /* [536] */ + { /* [535] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8292,7 +8277,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask" #endif }, - { /* [537] */ + { /* [536] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8307,7 +8292,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlSetEcThrottleMode" #endif }, - { /* [538] */ + { /* [537] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8322,7 +8307,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples" #endif }, - { /* [539] */ + { /* [538] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -8342,7 +8327,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice = { - /*numEntries=*/ 540, + /*numEntries=*/ 539, /*pExportEntries=*/ __nvoc_exported_method_def_Subdevice }; @@ -10025,10 +10010,6 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdEccGetClientExposedCounters__ = &subdeviceCtrlCmdEccGetClientExposedCounters_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdEccGetEciCounters__ = &subdeviceCtrlCmdEccGetEciCounters_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdEccGetVolatileCounts__ = &subdeviceCtrlCmdEccGetVolatileCounts_IMPL; #endif @@ -10554,6 +10535,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State_IMPL; #endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State_IMPL; +#endif } static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -10564,10 +10549,6 @@ static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner * PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit__ = &subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit_IMPL; #endif diff --git a/src/nvidia/generated/g_subdevice_nvoc.h b/src/nvidia/generated/g_subdevice_nvoc.h index 7281f6a24..b765006cc 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.h +++ b/src/nvidia/generated/g_subdevice_nvoc.h @@ -500,7 +500,6 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalFlcnSetVideoEventBufferMemory__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEccGetClientExposedCounters__)(struct Subdevice *, NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdEccGetEciCounters__)(struct Subdevice *, NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEccGetVolatileCounts__)(struct Subdevice *, NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuQueryEccConfiguration__)(struct Subdevice *, NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetEccConfiguration__)(struct Subdevice *, NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS *); @@ -1152,7 +1151,6 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags(pSubdevice, pParams) subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalFlcnSetVideoEventBufferMemory(pSubdevice, pParams) subdeviceCtrlCmdInternalFlcnSetVideoEventBufferMemory_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdEccGetClientExposedCounters(pSubdevice, pParams) subdeviceCtrlCmdEccGetClientExposedCounters_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdEccGetEciCounters(pSubdevice, pParams) subdeviceCtrlCmdEccGetEciCounters_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdEccGetVolatileCounts(pSubdevice, pParams) subdeviceCtrlCmdEccGetVolatileCounts_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuQueryEccConfiguration(pSubdevice, pConfig) subdeviceCtrlCmdGpuQueryEccConfiguration_DISPATCH(pSubdevice, pConfig) #define subdeviceCtrlCmdGpuQueryEccConfiguration_HAL(pSubdevice, pConfig) subdeviceCtrlCmdGpuQueryEccConfiguration_DISPATCH(pSubdevice, pConfig) @@ -3720,12 +3718,6 @@ static inline NV_STATUS subdeviceCtrlCmdEccGetClientExposedCounters_DISPATCH(str return pSubdevice->__subdeviceCtrlCmdEccGetClientExposedCounters__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdEccGetEciCounters_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdEccGetEciCounters_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdEccGetEciCounters__(pSubdevice, pParams); -} - NV_STATUS subdeviceCtrlCmdEccGetVolatileCounts_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdEccGetVolatileCounts_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS *pParams) { diff --git a/src/nvidia/generated/rmconfig.h b/src/nvidia/generated/rmconfig.h index 6543de04c..a0547157b 100644 --- a/src/nvidia/generated/rmconfig.h +++ b/src/nvidia/generated/rmconfig.h @@ -299,6 +299,7 @@ #define RMCFG_FEATURE_MULTICAST_FABRIC 1 // Support for MULTICAST_FABRIC #define RMCFG_FEATURE_NVLINK_ERROR_THRESHOLD 1 // Support for NVLINK_ERROR_THRESHOLD #define RMCFG_FEATURE_GSP_SEC2_ENC_CHNLMGMT_RC_WAR 1 // WAR required for RC handling. See comment #36 of bug 4406277 +#define RMCFG_FEATURE_TPC_REPAIR 1 // Support for TPC swapping in-field #define RMCFG_FEATURE_FABRIC_LINEAR_ADDRESSING 1 // Unicast fabric memory management diff --git a/src/nvidia/kernel/inc/vgpu/rpc_vgpu.h b/src/nvidia/kernel/inc/vgpu/rpc_vgpu.h index 76090de05..eb338038e 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_vgpu.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_vgpu.h @@ -88,12 +88,12 @@ static NV_INLINE void NV_RM_RPC_UPDATE_GPU_PDES(OBJGPU *pGpu, ...) { } status = rpcSetSurfaceProperties_HAL(pGpu, pRpc, hClient, pParams, bSkipCompare); \ } while (0) -#define NV_RM_RPC_CLEANUP_SURFACE(pGpu, pParams, status) \ +#define NV_RM_RPC_CLEANUP_SURFACE(pGpu, hClient, pParams, status) \ do \ { \ OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ if ((status == NV_OK) && (pRpc != NULL)) \ - status = rpcCleanupSurface_HAL(pGpu, pRpc, pParams); \ + status = rpcCleanupSurface_HAL(pGpu, pRpc, hClient, pParams); \ } while (0) #define NV_RM_RPC_SWITCH_TO_VGA(pGpu, status) \ diff --git a/src/nvidia/kernel/vgpu/nv/rpc.c b/src/nvidia/kernel/vgpu/nv/rpc.c index 158c179b4..9f59df213 100644 --- a/src/nvidia/kernel/vgpu/nv/rpc.c +++ b/src/nvidia/kernel/vgpu/nv/rpc.c @@ -2716,11 +2716,12 @@ NV_STATUS rpcLog_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, const char *logstr, NvU32 lo NV_STATUS status; NvU32 length; - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_LOG, sizeof(rpc_log_v03_00)); + length = (NvU32)portStringLength(logstr) + 1; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_LOG, sizeof(rpc_log_v03_00) + length); if (status != NV_OK) return status; - length = (NvU32)portStringLength(logstr) + 1; if (length > sizeof(rpc_log_v03_00) + pRpc->maxRpcSize) { NV_PRINTF(LEVEL_ERROR, "LOG RPC - string too long\n"); @@ -7893,7 +7894,8 @@ done: return status; } -NV_STATUS rpcCleanupSurface_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pParams) +NV_STATUS rpcCleanupSurface_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, + NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pParams) { NV_STATUS status = NV_OK; OBJVGPU *pVgpu = GPU_GET_VGPU(pGpu); @@ -7904,7 +7906,8 @@ NV_STATUS rpcCleanupSurface_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NVA080_CTRL_VGPU_ if (pVgpu && !pVgpu->bVncSupported) return status; - if (pVgpu && (pVgpu->last_surface_info.last_surface.headIndex == pParams->headIndex)) + if (pVgpu && (pVgpu->last_surface_info.last_surface.headIndex == pParams->headIndex) && + (pVgpu->last_surface_info.hClient == hClient)) { /* remove last surface information */ portMemSet((void *)&(pVgpu->last_surface_info), 0, sizeof (pVgpu->last_surface_info)); diff --git a/src/nvidia/kernel/vgpu/nv/vgpuctrl.c b/src/nvidia/kernel/vgpu/nv/vgpuctrl.c index caef4798e..ed61bc3ee 100644 --- a/src/nvidia/kernel/vgpu/nv/vgpuctrl.c +++ b/src/nvidia/kernel/vgpu/nv/vgpuctrl.c @@ -108,7 +108,7 @@ vgpuapiCtrlCmdVgpuDisplayCleanupSurface_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuApi); NV_STATUS rmStatus = NV_OK; - NV_RM_RPC_CLEANUP_SURFACE(pGpu, pParams, rmStatus); + NV_RM_RPC_CLEANUP_SURFACE(pGpu, RES_GET_CLIENT_HANDLE(pVgpuApi), pParams, rmStatus); return rmStatus; } diff --git a/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c b/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c index 6275f4f71..e98b53f67 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,9 +27,14 @@ #include "published/ada/ad102/dev_bus.h" #include "published/ada/ad102/dev_bus_addendum.h" +#include "published/ada/ad102/dev_nv_pcfg_xve_regmap.h" static NvBool _kbifPreOsCheckErotGrantAllowed_AD102(OBJGPU *pGpu, void *pVoid); +// XVE register map for PCIe config space +static const NvU32 xveRegMapValid[] = NV_PCFG_XVE_REGISTER_VALID_MAP; +static const NvU32 xveRegMapWrite[] = NV_PCFG_XVE_REGISTER_WR_MAP; + /*! * Signals preOs to have eRoT hand over control of EEPROM to RM * @@ -74,6 +79,60 @@ kbifPreOsGlobalErotGrantRequest_AD102 return status; } +/*! + * This function setups the xve register map pointers + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * @param[in] func PCIe function number + * + * @return 'NV_OK' if successful, an RM error code otherwise. + * + * Todo by rjindal: (Bug: 5020203) Create an IMPL for kbifInitXveRegMap + * and reduce the HALs for this function in a cleanup CL. + */ + +NV_STATUS +kbifInitXveRegMap_AD102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU8 func +) +{ + extern NvU32 kbifInitXveRegMap_GM107(OBJGPU *pGpu, KernelBif *pKernelBif, NvU8 func); + NV_STATUS status = NV_OK; + NvU32 controlSize = 0; + + if (func == 0) + { + pKernelBif->xveRegmapRef[0].nFunc = 0; + pKernelBif->xveRegmapRef[0].xveRegMapValid = xveRegMapValid; + pKernelBif->xveRegmapRef[0].xveRegMapWrite = xveRegMapWrite; + pKernelBif->xveRegmapRef[0].numXveRegMapValid = NV_ARRAY_ELEMENTS(xveRegMapValid); + pKernelBif->xveRegmapRef[0].numXveRegMapWrite = NV_ARRAY_ELEMENTS(xveRegMapWrite); + pKernelBif->xveRegmapRef[0].bufBootConfigSpace = pKernelBif->cacheData.gpuBootConfigSpace; + // Each MSIX table entry is 4 NvU32s + controlSize = kbifGetMSIXTableVectorControlSize_HAL(pGpu, pKernelBif); + if (pKernelBif->xveRegmapRef[0].bufMsixTable == NULL) + pKernelBif->xveRegmapRef[0].bufMsixTable = portMemAllocNonPaged(controlSize * 4 * sizeof(NvU32)); + NV_ASSERT_OR_RETURN(pKernelBif->xveRegmapRef[0].bufMsixTable != NULL, NV_ERR_NO_MEMORY); + } + else if (func == 1) + { + // Init regmap for Fn1 using older HAL + status = kbifInitXveRegMap_GM107(pGpu, pKernelBif, 1); + } + else + { + NV_PRINTF(LEVEL_ERROR, "Invalid argument, func: %d.\n", func); + NV_ASSERT(0); + status = NV_ERR_INVALID_ARGUMENT; + } + + return status; +} + static NvBool _kbifPreOsCheckErotGrantAllowed_AD102 ( diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c index 8687cb44f..fa0c5a344 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c @@ -1334,6 +1334,7 @@ kfifoChidMgrAllocChannelGroupHwID_IMPL ) { NvU32 maxChannelGroups; + char logMessage[256] = ""; if (pChGrpID == NULL) return NV_ERR_INVALID_ARGUMENT; @@ -1358,6 +1359,13 @@ kfifoChidMgrAllocChannelGroupHwID_IMPL { *pChGrpID = maxChannelGroups; NV_PRINTF(LEVEL_ERROR, "No allocatable FIFO available.\n"); + + // For vGPU, log the error message on host side as well + if (IS_VIRTUAL(pGpu)) + { + nvDbgSnprintf(logMessage, sizeof(logMessage), "Guest attempted to allocate channel above its max per engine channel limit 0x%x", maxChannelGroups); + NV_RM_RPC_LOG(pGpu, (const char *)logMessage, NV_VGPU_LOG_LEVEL_ERROR); + } return NV_ERR_NO_FREE_FIFOS; } return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc.c index ede69454c..94f84223c 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc.c @@ -301,20 +301,28 @@ krcReportXid_IMPL char pid_string[12] = "''"; // - // Get PID of channel creator if available, or get the current PID for - // exception types that never have an associated channel + // When the channel context is available, use the allocating process' + // PID/name, which were populated when the channel was allocated. + // For errors without a channel context, use the current process + // information, if there's a Resource Server CALL_CONTEXT present + // in TLS, indicating we're servicing an RMAPI request. // - // Check for API lock since this can be called from parallel init - // path without API lock, and RES_GET_CLIENT requires API lock - // - if (rmapiLockIsOwner() && (pKernelChannel != NULL)) + if (pKernelChannel != NULL) { + // + // This function executes under (at least) the GPU lock, so the + // pKernelChannel resource can be accessed, regardless of whether + // the API lock is held: the pKernelChannel can't go away while the + // GPU lock is held, so the owning client can't go away either. + // Duping requires holding all GPU locks, so the client's process/ + // name can't change in this context either. + // RsClient *pClient = RES_GET_CLIENT(pKernelChannel); RmClient *pRmClient = dynamicCast(pClient, RmClient); procname = pRmClient->name; nvDbgSnprintf(pid_string, sizeof(pid_string), "%u", pKernelChannel->ProcessID); } - else if (exceptType == GSP_RPC_TIMEOUT) + else if (resservGetTlsCallContext() != NULL) { NvU32 current_pid = osGetCurrentProcess(); diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c index bee1d52a7..6e2a7b89d 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c @@ -1672,6 +1672,47 @@ subdeviceCtrlCmdGpuGetFermiTpcInfo_IMPL return NV_OK; } +#if (defined(DEBUG) || defined(DEVELOP)) +// +// subdeviceCtrlCmdGpuGetTpcReconfigMask +// +// Lock Requirements: +// Assert that API lock and GPUs lock held on entry +// +NV_STATUS +subdeviceCtrlCmdGpuGetTpcReconfigMask_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + NvHandle hSubdevice = RES_GET_HANDLE(pSubdevice); + + NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS tpcReconfigMaskParams; + + NV_ASSERT_OR_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(GPU_RES_GET_GPU(pSubdevice)->gpuInstance), + NV_ERR_INVALID_LOCK_STATE); + + portMemSet(&tpcReconfigMaskParams, 0, sizeof(tpcReconfigMaskParams)); + tpcReconfigMaskParams.gpc = pParams->gpc; + + NV_CHECK_OK_OR_RETURN( + LEVEL_ERROR, + pRmApi->Control(pRmApi, + hClient, + hSubdevice, + NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK, + &tpcReconfigMaskParams, + sizeof(tpcReconfigMaskParams))); + + pParams->tpcReconfigMask = tpcReconfigMaskParams.tpcReconfigMask; + return NV_OK; +} +#endif // defined(DEBUG) || defined(DEVELOP) + // // subdeviceCtrlCmdGpuGetFermiZcullInfo // diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_vgpu.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_vgpu.c index 2069cb3bf..66bb3599d 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_vgpu.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_vgpu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -138,11 +138,14 @@ subdeviceCtrlCmdGpuResetEccErrorStatus_VF NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS *pParams ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); - VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NvBool bMigEnabled = IS_MIG_ENABLED(pGpu); NvU32 i; + NV_CHECK_OR_RETURN(LEVEL_INFO, !bMigEnabled, NV_ERR_NOT_SUPPORTED); + if ((pVGpu == NULL) || (!pVGpu->bECCSupported) || (pParams->statuses & NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE)) { diff --git a/src/nvidia/src/kernel/mem_mgr/mem.c b/src/nvidia/src/kernel/mem_mgr/mem.c index 78fef97d9..2c7372737 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem.c +++ b/src/nvidia/src/kernel/mem_mgr/mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c index 48758326d..d6c9c0a74 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2000-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2000-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -71,7 +71,7 @@ static void objClGpuUnmapRootPort(OBJGPU *); static void objClGpuMapEnhCfgSpace(OBJGPU *, OBJCL *); static void objClGpuUnmapEnhCfgSpace(OBJGPU *); static NV_STATUS objClGpuIs3DController(OBJGPU *); -static void objClLoadPcieVirtualP2PApproval(OBJGPU *, OBJCL *); +static void objClLoadPcieVirtualP2PApproval(OBJGPU *); static void _objClAdjustTcVcMap(OBJGPU *, OBJCL *, PORTDATA *); static void _objClGetDownstreamAtomicsEnabledMask(void *, NvU32, NvU32 *); static void _objClGetUpstreamAtomicRoutingCap(void *, NvU32, NvBool *); @@ -949,7 +949,7 @@ clUpdatePcieConfig_IMPL(OBJGPU *pGpu, OBJCL *pCl) } // Load PCI Express virtual P2P approval config - objClLoadPcieVirtualP2PApproval(pGpu, pCl); + objClLoadPcieVirtualP2PApproval(pGpu); // // Disable NOSNOOP bit for Passthrough. @@ -4256,13 +4256,12 @@ clFreePcieConfigSpaceBase_IMPL(OBJCL *pCl) // other. // static void -objClLoadPcieVirtualP2PApproval(OBJGPU *pGpu, OBJCL *pCl) +objClLoadPcieVirtualP2PApproval(OBJGPU *pGpu) { void *handle; NvU32 data32; NvU8 version; NvU8 cap; - NvU8 rlxdOrderingCfg = 0; NvU8 bus = gpuGetBus(pGpu); NvU8 device = gpuGetDevice(pGpu); NvU32 domain = gpuGetDomain(pGpu); @@ -4322,19 +4321,6 @@ objClLoadPcieVirtualP2PApproval(OBJGPU *pGpu, OBJCL *pCl) _PEER_CLIQUE_ID, data32); pGpu->pciePeerClique.bValid = NV_TRUE; - rlxdOrderingCfg = (NvU8)DRF_VAL(_PCI, _VIRTUAL_P2P_APPROVAL_CAP_1, - _RELAXED_ORDERING, data32); - - if (rlxdOrderingCfg == NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING_DISABLE) - { - // Unset relaxed ordering based on hypervisor's request - pCl->setProperty(pCl, PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE, NV_TRUE); - - NV_PRINTF(LEVEL_INFO, - "Hypervisor has disabled relaxed ordering on GPU%u\n", - gpuGetInstance(pGpu)); - } - NV_PRINTF(LEVEL_INFO, "Hypervisor has assigned GPU%u to peer clique %u\n", gpuGetInstance(pGpu), pGpu->pciePeerClique.id); diff --git a/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c b/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c index cfb843e8a..e6dcb1385 100644 --- a/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c +++ b/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -406,6 +406,11 @@ destroyKernelHostVgpuDeviceShare(OBJGPU *pGpu, KernelHostVgpuDeviceShr* pShare) RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS shutdownParams = { 0 }; NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS cleanupResourcesParams = {0}; + // Extend timeout to 30s for these calls to account for long-running mass client free (bug 4928590) + // Otherwise this can hit XID 119 and orphan all remaining clients on GSP side + NvU32 defaultus = pGpu->timeoutData.defaultus; + + pGpu->timeoutData.defaultus = 30*1000*1000; shutdownParams.gfid = pKernelHostVgpuDevice->gfid; @@ -419,6 +424,7 @@ destroyKernelHostVgpuDeviceShare(OBJGPU *pGpu, KernelHostVgpuDeviceShr* pShare) status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP, &cleanupResourcesParams, sizeof(cleanupResourcesParams)); + pGpu->timeoutData.defaultus = defaultus; if (status != NV_OK) NV_PRINTF(LEVEL_ERROR, "Failed to call cleanup plugin resources\n"); diff --git a/src/nvidia/src/libraries/crashcat/crashcat_report.c b/src/nvidia/src/libraries/crashcat/crashcat_report.c index 3d55aadad..1be8f4272 100644 --- a/src/nvidia/src/libraries/crashcat/crashcat_report.c +++ b/src/nvidia/src/libraries/crashcat/crashcat_report.c @@ -84,8 +84,7 @@ void crashcatReportLog_IMPL(CrashCatReport *pReport) } FOR_EACH_INDEX_IN_MASK_END; - crashcatEnginePrintf(pReport->pEngine, NV_FALSE, - CRASHCAT_LOG_PREFIX "------------[ end crash report ]------------"); + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "------------[ end crash report ]------------\n"); } // xcause CSR format and codes are a backward-compatible part of the RISC-V standard diff --git a/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c b/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c index 818afb698..8a3508d1b 100644 --- a/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c +++ b/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c @@ -26,6 +26,8 @@ #include "crashcat/crashcat_engine.h" #include "utils/nvassert.h" #include "nv-crashcat-decoder.h" +#include "utils/nvprintf.h" + static NV_INLINE NvUPtr ptrDiff(void *pStart, void *pEnd) { @@ -353,33 +355,33 @@ void crashcatReportLogRiscv64CsrState_V1(CrashCatReport *pReport) // correct as of this writing because there isn't an M-mode implementer on NVRISCV 2.x+, // but we should have a way of distinguishing in the protocol. // - CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "RISC-V CSR State:"); + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "RISC-V CSR State:\n"); switch (mode) { case NV_CRASHCAT_RISCV_MODE_M: CRASHCAT_REPORT_LOG_DATA(pReport, - "mstatus:0x%016" NvU64_fmtx " mscratch:0x%016" NvU64_fmtx " mie:0x%016" NvU64_fmtx " mip:0x%016" NvU64_fmtx, + "mstatus:0x%016" NvU64_fmtx " mscratch:0x%016" NvU64_fmtx " mie:0x%016" NvU64_fmtx " mip:0x%016" NvU64_fmtx "\n", pCsrStateV1->xstatus, pCsrStateV1->xscratch, pCsrStateV1->xie, pCsrStateV1->xip); CRASHCAT_REPORT_LOG_DATA(pReport, - " mepc:0x%016" NvU64_fmtx " mbadaddr:0x%016" NvU64_fmtx " mcause:0x%016" NvU64_fmtx, + "mepc:0x%016" NvU64_fmtx " mbadaddr:0x%016" NvU64_fmtx " mcause:0x%016" NvU64_fmtx "\n", pCsrStateV1->xepc, pCsrStateV1->xtval, pCsrStateV1->xcause); break; case NV_CRASHCAT_RISCV_MODE_S: CRASHCAT_REPORT_LOG_DATA(pReport, - "sstatus:0x%016" NvU64_fmtx " sscratch:0x%016" NvU64_fmtx " sie:0x%016" NvU64_fmtx " sip:0x%016" NvU64_fmtx, + "sstatus:0x%016" NvU64_fmtx " sscratch:0x%016" NvU64_fmtx " sie:0x%016" NvU64_fmtx " sip:0x%016" NvU64_fmtx "\n", pCsrStateV1->xstatus, pCsrStateV1->xscratch, pCsrStateV1->xie, pCsrStateV1->xip); CRASHCAT_REPORT_LOG_DATA(pReport, - " sepc:0x%016" NvU64_fmtx " stval:0x%016" NvU64_fmtx " scause:0x%016" NvU64_fmtx, + "sepc:0x%016" NvU64_fmtx " stval:0x%016" NvU64_fmtx " scause:0x%016" NvU64_fmtx "\n", pCsrStateV1->xepc, pCsrStateV1->xtval, pCsrStateV1->xcause); break; default: // We don't expect CSR dumps from other modes NV_PRINTF(LEVEL_WARNING, "Unexpected RISC-V mode (%u) CSR dump\n", mode); CRASHCAT_REPORT_LOG_DATA(pReport, - "xstatus:0x%016" NvU64_fmtx " xscratch:0x%016" NvU64_fmtx " xie:0x%016" NvU64_fmtx " xip:0x%016" NvU64_fmtx, + "xstatus:0x%016" NvU64_fmtx " xscratch:0x%016" NvU64_fmtx " xie:0x%016" NvU64_fmtx " xip:0x%016" NvU64_fmtx "\n", pCsrStateV1->xstatus, pCsrStateV1->xscratch, pCsrStateV1->xie, pCsrStateV1->xip); CRASHCAT_REPORT_LOG_DATA(pReport, - " xepc:0x%016" NvU64_fmtx " xtval:0x%016" NvU64_fmtx " xcause:0x%016" NvU64_fmtx, + "xepc:0x%016" NvU64_fmtx " xtval:0x%016" NvU64_fmtx " xcause:0x%016" NvU64_fmtx "\n", pCsrStateV1->xepc, pCsrStateV1->xtval, pCsrStateV1->xcause); break; } @@ -390,43 +392,33 @@ void crashcatReportLogRiscv64GprState_V1(CrashCatReport *pReport) NvCrashCatRiscv64GprState_V1 *pGprStateV1 = &pReport->v1.riscv64GprState; // TODO: log the mode of the GPR state - CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "RISC-V GPR State:"); + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "RISC-V GPR State:\n"); CRASHCAT_REPORT_LOG_DATA(pReport, - "ra:0x%016" NvU64_fmtx " sp:0x%016" NvU64_fmtx " gp:0x%016" NvU64_fmtx " tp:0x%016" NvU64_fmtx, + "ra:0x%016" NvU64_fmtx " sp:0x%016" NvU64_fmtx " gp:0x%016" NvU64_fmtx " tp:0x%016" NvU64_fmtx "\n", pGprStateV1->ra, pGprStateV1->sp, pGprStateV1->gp, pGprStateV1->tp); CRASHCAT_REPORT_LOG_DATA(pReport, - "a0:0x%016" NvU64_fmtx " a1:0x%016" NvU64_fmtx " a2:0x%016" NvU64_fmtx " a3:0x%016" NvU64_fmtx, + "a0:0x%016" NvU64_fmtx " a1:0x%016" NvU64_fmtx " a2:0x%016" NvU64_fmtx " a3:0x%016" NvU64_fmtx "\n", pGprStateV1->a0, pGprStateV1->a1, pGprStateV1->a2, pGprStateV1->a3); CRASHCAT_REPORT_LOG_DATA(pReport, - "a4:0x%016" NvU64_fmtx " a5:0x%016" NvU64_fmtx " a6:0x%016" NvU64_fmtx " a7:0x%016" NvU64_fmtx, + "a4:0x%016" NvU64_fmtx " a5:0x%016" NvU64_fmtx " a6:0x%016" NvU64_fmtx " a7:0x%016" NvU64_fmtx "\n", pGprStateV1->a4, pGprStateV1->a5, pGprStateV1->a6, pGprStateV1->a7); CRASHCAT_REPORT_LOG_DATA(pReport, - "s0:0x%016" NvU64_fmtx " s1:0x%016" NvU64_fmtx " s2:0x%016" NvU64_fmtx " s3:0x%016" NvU64_fmtx, + "s0:0x%016" NvU64_fmtx " s1:0x%016" NvU64_fmtx " s2:0x%016" NvU64_fmtx " s3:0x%016" NvU64_fmtx "\n", pGprStateV1->s0, pGprStateV1->s1, pGprStateV1->s2, pGprStateV1->s3); CRASHCAT_REPORT_LOG_DATA(pReport, - "s4:0x%016" NvU64_fmtx " s5:0x%016" NvU64_fmtx " s6:0x%016" NvU64_fmtx " s7:0x%016" NvU64_fmtx, + "s4:0x%016" NvU64_fmtx " s5:0x%016" NvU64_fmtx " s6:0x%016" NvU64_fmtx " s7:0x%016" NvU64_fmtx "\n", pGprStateV1->s4, pGprStateV1->s5, pGprStateV1->s6, pGprStateV1->s7); CRASHCAT_REPORT_LOG_DATA(pReport, - "s8:0x%016" NvU64_fmtx " s9:0x%016" NvU64_fmtx " s10:0x%016" NvU64_fmtx " s11:0x%016" NvU64_fmtx, + "s8:0x%016" NvU64_fmtx " s9:0x%016" NvU64_fmtx " s10:0x%016" NvU64_fmtx " s11:0x%016" NvU64_fmtx "\n", pGprStateV1->s8, pGprStateV1->s9, pGprStateV1->s10, pGprStateV1->s11); CRASHCAT_REPORT_LOG_DATA(pReport, - "t0:0x%016" NvU64_fmtx " t1:0x%016" NvU64_fmtx " t2:0x%016" NvU64_fmtx " t3:0x%016" NvU64_fmtx, + "t0:0x%016" NvU64_fmtx " t1:0x%016" NvU64_fmtx " t2:0x%016" NvU64_fmtx " t3:0x%016" NvU64_fmtx "\n", pGprStateV1->t0, pGprStateV1->t1, pGprStateV1->t2, pGprStateV1->t3); CRASHCAT_REPORT_LOG_DATA(pReport, - "t4:0x%016" NvU64_fmtx " t5:0x%016" NvU64_fmtx " t6:0x%016" NvU64_fmtx, + "t4:0x%016" NvU64_fmtx " t5:0x%016" NvU64_fmtx " t6:0x%016" NvU64_fmtx "\n", pGprStateV1->t4, pGprStateV1->t5, pGprStateV1->t6); } -static NV_INLINE const char *crashcatRiscv64TraceTypeToString_V1(NV_CRASHCAT_TRACE_TYPE traceType) -{ - switch (traceType) - { - case NV_CRASHCAT_TRACE_TYPE_STACK: return MAKE_NV_PRINTF_STR("Stack"); - case NV_CRASHCAT_TRACE_TYPE_NVRVTB: return MAKE_NV_PRINTF_STR("PC"); - default: return MAKE_NV_PRINTF_STR("Address"); - } -} - static void crashcatReportLogRiscv64Trace_V1 ( CrashCatReport *pReport, @@ -437,8 +429,17 @@ static void crashcatReportLogRiscv64Trace_V1 NV_CRASHCAT_TRACE_TYPE traceType = crashcatRiscv64TraceV1Type(pTraceV1); // TODO: log the mode of the trace using implementer terminology (e.g., kernel/task) - CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "%s Trace:", - crashcatRiscv64TraceTypeToString_V1(traceType)); + switch (traceType) + { + case NV_CRASHCAT_TRACE_TYPE_STACK: + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Stack Trace:\n"); + break; + case NV_CRASHCAT_TRACE_TYPE_NVRVTB: + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "PC Trace:\n"); + break; + default: + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Address Trace:\n"); + } if (traceType == NV_CRASHCAT_TRACE_TYPE_NVRVTB) { @@ -450,7 +451,7 @@ static void crashcatReportLogRiscv64Trace_V1 { CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " " - "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx, + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx "\n", pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1], pTraceV1->addr[idx + 2], pTraceV1->addr[idx + 3], pTraceV1->addr[idx + 4]); } @@ -460,21 +461,21 @@ static void crashcatReportLogRiscv64Trace_V1 case 4: CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " " - "0x%016" NvU64_fmtx, + "0x%016" NvU64_fmtx "\n", pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1], pTraceV1->addr[idx + 2], pTraceV1->addr[idx + 3]); break; case 3: CRASHCAT_REPORT_LOG_DATA(pReport, - "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx, + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx "\n", pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1], pTraceV1->addr[idx + 2]); break; case 2: - CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx, + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx "\n", pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1]); break; case 1: - CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx, pTraceV1->addr[idx + 0]); + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx "\n", pTraceV1->addr[idx + 0]); break; default: break; @@ -483,7 +484,9 @@ static void crashcatReportLogRiscv64Trace_V1 else { for (NvU16 idx = 0; idx < entries; idx++) - CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx, pTraceV1->addr[idx]); + { + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx "\n", pTraceV1->addr[idx]); + } } } @@ -495,30 +498,30 @@ void crashcatReportLogRiscv64Traces_V1(CrashCatReport *pReport) crashcatReportLogRiscv64Trace_V1(pReport, pReport->v1.pRiscv64PcTrace); } -static NV_INLINE const char *crashcatIo32ApertureToString_V1(NV_CRASHCAT_IO_APERTURE aperture) -{ - switch (aperture) - { - case NV_CRASHCAT_IO_APERTURE_INTIO: return MAKE_NV_PRINTF_STR("Local I/O"); - case NV_CRASHCAT_IO_APERTURE_EXTIO: return MAKE_NV_PRINTF_STR("External I/O"); - default: return MAKE_NV_PRINTF_STR("Additional"); - } -} - void crashcatReportLogIo32State_V1(CrashCatReport *pReport) { NvCrashCatIo32State_V1 *pIo32StateV1 = pReport->v1.pIo32State; NvU16 entries = crashcatPacketHeaderPayloadSize(pIo32StateV1->header) >> 3; NV_CRASHCAT_IO_APERTURE aperture = crashcatIo32StateV1Aperture(pIo32StateV1); - CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "%s Register State:", - crashcatIo32ApertureToString_V1(aperture)); + + switch (aperture) + { + case NV_CRASHCAT_IO_APERTURE_INTIO: + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Local I/O Register State:\n"); + break; + case NV_CRASHCAT_IO_APERTURE_EXTIO: + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "External I/O Register State:\n"); + break; + default: + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Additional Register State:\n"); + } // Print 4 registers on a line to save space const NvU8 REGS_PER_LINE = 4; NvU16 idx; for (idx = 0; idx < (entries / REGS_PER_LINE) * REGS_PER_LINE; idx += REGS_PER_LINE) CRASHCAT_REPORT_LOG_DATA(pReport, - "0x%08x:0x%08x 0x%08x:0x%08x 0x%08x:0x%08x 0x%08x:0x%08x", + "0x%08x:0x%08x 0x%08x:0x%08x 0x%08x:0x%08x 0x%08x:0x%08x\n", pIo32StateV1->regs[idx + 0].offset, pIo32StateV1->regs[idx + 0].value, pIo32StateV1->regs[idx + 1].offset, pIo32StateV1->regs[idx + 1].value, pIo32StateV1->regs[idx + 2].offset, pIo32StateV1->regs[idx + 2].value, @@ -527,18 +530,18 @@ void crashcatReportLogIo32State_V1(CrashCatReport *pReport) switch (entries - idx) { case 3: - CRASHCAT_REPORT_LOG_DATA(pReport, "0x%08x:0x%08x 0x%08x:0x%08x 0x%08x:0x%08x", + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%08x:0x%08x 0x%08x:0x%08x 0x%08x:0x%08x\n", pIo32StateV1->regs[idx + 0].offset, pIo32StateV1->regs[idx + 0].value, pIo32StateV1->regs[idx + 1].offset, pIo32StateV1->regs[idx + 1].value, pIo32StateV1->regs[idx + 2].offset, pIo32StateV1->regs[idx + 2].value); break; case 2: - CRASHCAT_REPORT_LOG_DATA(pReport, "0x%08x:0x%08x 0x%08x:0x%08x", + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%08x:0x%08x 0x%08x:0x%08x\n", pIo32StateV1->regs[idx + 0].offset, pIo32StateV1->regs[idx + 0].value, pIo32StateV1->regs[idx + 1].offset, pIo32StateV1->regs[idx + 1].value); break; case 1: - CRASHCAT_REPORT_LOG_DATA(pReport, "0x%08x:0x%08x", + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%08x:0x%08x\n", pIo32StateV1->regs[idx + 0].offset, pIo32StateV1->regs[idx + 0].value); break; default: diff --git a/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c index be64974ec..4e547dbf2 100644 --- a/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c +++ b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c @@ -74,7 +74,7 @@ void crashcatReportLogReporter_V1_GENERIC(CrashCatReport *pReport) // macro to get the correct prefix/indentation for the reporter information. // CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, - "Reported by partition:%u ucode:%u [%c-mode] version:%u @ %u", + "Reported by partition:%u ucode:%u [%c-mode] version:%u @ %u\n", partition, ucodeId, crashcatReportModeToChar_GENERIC(riscvMode), crashcatReportV1ReporterVersion(pReportV1), crashcatReportV1ReporterTimestamp(pReportV1)); diff --git a/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c index 51c038a6d..d9daa9106 100644 --- a/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c +++ b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c @@ -120,7 +120,7 @@ void crashcatReportLogReporter_V1_LIBOS2(CrashCatReport *pReport) // if (taskId == NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS2_TASK_ID_UNSPECIFIED) { - CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Reported by libos kernel v%u.%u [%u] @ %u", + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Reported by libos kernel v%u.%u [%u] @ %u\n", crashcatReportV1ReporterVersionLibos2Major(pReportV1), crashcatReportV1ReporterVersionLibos2Minor(pReportV1), crashcatReportV1ReporterVersionLibos2Cl(pReportV1), @@ -128,7 +128,7 @@ void crashcatReportLogReporter_V1_LIBOS2(CrashCatReport *pReport) } else { - CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Reported by libos task:%u v%u.%u [%u] @ ts:%u", + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "Reported by libos task:%u v%u.%u [%u] @ ts:%u\n", taskId, crashcatReportV1ReporterVersionLibos2Major(pReportV1), crashcatReportV1ReporterVersionLibos2Minor(pReportV1), crashcatReportV1ReporterVersionLibos2Cl(pReportV1), diff --git a/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c index 975fb5cfd..90ff9386e 100644 --- a/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c +++ b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c @@ -132,7 +132,7 @@ void crashcatReportLogReporter_V1_LIBOS3(CrashCatReport *pReport) if (taskId == NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_TASK_ID_UNSPECIFIED) { CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, - "Reported by libos partition:%u#%u kernel v%u.%u [%u] @ ts:%u", + "Reported by libos partition:%u#%u kernel v%u.%u [%u] @ ts:%u\n", crashcatReportV1ReporterPartition(pReportV1), crashcatReportV1ReporterUcodeId(pReportV1), crashcatReportV1ReporterVersionLibos3Major(pReportV1), @@ -143,7 +143,7 @@ void crashcatReportLogReporter_V1_LIBOS3(CrashCatReport *pReport) else { CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, - "Reported by libos partition:%u#%u task:%u v%u.%u [%u] @ ts:%u", + "Reported by libos partition:%u#%u task:%u v%u.%u [%u] @ ts:%u\n", crashcatReportV1ReporterPartition(pReportV1), crashcatReportV1ReporterUcodeId(pReportV1), taskId, crashcatReportV1ReporterVersionLibos3Major(pReportV1), diff --git a/version.mk b/version.mk index 44bad3f8d..928954cc4 100644 --- a/version.mk +++ b/version.mk @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 550.144.03 +NVIDIA_VERSION = 550.163.01 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))