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535.54.03

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This commit is contained in:
Andy Ritger
2023-06-14 12:37:59 -07:00
parent eb5c7665a1
commit 26458140be
120 changed files with 83370 additions and 81507 deletions
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1
src/common/inc/gps.h
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@@ -30,6 +30,7 @@
#define GPS_FUNC_SUPPORT 0x00000000 // Bit list of supported functions
#define GPS_FUNC_GETOBJBYTYPE 0x00000010 // Fetch any specific Object by Type
#define GPS_FUNC_GETALLOBJS 0x00000011 // Fetch all Objects
#define GPS_FUNC_REQUESTDXSTATE 0x00000012 // Request D-Notifier state
#define GPS_FUNC_GETCALLBACKS 0x00000013 // Get system requested callbacks
#define GPS_FUNC_PCONTROL 0x0000001C // GPU power control function
#define GPS_FUNC_PSHARESTATUS 0x00000020 // Get system requested Power Steering settings

20
src/common/inc/nvBldVer.h
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@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r535_87
#define NV_BUILD_BRANCH r536_08
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r535_87
#define NV_PUBLIC_BRANCH r536_08
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r535_87-122"
#define NV_BUILD_CHANGELIST_NUM (32882771)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r536_08-145"
#define NV_BUILD_CHANGELIST_NUM (32940552)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r535/r535_87-122"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32882771)
#define NV_BUILD_NAME "rel/gpu_drv/r535/r536_08-145"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32940552)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r535_87-4"
#define NV_BUILD_CHANGELIST_NUM (32875904)
#define NV_BUILD_BRANCH_VERSION "r536_08-4"
#define NV_BUILD_CHANGELIST_NUM (32940552)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "535.93"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32875904)
#define NV_BUILD_NAME "536.19"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32940552)
#define NV_BUILD_BRANCH_BASE_VERSION R535
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "535.43.02"
#define NV_VERSION_STRING "535.54.03"
#else

26
src/common/inc/nvlog_defs.h
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@@ -120,12 +120,14 @@ struct _NVLOG_BUFFER
#if !PORT_IS_KERNEL_BUILD
typedef struct PORT_SPINLOCK PORT_SPINLOCK;
typedef struct PORT_MUTEX PORT_MUTEX;
#else
#include "nvport/nvport.h"
#endif
#elif !defined(PORT_IS_KERNEL_BUILD)
typedef struct PORT_SPINLOCK PORT_SPINLOCK;
typedef struct PORT_MUTEX PORT_MUTEX;
#else
#include "nvport/nvport.h"
#endif
@@ -143,11 +145,33 @@ typedef struct _NVLOG_LOGGER
NvU32 nextFree;
/** Total number of free buffer slots */
NvU32 totalFree;
/** Lock for all buffer oprations */
/** Lock for some buffer oprations */
PORT_SPINLOCK* mainLock;
/** Lock for creating/deleting pBuffers and accessing them from RmCtrls */
PORT_MUTEX* buffersLock;
} NVLOG_LOGGER;
extern NVLOG_LOGGER NvLogLogger;
/**
* NvLog uses two locks:
* - NVLOG_LOGGER::mainLock is used to protect some accesses to pBuffers, or
* an individual pBuffers entry depending on locking flags.
* - NVLOG_LOGGER::buffersLock is used to protect creating/deleting pBuffers and accessing them
* from certain RmCtrl handlers.
*
* Historically in most contexts obtaining RMAPI lock would suffice, and mainLock would optionally
* be used for certain buffers. Ioctl NV_ESC_RM_NVLOG_CTRL cannot touch RMAPI lock and needs
* to access NvLog. The latter operation might race if called at an inopportune time: e.g. if the
* ioctl is called during RM init when KGSP creates/deletes GSP NvLog buffers. Using buffersLock is
* thus necessary to resolve the potential race.
*
* This leads to an unfortunate sequence where mainLock and buffersLock are nested. The latter lock
* cannot be removed as it is used in IRQ paths.
*
* This should be refactored to use a single RWLock that does conditional acquire in possible IRQ
* paths.
*/
//
// Buffer flags
//

9
src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h
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@@ -39,8 +39,12 @@
#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE 31:24 /* R-IVF */
#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE_3D 0x00000003 /* R-I-V */
#define NV_EP_PCFG_GPU_BARREG0 0x00000010 /* RW-4R */
#define NV_EP_PCFG_GPU_BARREG0_REG_ADDR_TYPE 2:1 /* R-IVF */
#define NV_EP_PCFG_GPU_BARREG0_REG_ADDR_TYPE_32BIT 0x00000000 /* R-I-V */
#define NV_EP_PCFG_GPU_BARREG0_REG_ADDR_TYPE_64BIT 0x00000002 /* R---V */
#define NV_EP_PCFG_GPU_BARREG0_REG_BASE_ADDRESS 31:18 /* RWIVF */
#define NV_EP_PCFG_GPU_BARREG0_REG_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_EP_PCFG_GPU_BARREG5 0x00000024 /* RW-4R */
#define NV_EP_PCFG_GPU_SUBSYSTEM_ID 0x0000002C /* R--4R */
#define NV_EP_PCFG_GPU_MSI_64_HEADER 0x00000048 /* RW-4R */
#define NV_EP_PCFG_GPU_MSI_64_HEADER_MSI_ENABLE 16:16 /* RWIVF */
@@ -79,6 +83,11 @@
#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER 8:8 /* RWCVF */
#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT 12:12 /* RWCVF */
#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR 13:13 /* RWCVF */
#define NV_EP_PCFG_GPU_SRIOV_INIT_TOT_VF 0x0000025C /* R--4R */
#define NV_EP_PCFG_GPU_SRIOV_INIT_TOT_VF_TOTAL_VFS 31:16 /* R-EVF */
#define NV_EP_PCFG_GPU_SRIOV_FIRST_VF_STRIDE 0x00000264 /* R--4R */
#define NV_EP_PCFG_GPU_SRIOV_FIRST_VF_STRIDE_FIRST_VF_OFFSET 15:0 /* R-IVF */
#define NV_EP_PCFG_GPU_VF_BAR0 0x00000274 /* RW-4R */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC 0x000002B4 /* R--4R */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FUSE_POD 0:0 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FUSE_SCPM 1:1 /* R-CVF */

11
src/common/inc/swref/published/turing/tu102/dev_nv_xve.h
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@@ -23,9 +23,18 @@
#ifndef __tu102_dev_nv_xve_h__
#define __tu102_dev_nv_xve_h__
#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */
#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */
#define NV_XVE_MSIX_CAP_HDR 0x000000C8 /* RW-4R */
#define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */
#define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */
#define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */
#define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */
#define NV_XVE_SRIOV_CAP_HDR5_FIRST_VF_OFFSET 15:0 /* R-IVF */
#define NV_XVE_SRIOV_CAP_HDR9 0x00000BF0 /* RW-4R */
#define NV_XVE_SRIOV_CAP_HDR10 0x00000BF4 /* RW-4R */
#define NV_XVE_SRIOV_CAP_HDR11_VF_BAR1_HI 0x00000BF8 /* RW-4R */
#define NV_XVE_SRIOV_CAP_HDR12 0x00000BFC /* RW-4R */
#define NV_XVE_SRIOV_CAP_HDR13_VF_BAR2_HI 0x00000C00 /* RW-4R */
#endif // __tu102_dev_nv_xve_h__

4
src/common/nvswitch/kernel/ls10/ls10.c
View File

@@ -1505,7 +1505,7 @@ nvswitch_reset_and_drain_links_ls10
// DEBUG_CLEAR (0x144) register
// - Assert NPortWarmReset[i] using the WARMRESET (0x140) register
//
// nvswitch_soe_issue_nport_reset_ls10(device, link);
nvswitch_soe_issue_nport_reset_ls10(device, link);
//
// Step 5.0 : Issue Minion request to perform the link reset sequence
@@ -1583,7 +1583,7 @@ nvswitch_reset_and_drain_links_ls10
// - Assert NPORT INITIALIZATION and program the state tracking RAMS
// - Restore NPORT state after reset
//
// nvswitch_soe_restore_nport_state_ls10(device, link);
nvswitch_soe_restore_nport_state_ls10(device, link);
// Step 7.0 : Re-program the routing table for DBEs

42
src/common/sdk/nvidia/inc/ctrl/ctrl0050.h
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@@ -72,6 +72,19 @@
* identity mapped. To use this feature, users need to pass in the
* hVaspace with identity mapped addresses for the entire memory during
* construct.
* PIPELINED
* This flag allows the copy/memset operation to be pipelined with previous dma operations on the same channel
* It means that its reads/writes are allowed happen before writes of preceding operations are tlb-acked
* The flag can be useful when dealing with non-inersecting async operations,
* but it can result in races when 2 async CE operations target the same allocation, and the second operation uses the flag
* Race example:
* 1. async copy A -> B
* 2. pipelined copy B -> C
* Here copy 2 can read B before copy finishes writing it, which will result in C containing invalid data
* Technical details:
* By default, first _LAUNCH_DMA method of a CE operation is marked has _TRANSFER_TYPE_NON_PIPELINED, which the flag overrides
* Subsequent _LAUNCH_DMA methods belonging to the same operation use _TRANSFER_TYPE_PIPELINED, as each of these methods should
* target different addresses
*
* submittedWorkId [OUT]
* The work submission token users can poll on to wait for work
@@ -79,8 +92,9 @@
*/
#define NV0050_CTRL_MEMSET_FLAGS_DEFAULT 0
#define NV0050_CTRL_MEMSET_FLAGS_ASYNC NVBIT(0)
#define NV0050_CTRL_MEMSET_FLAGS_VIRTUAL NVBIT(1)
#define NV0050_CTRL_MEMSET_FLAGS_ASYNC NVBIT(0)
#define NV0050_CTRL_MEMSET_FLAGS_VIRTUAL NVBIT(1)
#define NV0050_CTRL_MEMSET_FLAGS_PIPELINED NVBIT(2)
#define NV0050_CTRL_CMD_MEMSET (0x500101U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8) | NV0050_CTRL_MEMSET_PARAMS_MESSAGE_ID" */
@@ -98,7 +112,7 @@ typedef struct NV0050_CTRL_MEMSET_PARAMS {
/*
* NV0050_CTRL_CMD_MEMCOPY
*
* Copies from a source memoryto ssdestination memory and releases a semaphore
* Copies from a source memoryto ssdestination memory and releases a semaphore
* on completion
*
* hDstMemory [IN]
@@ -131,6 +145,19 @@ typedef struct NV0050_CTRL_MEMSET_PARAMS {
* identity mapped. To use this feature, users need to pass in the
* hVaspace with identity mapped addresses for the entire memory during
* construct.
* PIPELINED
* This flag allows the copy/memset operation to be pipelined with previous dma operations on the same channel
* It means that its reads/writes are allowed happen before writes of preceding operations are tlb-acked
* The flag can be useful when dealing with non-inersecting async operations,
* but it can result in races when 2 async CE operations target the same allocation, and the second operation uses the flag
* Race example:
* 1. async copy A -> B
* 2. pipelined copy B -> C
* Here copy 2 can read B before copy finishes writing it, which will result in C containing invalid data
* Technical details:
* By default, first _LAUNCH_DMA method of a CE operation is marked has _TRANSFER_TYPE_NON_PIPELINED, which the flag overrides
* Subsequent _LAUNCH_DMA methods belonging to the same operation use _TRANSFER_TYPE_PIPELINED, as each of these methods should
* target different addresses
*
* submittedWorkId [OUT]
* The work submission token users can poll on to wait for work
@@ -138,8 +165,9 @@ typedef struct NV0050_CTRL_MEMSET_PARAMS {
*/
#define NV0050_CTRL_MEMCOPY_FLAGS_DEFAULT 0
#define NV0050_CTRL_MEMCOPY_FLAGS_ASYNC NVBIT(1)
#define NV0050_CTRL_MEMCOPY_FLAGS_VIRTUAL NVBIT(2)
#define NV0050_CTRL_MEMCOPY_FLAGS_ASYNC NVBIT(0)
#define NV0050_CTRL_MEMCOPY_FLAGS_VIRTUAL NVBIT(1)
#define NV0050_CTRL_MEMCOPY_FLAGS_PIPELINED NVBIT(2)
#define NV0050_CTRL_CMD_MEMCOPY (0x500102U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8 | NV0050_CTRL_MEMCOPY_PARAMS_MESSAGE_ID)" */
@@ -157,12 +185,12 @@ typedef struct NV0050_CTRL_MEMCOPY_PARAMS {
/*
* NV0050_CTRL_CMD_CHECK_PROGRESS
*
*
* Check if a previously submitted work item has been completed by HW.
*
* submittedWorkId [IN]
* The work submission token users can poll on to wait for work
* completed by CE.
* completed by CE.
*
*/
#define NV0050_CTRL_CHECK_PROGRESS_RESULT_DEFAULT 0

18
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h
View File

@@ -208,11 +208,11 @@ typedef struct NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS {
* guestMSIData
* This parameter indicates the MSI data set by the guest OS.
*
* vmIdType
* This parameter specifies the type of guest virtual machine identifier
* vgpuUuid
* This parameter specifies the uuid of vGPU assigned to VM.
*
* guestVmId
* This parameter specifies the guest virtual machine identifier
* domainId
* This parameter specifies the unique guest virtual machine identifier
*
* Possible status values returned are:
* NV_OK
@@ -225,11 +225,11 @@ typedef struct NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS {
typedef struct NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS {
NV_DECLARE_ALIGNED(NvU64 guestMSIAddr, 8);
NvU32 guestMSIData;
NvHandle hSemMemory;
NvBool isReset;
VM_ID_TYPE vmIdType;
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
NvU32 guestMSIData;
NvHandle hSemMemory;
NvBool isReset;
NvU8 vgpuUuid[VM_UUID_SIZE];
NV_DECLARE_ALIGNED(NvU64 domainId, 8);
} NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS;