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580.76.05

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This commit is contained in:
Maneet Singh
2025-08-12 12:13:43 -07:00
parent 307159f262
commit 288f16e614
64 changed files with 2037 additions and 863 deletions
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12
src/nvidia/generated/g_gpu_nvoc.c
View File

@@ -513,7 +513,17 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
pThis->setProperty(pThis, PDB_PROP_GPU_RUSD_POLLING_SUPPORT_MONOLITHIC, NV_FALSE);
}
pThis->setProperty(pThis, PDB_PROP_GPU_RECOVERY_REBOOT_REQUIRED, NV_FALSE);
pThis->setProperty(pThis, PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT, NV_FALSE);
// NVOC Property Hal field -- PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT
if (( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB20B | GB20C */
{
pThis->setProperty(pThis, PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT, NV_TRUE);
}
// default
else
{
pThis->setProperty(pThis, PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT, NV_FALSE);
}
pThis->deviceInstance = 32;

5
src/nvidia/generated/g_gpu_nvoc.h
View File

@@ -1344,6 +1344,7 @@ struct OBJGPU {
DEVICE_MAPPING *pDeviceMappingsByDeviceInstance[13];
void *gpuCfgAddr;
TIMEOUT_DATA timeoutData;
NvU32 bug5203024OverrideTimeouts;
NvU32 computeModeRules;
NvS32 computeModeRefCount;
NvHandle hComputeModeReservation;
@@ -4460,6 +4461,8 @@ NV_STATUS gpuGetNameString_T234D(struct OBJGPU *pGpu, NvU32 arg2, void *arg3);
NV_STATUS gpuGetNameString_FWCLIENT(struct OBJGPU *pGpu, NvU32 arg2, void *arg3);
NV_STATUS gpuGetNameString_GB20B(struct OBJGPU *pGpu, NvU32 arg2, void *arg3);
NV_STATUS gpuGetNameString_IMPL(struct OBJGPU *pGpu, NvU32 arg2, void *arg3);
NV_STATUS gpuGetShortNameString_VF(struct OBJGPU *pGpu, NvU8 *arg2);
@@ -4468,6 +4471,8 @@ NV_STATUS gpuGetShortNameString_T234D(struct OBJGPU *pGpu, NvU8 *arg2);
NV_STATUS gpuGetShortNameString_FWCLIENT(struct OBJGPU *pGpu, NvU8 *arg2);
NV_STATUS gpuGetShortNameString_GB20B(struct OBJGPU *pGpu, NvU8 *arg2);
NV_STATUS gpuGetShortNameString_IMPL(struct OBJGPU *pGpu, NvU8 *arg2);
static inline NV_STATUS gpuInitBranding_56cd7a(struct OBJGPU *pGpu) {

2
src/nvidia/generated/g_kern_gmmu_nvoc.c
View File

@@ -1048,7 +1048,7 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, GpuHalspecOwne
// kgmmuReadShadowBufPutIndex -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x70000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000006UL) )) /* ChipHal: GH100 | GB100 | GB102 | GB110 | GB112 */
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: GH100 | GB100 | GB102 | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kgmmuReadShadowBufPutIndex__ = &kgmmuReadShadowBufPutIndex_GH100;
}

12
src/nvidia/generated/g_mem_desc_nvoc.h
View File

@@ -123,6 +123,7 @@ typedef NvU32 NV_ADDRESS_SPACE;
typedef NvU32 MEMDESC_CUSTOM_HEAP;
#define MEMDESC_CUSTOM_HEAP_NONE 0
#define MEMDESC_CUSTOM_HEAP_ACR 1
#define MEMDESC_CUSTOM_HEAP_SCANOUT_CARVEOUT 2
//
// Address translation identifiers:
@@ -426,6 +427,7 @@ typedef struct ADDRESS_TRANSLATION_ *ADDRESS_TRANSLATION;
//
#define MEMDESC_FLAGS_ALLOC_AS_LOCALIZED NVBIT64(50)
// Indicate whether memdesc tracks the memory allocated from the scanout-carevout heap.
#define MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT NVBIT64(51)
// Force-compress pte kind when mapping with virtual pte kind
@@ -441,6 +443,9 @@ typedef struct ADDRESS_TRANSLATION_ *ADDRESS_TRANSLATION;
// Indicate if memdesc is allocated for non IO-coherent memory.
#define MEMDESC_FLAGS_NON_IO_COHERENT NVBIT64(54)
// Indicate if memdesc is tracking the uefi carveout memory.
#define MEMDESC_FLAGS_ALLOC_FROM_UEFI_CARVEOUT NVBIT64(55)
//
// RM internal allocations owner tags
// Total 200 tags are introduced, out of which some are already
@@ -1216,6 +1221,13 @@ NV_STATUS memdescFillMemdescForPhysAttr(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRA
NvBool memdescIsEgm(MEMORY_DESCRIPTOR *pMemDesc);
NvU64 memdescGetAdjustedPageSize(MEMORY_DESCRIPTOR *pMemDesc);
static inline NvBool
memdescIsCarveoutMemory(MEMORY_DESCRIPTOR *pMemDesc)
{
return !!(pMemDesc->_flags & (MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT |
MEMDESC_FLAGS_ALLOC_FROM_UEFI_CARVEOUT));
}
/*!
* @brief Get PTE kind
*

120
src/nvidia/generated/g_mem_mgr_nvoc.c
View File

@@ -541,14 +541,28 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, GpuHalsp
pThis->__memmgrInitFbRegions__ = &memmgrInitFbRegions_IMPL;
}
// memmgrAllocateConsoleRegion -- halified (2 hals) body
// memmgrAllocateConsoleRegion -- halified (4 hals) body
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
{
pThis->__memmgrAllocateConsoleRegion__ = &memmgrAllocateConsoleRegion_56cd7a;
}
else
{
pThis->__memmgrAllocateConsoleRegion__ = &memmgrAllocateConsoleRegion_IMPL;
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrAllocateConsoleRegion__ = &memmgrAllocateConsoleRegion_GB10B;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x71f0ffe0UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e6UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 */
{
pThis->__memmgrAllocateConsoleRegion__ = &memmgrAllocateConsoleRegion_GM107;
}
// default
else
{
pThis->__memmgrAllocateConsoleRegion__ = &memmgrAllocateConsoleRegion_56cd7a;
}
}
// memmgrScrubHandlePostSchedulingEnable -- halified (2 hals) body
@@ -1334,6 +1348,102 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, GpuHalsp
pThis->__memmgrGetFBEndReserveSizeEstimate__ = &memmgrGetFBEndReserveSizeEstimate_GM107;
}
// memmgrInitZeroFbRegionsHal -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrInitZeroFbRegionsHal__ = &memmgrInitZeroFbRegionsHal_GB10B;
}
// default
else
{
pThis->__memmgrInitZeroFbRegionsHal__ = &memmgrInitZeroFbRegionsHal_56cd7a;
}
// memmgrAllocScanoutCarveoutRegionResources -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrAllocScanoutCarveoutRegionResources__ = &memmgrAllocScanoutCarveoutRegionResources_GB10B;
}
// default
else
{
pThis->__memmgrAllocScanoutCarveoutRegionResources__ = &memmgrAllocScanoutCarveoutRegionResources_46f6a7;
}
// memmgrAllocFromScanoutCarveoutRegion -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrAllocFromScanoutCarveoutRegion__ = &memmgrAllocFromScanoutCarveoutRegion_GB10B;
}
// default
else
{
pThis->__memmgrAllocFromScanoutCarveoutRegion__ = &memmgrAllocFromScanoutCarveoutRegion_46f6a7;
}
// memmgrFreeScanoutCarveoutRegionResources -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrFreeScanoutCarveoutRegionResources__ = &memmgrFreeScanoutCarveoutRegionResources_GB10B;
}
// default
else
{
pThis->__memmgrFreeScanoutCarveoutRegionResources__ = &memmgrFreeScanoutCarveoutRegionResources_b3696a;
}
// memmgrFreeFromScanoutCarveoutRegion -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrFreeFromScanoutCarveoutRegion__ = &memmgrFreeFromScanoutCarveoutRegion_GB10B;
}
// default
else
{
pThis->__memmgrFreeFromScanoutCarveoutRegion__ = &memmgrFreeFromScanoutCarveoutRegion_b3696a;
}
// memmgrCreateScanoutCarveoutHeap -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrCreateScanoutCarveoutHeap__ = &memmgrCreateScanoutCarveoutHeap_GB10B;
}
// default
else
{
pThis->__memmgrCreateScanoutCarveoutHeap__ = &memmgrCreateScanoutCarveoutHeap_46f6a7;
}
// memmgrDestroyScanoutCarveoutHeap -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrDestroyScanoutCarveoutHeap__ = &memmgrDestroyScanoutCarveoutHeap_GB10B;
}
// default
else
{
pThis->__memmgrDestroyScanoutCarveoutHeap__ = &memmgrDestroyScanoutCarveoutHeap_46f6a7;
}
// memmgrDuplicateFromScanoutCarveoutRegion -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
{
pThis->__memmgrDuplicateFromScanoutCarveoutRegion__ = &memmgrDuplicateFromScanoutCarveoutRegion_GB10B;
}
// default
else
{
pThis->__memmgrDuplicateFromScanoutCarveoutRegion__ = &memmgrDuplicateFromScanoutCarveoutRegion_46f6a7;
}
// memmgrIsMemoryIoCoherent -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB20B | GB20C */
{
@@ -1380,13 +1490,13 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, GpuHalsp
{
pThis->__memmgrGetLocalizedMemorySupported__ = &memmgrGetLocalizedMemorySupported_3dd2c9;
}
} // End __nvoc_init_funcTable_MemoryManager_1 with approximately 175 basic block(s).
} // End __nvoc_init_funcTable_MemoryManager_1 with approximately 193 basic block(s).
// Initialize vtable(s) for 91 virtual method(s).
// Initialize vtable(s) for 99 virtual method(s).
void __nvoc_init_funcTable_MemoryManager(MemoryManager *pThis, GpuHalspecOwner *pGpuhalspecowner, RmHalspecOwner *pRmhalspecowner) {
// Initialize vtable(s) with 77 per-object function pointer(s).
// Initialize vtable(s) with 85 per-object function pointer(s).
__nvoc_init_funcTable_MemoryManager_1(pThis, pGpuhalspecowner, pRmhalspecowner);
}

147
src/nvidia/generated/g_mem_mgr_nvoc.h
View File

@@ -501,7 +501,6 @@ struct __nvoc_inner_struc_MemoryManager_2__ {
NvU64 minFBPSize;
NvU32 fbRegionPriority[16];
NvU64 ReservedConsoleDispMemSize;
PMEMORY_DESCRIPTOR pReservedConsoleMemDesc;
NvU32 lowerRangeMag;
NvU32 lowerRangeScale;
NvU32 middleRangeMag;
@@ -536,12 +535,12 @@ struct MemoryManager {
struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; // engstate super
struct MemoryManager *__nvoc_pbase_MemoryManager; // memmgr
// Vtable with 77 per-object function pointers
// Vtable with 85 per-object function pointers
NvU64 (*__memmgrDeterminePageSize__)(struct MemoryManager * /*this*/, NvHandle, NvU64, NvU32, NvU32, NvU32 *, NvU32 *); // halified (2 hals) body
NV_STATUS (*__memmgrFreeHwResources__)(OBJGPU *, struct MemoryManager * /*this*/, FB_ALLOC_INFO *); // halified (2 hals) body
NV_STATUS (*__memmgrCreateHeap__)(struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrInitFbRegions__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrAllocateConsoleRegion__)(OBJGPU *, struct MemoryManager * /*this*/, FB_REGION_DESCRIPTOR *); // halified (2 hals) body
NV_STATUS (*__memmgrAllocateConsoleRegion__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (4 hals) body
NV_STATUS (*__memmgrScrubHandlePostSchedulingEnable__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrScrubHandlePreSchedulingDisable__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrMemUtilsChannelInitialize__)(OBJGPU *, struct MemoryManager * /*this*/, OBJCHANNEL *); // halified (2 hals) body
@@ -610,6 +609,14 @@ struct MemoryManager {
NV_STATUS (*__memmgrGetBlackListPages__)(OBJGPU *, struct MemoryManager * /*this*/, BLACKLIST_ADDRESS *, NvU32 *); // halified (3 hals) body
NV_STATUS (*__memmgrDiscoverMIGPartitionableMemoryRange__)(OBJGPU *, struct MemoryManager * /*this*/, struct NV_RANGE *); // halified (2 hals) body
NvU32 (*__memmgrGetFBEndReserveSizeEstimate__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals)
NV_STATUS (*__memmgrInitZeroFbRegionsHal__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrAllocScanoutCarveoutRegionResources__)(struct MemoryManager * /*this*/, NV_MEMORY_ALLOCATION_PARAMS *, NvU32, NvU32 *, MEMORY_DESCRIPTOR *); // halified (2 hals) body
NV_STATUS (*__memmgrAllocFromScanoutCarveoutRegion__)(POBJGPU, struct MemoryManager * /*this*/, NvU32, NV_MEMORY_ALLOCATION_PARAMS *, NvU32 *, PMEMORY_DESCRIPTOR *); // halified (2 hals) body
void (*__memmgrFreeScanoutCarveoutRegionResources__)(struct MemoryManager * /*this*/, NvU64); // halified (2 hals) body
void (*__memmgrFreeFromScanoutCarveoutRegion__)(POBJGPU, struct MemoryManager * /*this*/, PMEMORY_DESCRIPTOR); // halified (2 hals) body
NV_STATUS (*__memmgrCreateScanoutCarveoutHeap__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrDestroyScanoutCarveoutHeap__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NV_STATUS (*__memmgrDuplicateFromScanoutCarveoutRegion__)(POBJGPU, struct MemoryManager * /*this*/, PMEMORY_DESCRIPTOR); // halified (2 hals) body
NvBool (*__memmgrIsMemoryIoCoherent__)(OBJGPU *, struct MemoryManager * /*this*/, NV_MEMORY_ALLOCATION_PARAMS *); // halified (2 hals) body
NvU8 (*__memmgrGetLocalizedOffset__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
NvBool (*__memmgrIsFlaSysmemSupported__)(OBJGPU *, struct MemoryManager * /*this*/); // halified (2 hals) body
@@ -619,6 +626,7 @@ struct MemoryManager {
// NvBool PDB_PROP_MEMMGR_IS_MISSING inherited from OBJENGSTATE
// Data members
OBJEHEAP *pScanoutHeap;
NvBool bFbsrWddmModeEnabled;
NvBool bFbRegionsSupported;
NvBool bPmaSupportedOnPlatform;
@@ -674,6 +682,7 @@ struct MemoryManager {
NvBool bDisableGlobalCeUtils;
OBJSCRUB eccScrubberState;
struct __nvoc_inner_struc_MemoryManager_2__ Ram;
PMEMORY_DESCRIPTOR pReservedConsoleMemDesc;
NvU32 PteKindOverride;
NvU32 zbcSurfaces;
NvU64 overrideInitHeapMin;
@@ -1110,12 +1119,12 @@ static inline NV_STATUS memmgrReserveVbiosVgaRegions(OBJGPU *pGpu, struct Memory
#endif // __nvoc_mem_mgr_h_disabled
#ifdef __nvoc_mem_mgr_h_disabled
static inline NV_STATUS memmgrReserveConsoleRegion(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg3) {
static inline NV_STATUS memmgrReserveConsoleRegion(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_mem_mgr_h_disabled
#define memmgrReserveConsoleRegion(pGpu, pMemoryManager, arg3) memmgrReserveConsoleRegion_56cd7a(pGpu, pMemoryManager, arg3)
#define memmgrReserveConsoleRegion(pGpu, pMemoryManager) memmgrReserveConsoleRegion_56cd7a(pGpu, pMemoryManager)
#endif // __nvoc_mem_mgr_h_disabled
void memmgrReleaseConsoleRegion_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
@@ -1727,7 +1736,7 @@ static inline NV_STATUS memmgrGetCarveoutRegionInfo(POBJGPU pGpu, struct MemoryM
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_mem_mgr_h_disabled
#define memmgrGetCarveoutRegionInfo(pGpu, pMemoryManager, pParams) memmgrGetCarveoutRegionInfo_56cd7a(pGpu, pMemoryManager, pParams)
#define memmgrGetCarveoutRegionInfo(pGpu, pMemoryManager, pParams) memmgrGetCarveoutRegionInfo_KERNEL(pGpu, pMemoryManager, pParams)
#endif // __nvoc_mem_mgr_h_disabled
@@ -1763,10 +1772,10 @@ static inline NV_STATUS memmgrGetCarveoutRegionInfo(POBJGPU pGpu, struct MemoryM
#define memmgrInitFbRegions(pGpu, pMemoryManager) memmgrInitFbRegions_DISPATCH(pGpu, pMemoryManager)
#define memmgrInitFbRegions_HAL(pGpu, pMemoryManager) memmgrInitFbRegions_DISPATCH(pGpu, pMemoryManager)
#define memmgrReserveVbiosVgaRegions_HAL(pGpu, pMemoryManager) memmgrReserveVbiosVgaRegions(pGpu, pMemoryManager)
#define memmgrReserveConsoleRegion_HAL(pGpu, pMemoryManager, arg3) memmgrReserveConsoleRegion(pGpu, pMemoryManager, arg3)
#define memmgrReserveConsoleRegion_HAL(pGpu, pMemoryManager) memmgrReserveConsoleRegion(pGpu, pMemoryManager)
#define memmgrAllocateConsoleRegion_FNPTR(pMemoryManager) pMemoryManager->__memmgrAllocateConsoleRegion__
#define memmgrAllocateConsoleRegion(pGpu, pMemoryManager, arg3) memmgrAllocateConsoleRegion_DISPATCH(pGpu, pMemoryManager, arg3)
#define memmgrAllocateConsoleRegion_HAL(pGpu, pMemoryManager, arg3) memmgrAllocateConsoleRegion_DISPATCH(pGpu, pMemoryManager, arg3)
#define memmgrAllocateConsoleRegion(pGpu, pMemoryManager) memmgrAllocateConsoleRegion_DISPATCH(pGpu, pMemoryManager)
#define memmgrAllocateConsoleRegion_HAL(pGpu, pMemoryManager) memmgrAllocateConsoleRegion_DISPATCH(pGpu, pMemoryManager)
#define memmgrGetKindComprForGpu_HAL(pMemoryManager, arg2, pGpu, offset, kind, pComprInfo) memmgrGetKindComprForGpu(pMemoryManager, arg2, pGpu, offset, kind, pComprInfo)
#define memmgrScrubInit_HAL(pGpu, pMemoryManager) memmgrScrubInit(pGpu, pMemoryManager)
#define memmgrScrubHandlePostSchedulingEnable_FNPTR(pMemoryManager) pMemoryManager->__memmgrScrubHandlePostSchedulingEnable__
@@ -2001,6 +2010,30 @@ static inline NV_STATUS memmgrGetCarveoutRegionInfo(POBJGPU pGpu, struct MemoryM
#define memmgrFreeFbsrMemory_HAL(pGpu, pMemoryManager) memmgrFreeFbsrMemory(pGpu, pMemoryManager)
#define memmgrReserveVgaWorkspaceMemDescForFbsr_HAL(pGpu, pMemoryManager) memmgrReserveVgaWorkspaceMemDescForFbsr(pGpu, pMemoryManager)
#define memmgrCalculateHeapOffsetWithGSP_HAL(pGpu, pMemoryManager, offset) memmgrCalculateHeapOffsetWithGSP(pGpu, pMemoryManager, offset)
#define memmgrInitZeroFbRegionsHal_FNPTR(pMemoryManager) pMemoryManager->__memmgrInitZeroFbRegionsHal__
#define memmgrInitZeroFbRegionsHal(pGpu, pMemoryManager) memmgrInitZeroFbRegionsHal_DISPATCH(pGpu, pMemoryManager)
#define memmgrInitZeroFbRegionsHal_HAL(pGpu, pMemoryManager) memmgrInitZeroFbRegionsHal_DISPATCH(pGpu, pMemoryManager)
#define memmgrAllocScanoutCarveoutRegionResources_FNPTR(pMemoryManager) pMemoryManager->__memmgrAllocScanoutCarveoutRegionResources__
#define memmgrAllocScanoutCarveoutRegionResources(pMemoryManager, pAllocData, owner, pHeapFlag, pMemDesc) memmgrAllocScanoutCarveoutRegionResources_DISPATCH(pMemoryManager, pAllocData, owner, pHeapFlag, pMemDesc)
#define memmgrAllocScanoutCarveoutRegionResources_HAL(pMemoryManager, pAllocData, owner, pHeapFlag, pMemDesc) memmgrAllocScanoutCarveoutRegionResources_DISPATCH(pMemoryManager, pAllocData, owner, pHeapFlag, pMemDesc)
#define memmgrAllocFromScanoutCarveoutRegion_FNPTR(pMemoryManager) pMemoryManager->__memmgrAllocFromScanoutCarveoutRegion__
#define memmgrAllocFromScanoutCarveoutRegion(pGpu, pMemoryManager, owner, pVidHeapAlloc, pHeapFlag, ppMemDesc) memmgrAllocFromScanoutCarveoutRegion_DISPATCH(pGpu, pMemoryManager, owner, pVidHeapAlloc, pHeapFlag, ppMemDesc)
#define memmgrAllocFromScanoutCarveoutRegion_HAL(pGpu, pMemoryManager, owner, pVidHeapAlloc, pHeapFlag, ppMemDesc) memmgrAllocFromScanoutCarveoutRegion_DISPATCH(pGpu, pMemoryManager, owner, pVidHeapAlloc, pHeapFlag, ppMemDesc)
#define memmgrFreeScanoutCarveoutRegionResources_FNPTR(pMemoryManager) pMemoryManager->__memmgrFreeScanoutCarveoutRegionResources__
#define memmgrFreeScanoutCarveoutRegionResources(pMemoryManager, base) memmgrFreeScanoutCarveoutRegionResources_DISPATCH(pMemoryManager, base)
#define memmgrFreeScanoutCarveoutRegionResources_HAL(pMemoryManager, base) memmgrFreeScanoutCarveoutRegionResources_DISPATCH(pMemoryManager, base)
#define memmgrFreeFromScanoutCarveoutRegion_FNPTR(pMemoryManager) pMemoryManager->__memmgrFreeFromScanoutCarveoutRegion__
#define memmgrFreeFromScanoutCarveoutRegion(pGpu, pMemoryManager, pMemDesc) memmgrFreeFromScanoutCarveoutRegion_DISPATCH(pGpu, pMemoryManager, pMemDesc)
#define memmgrFreeFromScanoutCarveoutRegion_HAL(pGpu, pMemoryManager, pMemDesc) memmgrFreeFromScanoutCarveoutRegion_DISPATCH(pGpu, pMemoryManager, pMemDesc)
#define memmgrCreateScanoutCarveoutHeap_FNPTR(pMemoryManager) pMemoryManager->__memmgrCreateScanoutCarveoutHeap__
#define memmgrCreateScanoutCarveoutHeap(pGpu, pMemoryManager) memmgrCreateScanoutCarveoutHeap_DISPATCH(pGpu, pMemoryManager)
#define memmgrCreateScanoutCarveoutHeap_HAL(pGpu, pMemoryManager) memmgrCreateScanoutCarveoutHeap_DISPATCH(pGpu, pMemoryManager)
#define memmgrDestroyScanoutCarveoutHeap_FNPTR(pMemoryManager) pMemoryManager->__memmgrDestroyScanoutCarveoutHeap__
#define memmgrDestroyScanoutCarveoutHeap(pGpu, pMemoryManager) memmgrDestroyScanoutCarveoutHeap_DISPATCH(pGpu, pMemoryManager)
#define memmgrDestroyScanoutCarveoutHeap_HAL(pGpu, pMemoryManager) memmgrDestroyScanoutCarveoutHeap_DISPATCH(pGpu, pMemoryManager)
#define memmgrDuplicateFromScanoutCarveoutRegion_FNPTR(pMemoryManager) pMemoryManager->__memmgrDuplicateFromScanoutCarveoutRegion__
#define memmgrDuplicateFromScanoutCarveoutRegion(pGpu, pMemoryManager, pMemDesc) memmgrDuplicateFromScanoutCarveoutRegion_DISPATCH(pGpu, pMemoryManager, pMemDesc)
#define memmgrDuplicateFromScanoutCarveoutRegion_HAL(pGpu, pMemoryManager, pMemDesc) memmgrDuplicateFromScanoutCarveoutRegion_DISPATCH(pGpu, pMemoryManager, pMemDesc)
#define memmgrGetCarveoutRegionInfo_HAL(pGpu, pMemoryManager, pParams) memmgrGetCarveoutRegionInfo(pGpu, pMemoryManager, pParams)
#define memmgrIsMemoryIoCoherent_FNPTR(pMemoryManager) pMemoryManager->__memmgrIsMemoryIoCoherent__
#define memmgrIsMemoryIoCoherent(pGpu, pMemoryManager, pAllocData) memmgrIsMemoryIoCoherent_DISPATCH(pGpu, pMemoryManager, pAllocData)
@@ -2076,8 +2109,8 @@ static inline NV_STATUS memmgrInitFbRegions_DISPATCH(OBJGPU *pGpu, struct Memory
return pMemoryManager->__memmgrInitFbRegions__(pGpu, pMemoryManager);
}
static inline NV_STATUS memmgrAllocateConsoleRegion_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg3) {
return pMemoryManager->__memmgrAllocateConsoleRegion__(pGpu, pMemoryManager, arg3);
static inline NV_STATUS memmgrAllocateConsoleRegion_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return pMemoryManager->__memmgrAllocateConsoleRegion__(pGpu, pMemoryManager);
}
static inline NV_STATUS memmgrScrubHandlePostSchedulingEnable_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
@@ -2352,6 +2385,38 @@ static inline NvU32 memmgrGetFBEndReserveSizeEstimate_DISPATCH(OBJGPU *pGpu, str
return pMemoryManager->__memmgrGetFBEndReserveSizeEstimate__(pGpu, pMemoryManager);
}
static inline NV_STATUS memmgrInitZeroFbRegionsHal_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return pMemoryManager->__memmgrInitZeroFbRegionsHal__(pGpu, pMemoryManager);
}
static inline NV_STATUS memmgrAllocScanoutCarveoutRegionResources_DISPATCH(struct MemoryManager *pMemoryManager, NV_MEMORY_ALLOCATION_PARAMS *pAllocData, NvU32 owner, NvU32 *pHeapFlag, MEMORY_DESCRIPTOR *pMemDesc) {
return pMemoryManager->__memmgrAllocScanoutCarveoutRegionResources__(pMemoryManager, pAllocData, owner, pHeapFlag, pMemDesc);
}
static inline NV_STATUS memmgrAllocFromScanoutCarveoutRegion_DISPATCH(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NvU32 owner, NV_MEMORY_ALLOCATION_PARAMS *pVidHeapAlloc, NvU32 *pHeapFlag, PMEMORY_DESCRIPTOR *ppMemDesc) {
return pMemoryManager->__memmgrAllocFromScanoutCarveoutRegion__(pGpu, pMemoryManager, owner, pVidHeapAlloc, pHeapFlag, ppMemDesc);
}
static inline void memmgrFreeScanoutCarveoutRegionResources_DISPATCH(struct MemoryManager *pMemoryManager, NvU64 base) {
pMemoryManager->__memmgrFreeScanoutCarveoutRegionResources__(pMemoryManager, base);
}
static inline void memmgrFreeFromScanoutCarveoutRegion_DISPATCH(POBJGPU pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR pMemDesc) {
pMemoryManager->__memmgrFreeFromScanoutCarveoutRegion__(pGpu, pMemoryManager, pMemDesc);
}
static inline NV_STATUS memmgrCreateScanoutCarveoutHeap_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return pMemoryManager->__memmgrCreateScanoutCarveoutHeap__(pGpu, pMemoryManager);
}
static inline NV_STATUS memmgrDestroyScanoutCarveoutHeap_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return pMemoryManager->__memmgrDestroyScanoutCarveoutHeap__(pGpu, pMemoryManager);
}
static inline NV_STATUS memmgrDuplicateFromScanoutCarveoutRegion_DISPATCH(POBJGPU pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR pMemDesc) {
return pMemoryManager->__memmgrDuplicateFromScanoutCarveoutRegion__(pGpu, pMemoryManager, pMemDesc);
}
static inline NvBool memmgrIsMemoryIoCoherent_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_MEMORY_ALLOCATION_PARAMS *pAllocData) {
return pMemoryManager->__memmgrIsMemoryIoCoherent__(pGpu, pMemoryManager, pAllocData);
}
@@ -2403,7 +2468,7 @@ static inline NV_STATUS memmgrReserveVbiosVgaRegions_56cd7a(OBJGPU *pGpu, struct
}
static inline NV_STATUS memmgrReserveConsoleRegion_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg3) {
static inline NV_STATUS memmgrReserveConsoleRegion_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return NV_OK;
}
@@ -2580,6 +2645,10 @@ static inline NV_STATUS memmgrCalculateHeapOffsetWithGSP_46f6a7(OBJGPU *pGpu, st
}
NV_STATUS memmgrGetCarveoutRegionInfo_KERNEL(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS *pParams);
NV_STATUS memmgrGetCarveoutRegionInfo_GB10B(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS *pParams);
static inline NV_STATUS memmgrGetCarveoutRegionInfo_56cd7a(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS *pParams) {
return NV_OK;
}
@@ -2625,11 +2694,13 @@ static inline NV_STATUS memmgrInitFbRegions_56cd7a(OBJGPU *pGpu, struct MemoryMa
NV_STATUS memmgrInitFbRegions_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
static inline NV_STATUS memmgrAllocateConsoleRegion_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg3) {
static inline NV_STATUS memmgrAllocateConsoleRegion_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return NV_OK;
}
NV_STATUS memmgrAllocateConsoleRegion_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg3);
NV_STATUS memmgrAllocateConsoleRegion_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
NV_STATUS memmgrAllocateConsoleRegion_GB10B(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
NV_STATUS memmgrScrubHandlePostSchedulingEnable_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
@@ -3087,6 +3158,54 @@ NvU32 memmgrGetFBEndReserveSizeEstimate_GB100(OBJGPU *pGpu, struct MemoryManager
NvU32 memmgrGetFBEndReserveSizeEstimate_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
NV_STATUS memmgrInitZeroFbRegionsHal_GB10B(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
static inline NV_STATUS memmgrInitZeroFbRegionsHal_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return NV_OK;
}
NV_STATUS memmgrAllocScanoutCarveoutRegionResources_GB10B(struct MemoryManager *pMemoryManager, NV_MEMORY_ALLOCATION_PARAMS *pAllocData, NvU32 owner, NvU32 *pHeapFlag, MEMORY_DESCRIPTOR *pMemDesc);
static inline NV_STATUS memmgrAllocScanoutCarveoutRegionResources_46f6a7(struct MemoryManager *pMemoryManager, NV_MEMORY_ALLOCATION_PARAMS *pAllocData, NvU32 owner, NvU32 *pHeapFlag, MEMORY_DESCRIPTOR *pMemDesc) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS memmgrAllocFromScanoutCarveoutRegion_GB10B(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NvU32 owner, NV_MEMORY_ALLOCATION_PARAMS *pVidHeapAlloc, NvU32 *pHeapFlag, PMEMORY_DESCRIPTOR *ppMemDesc);
static inline NV_STATUS memmgrAllocFromScanoutCarveoutRegion_46f6a7(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NvU32 owner, NV_MEMORY_ALLOCATION_PARAMS *pVidHeapAlloc, NvU32 *pHeapFlag, PMEMORY_DESCRIPTOR *ppMemDesc) {
return NV_ERR_NOT_SUPPORTED;
}
void memmgrFreeScanoutCarveoutRegionResources_GB10B(struct MemoryManager *pMemoryManager, NvU64 base);
static inline void memmgrFreeScanoutCarveoutRegionResources_b3696a(struct MemoryManager *pMemoryManager, NvU64 base) {
return;
}
void memmgrFreeFromScanoutCarveoutRegion_GB10B(POBJGPU pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR pMemDesc);
static inline void memmgrFreeFromScanoutCarveoutRegion_b3696a(POBJGPU pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR pMemDesc) {
return;
}
NV_STATUS memmgrCreateScanoutCarveoutHeap_GB10B(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
static inline NV_STATUS memmgrCreateScanoutCarveoutHeap_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS memmgrDestroyScanoutCarveoutHeap_GB10B(OBJGPU *pGpu, struct MemoryManager *pMemoryManager);
static inline NV_STATUS memmgrDestroyScanoutCarveoutHeap_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS memmgrDuplicateFromScanoutCarveoutRegion_GB10B(POBJGPU pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR pMemDesc);
static inline NV_STATUS memmgrDuplicateFromScanoutCarveoutRegion_46f6a7(POBJGPU pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR pMemDesc) {
return NV_ERR_NOT_SUPPORTED;
}
NvBool memmgrIsMemoryIoCoherent_GB20B(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_MEMORY_ALLOCATION_PARAMS *pAllocData);
static inline NvBool memmgrIsMemoryIoCoherent_88bc07(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_MEMORY_ALLOCATION_PARAMS *pAllocData) {

9
src/nvidia/generated/g_nv_name_released.h
View File

@@ -5416,6 +5416,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2941, 0x21ca, 0x10de, "NVIDIA GB200" },
{ 0x2B85, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090" },
{ 0x2B87, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 D" },
{ 0x2B8C, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 D V2" },
{ 0x2BB1, 0x204b, 0x1028, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
{ 0x2BB1, 0x204b, 0x103c, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
{ 0x2BB1, 0x204b, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
@@ -5437,6 +5438,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2C31, 0x2051, 0x103c, "NVIDIA RTX PRO 4500 Blackwell" },
{ 0x2C31, 0x2051, 0x10de, "NVIDIA RTX PRO 4500 Blackwell" },
{ 0x2C31, 0x2051, 0x17aa, "NVIDIA RTX PRO 4500 Blackwell" },
{ 0x2C33, 0x2053, 0x1028, "NVIDIA RTX PRO 4000 Blackwell SFF Edition" },
{ 0x2C33, 0x2053, 0x103c, "NVIDIA RTX PRO 4000 Blackwell SFF Edition" },
{ 0x2C33, 0x2053, 0x10de, "NVIDIA RTX PRO 4000 Blackwell SFF Edition" },
{ 0x2C33, 0x2053, 0x17aa, "NVIDIA RTX PRO 4000 Blackwell SFF Edition" },
{ 0x2C34, 0x2052, 0x1028, "NVIDIA RTX PRO 4000 Blackwell" },
{ 0x2C34, 0x2052, 0x103c, "NVIDIA RTX PRO 4000 Blackwell" },
{ 0x2C34, 0x2052, 0x10de, "NVIDIA RTX PRO 4000 Blackwell" },
@@ -5449,6 +5454,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2D05, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060" },
{ 0x2D18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D19, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },
{ 0x2D30, 0x2054, 0x1028, "NVIDIA RTX PRO 2000 Blackwell" },
{ 0x2D30, 0x2054, 0x103c, "NVIDIA RTX PRO 2000 Blackwell" },
{ 0x2D30, 0x2054, 0x10de, "NVIDIA RTX PRO 2000 Blackwell" },
{ 0x2D30, 0x2054, 0x17aa, "NVIDIA RTX PRO 2000 Blackwell" },
{ 0x2D39, 0x0000, 0x0000, "NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU" },
{ 0x2D58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },

1111
src/nvidia/generated/g_subdevice_nvoc.c
View File

File diff suppressed because it is too large Load Diff

12
src/nvidia/generated/g_subdevice_nvoc.h
View File

@@ -2932,6 +2932,16 @@ static inline NV_STATUS subdeviceCtrlCmdGpuGetCachedInfo(struct Subdevice *pSubd
#define subdeviceCtrlCmdGpuGetCachedInfo(pSubdevice, pGpuInfoParams) subdeviceCtrlCmdGpuGetCachedInfo_IMPL(pSubdevice, pGpuInfoParams)
#endif // __nvoc_subdevice_h_disabled
NV_STATUS subdeviceCtrlCmdGpuForceGspUnload_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS *pGpuInfoParams);
#ifdef __nvoc_subdevice_h_disabled
static inline NV_STATUS subdeviceCtrlCmdGpuForceGspUnload(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS *pGpuInfoParams) {
NV_ASSERT_FAILED_PRECOMP("Subdevice was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_subdevice_h_disabled
#define subdeviceCtrlCmdGpuForceGspUnload(pSubdevice, pGpuInfoParams) subdeviceCtrlCmdGpuForceGspUnload_IMPL(pSubdevice, pGpuInfoParams)
#endif // __nvoc_subdevice_h_disabled
NV_STATUS subdeviceCtrlCmdGpuGetInfoV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pGpuInfoParams);
#ifdef __nvoc_subdevice_h_disabled
static inline NV_STATUS subdeviceCtrlCmdGpuGetInfoV2(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pGpuInfoParams) {
@@ -7555,6 +7565,8 @@ NV_STATUS subdeviceCtrlCmdGrStaticGetFecsTraceDefines_IMPL(struct Subdevice *pSu
NV_STATUS subdeviceCtrlCmdGpuGetCachedInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pGpuInfoParams);
NV_STATUS subdeviceCtrlCmdGpuForceGspUnload_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS *pGpuInfoParams);
NV_STATUS subdeviceCtrlCmdGpuGetInfoV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pGpuInfoParams);
NV_STATUS subdeviceCtrlCmdGpuGetIpVersion_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS *pGpuIpVersionParams);

2
src/nvidia/generated/g_system_mem_nvoc.c
View File

@@ -487,8 +487,10 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info__SystemMemory =
/*pExportEntries=*/ __nvoc_exported_method_def_SystemMemory
};
void __nvoc_sysmemDestruct(SystemMemory*);
void __nvoc_dtor_StandardMemory(StandardMemory*);
void __nvoc_dtor_SystemMemory(SystemMemory *pThis) {
__nvoc_sysmemDestruct(pThis);
__nvoc_dtor_StandardMemory(&pThis->__nvoc_base_StandardMemory);
PORT_UNREFERENCED_VARIABLE(pThis);
}

3
src/nvidia/generated/g_system_mem_nvoc.h
View File

@@ -180,6 +180,9 @@ static inline NV_STATUS sysmemCtrlCmdGetSurfacePhysPages(struct SystemMemory *pS
#define sysmemCtrlCmdGetSurfacePhysPages(pStandardMemory, pParams) sysmemCtrlCmdGetSurfacePhysPages_IMPL(pStandardMemory, pParams)
#endif // __nvoc_system_mem_h_disabled
void sysmemDestruct_IMPL(struct SystemMemory *pSystemMemory);
#define __nvoc_sysmemDestruct(pSystemMemory) sysmemDestruct_IMPL(pSystemMemory)
// Wrapper macros for halified functions
#define sysmemInitAllocRequest_FNPTR(pSystemMemory) pSystemMemory->__sysmemInitAllocRequest__

1
src/nvidia/generated/g_system_nvoc.c
View File

@@ -116,6 +116,7 @@ void __nvoc_init_dataField_OBJSYS(OBJSYS *pThis) {
pThis->clientListDeferredFreeLimit = 0;
pThis->setProperty(pThis, PDB_PROP_SYS_RECOVERY_REBOOT_REQUIRED, NV_FALSE);
pThis->setProperty(pThis, PDB_PROP_SYS_SUPPORTS_S0IX, (0));
}
NV_STATUS __nvoc_ctor_Object(Object* );

5
src/nvidia/generated/g_system_nvoc.h
View File

@@ -430,7 +430,7 @@ struct OBJSYS {
struct OBJTRACEABLE *__nvoc_pbase_OBJTRACEABLE; // traceable super
struct OBJSYS *__nvoc_pbase_OBJSYS; // sys
// 35 PDB properties
// 36 PDB properties
NvBool PDB_PROP_SYS_SBIOS_NVIF_POWERMIZER_LIMIT;
NvBool PDB_PROP_SYS_MXM_THERMAL_CONTROL_PRESENT;
NvBool PDB_PROP_SYS_POWER_BATTERY;
@@ -466,6 +466,7 @@ struct OBJSYS {
NvBool PDB_PROP_SYS_DESTRUCTING;
NvBool PDB_PROP_SYS_ALLOW_UNKNOWN_4PART_IDS;
NvBool PDB_PROP_SYS_RECOVERY_REBOOT_REQUIRED;
NvBool PDB_PROP_SYS_SUPPORTS_S0IX;
// Data members
NvU32 apiLockMask;
@@ -619,6 +620,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJSYS;
#define PDB_PROP_SYS_ALLOW_UNKNOWN_4PART_IDS_BASE_NAME PDB_PROP_SYS_ALLOW_UNKNOWN_4PART_IDS
#define PDB_PROP_SYS_RECOVERY_REBOOT_REQUIRED_BASE_CAST
#define PDB_PROP_SYS_RECOVERY_REBOOT_REQUIRED_BASE_NAME PDB_PROP_SYS_RECOVERY_REBOOT_REQUIRED
#define PDB_PROP_SYS_SUPPORTS_S0IX_BASE_CAST
#define PDB_PROP_SYS_SUPPORTS_S0IX_BASE_NAME PDB_PROP_SYS_SUPPORTS_S0IX
NV_STATUS __nvoc_objCreateDynamic_OBJSYS(OBJSYS**, Dynamic*, NvU32, va_list);

1
src/nvidia/generated/rmconfig.h
View File

@@ -323,6 +323,7 @@
#define RMCFG_FEATURE_VBLANK_CALLBACK 1 // Vblank callback functionality within RM
#define RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY 1 // Tegra SOC NvDisplay Driver
#define RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY_MINIMAL 0 // Enable only those parts of display code which are needed for Tegra SOC NvDisplay Driver
#define RMCFG_FEATURE_TEGRA_SOC_SCANOUT_CARVEOUT 1 // Enable scanout carveout Tegra SOC NvDisplay Driver
#define RMCFG_FEATURE_HEAD_REGIONAL_CRC 1 // Display Head Regional CRC support
#define RMCFG_FEATURE_FEATURE_GH180 1 // RMconfig to encapsulate GH180 features
#define RMCFG_FEATURE_MIG_GFX 1 // RMconfig to encapsulate MIG With GFX support (SMG)