535.86.10

kernel-open/Kbuild

@@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
 EXTRA_CFLAGS += -I$(src)
 EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
 EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
-EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.86.05\"
+EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.86.10\"
 
 ifneq ($(SYSSRCHOST1X),)
  EXTRA_CFLAGS += -I$(SYSSRCHOST1X)

kernel-open/nvidia-uvm/uvm_channel.c

@@ -2703,7 +2703,15 @@ static void init_channel_manager_conf(uvm_channel_manager_t *manager)
     // access through the bus, because no cache coherence message is exchanged.
     if (uvm_gpu_is_coherent(gpu->parent)) {
         manager->conf.gpfifo_loc = UVM_BUFFER_LOCATION_SYS;
-        manager->conf.gpput_loc = UVM_BUFFER_LOCATION_SYS;
+
+        // On GPUs with limited ESCHED addressing range, e.g., Volta on P9, RM
+        // cannot guarantee that USERD/GPPUT physical address is accessible by
+        // ESCHED. We set GPPUT location to vidmem where physical addresses are
+        // all accessible by ESCHED. We use the max_host_va as a proxy for the
+        // PA limitation, since all architectures with 40b VA limits also have
+        // 40b PA limits.
+        manager->conf.gpput_loc = gpu->parent->max_host_va == (1ull << 40) ? UVM_BUFFER_LOCATION_VID :
+                                                                             UVM_BUFFER_LOCATION_SYS;
     }
     else {
         // By default we place GPFIFO and GPPUT on vidmem as it potentially has

kernel-open/nvidia/nvlink_export.h

@@ -46,11 +46,6 @@ NvlStatus nvlink_lib_unload(void);
 */
 NvlStatus nvlink_lib_ioctl_ctrl(nvlink_ioctrl_params *ctrl_params);
 
-/*
-* Gets number of devices with type deviceType
-*/
-NvlStatus nvlink_lib_return_device_count_by_type(NvU32 deviceType, NvU32 *numDevices);
-
 #ifdef __cplusplus
 }
 #endif