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535.86.10
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@@ -2703,7 +2703,15 @@ static void init_channel_manager_conf(uvm_channel_manager_t *manager)
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// access through the bus, because no cache coherence message is exchanged.
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if (uvm_gpu_is_coherent(gpu->parent)) {
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manager->conf.gpfifo_loc = UVM_BUFFER_LOCATION_SYS;
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manager->conf.gpput_loc = UVM_BUFFER_LOCATION_SYS;
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// On GPUs with limited ESCHED addressing range, e.g., Volta on P9, RM
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// cannot guarantee that USERD/GPPUT physical address is accessible by
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// ESCHED. We set GPPUT location to vidmem where physical addresses are
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// all accessible by ESCHED. We use the max_host_va as a proxy for the
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// PA limitation, since all architectures with 40b VA limits also have
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// 40b PA limits.
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manager->conf.gpput_loc = gpu->parent->max_host_va == (1ull << 40) ? UVM_BUFFER_LOCATION_VID :
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UVM_BUFFER_LOCATION_SYS;
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}
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else {
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// By default we place GPFIFO and GPPUT on vidmem as it potentially has
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