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580.105.08

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This commit is contained in:
Maneet Singh
2025-11-04 12:45:59 -08:00
parent 2b436058a6
commit 2af9f1f0f7
112 changed files with 56415 additions and 54596 deletions
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6
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -265,6 +265,12 @@ namespace DisplayPort
//
bool bHDMIOnDPPlusPlus;
//
// Flag to enable accounting available DP tunnelling BW while generating PPS
// for the mode
//
bool bOptimizeDscBppForTunnellingBw;
bool bSkipResetLinkStateDuringPlug;
// Flag to check if LT should be skipped.

4
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -106,6 +106,9 @@
// This regkey ensures DPLib takes into account Displayport++ supports HDMI.
#define NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS "HDMI_ON_DP_PLUS_PLUS"
// This regkey ensures DP IMP takes DP tunnelling BW into account while calculating DSC BPP
#define NV_DP_REGKEY_OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW "OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW"
#define NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC "DP_IGNORE_CAPS_AND_FORCE_HIGHEST_LC_WAR"
//
@@ -153,6 +156,7 @@ struct DP_REGKEY_DATABASE
bool bEnableDevId;
bool bHDMIOnDPPlusPlus;
bool bIgnoreCapsAndForceHighestLc;
bool bOptimizeDscBppForTunnellingBw;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;

22
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -199,6 +199,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bIgnoreCapsAndForceHighestLc = dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc;
this->bDisableEffBppSST8b10b = dpRegkeyDatabase.bDisableEffBppSST8b10b;
this->bHDMIOnDPPlusPlus = dpRegkeyDatabase.bHDMIOnDPPlusPlus;
this->bOptimizeDscBppForTunnellingBw = dpRegkeyDatabase.bOptimizeDscBppForTunnellingBw;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -1201,12 +1202,14 @@ bool ConnectorImpl::compoundQueryAttachTunneling(const DpModesetParams &modesetP
}
NvU64 bpp = modesetParams.modesetInfo.depth;
NvU32 dscFactor = 1U;
if (pDscParams->bEnableDsc)
{
bpp = divide_ceil(pDscParams->bitsPerPixelX16, 16);
dscFactor = 16U;
}
NvU64 modeBwRequired = modesetParams.modesetInfo.pixelClockHz * bpp;
NvU64 modeBwRequired = (modesetParams.modesetInfo.pixelClockHz * bpp)/dscFactor;
NvU64 freeTunnelingBw = allocatedDpTunnelBw - compoundQueryUsedTunnelingBw;
if (modeBwRequired > freeTunnelingBw)
@@ -1895,6 +1898,15 @@ bool ConnectorImpl::compoundQueryAttachSSTDsc
availableBandwidthBitsPerSecond = lc.convertMinRateToDataRate() * 8 * lc.lanes;
if (this-> bOptimizeDscBppForTunnellingBw && hal->isDpTunnelBwAllocationEnabled())
{
NvU64 freeTunnelingBw = allocatedDpTunnelBw - compoundQueryUsedTunnelingBw;
if (freeTunnelingBw < availableBandwidthBitsPerSecond)
{
availableBandwidthBitsPerSecond = freeTunnelingBw;
}
}
warData.dpData.linkRateHz = lc.peakRate;
warData.dpData.bIs128b132bChannelCoding = lc.bIs128b132bChannelCoding;
warData.dpData.bDisableEffBppSST8b10b = this->bDisableEffBppSST8b10b;
@@ -1960,6 +1972,7 @@ bool ConnectorImpl::compoundQueryAttachSSTDsc
{
pDscParams->bEnableDsc = true;
result = true;
pDscParams->bitsPerPixelX16 = bitsPerPixelX16;
if (pDscParams->pDscOutParams != NULL)
{
@@ -1968,7 +1981,6 @@ bool ConnectorImpl::compoundQueryAttachSSTDsc
// possible with DSC and calculated PPS and bits per pixel.
//
dpMemCopy(pDscParams->pDscOutParams->PPS, PPS, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD);
pDscParams->bitsPerPixelX16 = bitsPerPixelX16;
}
else
{
@@ -6793,7 +6805,9 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
// Some panels whose TCON erroneously sets DPCD 0x200 SINK_COUNT=0.
if (main->isEDP() && hal->getSinkCount() == 0)
{
hal->setSinkCount(1);
}
// disconnect all devices
for (ListElement * i = activeGroups.begin(); i != activeGroups.end(); i = i->next) {
@@ -7510,7 +7524,7 @@ void ConnectorImpl::notifyShortPulse()
bool ConnectorImpl::detectSinkCountChange()
{
if (this->linkUseMultistream())
if (this->linkUseMultistream() || main->isEDP())
return false;
DeviceImpl * existingDev = findDeviceInList(Address());

3
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -109,7 +109,8 @@ const struct
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS, &dpRegkeyDatabase.bHDMIOnDPPlusPlus, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC, &dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC, &dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW, &dpRegkeyDatabase.bOptimizeDscBppForTunnellingBw, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

44
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -125,7 +125,7 @@ void ConnectorImpl2x::applyOuiWARs()
bStuffDummySymbolsFor8b10b = true;
}
break;
}
}
@@ -513,16 +513,25 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
// LG
case 0xE430:
if (ProductID == 0x0469)
switch (ProductID)
{
//
// The LG display can't be driven at FHD with 2*RBR.
// Force max link config
//
this->WARFlags.forceMaxLinkConfig = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Force maximum link config WAR required on LG panel.");
DP_PRINTF(DP_NOTICE, "DP-WAR> bug 1649626");
break;
case 0x0469:
{
//
// The LG display can't be driven at FHD with 2*RBR.
// Force max link config
//
this->WARFlags.forceMaxLinkConfig = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Force maximum link config WAR required on LG panel.");
DP_PRINTF(DP_NOTICE, "DP-WAR> bug 1649626");
break;
}
case 0x06DB:
{
this->WARFlags.useLegacyAddress = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> LG eDP implements only Legacy interrupt address range");
break;
}
}
break;
case 0x8F34:
@@ -675,11 +684,18 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
}
break;
case 0xAC10:
if (ProductID == 0x42AD || ProductID == 0x42AC)
switch (ProductID)
{
this->WARFlags.bApplyStuffDummySymbolsWAR = true;
this->WARData.bStuffDummySymbolsFor128b132b = true;
this->WARData.bStuffDummySymbolsFor8b10b = false;
case 0x42AD:
case 0x42AC:
this->WARFlags.bApplyStuffDummySymbolsWAR = true;
this->WARData.bStuffDummySymbolsFor128b132b = true;
this->WARData.bStuffDummySymbolsFor8b10b = false;
break;
case 0xA21F:
this->WARFlags.bForceHeadShutdown = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Force head shutdown for Dell AW2524H.");
break;
}
break;
default:

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r581_36
#define NV_BUILD_BRANCH r581_66
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r581_36
#define NV_PUBLIC_BRANCH r581_66
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/r581_36-271"
#define NV_BUILD_CHANGELIST_NUM (36580581)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/r581_66-314"
#define NV_BUILD_CHANGELIST_NUM (36773567)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r580/r581_36-271"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36580581)
#define NV_BUILD_NAME "rel/gpu_drv/r580/r581_66-314"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36773567)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r581_36-3"
#define NV_BUILD_CHANGELIST_NUM (36570941)
#define NV_BUILD_BRANCH_VERSION "r581_66-7"
#define NV_BUILD_CHANGELIST_NUM (36773154)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "581.42"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36570941)
#define NV_BUILD_NAME "581.80"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36773154)
#define NV_BUILD_BRANCH_BASE_VERSION R580
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "580.95.05"
#define NV_VERSION_STRING "580.105.08"
#else

37
src/common/modeset/hdmipacket/nvhdmipkt_C671.c
View File

@@ -175,6 +175,7 @@ static NVHDMIPKT_RESULT SetFRLLinkRate(NVHDMIPKT_CLASS *pThis,
const NvU32 subDevice,
const NvU32 displayId,
const NvBool bFakeLt,
const NvBool bDoNotSkipLt,
const NvBool bLinkAssessmentOnly,
const NvU32 frlRate)
{
@@ -184,6 +185,7 @@ static NVHDMIPKT_RESULT SetFRLLinkRate(NVHDMIPKT_CLASS *pThis,
params.displayId = displayId;
params.data = frlRate;
params.bFakeLt = bFakeLt;
params.bDoNotSkipLt = bDoNotSkipLt;
params.bLinkAssessmentOnly = bLinkAssessmentOnly;
#if NVHDMIPKT_RM_CALLS_INTERNAL
@@ -275,14 +277,16 @@ performLinkTraningToAssessFRLLink(NVHDMIPKT_CLASS *pThis,
{
// If the display is active and the maximum link rate matches the link
// rate required for the current mode timings, avoid marking the set
// link configuration call as an assessment only. This prevents
// re-training after the assessment.
// link configuration call as an assessment only. This allows us to
// re-train the existing link now instead of after the assessment.
// In addition, do not allow link training to be skipped to ensure
// we succesfully recover an existing FRL config.
const NvBool bLinkAssessmentOnly =
bIsDisplayActive ? (nv0073currFRLRate != maxFRLRate) : NV_TRUE;
if (SetFRLLinkRate(pThis, subDevice, displayId,
NV_FALSE /* bFakeLt */, bLinkAssessmentOnly,
maxFRLRate) == NVHDMIPKT_SUCCESS)
NV_FALSE /* bFakeLt */, NV_TRUE /* bDoNotSkipLt */,
bLinkAssessmentOnly, maxFRLRate) == NVHDMIPKT_SUCCESS)
{
break;
}
@@ -299,11 +303,13 @@ performLinkTraningToAssessFRLLink(NVHDMIPKT_CLASS *pThis,
if (SetFRLLinkRate(pThis, subDevice, displayId,
bFakeLt, NV_FALSE /* bLinkAssessmentOnly */,
NV_FALSE /* bDoNotSkipLt */,
currFRLRate) != NVHDMIPKT_SUCCESS)
{
if (!bFakeLt) {
if (SetFRLLinkRate(pThis, subDevice, displayId,
NV_TRUE, NV_FALSE /* bLinkAssessmentOnly */,
NV_FALSE /* bDoNotSkipLt */,
currFRLRate) != NVHDMIPKT_SUCCESS) {
NvHdmiPkt_Assert(0);
}
@@ -1130,6 +1136,19 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
NvU32 bppMinX16Itr, bppMaxX16Itr;
NvBool bHasPreCalcFRLData = NV_FALSE;
NvBool forceFRLRateDSC = pClientCtrl->forceFRLRate;
HDMI_FRL_DATA_RATE requestedFRLRate = pClientCtrl->frlRate;
#if defined(NVHDMIPKT_NVKMS)
NvU32 rr = (pVidTransInfo->pTiming->pclk * (NvU64)10000) /
(pVidTransInfo->pTiming->HTotal * (NvU64)pVidTransInfo->pTiming->VTotal);
if (!pVidTransInfo->pTiming->interlaced && (rr >= 480)) {
forceFRLRateDSC = NV_TRUE;
requestedFRLRate = dscMaxFRLRate;
}
#endif
// DSC_All_bpp = 1:
// Lower the compression ratio better the pixel quality, hence a high bppTarget value will be ideal
// DSC_All_bpp = 1 allows us the flexibility to use a bppTarget setting different from the primary compressed format
@@ -1237,16 +1256,16 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
frlParams.compressionInfo.hSlices = NV_UNSIGNED_DIV_CEIL(pVidTransInfo->pTiming->HVisible, pClientCtrl->sliceWidth);
}
if (pClientCtrl->forceFRLRate)
if (forceFRLRateDSC)
{
if (pClientCtrl->frlRate > dscMaxFRLRate)
if (requestedFRLRate > dscMaxFRLRate)
{
result = NVHDMIPKT_FAIL;
goto frlQuery_fail;
}
minFRLRateItr = pClientCtrl->frlRate;
maxFRLRateItr = pClientCtrl->frlRate;
minFRLRateItr = requestedFRLRate;
maxFRLRateItr = requestedFRLRate;
}
if (pClientCtrl->forceBppx16)
@@ -1419,6 +1438,7 @@ hdmiSetFRLConfigC671(NVHDMIPKT_CLASS *pThis,
{
return SetFRLLinkRate(pThis, subDevice, displayId, bFakeLt,
NV_FALSE /* bLinkAssessmentOnly */,
NV_FALSE /* bDoNotSkipLt */,
translateFRLRateToNv0073SetHdmiFrlConfig(pFRLConfig->frlRate));
}
@@ -1432,6 +1452,7 @@ hdmiClearFRLConfigC671(NVHDMIPKT_CLASS *pThis,
{
return SetFRLLinkRate(pThis, subDevice, displayId,
NV_FALSE, NV_FALSE /* bLinkAssessmentOnly */,
NV_FALSE /* bDoNotSkipLt */,
NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE);
}

1
src/common/nvlink/inband/interface/nvlink_inband_msg.h
View File

@@ -84,6 +84,7 @@ typedef struct
#define NVLINK_INBAND_GPU_PROBE_CAPS_ATS_SUPPORT NVBIT(3)
#define NVLINK_INBAND_GPU_PROBE_CAPS_LINK_RETRAIN_SUPPORT NVBIT(4)
#define NVLINK_INBAND_GPU_PROBE_CAPS_HEALTH_SUMMARY NVBIT(6)
#define NVLINK_INBAND_GPU_PROBE_CAPS_MC_RETRY NVBIT(8)
/* Add more caps as need in the future */

1
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
View File

@@ -1377,6 +1377,7 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS {
NvU32 displayId;
NvU32 data;
NvBool bFakeLt;
NvBool bDoNotSkipLt;
NvBool bLtSkipped;
NvBool bLinkAssessmentOnly;
} NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS;

25
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
View File

@@ -564,6 +564,31 @@ typedef struct NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS {
/*
* NV2080_CTRL_CMD_FIFO_CONFIG_CTXSW_TIMEOUT
*
* This command can be used to enable and set the engine
* context switch timeout
*
* timeout: Timeout in number of microsec PTIMER ticks
* 1 microsec PTIMER tick = 1024 PTIMER nanoseconds
* bEnable: TRUE/FALSE
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FIFO_CONFIG_CTXSW_TIMEOUT (0x20801110) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS {
NvU32 timeout;
NvBool bEnable;
} NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE
*

3
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -165,7 +165,8 @@
#define ROBUST_CHANNEL_UNUSED_ERROR_170 (170)
#define UNCORRECTABLE_DRAM_ERROR (171)
#define UNCORRECTABLE_SRAM_ERROR (172)
#define ROBUST_CHANNEL_LAST_ERROR (172)
#define C2C_FATAL_LINK_FAILURE (173)
#define ROBUST_CHANNEL_LAST_ERROR (173)
// Indexed CE reference
#define ROBUST_CHANNEL_CE_ERROR(x) \

1
src/common/sdk/nvidia/inc/nvstatuscodes.h
View File

@@ -165,6 +165,7 @@ NV_STATUS_CODE(NV_ERR_FABRIC_STATE_OUT_OF_SYNC, 0x00000087, "NVLink fabri
NV_STATUS_CODE(NV_ERR_BUFFER_FULL, 0x00000088, "Buffer is full")
NV_STATUS_CODE(NV_ERR_BUFFER_EMPTY, 0x00000089, "Buffer is empty")
NV_STATUS_CODE(NV_ERR_MC_FLA_OFFSET_TABLE_FULL, 0x0000008A, "Multicast FLA offset table has no available slots")
NV_STATUS_CODE(NV_ERR_DMA_XFER_FAILED, 0x0000008B, "DMA transfer failed")
// Warnings:
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")

3
src/common/shared/inc/detect-self-hosted.h
View File

@@ -32,7 +32,8 @@ static inline int pci_devid_is_self_hosted_hopper(unsigned short devid)
static inline int pci_devid_is_self_hosted_blackwell(unsigned short devid)
{
return (devid >= 0x2940 && devid <= 0x297f) // GB100 Self-Hosted
|| (devid >= 0x31c0 && devid <= 0x31ff); // GB110 Self-Hosted
|| (devid >= 0x31c0 && devid <= 0x31ff) // GB110 Self-Hosted
|| (devid == 0x31a1); //
}
static inline int pci_devid_is_self_hosted(unsigned short devid)

4
src/common/shared/msgq/inc/msgq/msgq.h
View File

@@ -68,8 +68,8 @@ typedef void (*msgqFcnBarrier)(void);
// Function to access backend memory (if it's not memory mapped).
// Keep in mind than when using it, pointers given by peek can't be trusted
// Should return 0 on success.
typedef int (*msgqFcnBackendRw)(void *pDest, const void *pSrc, unsigned size,
unsigned flags, void *pArg);
typedef unsigned (*msgqFcnBackendRw)(void *pDest, const void *pSrc, unsigned size,
unsigned flags, void *pArg);
/**
* @brief Return size of metadata (that must be allocated)

112
src/common/shared/msgq/msgq.c
View File

@@ -104,35 +104,45 @@ msgqSetBarrier(msgqHandle handle, msgqFcnBarrier fcn)
/*
* Helper functions to access indirect backend.
*/
sysSHARED_CODE static void
// TODO: Make these funcions return NV_STATUS instead of int wherever possible.
sysSHARED_CODE static int
_backendRead32(msgqMetadata *pQueue, volatile const void *pAddr, NvU32 *pVal, unsigned flags)
{
if (pQueue->fcnBackendRw != NULL)
{
pQueue->fcnBackendRw(pVal, (const void *)pAddr, sizeof(*pVal),
flags | FCN_FLAG_BACKEND_ACCESS_READ,
pQueue->fcnBackendRwArg);
int status = pQueue->fcnBackendRw(pVal, (const void *)pAddr, sizeof(*pVal),
flags | FCN_FLAG_BACKEND_ACCESS_READ,
pQueue->fcnBackendRwArg);
if (status != 0)
{
return -1;
}
}
else
{
*pVal = *(volatile const NvU32*)pAddr;
}
return 0;
}
sysSHARED_CODE static void
sysSHARED_CODE static int
_backendWrite32(msgqMetadata *pQueue, volatile void *pAddr, NvU32 *pVal, unsigned flags)
{
if (pQueue->fcnBackendRw != NULL)
{
pQueue->fcnBackendRw((void*)pAddr, pVal, sizeof(*pVal),
flags | FCN_FLAG_BACKEND_ACCESS_WRITE,
pQueue->fcnBackendRwArg);
int status = pQueue->fcnBackendRw((void*)pAddr, pVal, sizeof(*pVal),
flags | FCN_FLAG_BACKEND_ACCESS_WRITE,
pQueue->fcnBackendRwArg);
if (status != 0)
{
return -1;
}
}
else
{
*(volatile NvU32*)pAddr = *pVal;
}
return 0;
}
/**
@@ -142,7 +152,7 @@ _backendWrite32(msgqMetadata *pQueue, volatile void *pAddr, NvU32 *pVal, unsigne
sysSHARED_CODE static void
msgqRiscvDefaultBarrier(void)
{
asm volatile("fence iorw,iorw");
__asm__ volatile("fence iorw,iorw");
}
#endif
@@ -188,6 +198,7 @@ msgqTxCreate
{
msgqMetadata *pQueue = (msgqMetadata*)handle;
msgqTxHeader *pTx;
int status;
if ((pQueue == NULL) || pQueue->txLinked)
{
@@ -282,10 +293,15 @@ msgqTxCreate
// Indirect access to backend
if (pQueue->fcnBackendRw != NULL)
{
pQueue->fcnBackendRw(pTx, &pQueue->tx, sizeof *pTx,
FCN_FLAG_BACKEND_ACCESS_WRITE | FCN_FLAG_BACKEND_QUEUE_TX,
pQueue->fcnBackendRwArg);
} else
status = pQueue->fcnBackendRw(pTx, &pQueue->tx, sizeof *pTx,
FCN_FLAG_BACKEND_ACCESS_WRITE | FCN_FLAG_BACKEND_QUEUE_TX,
pQueue->fcnBackendRwArg);
if (status != 0)
{
return -1;
}
}
else
{
memcpy(pTx, &pQueue->tx, sizeof *pTx);
}
@@ -315,6 +331,7 @@ sysSHARED_CODE int
msgqRxLink(msgqHandle handle, const void *pBackingStore, unsigned size, unsigned msgSize)
{
msgqMetadata *pQueue = (msgqMetadata*)handle;
int status;
if ((pQueue == NULL) || pQueue->rxLinked)
{
@@ -347,10 +364,14 @@ msgqRxLink(msgqHandle handle, const void *pBackingStore, unsigned size, unsigned
// copy their metadata
if (pQueue->fcnBackendRw != NULL)
{
pQueue->fcnBackendRw(&pQueue->rx, (const void *)pQueue->pTheirTxHdr,
sizeof pQueue->rx,
FCN_FLAG_BACKEND_ACCESS_READ | FCN_FLAG_BACKEND_QUEUE_RX,
pQueue->fcnBackendRwArg);
status = pQueue->fcnBackendRw(&pQueue->rx, (const void *)pQueue->pTheirTxHdr,
sizeof pQueue->rx,
FCN_FLAG_BACKEND_ACCESS_READ | FCN_FLAG_BACKEND_QUEUE_RX,
pQueue->fcnBackendRwArg);
if (status != 0)
{
return -11;
}
}
else
{
@@ -413,8 +434,13 @@ msgqRxLink(msgqHandle handle, const void *pBackingStore, unsigned size, unsigned
}
pQueue->rxReadPtr = 0;
_backendWrite32(pQueue, pQueue->pReadOutgoing, &pQueue->rxReadPtr,
pQueue->rxSwapped ? FCN_FLAG_BACKEND_QUEUE_TX : FCN_FLAG_BACKEND_QUEUE_RX);
status = _backendWrite32(pQueue, pQueue->pReadOutgoing, &pQueue->rxReadPtr,
pQueue->rxSwapped ? FCN_FLAG_BACKEND_QUEUE_TX : FCN_FLAG_BACKEND_QUEUE_RX);
if (status != 0)
{
return -12;
}
if (pQueue->fcnFlush != NULL)
{
pQueue->fcnFlush(pQueue->pReadOutgoing, sizeof(NvU32));
@@ -451,8 +477,12 @@ msgqTxGetFreeSpace(msgqHandle handle)
return 0;
}
_backendRead32(pQueue, pQueue->pReadIncoming, &pQueue->txReadPtr,
pQueue->rxSwapped ? FCN_FLAG_BACKEND_QUEUE_RX : FCN_FLAG_BACKEND_QUEUE_TX);
if (_backendRead32(pQueue, pQueue->pReadIncoming, &pQueue->txReadPtr,
pQueue->rxSwapped ? FCN_FLAG_BACKEND_QUEUE_RX : FCN_FLAG_BACKEND_QUEUE_TX) != 0)
{
return 0;
}
if (pQueue->txReadPtr >= pQueue->tx.msgCount)
{
return 0;
@@ -505,6 +535,7 @@ sysSHARED_CODE int
msgqTxSubmitBuffers(msgqHandle handle, unsigned n)
{
msgqMetadata *pQueue = (msgqMetadata*)handle;
int status;
if ((pQueue == NULL) || !pQueue->txLinked)
{
@@ -531,8 +562,19 @@ msgqTxSubmitBuffers(msgqHandle handle, unsigned n)
pQueue->tx.writePtr -= pQueue->tx.msgCount;
}
_backendWrite32(pQueue, pQueue->pWriteOutgoing,
&pQueue->tx.writePtr, FCN_FLAG_BACKEND_QUEUE_TX);
status = _backendWrite32(pQueue, pQueue->pWriteOutgoing,
&pQueue->tx.writePtr, FCN_FLAG_BACKEND_QUEUE_TX);
if (status != 0)
{
// restore write pointer
if (pQueue->tx.writePtr < n)
{
pQueue->tx.writePtr += pQueue->tx.msgCount;
}
pQueue->tx.writePtr -= n;
return -2;
}
// Adjust cached value for number of free elements.
pQueue->txFree -= n;
@@ -606,7 +648,11 @@ msgqRxGetReadAvailable(msgqHandle handle)
return 0;
}
_backendRead32(pQueue, pQueue->pWriteIncoming, &pQueue->rx.writePtr, FCN_FLAG_BACKEND_QUEUE_RX);
if (_backendRead32(pQueue, pQueue->pWriteIncoming, &pQueue->rx.writePtr, FCN_FLAG_BACKEND_QUEUE_RX) != 0)
{
return 0;
}
if (pQueue->rx.writePtr >= pQueue->rx.msgCount)
{
return 0;
@@ -659,6 +705,7 @@ sysSHARED_CODE int
msgqRxMarkConsumed(msgqHandle handle, unsigned n)
{
msgqMetadata *pQueue = (msgqMetadata*)handle;
int status;
if ((pQueue == NULL) || !pQueue->rxLinked)
{
@@ -679,8 +726,19 @@ msgqRxMarkConsumed(msgqHandle handle, unsigned n)
}
// Copy to backend
_backendWrite32(pQueue, pQueue->pReadOutgoing, &pQueue->rxReadPtr,
pQueue->rxSwapped ? FCN_FLAG_BACKEND_QUEUE_TX : FCN_FLAG_BACKEND_QUEUE_RX);
status = _backendWrite32(pQueue, pQueue->pReadOutgoing, &pQueue->rxReadPtr,
pQueue->rxSwapped ? FCN_FLAG_BACKEND_QUEUE_TX : FCN_FLAG_BACKEND_QUEUE_RX);
if (status != 0)
{
// restore read pointer
if (pQueue->rxReadPtr < n)
{
pQueue->rxReadPtr += pQueue->rx.msgCount;
}
pQueue->rxReadPtr -= n;
return -2;
}
// Adjust cached value for number of available elements.
pQueue->rxAvail -= n;