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580.95.05

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This commit is contained in:
Maneet Singh
2025-09-30 12:52:14 -07:00
parent 87c0b12473
commit 2b436058a6
147 changed files with 56986 additions and 55176 deletions
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8
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -259,6 +259,12 @@ namespace DisplayPort
// Flag to check if the system is UEFI.
bool bIsUefiSystem;
//
// Flag to ensure we take into account that
// Displayport++ supports HDMI as well.
//
bool bHDMIOnDPPlusPlus;
bool bSkipResetLinkStateDuringPlug;
// Flag to check if LT should be skipped.
@@ -342,6 +348,8 @@ namespace DisplayPort
//
NvU32 LT2FecLatencyMs;
bool bIgnoreCapsAndForceHighestLc;
// On eDP, do not cache the source OUI if it reads 0. See bug 4793112
bool bSkipZeroOuiCache;

6
src/common/displayport/inc/dp_hostimp.h
View File

@@ -39,7 +39,11 @@ extern "C" void dpFree(void * ptr);
extern "C" void dpDebugBreakpoint();
// Note: dpPrint() implementations are expected to append a newline themselves.
extern "C" void dpPrint(const char * formatter, ...);
extern "C" void dpPrintf(DP_LOG_LEVEL severity, const char * formatter, ...);
extern "C" void dpPrintf(DP_LOG_LEVEL severity, const char * formatter, ...)
#if defined(__GNUC__)
__attribute__ ((format (printf, 2, 3)))
#endif
;
extern "C" void dpTraceEvent(NV_DP_TRACING_EVENT event,
NV_DP_TRACING_PRIORITY priority, NvU32 numArgs, ...);

2
src/common/displayport/inc/dp_linkconfig.h
View File

@@ -42,6 +42,8 @@ extern NvU32 bSupportInternalUhbrOnFpga;
namespace DisplayPort
{
typedef NvU64 LinkRate;
#define LinkRate_fmtx NvU64_fmtx
#define LinkRate_fmtu NvU64_fmtu
class LinkRates : virtual public Object
{

4
src/common/displayport/inc/dp_printf.h
View File

@@ -43,10 +43,6 @@ typedef enum
DP_FATAL,
} DP_LOG_LEVEL;
#if defined(_DEBUG) || defined(DEBUG)
#define DP_PRINTF(severity, format, ...) dpPrintf(severity, format, ##__VA_ARGS__)
#else
#define DP_PRINTF(severity, format, ...)
#endif // _DEBUG || DEBUG
#endif // INCLUDED_DP_PRINTF_H

7
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -103,6 +103,11 @@
// This regkey forces devID to be exposed to vendors via DPCD 0x309 for DSC-enabled SKUs.
#define NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR "DP_DSC_DEVID_WAR"
// This regkey ensures DPLib takes into account Displayport++ supports HDMI.
#define NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS "HDMI_ON_DP_PLUS_PLUS"
#define NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC "DP_IGNORE_CAPS_AND_FORCE_HIGHEST_LC_WAR"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -146,6 +151,8 @@ struct DP_REGKEY_DATABASE
bool bEnable5147205Fix;
bool bForceHeadShutdown;
bool bEnableDevId;
bool bHDMIOnDPPlusPlus;
bool bIgnoreCapsAndForceHighestLc;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;

2
src/common/displayport/src/dp_configcaps2x.cpp
View File

@@ -616,7 +616,7 @@ void DPCDHALImpl2x::overrideCableIdCap(LinkRate linkRate, bool bEnable)
caps2x.rxCableCaps .bUHBR_10GSupported = bEnable;
break;
default:
DP_PRINTF(DP_ERROR, "DPHAL> Invalid link rate (%d) to override.", linkRate);
DP_PRINTF(DP_ERROR, "DPHAL> Invalid link rate (%" LinkRate_fmtu ") to override.", linkRate);
}
}

59
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -196,7 +196,9 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bSkipZeroOuiCache = dpRegkeyDatabase.bSkipZeroOuiCache;
this->bForceHeadShutdownFromRegkey = dpRegkeyDatabase.bForceHeadShutdown;
this->bEnableDevId = dpRegkeyDatabase.bEnableDevId;
this->bIgnoreCapsAndForceHighestLc = dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc;
this->bDisableEffBppSST8b10b = dpRegkeyDatabase.bDisableEffBppSST8b10b;
this->bHDMIOnDPPlusPlus = dpRegkeyDatabase.bHDMIOnDPPlusPlus;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -410,7 +412,16 @@ void ConnectorImpl::processNewDevice(const DiscoveryManager::Device & device,
{
case DISPLAY_PORT:
case DISPLAY_PORT_PLUSPLUS: // DP port that supports DP and TMDS
connector = connectorDisplayPort;
if (bHDMIOnDPPlusPlus &&
existingDev &&
existingDev->connectorType == connectorHDMI)
{
connector = connectorHDMI;
}
else
{
connector = connectorDisplayPort;
}
break;
case ANALOG_VGA:
@@ -2531,11 +2542,11 @@ void ConnectorImpl::fireEventsInternal()
if (dev->complianceDeviceEdidReadTest)
{
// the zombie event will be hidden for DD/OS
DP_PRINTF(DP_WARNING, "DPCONN> Compliance: Device Internal Zombie? : %d 0x%x", dev->shadow.zombie ? 1 : 0, dev);
DP_PRINTF(DP_WARNING, "DPCONN> Compliance: Device Internal Zombie? : %d %p", dev->shadow.zombie ? 1 : 0, dev);
return;
}
bMitigateZombie = false;
DP_PRINTF(DP_WARNING, "DPCONN> Zombie? : %d 0x%x", dev->shadow.zombie ? 1 : 0, dev);
DP_PRINTF(DP_WARNING, "DPCONN> Zombie? : %d %p", dev->shadow.zombie ? 1 : 0, dev);
sink->notifyZombieStateChange(dev, dev->shadow.zombie);
}
@@ -2600,7 +2611,7 @@ void ConnectorImpl::fireEventsInternal()
{
// If yes, then we need to report this lost device first.
_device->shadow.plugged = false;
DP_PRINTF(DP_WARNING, "DPCONN> Lost device 0x%x", _device);
DP_PRINTF(DP_WARNING, "DPCONN> Lost device %p", _device);
sink->lostDevice(_device);
DP_ASSERT(!_device->activeGroup && "DD didn't remove panel from group");
delete _device;
@@ -3253,7 +3264,7 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr
}
}
DP_PRINTF(DP_NOTICE, "DPCONN> Notify Attach Begin (Head %d, pclk %d raster %d x %d %d bpp)",
DP_PRINTF(DP_NOTICE, "DPCONN> Notify Attach Begin (Head %d, pclk %" NvU64_fmtu " raster %d x %d %d bpp)",
modesetParams.headIndex, pixelClockHz, rasterWidth, rasterHeight, depth);
NV_DPTRACE_INFO(NOTIFY_ATTACH_BEGIN, modesetParams.headIndex, pixelClockHz, rasterWidth, rasterHeight,
depth, bEnableDsc, bEnableFEC);
@@ -4202,7 +4213,7 @@ bool ConnectorImpl::allocateDpTunnelBw(NvU64 bandwidth)
return false;
}
DP_PRINTF(DP_INFO, "Estimated BW: %d Mbps, Requested BW: %d Mbps",
DP_PRINTF(DP_INFO, "Estimated BW: %" NvU64_fmtu " Mbps, Requested BW: %" NvU64_fmtu " Mbps",
((NvU64) estimatedBw * 1000) / (NvU64) granularityMultiplier,
bandwidth / (1000 * 1000));
@@ -4242,7 +4253,7 @@ bool ConnectorImpl::allocateDpTunnelBw(NvU64 bandwidth)
return false;
}
DP_PRINTF(DP_INFO, "Failed to get requested BW, requesting updated Estimated BW: %d\n",
DP_PRINTF(DP_INFO, "Failed to get requested BW, requesting updated Estimated BW: %" NvU64_fmtu "\n",
((NvU64) estimatedBw * 1000) / (NvU64) granularityMultiplier);
requestBw = estimatedBw;
@@ -4262,7 +4273,7 @@ bool ConnectorImpl::allocateDpTunnelBw(NvU64 bandwidth)
// Convert this back to bps and record the allocated BW
this->allocatedDpTunnelBw = ((NvU64) requestBw * 1000 * 1000 * 1000) / (NvU64) granularityMultiplier;
this->allocatedDpTunnelBwShadow = 0;
DP_PRINTF(DP_INFO, "Allocated BW: %d Mbps", this->allocatedDpTunnelBw / (1000 * 1000));
DP_PRINTF(DP_INFO, "Allocated BW: %" NvU64_fmtu " Mbps", this->allocatedDpTunnelBw / (1000 * 1000));
}
return requestStatus;
@@ -4278,7 +4289,7 @@ bool ConnectorImpl::allocateMaxDpTunnelBw()
NvU64 bandwidth = getMaxTunnelBw();
if (!allocateDpTunnelBw(bandwidth))
{
DP_PRINTF(DP_ERROR, "Failed to allocate DP Tunnel BW. Requested BW: %d Mbps",
DP_PRINTF(DP_ERROR, "Failed to allocate DP Tunnel BW. Requested BW: %" NvU64_fmtu " Mbps",
bandwidth / (1000 * 1000));
return false;
}
@@ -4553,7 +4564,7 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType)
else
{
DP_PRINTF(DP_WARNING,
"DP> assessLink(): Failed to reach max link configuration (%d x %d).",
"DP> assessLink(): Failed to reach max link configuration (%d x %" LinkRate_fmtu ").",
lConfig.lanes, lConfig.peakRate);
}
}
@@ -5627,13 +5638,13 @@ bool ConnectorImpl::validateLinkConfiguration(const LinkConfiguration & lConfig)
{
if (!IS_VALID_LINKBW_10M(linkRate10M))
{
DP_PRINTF(DP_ERROR, "DPCONN> Requested link rate=%d is not valid", linkRate10M);
DP_PRINTF(DP_ERROR, "DPCONN> Requested link rate=%" NvU64_fmtu " is not valid", linkRate10M);
return false;
}
if (linkRate10M > hal->getMaxLinkRate())
{
DP_PRINTF(DP_ERROR, "DPCONN> Requested link rate=%d is larger than sinkMaxLinkRate=%d",
DP_PRINTF(DP_ERROR, "DPCONN> Requested link rate=%" NvU64_fmtu " is larger than sinkMaxLinkRate=%" NvU64_fmtu,
linkRate10M, hal->getMaxLinkRate());
return false;
}
@@ -5644,7 +5655,7 @@ bool ConnectorImpl::validateLinkConfiguration(const LinkConfiguration & lConfig)
NvU32 i;
if (!hal->isIndexedLinkrateEnabled())
{
DP_PRINTF(DP_ERROR, "DPCONN> Indexed Link Rate=%d is Not Enabled in Sink", linkRate10M);
DP_PRINTF(DP_ERROR, "DPCONN> Indexed Link Rate=%" NvU64_fmtu " is Not Enabled in Sink", linkRate10M);
return false;
}
@@ -5659,14 +5670,14 @@ bool ConnectorImpl::validateLinkConfiguration(const LinkConfiguration & lConfig)
break;
if (ilrTable[i] == 0)
{
DP_PRINTF(DP_ERROR, "DPCONN> Indexed Link Rate=%d is Not Found", linkRate10M);
DP_PRINTF(DP_ERROR, "DPCONN> Indexed Link Rate=%" NvU64_fmtu " is Not Found", linkRate10M);
return false;
}
}
if (i == NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES)
{
DP_PRINTF(DP_ERROR, "DPCONN> Indexed Link Rate=%d is Not Found", linkRate10M);
DP_PRINTF(DP_ERROR, "DPCONN> Indexed Link Rate=%" NvU64_fmtu " is Not Found", linkRate10M);
return false;
}
}
@@ -5687,6 +5698,12 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
return false;
}
if (this->bIgnoreCapsAndForceHighestLc)
{
force = true;
hal->setPowerState(PowerStateD3);
}
//
// Cancel pending HDCP authentication callbacks if have or may interrupt
// active link training that violates spec.
@@ -6702,19 +6719,19 @@ bool ConnectorImpl::updateDpTunnelBwAllocation()
connectorTunnelBw += devMaxModeBwRequired;
}
DP_PRINTF(DP_INFO, "Required Connector Tunnel BW: %d Mbps", connectorTunnelBw / (1000 * 1000));
DP_PRINTF(DP_INFO, "Required Connector Tunnel BW: %" NvU64_fmtu " Mbps", connectorTunnelBw / (1000 * 1000));
NvU64 maxTunnelBw = getMaxTunnelBw();
if (connectorTunnelBw > maxTunnelBw)
{
DP_PRINTF(DP_INFO, "Requested connector tunnel BW is larger than max Tunnel BW of %d Mbps. Overriding Max Tunnel BW\n",
DP_PRINTF(DP_INFO, "Requested connector tunnel BW is larger than max Tunnel BW of %" NvU64_fmtu " Mbps. Overriding Max Tunnel BW\n",
maxTunnelBw / (1000 * 1000));
connectorTunnelBw = maxTunnelBw;
}
if (!allocateDpTunnelBw(connectorTunnelBw))
{
DP_PRINTF(DP_ERROR, "Failed to allocate Dp Tunnel BW: %d Mbps", connectorTunnelBw / (1000 * 1000));
DP_PRINTF(DP_ERROR, "Failed to allocate Dp Tunnel BW: %" NvU64_fmtu " Mbps", connectorTunnelBw / (1000 * 1000));
return false;
}
return true;
@@ -7537,7 +7554,7 @@ bool ConnectorImpl::setPreferredLinkConfig(LinkConfiguration & lc, bool commit,
if (!validateLinkConfiguration(lc))
{
DP_PRINTF(DP_ERROR, "Client requested bad LinkConfiguration. peakRate=%d, lanes=%d, bIs128b132ChannelCoding=%d",
DP_PRINTF(DP_ERROR, "Client requested bad LinkConfiguration. peakRate=%" LinkRate_fmtu ", lanes=%d, bIs128b132ChannelCoding=%d",
lc.peakRate, lc.lanes, lc.bIs128b132bChannelCoding);
return false;
}
@@ -8166,7 +8183,7 @@ bool ConnectorImpl::handleTestLinkTrainRequest()
DP_ASSERT(0 && "Compliance: no group attached");
}
DP_PRINTF(DP_NOTICE, "DP> Compliance: LT on IRQ request: 0x%x, %d.", requestedRate, requestedLanes);
DP_PRINTF(DP_NOTICE, "DP> Compliance: LT on IRQ request: 0x%" LinkRate_fmtx ", %d.", requestedRate, requestedLanes);
// now see whether the current resolution is supported on the requested link config
LinkConfiguration lc(&linkPolicy, requestedLanes, requestedRate,
hal->getEnhancedFraming(),
@@ -8180,7 +8197,7 @@ bool ConnectorImpl::handleTestLinkTrainRequest()
{
if (willLinkSupportModeSST(lc, groupAttached->lastModesetInfo))
{
DP_PRINTF(DP_NOTICE, "DP> Compliance: Executing LT on IRQ: 0x%x, %d.", requestedRate, requestedLanes);
DP_PRINTF(DP_NOTICE, "DP> Compliance: Executing LT on IRQ: 0x%" LinkRate_fmtx ", %d.", requestedRate, requestedLanes);
// we need to force the requirement irrespective of whether is supported or not.
if (!enableFlush())
{

18
src/common/displayport/src/dp_connectorimpl2x.cpp
View File

@@ -247,13 +247,13 @@ bool ConnectorImpl2x::validateLinkConfiguration(const LinkConfiguration &lConfig
{
if (!IS_VALID_DP2_X_LINKBW(linkRate10M))
{
DP_PRINTF(DP_ERROR, "DP2xCONN> Requested link rate=%d is not valid", linkRate10M);
DP_PRINTF(DP_ERROR, "DP2xCONN> Requested link rate=%" NvU64_fmtu " is not valid", linkRate10M);
return false;
}
if (lConfig.peakRate > hal->getMaxLinkRate())
{
DP_PRINTF(DP_ERROR, "DP2xCONN> Requested link rate=%d is larger than sinkMaxLinkRate=%d",
DP_PRINTF(DP_ERROR, "DP2xCONN> Requested link rate=%" NvU64_fmtu " is larger than sinkMaxLinkRate=%" LinkRate_fmtu,
linkRate10M, hal->getMaxLinkRate());
return false;
}
@@ -264,7 +264,7 @@ bool ConnectorImpl2x::validateLinkConfiguration(const LinkConfiguration &lConfig
NvU32 i;
if (!hal->isIndexedLinkrateEnabled())
{
DP_PRINTF(DP_ERROR, "DP2xCONN> Indexed Link Rate=%d is Not Enabled in Sink", linkRate10M);
DP_PRINTF(DP_ERROR, "DP2xCONN> Indexed Link Rate=%" NvU64_fmtu " is Not Enabled in Sink", linkRate10M);
return false;
}
@@ -279,13 +279,13 @@ bool ConnectorImpl2x::validateLinkConfiguration(const LinkConfiguration &lConfig
break;
if (ilrTable[i] == 0)
{
DP_PRINTF(DP_ERROR, "DP2xCONN> Indexed Link Rate=%d is Not Found", linkRate10M);
DP_PRINTF(DP_ERROR, "DP2xCONN> Indexed Link Rate=%" NvU64_fmtu " is Not Found", linkRate10M);
return false;
}
}
if (i == NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES)
{
DP_PRINTF(DP_ERROR, "DP2xCONN> Indexed Link Rate=%d is Not Found", linkRate10M);
DP_PRINTF(DP_ERROR, "DP2xCONN> Indexed Link Rate=%" NvU64_fmtu " is Not Found", linkRate10M);
return false;
}
}
@@ -657,7 +657,7 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
}
}
DP_PRINTF(DP_NOTICE, "DP2xCONN> Notify Attach Begin (Head %d, pclk %d (KHz) raster %d x %d %d bpp)",
DP_PRINTF(DP_NOTICE, "DP2xCONN> Notify Attach Begin (Head %d, pclk %" NvU64_fmtu " (KHz) raster %d x %d %d bpp)",
modesetParams.headIndex, (pixelClockHz/1000), rasterWidth, rasterHeight, depth);
NV_DPTRACE_INFO(NOTIFY_ATTACH_BEGIN, modesetParams.headIndex, pixelClockHz, rasterWidth, rasterHeight,
depth, bEnableDsc, bEnableFEC);
@@ -1763,7 +1763,7 @@ bool ConnectorImpl2x::handleTestLinkTrainRequest()
DP_ASSERT(0 && "Compliance: no group attached");
}
DP_PRINTF(DP_NOTICE, "DP> Compliance: LT on IRQ request: 0x%x, %d.", requestedRate, requestedLanes);
DP_PRINTF(DP_NOTICE, "DP> Compliance: LT on IRQ request: 0x%" LinkRate_fmtx ", %d.", requestedRate, requestedLanes);
// now see whether the current resolution is supported on the requested link config
LinkConfiguration lc(&linkPolicy, requestedLanes, requestedRate, hal->getEnhancedFraming(),
false, // MST
@@ -1776,7 +1776,7 @@ bool ConnectorImpl2x::handleTestLinkTrainRequest()
{
if (willLinkSupportMode(lc, groupAttached->lastModesetInfo, groupAttached->headIndex, NULL, NULL))
{
DP_PRINTF(DP_NOTICE, "DP> Compliance: Executing LT on IRQ: 0x%x, %d.", requestedRate, requestedLanes);
DP_PRINTF(DP_NOTICE, "DP> Compliance: Executing LT on IRQ: 0x%" LinkRate_fmtx ", %d.", requestedRate, requestedLanes);
// we need to force the requirement irrespective of whether is supported or not.
if (!enableFlush())
{
@@ -1801,7 +1801,7 @@ bool ConnectorImpl2x::handleTestLinkTrainRequest()
}
else // linkconfig is not supporting bandwidth. Simply return NACK
{
DP_PRINTF(DP_ERROR, "DP> Compliance: IMP failed with requested link configuration: 0x%x, %d.",
DP_PRINTF(DP_ERROR, "DP> Compliance: IMP failed with requested link configuration: 0x%" LinkRate_fmtx ", %d.",
requestedRate, requestedLanes);
hal->setTestResponse(false);
return false;

2
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -3333,7 +3333,7 @@ bool DeviceImpl::setModeList(DisplayPort::DpModesetParams *modeList, unsigned nu
connector->endCompoundQuery();
}
DP_PRINTF(DP_INFO, "Computed Max mode BW: %d Mbps", maxModeBwRequired / (1000 * 1000));
DP_PRINTF(DP_INFO, "Computed Max mode BW: %" NvU64_fmtu " Mbps", maxModeBwRequired / (1000 * 1000));
connector->updateDpTunnelBwAllocation();

4
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -107,7 +107,9 @@ const struct
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FIX_FOR_5147205, &dpRegkeyDatabase.bEnable5147205Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_HDMI_ON_DP_PLUS_PLUS, &dpRegkeyDatabase.bHDMIOnDPPlusPlus, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC, &dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r581_07
#define NV_BUILD_BRANCH r581_36
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r581_07
#define NV_PUBLIC_BRANCH r581_36
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/r581_07-228"
#define NV_BUILD_CHANGELIST_NUM (36467788)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/r581_36-271"
#define NV_BUILD_CHANGELIST_NUM (36580581)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r580/r581_07-228"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36467788)
#define NV_BUILD_NAME "rel/gpu_drv/r580/r581_36-271"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36580581)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r581_07-5"
#define NV_BUILD_CHANGELIST_NUM (36456855)
#define NV_BUILD_BRANCH_VERSION "r581_36-3"
#define NV_BUILD_CHANGELIST_NUM (36570941)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "581.19"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36456855)
#define NV_BUILD_NAME "581.42"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36570941)
#define NV_BUILD_BRANCH_BASE_VERSION R580
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "580.82.09"
#define NV_VERSION_STRING "580.95.05"
#else

30
src/common/modeset/hdmipacket/nvhdmi_frlInterface.h
View File

@@ -199,6 +199,7 @@ typedef struct tagHDMI_FRL_CONFIG
* *
* Calls RM to get DSC related src side caps. Performs physical link training to determine if *
* sink reported max FRL rate can actually be supported on the physical link *
* This API is deprecated. Instead, use NvHdmi_AssessLinkCapabilities2(). *
*************************************************************************************************/
NVHDMIPKT_RESULT
NvHdmi_AssessLinkCapabilities(NvHdmiPkt_Handle libHandle,
@@ -208,6 +209,35 @@ NvHdmi_AssessLinkCapabilities(NvHdmiPkt_Handle libHandle,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps);
/************************************************************************************************
* NvHdmi_AssessLinkCapabilities2: *
* *
* Input parameters: *
* subDevice - Sub Device ID. *
* displayId - Display ID. *
* pSinkEdid - EDID of sink *
* bPerformLinkTrainingToAssess - Perform link training to determin max supported link rate. *
* bIsDisplayActive - Is the given displayId actively attached to head. *
* currFRLRate - If the given displayId is active then provide current FRL link rate. *
* *
* Output parameters: *
* pSrcCaps - src capabilities - DSC caps *
* pSinkCaps - sink capabilities - actual caps calculated from link training *
* *
* Calls RM to get DSC related src side caps. Performs physical link training to determine if *
* sink reported max FRL rate can actually be supported on the physical link *
*************************************************************************************************/
NVHDMIPKT_RESULT
NvHdmi_AssessLinkCapabilities2(NvHdmiPkt_Handle libHandle,
NvU32 subDevice,
NvU32 displayId,
NVT_EDID_INFO const * const pSinkEdid,
const NvBool bPerformLinkTrainingToAssess,
const NvBool bIsDisplayActive,
const HDMI_FRL_DATA_RATE currFRLRate,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps);
/************************************************************************************************
* NvHdmi_QueryFRLConfig: *
* *

29
src/common/modeset/hdmipacket/nvhdmipkt.c
View File

@@ -384,6 +384,28 @@ NvHdmi_AssessLinkCapabilities(NvHdmiPkt_Handle libHandle,
NVT_EDID_INFO const * const pSinkEdid,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps)
{
return NvHdmi_AssessLinkCapabilities2(libHandle,
subDevice,
displayId,
pSinkEdid,
NV_FALSE /* bPerformLinkTrainingToAssess */,
NV_FALSE /* bIsDisplayActive */,
HDMI_FRL_DATA_RATE_NONE /* currFRLRate */,
pSrcCaps,
pSinkCaps);
}
NVHDMIPKT_RESULT
NvHdmi_AssessLinkCapabilities2(NvHdmiPkt_Handle libHandle,
NvU32 subDevice,
NvU32 displayId,
NVT_EDID_INFO const * const pSinkEdid,
const NvBool bPerformLinkTrainingToAssess,
const NvBool bIsDisplayActive,
const HDMI_FRL_DATA_RATE currFRLRate,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps)
{
if (libHandle == NVHDMIPKT_INVALID_HANDLE)
{
@@ -402,9 +424,13 @@ NvHdmi_AssessLinkCapabilities(NvHdmiPkt_Handle libHandle,
subDevice,
displayId,
pSinkEdid,
bPerformLinkTrainingToAssess,
bIsDisplayActive,
currFRLRate,
pSrcCaps,
pSinkCaps);
}
/*
* NvHdmi_QueryFRLConfig
*/
@@ -686,8 +712,9 @@ NvHdmiPkt_InitializeLibrary(NvU32 const hwClass,
pClass->callback.checkTimeout = pCallbacks->checkTimeout;
#endif
#if defined (DEBUG)
pClass->callback.print = pCallbacks->print;
#if defined (DEBUG)
pClass->callback.assert = pCallbacks->assert;
#endif

13
src/common/modeset/hdmipacket/nvhdmipkt_0073.c
View File

@@ -308,12 +308,15 @@ hdmiWriteDummyPacketCtrl(NVHDMIPKT_CLASS* pThis,
}
NVHDMIPKT_RESULT
hdmiAssessLinkCapabilitiesDummy(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
hdmiAssessLinkCapabilitiesDummy(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
NVT_EDID_INFO const * const pSinkEdid,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps)
const NvBool bPerformLinkTrainingToAssess,
const NvBool bIsDisplayActive,
HDMI_FRL_DATA_RATE currFRLRate,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps)
{
NvHdmiPkt_Print(pThis, "ERROR - Dummy function hdmiAssessLinkCapabilitiesDummy called. "
"Should never be called.");

259
src/common/modeset/hdmipacket/nvhdmipkt_C671.c
View File

@@ -171,6 +171,168 @@ static void populateAudioCaps(NVT_EDID_CEA861_INFO const * const p861ExtBlock,
}
}
static NVHDMIPKT_RESULT SetFRLLinkRate(NVHDMIPKT_CLASS *pThis,
const NvU32 subDevice,
const NvU32 displayId,
const NvBool bFakeLt,
const NvBool bLinkAssessmentOnly,
const NvU32 frlRate)
{
NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS params = {0};
NVMISC_MEMSET(&params, 0, sizeof(params));
params.subDeviceInstance = subDevice;
params.displayId = displayId;
params.data = frlRate;
params.bFakeLt = bFakeLt;
params.bLinkAssessmentOnly = bLinkAssessmentOnly;
#if NVHDMIPKT_RM_CALLS_INTERNAL
if (CALL_DISP_RM(NvRmControl)(pThis->clientHandles.hClient,
pThis->clientHandles.hDisplay,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG,
&params,
sizeof(params)) != NVOS_STATUS_SUCCESS)
#else // !NVHDMIPKT_RM_CALLS_INTERNAL
NvBool bSuccess = pThis->callback.rmDispControl2(pThis->cbHandle,
params.subDeviceInstance,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG,
&params,
sizeof(params));
if (bSuccess == NV_FALSE)
#endif // NVHDMIPKT_RM_CALLS_INTERNAL
{
NvHdmiPkt_Print(pThis, "ERROR - RM call to set HDMI FRL failed.");
NvHdmiPkt_Assert(0);
return NVHDMIPKT_FAIL;
}
return NVHDMIPKT_SUCCESS;
}
static NVHDMIPKT_RESULT
SetFRLFlushMode(NVHDMIPKT_CLASS *pThis,
const NvU32 subDevice,
const NvU32 displayId,
const NvU32 bEnable)
{
NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS params = {0};
NVMISC_MEMSET(&params, 0, sizeof(params));
params.subDeviceInstance = subDevice;
params.displayId = displayId;
params.bEnable = bEnable;
#if NVHDMIPKT_RM_CALLS_INTERNAL
if (CALL_DISP_RM(NvRmControl)(pThis->clientHandles.hClient,
pThis->clientHandles.hDisplay,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE,
&params,
sizeof(params)) != NVOS_STATUS_SUCCESS)
#else // !NVHDMIPKT_RM_CALLS_INTERNAL
NvBool bSuccess = pThis->callback.rmDispControl2(pThis->cbHandle,
params.subDeviceInstance,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE,
&params,
sizeof(params));
if (bSuccess == NV_FALSE)
#endif // NVHDMIPKT_RM_CALLS_INTERNAL
{
NvHdmiPkt_Print(pThis, "ERROR - RM call to set HDMI FRL Flush Mode failed.");
NvHdmiPkt_Assert(0);
return NVHDMIPKT_FAIL;
}
return NVHDMIPKT_SUCCESS;
}
static NVHDMIPKT_RESULT
performLinkTraningToAssessFRLLink(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
const NvBool bIsDisplayActive,
const HDMI_FRL_DATA_RATE currFRLRate,
NvU32 *pMaxFRLRate)
{
const NvU32 nv0073currFRLRate =
translateFRLRateToNv0073SetHdmiFrlConfig(currFRLRate);
NVHDMIPKT_RESULT ret = NVHDMIPKT_SUCCESS;
NvU32 maxFRLRate = *pMaxFRLRate;
if (bIsDisplayActive) {
ret = SetFRLFlushMode(pThis, subDevice, displayId,
NV_TRUE /* bEnable */);
if (ret != NVHDMIPKT_SUCCESS)
{
NvHdmiPkt_Assert(0);
return ret;
}
}
while(maxFRLRate != NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE)
{
// If the display is active and the maximum link rate matches the link
// rate required for the current mode timings, avoid marking the set
// link configuration call as an assessment only. This prevents
// re-training after the assessment.
const NvBool bLinkAssessmentOnly =
bIsDisplayActive ? (nv0073currFRLRate != maxFRLRate) : NV_TRUE;
if (SetFRLLinkRate(pThis, subDevice, displayId,
NV_FALSE /* bFakeLt */, bLinkAssessmentOnly,
maxFRLRate) == NVHDMIPKT_SUCCESS)
{
break;
}
maxFRLRate--;
}
if (bIsDisplayActive)
{
// If the displayId is currently attached to the head, restore the FRL
// link rate to prevent the display engine from hanging.
if (nv0073currFRLRate != maxFRLRate)
{
const NvBool bFakeLt = (nv0073currFRLRate > maxFRLRate);
if (SetFRLLinkRate(pThis, subDevice, displayId,
bFakeLt, NV_FALSE /* bLinkAssessmentOnly */,
currFRLRate) != NVHDMIPKT_SUCCESS)
{
if (!bFakeLt) {
if (SetFRLLinkRate(pThis, subDevice, displayId,
NV_TRUE, NV_FALSE /* bLinkAssessmentOnly */,
currFRLRate) != NVHDMIPKT_SUCCESS) {
NvHdmiPkt_Assert(0);
}
}
}
}
ret = SetFRLFlushMode(pThis, subDevice, displayId,
NV_FALSE /* bEnable */);
if (ret != NVHDMIPKT_SUCCESS)
{
NvHdmiPkt_Assert(0);
}
}
else
{
NVHDMIPKT_RESULT ret = hdmiClearFRLConfigC671(pThis, subDevice,
displayId);
if (ret != NVHDMIPKT_SUCCESS)
{
NvHdmiPkt_Assert(0);
}
}
*pMaxFRLRate = maxFRLRate;
return NVHDMIPKT_SUCCESS;
}
/*
* hdmiAssessLinkCapabilities
*
@@ -181,12 +343,15 @@ static void populateAudioCaps(NVT_EDID_CEA861_INFO const * const p861ExtBlock,
* but for now, no incentive to do so. In future move it out to better place as need arises
*/
static NVHDMIPKT_RESULT
hdmiAssessLinkCapabilitiesC671(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
hdmiAssessLinkCapabilitiesC671(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
NVT_EDID_INFO const * const pSinkEdid,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps)
const NvBool bPerformLinkTrainingToAssess,
const NvBool bIsDisplayActive,
const HDMI_FRL_DATA_RATE currFRLRate,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps)
{
// Read DSC caps from RM - gpu caps for DSC are same across DP and HDMI FRL (HDMI 2.1+)
@@ -264,11 +429,25 @@ hdmiAssessLinkCapabilitiesC671(NVHDMIPKT_CLASS *pThis,
populateAudioCaps(&pSinkEdid->ext861, pSinkCaps);
populateAudioCaps(&pSinkEdid->ext861_2, pSinkCaps);
NvU32 setFRLRate = pSinkEdid->hdmiForumInfo.max_FRL_Rate;
NvU32 maxFRLRate = pSinkEdid->hdmiForumInfo.max_FRL_Rate;
pSinkCaps->linkMaxFRLRate = translateFRLCapToFRLDataRate(setFRLRate);
if (bPerformLinkTrainingToAssess) {
NVHDMIPKT_RESULT ret = performLinkTraningToAssessFRLLink(pThis,
subDevice,
displayId,
bIsDisplayActive,
currFRLRate,
&maxFRLRate);
if (ret != NVHDMIPKT_SUCCESS) {
pSinkCaps->linkMaxFRLRate = HDMI_FRL_DATA_RATE_NONE;
pSinkCaps->linkMaxFRLRateDSC = HDMI_FRL_DATA_RATE_NONE;
return ret;
}
}
pSinkCaps->linkMaxFRLRate = translateFRLCapToFRLDataRate(maxFRLRate);
pSinkCaps->linkMaxFRLRateDSC = (pSrcCaps->dscCaps.dscCapable &&
(pSinkEdid->hdmiForumInfo.dsc_Max_FRL_Rate > setFRLRate)) ?
(pSinkEdid->hdmiForumInfo.dsc_Max_FRL_Rate > maxFRLRate)) ?
pSinkCaps->linkMaxFRLRate :
translateFRLCapToFRLDataRate(pSinkEdid->hdmiForumInfo.dsc_Max_FRL_Rate);
@@ -1238,36 +1417,9 @@ hdmiSetFRLConfigC671(NVHDMIPKT_CLASS *pThis,
NvBool bFakeLt,
HDMI_FRL_CONFIG *pFRLConfig)
{
NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS params = {0};
NVMISC_MEMSET(&params, 0, sizeof(params));
params.subDeviceInstance = subDevice;
params.displayId = displayId;
params.data = translateFRLRateToNv0073SetHdmiFrlConfig(pFRLConfig->frlRate);
params.bFakeLt = bFakeLt;
#if NVHDMIPKT_RM_CALLS_INTERNAL
if (CALL_DISP_RM(NvRmControl)(pThis->clientHandles.hClient,
pThis->clientHandles.hDisplay,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG,
&params,
sizeof(params)) != NVOS_STATUS_SUCCESS)
#else // !NVHDMIPKT_RM_CALLS_INTERNAL
NvBool bSuccess = pThis->callback.rmDispControl2(pThis->cbHandle,
params.subDeviceInstance,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG,
&params,
sizeof(params));
if (bSuccess == NV_FALSE)
#endif // NVHDMIPKT_RM_CALLS_INTERNAL
{
NvHdmiPkt_Print(pThis, "ERROR - RM call to set HDMI FRL failed.");
NvHdmiPkt_Assert(0);
return NVHDMIPKT_FAIL;
}
return NVHDMIPKT_SUCCESS;
return SetFRLLinkRate(pThis, subDevice, displayId, bFakeLt,
NV_FALSE /* bLinkAssessmentOnly */,
translateFRLRateToNv0073SetHdmiFrlConfig(pFRLConfig->frlRate));
}
/*
@@ -1278,34 +1430,9 @@ hdmiClearFRLConfigC671(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId)
{
NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS;
NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS params = {0};
NVMISC_MEMSET(&params, 0, sizeof(params));
params.subDeviceInstance = subDevice;
params.displayId = displayId;
params.data = NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE;
#if NVHDMIPKT_RM_CALLS_INTERNAL
if (CALL_DISP_RM(NvRmControl)(pThis->clientHandles.hClient,
pThis->clientHandles.hDisplay,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG,
&params,
sizeof(params)) != NVOS_STATUS_SUCCESS)
#else // !NVHDMIPKT_RM_CALLS_INTERNAL
NvBool bSuccess = pThis->callback.rmDispControl2(pThis->cbHandle,
params.subDeviceInstance,
NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_CONFIG,
&params,
sizeof(params));
if (bSuccess == NV_FALSE)
#endif // NVHDMIPKT_RM_CALLS_INTERNAL
{
NvHdmiPkt_Print(pThis, "WARNING - RM call to reset HDMI FRL failed.");
result = NVHDMIPKT_FAIL;
}
return result;
return SetFRLLinkRate(pThis, subDevice, displayId,
NV_FALSE, NV_FALSE /* bLinkAssessmentOnly */,
NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE);
}
static NVHDMIPKT_RESULT

13
src/common/modeset/hdmipacket/nvhdmipkt_class.h
View File

@@ -170,12 +170,15 @@ struct tagNVHDMIPKT_CLASS
// capacity required for target timing.
//
NVHDMIPKT_RESULT
(*hdmiAssessLinkCapabilities) (NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
(*hdmiAssessLinkCapabilities) (NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
NVT_EDID_INFO const * const pSinkEdid,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps);
const NvBool bPerformLinkTrainingToAssess,
const NvBool bIsDisplayActive,
HDMI_FRL_DATA_RATE currFRLRate,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps);
NVHDMIPKT_RESULT
(*hdmiQueryFRLConfig) (NVHDMIPKT_CLASS *pThis,
HDMI_VIDEO_TRANSPORT_INFO const * const pVidTransInfo,

17
src/common/modeset/hdmipacket/nvhdmipkt_common.h
View File

@@ -65,7 +65,6 @@ struct tagNVHDMIPKT_MEM_MAP
};
// HDMIPKT print define
#if defined (DEBUG)
#define NvHdmiPkt_Print(_p, ...) \
do { \
if ((_p)->callback.print) \
@@ -73,9 +72,6 @@ struct tagNVHDMIPKT_MEM_MAP
(_p)->callback.print((_p)->cbHandle, "HdmiPacketLibrary: " __VA_ARGS__); \
} \
} while(0)
#else
#define NvHdmiPkt_Print(_p, ...) /* nothing */
#endif
// HDMIPKT assert define
@@ -95,12 +91,15 @@ struct tagNVHDMIPKT_MEM_MAP
// Prototypes for common functions shared across implementations.
extern void hdmiWriteDummyPacket(NVHDMIPKT_CLASS*, NvU32*, NvU32, NvU32, NvU8 const *const);
extern NVHDMIPKT_RESULT hdmiAssessLinkCapabilitiesDummy(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
extern NVHDMIPKT_RESULT hdmiAssessLinkCapabilitiesDummy(NVHDMIPKT_CLASS *pThis,
NvU32 subDevice,
NvU32 displayId,
NVT_EDID_INFO const * const pSinkEdid,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps);
const NvBool bPerformLinkTrainingToAssess,
const NvBool bIsDisplayActive,
HDMI_FRL_DATA_RATE currFRLRate,
HDMI_SRC_CAPS *pSrcCaps,
HDMI_SINK_CAPS *pSinkCaps);
extern NVHDMIPKT_RESULT hdmiQueryFRLConfigDummy(NVHDMIPKT_CLASS *pThis,
HDMI_VIDEO_TRANSPORT_INFO const * const pVidTransInfo,
HDMI_QUERY_FRL_CLIENT_CONTROL const * const pClientCtrl,

30
src/common/sdk/nvidia/inc/class/cl0050.h
View File

@@ -45,31 +45,37 @@ typedef struct NV0050_ALLOCATION_PARAMETERS {
// Whether the CeUtils will allocate everything with RM client or external client
#define NV0050_CEUTILS_FLAGS_EXTERNAL 0:0
#define NV0050_CEUTILS_FLAGS_EXTERNAL_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_EXTERNAL_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_EXTERNAL_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_EXTERNAL_TRUE (0x00000001)
// Whether CeUtils will use virtual copy
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE 1:1
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_TRUE (0x00000001)
// Whether the CeUtils is using fifo lite mode. Has to be internal
#define NV0050_CEUTILS_FLAGS_FIFO_LITE 2:2
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_TRUE (0x00000001)
// Whether the CeUtils will use BAR1 or BAR2 for data copy
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE 3:3
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_TRUE (0x00000001)
// Force a specific CE engine to be used be setting forceCeId
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID 4:4
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_TRUE (0x00000001)
// Use a CC secure channel
#define NV0050_CEUTILS_FLAGS_CC_SECURE 5:5
#define NV0050_CEUTILS_FLAGS_CC_SECURE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_CC_SECURE_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_CC_SECURE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_CC_SECURE_TRUE (0x00000001)
// Enable callbacks at work completion
#define NV0050_CEUTILS_FLAGS_ENABLE_COMPLETION_CB 6:6
#define NV0050_CEUTILS_FLAGS_ENABLE_COMPLETION_CB_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_ENABLE_COMPLETION_CB_TRUE (0x00000001)

211
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -1672,4 +1672,215 @@ typedef struct NV0073_CTRL_DFP_SET_FORCE_BLACK_PIXELS_PARAMS {
NvBool bForceBlack;
} NV0073_CTRL_DFP_SET_FORCE_BLACK_PIXELS_PARAMS;
/*
* NV0073_CTRL_CMD_DFP_GET_DISP_PHY_INFO
*
* Return a high-level DISP PHY description that is independent of raw register
* encodings. Tools or firmware can use the information to reason about link
* routing and data-rate policy, etc.
*
* Parameters
* subDeviceInstance (in)
* Sub-device instance within NV04_DISPLAY_COMMON.
*
* edpClkSrc (out) enum NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC
* edpPllFreq (out) enum NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL
*
* padLink[4] (out) One entry per DP Pad-Link (DP0...DP3):
* sorSel enum NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL
* mode enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE
* cableOrient enum NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT
* modeStatusDone NvBool (Alt-mode exit / entry finished)
* safeMode enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE
*
* tpllForceVal enum NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL
* tpllForceEn NvBool (DA_XTP_LN_TPLL_SEL[16])
* pllPwrSeqEn NvBool (DP_PHY_DIG_PLL_CTL_0[0])
* pllPwrSeqState enum NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE
* bitRateSel enum NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL
* pdCableIdA NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO
* structured view of TOP_TYPEC_IPMUX_PD_CABLE_ID_A
* (DP-rate capability, pin sets, UHBR13.5 support,
* active component type, DP-AM version, ...)
*
* pdCableIdB NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO
* structured view of TOP_TYPEC_IPMUX_PD_CABLE_ID_B
* (VCONN source indication)
*
* Status values
* NV_OK
* NV_ERR_INVALID_ARGUMENT invalid subDeviceInstance
* NV_ERR_NOT_SUPPORTED device doesn't have a display
*/
#define NV0073_CTRL_DFP_DISP_DP_PADLINK_COUNT 4U
// eDP clock source selection (EDP_PHY_DIG_MISC[3:0])
typedef enum NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC {
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_NONE = 0,
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR0 = 1,
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR1 = 2,
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR2 = 4,
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR3 = 8,
} NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC;
// eDP PLL frequency selector (EDP_PHY_DIG_BIT_RATE[3:0])
typedef enum NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL {
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_1_62GHZ = 1,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_2_16GHZ = 2,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_2_43GHZ = 3,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_2_70GHZ = 4,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_3_24GHZ = 5,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_4_32GHZ = 6,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_5_40GHZ = 7,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_6_75GHZ = 8,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_8_10GHZ = 9,
} NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL;
// DP bit-rate selector (DP_PHY_DIG_BIT_RATE[2:0])
typedef enum NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL {
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_1_62GHZ = 0,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_2_70GHZ = 1,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_5_40GHZ = 2,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_8_10GHZ = 3,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_10_00GHZ = 4,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_13_50GHZ = 5,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_20_00GHZ = 6,
} NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL;
// DP_PHY_DIG_MISC[3:0]
typedef enum NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL {
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_NONE = 0,
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR0 = 1,
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR1 = 2,
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR2 = 3,
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR3 = 4,
} NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL;
// Type-C mux operating mode (TOP_TYPEC_IPMUX_CTRL[1:0])
typedef enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE {
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_USB4_2T2R = 0,
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_USB3_2T2R = 1,
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_DP_4T = 2,
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_DP_2T_USB3_1T1R = 3,
} NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE;
// Cable orientation (TOP_TYPEC_IPMUX_CTRL[2])
typedef enum NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT {
NV0073_CTRL_DFP_DISP_PHY_ORIENT_UNFLIPPED = 0,
NV0073_CTRL_DFP_DISP_PHY_ORIENT_FLIPPED = 1,
} NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT;
// Safe-mode control (TOP_TYPEC_IPMUX_CTRL[3])
typedef enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE {
NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE_ENABLED = 0, // IP-MUX held in Safe-Mode
NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE_ALT = 1, // Safe-Mode disabled so Alt-Mode allowed
} NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE;
// TPLL force-value codes (DA_XTP_LN_TPLL_SEL[15:8])
typedef enum NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL {
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_RBR_UHBR13_5 = 57, // RBR / UHBR13.5
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_HBR_HBR2 = 89, // HBR / HBR2
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_HBR3 = 121, // HBR3
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_UHBR10_UHBR20 = 26, // UHBR10 / UHBR20
} NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL;
// PLL power-sequence state (DP_PHY_DIG_PLL_CTL_0[2:1])
typedef enum NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE {
NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_PD = 0,
NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_BIAS_ON = 1,
NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_PLL_ON = 2,
NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_LANE_ON = 3,
} NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE;
// Supported DisplayPort data-rate capability (bits 5:2)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_NONE = 0,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_HBR3 = 1,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UHBR10_0 = 2,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_UHBR10_0 = 3,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UHBR20_0 = 4,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_HBR3_UHBR20_0 = 5,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UHBR10_0_UHBR20_0 = 6,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_UHBR20_0 = 7,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT;
// SRC / SINK pin-sets advertised by the cable (bits 15:8 / 23:16)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CD = 12,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_E = 16,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP;
// UHBR13.5 support is Boolean, using NvBool
// Active-component type (bits 29:28)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_COMP {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_PASSIVE = 0,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_RETIMER = 1,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_REDRIVER = 2,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_OPTICAL = 3,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_COMP;
// DP Alt-Mode version supported by the cable (bits 31:30)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS_UPTO_2_0 = 0,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS_2_1_OR_LATER = 1,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS;
// VCONN source indication (Cable-ID-B bit 0)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC_DPTX = 0,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC_DPRX = 1,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC;
typedef struct NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT dpProt;
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP srcPinSet;
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP sinkPinSet;
NvBool bUhbr13_5; // bit 26
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_COMP activeComp; // bits 29:28
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS dpamVers; // bits 31:30
} NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO;
typedef struct NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC vconnSrc; // bit 0
} NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO;
typedef struct NV0073_CTRL_DFP_DISP_PHY_PADLINK_INFO {
// SOR routing
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL sorSel;
// Type-C mux status
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE mode; // USB4_2T2R, etc
NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT cableOrient;
NvBool bModeStatusDone; // Type-C IP-MUX has finished its mode-change power-down / power-up sequence when entering or exiting an alternate mode
NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE safeMode;
// Data-rate / PLL settings
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL tpllForceVal;
NvBool bTpllForceEn; // 0 = let hardware pick the appropriate TPLL settings automatically, 1 = force the TPLL to use tpllForceVal.
NvBool bPllPwrSeqEn; // 0 = normal automatic power-sequencer operation, 1 = override; the PHY obeys the explicit power state given in pllPwrSeqState.
NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE pllPwrSeqState;
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL bitRateSel;
// USB-PD cable identification
NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO pdCableIdA;
NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO pdCableIdB;
} NV0073_CTRL_DFP_DISP_PHY_PADLINK_INFO;
#define NV0073_CTRL_CMD_DFP_GET_DISP_PHY_INFO (0x731180U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS_MESSAGE_ID (0x80U)
typedef struct NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS {
NvU32 subDeviceInstance;
// eDP-wide settings
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC edpClkSrc;
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL edpPllFreq;
// Per-Pad-Link (DP0...DP3) information
NV0073_CTRL_DFP_DISP_PHY_PADLINK_INFO padLink[NV0073_CTRL_DFP_DISP_DP_PADLINK_COUNT];
} NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS;
/* _ctrl0073dfp_h_ */

53
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
View File

@@ -1351,6 +1351,10 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS {
* bLtSkipped
* The flag returned indicating whether link training is skipped or not.
* TRUE if link training is skipped due to the link config is not changed.
* bLinkAssessmentOnly
* The flag as input to this command. It indicates that the client is doing
* link training only for the link assessment, no FRL video transmission is
* intended.
*
* Possible status values returned include:
* NV_OK -
@@ -1374,16 +1378,51 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS {
NvU32 data;
NvBool bFakeLt;
NvBool bLtSkipped;
NvBool bLinkAssessmentOnly;
} NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS;
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE 2:0
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE (0x00000000U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G (0x00000001U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G (0x00000002U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G (0x00000003U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G (0x00000004U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G (0x00000005U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G (0x00000006U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE (0x00000000U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G (0x00000001U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G (0x00000002U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G (0x00000003U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G (0x00000004U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G (0x00000005U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G (0x00000006U)
/*
* NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE
*
* This command is used to enable flush mode on given HDMI displayId in
* preparation for FRL link training. The flush mode can be enabled only if HDMI
* display is active and driven by FRL protocol. If display is not active then
* this control command does nothing.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
* displayID
* This parameter specifies the displayID for the display output resource to
* configure.
* bEnable
* This parameter is an inputto this command.
*
* Possible status values returned include:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* If any argument is invalid for this control call, NV_ERR_INVALID_ARGUMENT
* status will be returned.
*/
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE (0x73029bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS_MESSAGE_ID (0x9BU)
typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvBool bEnable;
} NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS;

4
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -68,7 +68,7 @@ typedef struct NV0080_CTRL_MSENC_GET_CAPS_PARAMS {
/* size in bytes of MSENC caps table */
#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 4
#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 5
/*
* NV0080_CTRL_CMD_MSENC_GET_CAPS_V2

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
View File

@@ -430,6 +430,8 @@ typedef enum NV2080_CTRL_CE_LCE_TYPE {
*
* [in] lceType
* LCE type. Should be one of NV2080_CTRL_CE_LCE_TYPE_* values.
* [in] metadataForLceType
* Metadata for LCE type.
* [out] numPces
* Number of PCEs supported per LCE
* [out] numLces
@@ -450,6 +452,7 @@ typedef enum NV2080_CTRL_CE_LCE_TYPE {
typedef struct NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS {
NV2080_CTRL_CE_LCE_TYPE lceType;
NvU32 metadataForLceType;
NvU32 numPces;
NvU32 numLces;
NvU32 supportedPceMask;

27
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -3714,5 +3714,32 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS {
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS;
/*
* NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME
* NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME
*
* These commands store/retrieve a 64 char null-terminated ASCII string which is
* treated by the NVLINK firmware as the node's hostname for fabric reporting
* purposes.
*/
typedef struct NV2080_CTRL_NVLINK_NODE_HOSTNAME {
NvU8 name[64];
} NV2080_CTRL_NVLINK_NODE_HOSTNAME;
#define NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS_MESSAGE_ID (0x9AU)
typedef struct NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS {
NV2080_CTRL_NVLINK_NODE_HOSTNAME hostname;
} NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SAVE_NODE_HOSTNAME (0x2080309aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS_MESSAGE_ID (0x9BU)
typedef struct NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS {
NV2080_CTRL_NVLINK_NODE_HOSTNAME hostname;
} NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_SAVED_NODE_HOSTNAME (0x2080309bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS_MESSAGE_ID" */
/* _ctrl2080nvlink_h_ */

1
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
View File

@@ -113,6 +113,7 @@ typedef struct NVA081_CTRL_VGPU_INFO {
NvU32 encoderCapacity;
NV_DECLARE_ALIGNED(NvU64 bar1Length, 8);
NvU32 frlEnable;
NvU16 vgpuSsvid;
NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH];
NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH];
NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];

4
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -109,7 +109,7 @@
#define ROBUST_CHANNEL_NVJPG5_ERROR (103)
#define ROBUST_CHANNEL_NVJPG6_ERROR (104)
#define ROBUST_CHANNEL_NVJPG7_ERROR (105)
#define DESTINATION_FLA_TRANSLATION_ERROR (108)
#define NVLINK_REMOTE_TRANSLATION_ERROR (108)
#define SEC_FAULT_ERROR (110)
#define GSP_RPC_TIMEOUT (119)
#define GSP_ERROR (120)
@@ -129,7 +129,7 @@
#define ROBUST_CHANNEL_CE18_ERROR (134)
#define ROBUST_CHANNEL_CE19_ERROR (135)
#define ALI_TRAINING_FAIL (136)
#define NVLINK_FLA_PRIV_ERR (137)
#define NVLINK_PRIV_ERR (137)
#define ROBUST_CHANNEL_DLA_ERROR (138)
#define ROBUST_CHANNEL_OFA1_ERROR (139)
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)

31
src/common/shared/inc/g_vgpu_chip_flags.h
View File

@@ -621,25 +621,6 @@ ENTRY(0x2238, 0x16B8, 0x10de, "NVIDIA A10M-10C"),
ENTRY(0x2238, 0x16B9, 0x10de, "NVIDIA A10M-20C"),
ENTRY(0x2238, 0x16E6, 0x10de, "NVIDIA A10M-1"),
ENTRY(0x2238, 0x2208, 0x10de, "NVIDIA A10M-3B"),
ENTRY(0x230E, 0x20F5, 0x10de, "NVIDIA H20L-1-15CME"),
ENTRY(0x230E, 0x20F6, 0x10de, "NVIDIA H20L-1-15C"),
ENTRY(0x230E, 0x20F7, 0x10de, "NVIDIA H20L-1-30C"),
ENTRY(0x230E, 0x20F8, 0x10de, "NVIDIA H20L-2-30C"),
ENTRY(0x230E, 0x20F9, 0x10de, "NVIDIA H20L-3-60C"),
ENTRY(0x230E, 0x20FA, 0x10de, "NVIDIA H20L-4-60C"),
ENTRY(0x230E, 0x20FB, 0x10de, "NVIDIA H20L-7-120C"),
ENTRY(0x230E, 0x20FC, 0x10de, "NVIDIA H20L-4C"),
ENTRY(0x230E, 0x20FD, 0x10de, "NVIDIA H20L-5C"),
ENTRY(0x230E, 0x20FE, 0x10de, "NVIDIA H20L-6C"),
ENTRY(0x230E, 0x20FF, 0x10de, "NVIDIA H20L-8C"),
ENTRY(0x230E, 0x2100, 0x10de, "NVIDIA H20L-10C"),
ENTRY(0x230E, 0x2101, 0x10de, "NVIDIA H20L-12C"),
ENTRY(0x230E, 0x2102, 0x10de, "NVIDIA H20L-15C"),
ENTRY(0x230E, 0x2103, 0x10de, "NVIDIA H20L-20C"),
ENTRY(0x230E, 0x2104, 0x10de, "NVIDIA H20L-30C"),
ENTRY(0x230E, 0x2105, 0x10de, "NVIDIA H20L-40C"),
ENTRY(0x230E, 0x2106, 0x10de, "NVIDIA H20L-60C"),
ENTRY(0x230E, 0x2107, 0x10de, "NVIDIA H20L-120C"),
ENTRY(0x2321, 0x1853, 0x10de, "NVIDIA H100L-1-12CME"),
ENTRY(0x2321, 0x1854, 0x10de, "NVIDIA H100L-1-12C"),
ENTRY(0x2321, 0x1855, 0x10de, "NVIDIA H100L-1-24C"),
@@ -1314,6 +1295,18 @@ ENTRY(0x2BB5, 0x21C6, 0x10de, "NVIDIA RTX Pro 6000 Blackwell DC-48"),
ENTRY(0x2BB5, 0x21C7, 0x10de, "NVIDIA RTX Pro 6000 Blackwell DC-96"),
ENTRY(0x2BB5, 0x21F8, 0x10de, "NVIDIA RTX Pro 6000 Blackwell DC-1-3B"),
ENTRY(0x2BB5, 0x21F9, 0x10de, "NVIDIA RTX Pro 6000 Blackwell DC-3B"),
ENTRY(0x2BB9, 0x2233, 0x10de, "NVIDIA RTX 6000D-1-42Q"),
ENTRY(0x2BB9, 0x2234, 0x10de, "NVIDIA RTX 6000D-1-42A"),
ENTRY(0x2BB9, 0x2235, 0x10de, "NVIDIA RTX 6000D-1-42C"),
ENTRY(0x2BB9, 0x2236, 0x10de, "NVIDIA RTX 6000D-1-42"),
ENTRY(0x2BB9, 0x2243, 0x10de, "NVIDIA RTX 6000D-2-84Q"),
ENTRY(0x2BB9, 0x2244, 0x10de, "NVIDIA RTX 6000D-2-84A"),
ENTRY(0x2BB9, 0x2245, 0x10de, "NVIDIA RTX 6000D-2-84C"),
ENTRY(0x2BB9, 0x2246, 0x10de, "NVIDIA RTX 6000D-2-84"),
ENTRY(0x2BB9, 0x226C, 0x10de, "NVIDIA RTX 6000D-84Q"),
ENTRY(0x2BB9, 0x226D, 0x10de, "NVIDIA RTX 6000D-84A"),
ENTRY(0x2BB9, 0x226E, 0x10de, "NVIDIA RTX 6000D-84C"),
ENTRY(0x2BB9, 0x226F, 0x10de, "NVIDIA RTX 6000D-84"),
};
#endif /* _G_VGPU_CHIP_FLAGS_H_ */

16
src/common/shared/inc/g_vgpu_resman_specific.h
View File

@@ -17,7 +17,6 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
{ 0x20B7, 0x1804, 0x20B7, 0x1532 },
{ 0x20B9, 0x157F, 0x20B7, 0x1532 },
{ 0x20FD, 0x17F8, 0x20F5, 0x0 },
{ 0x230E, 0x20DF, 0x230E, 0x20DF },
{ 0x2324, 0x17A8, 0x2324, 0x17A6 },
{ 0x2329, 0x198C, 0x2329, 0x198B },
{ 0x232C, 0x2064, 0x232C, 0x2063 },
@@ -122,13 +121,6 @@ static const struct {
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1094}, // GRID A800-4-20C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1095}, // GRID A800-7-40C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1091}, // GRID A800-1-10C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1499}, // NVIDIA H20L-1-15CME
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1500}, // NVIDIA H20L-1-15C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1501}, // NVIDIA H20L-1-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1502}, // NVIDIA H20L-2-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1503}, // NVIDIA H20L-3-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1504}, // NVIDIA H20L-4-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1505}, // NVIDIA H20L-7-120C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1061}, // NVIDIA H100L-1-12CME
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1062}, // NVIDIA H100L-1-12C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1063}, // NVIDIA H100L-1-24C
@@ -308,6 +300,14 @@ static const struct {
{0x2BB510DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 1619}, // NVIDIA RTX Pro 6000 Blackwell DC-4-48
{0x2BB510DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 1620}, // NVIDIA RTX Pro 6000 Blackwell DC-4-96
{0x2BB510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _QUARTER) , 2158}, // NVIDIA RTX Pro 6000 Blackwell DC-1-3B
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF) , 2199}, // NVIDIA RTX 6000D-1-42Q
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF) , 2200}, // NVIDIA RTX 6000D-1-42A
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF) , 2201}, // NVIDIA RTX 6000D-1-42C
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF) , 2202}, // NVIDIA RTX 6000D-1-42
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2203}, // NVIDIA RTX 6000D-2-84Q
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2204}, // NVIDIA RTX 6000D-2-84A
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2205}, // NVIDIA RTX 6000D-2-84C
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2206}, // NVIDIA RTX 6000D-2-84
};
#endif // GENERATE_vgpuSmcTypeIdMappings

1
src/common/shared/inc/nvdevid.h
View File

@@ -654,6 +654,7 @@ enum {
, CS_AMD_RPH
, CS_INTEL_B660
, CS_AMPERE_AMPEREONE192
, CS_NVIDIA_T254
, CS_MAX_PCIE
};

66
src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c
View File

@@ -1871,25 +1871,25 @@ NvBool isLibosPreserveLogBufferFull(LIBOS_LOG_DECODE *pLogDecode, NvU32 gpuInsta
{
NvU64 i = (NvU32)(pLogDecode->numLogBuffers);
NvU32 tag = LIBOS_LOG_NVLOG_BUFFER_TAG(pLogDecode->sourceName, i * 2);
NVLOG_BUFFER_HANDLE handle = 0;
NV_STATUS status = nvlogGetBufferHandleFromTag(tag, &handle);
if (status != NV_OK)
//
// Cannot use nvlogGetBufferHandleFromTag here since in multi GPU case,
// we can have multiple buffers with exact same tag, only differentiable
// from gpuInstance
//
for (i = 0; i < NVLOG_MAX_BUFFERS; i++)
{
return NV_FALSE;
}
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[handle];
if (pNvLogBuffer == NULL)
{
return NV_FALSE;
}
if (FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance &&
(pNvLogBuffer->pos >= pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
{
return NV_TRUE;
if (NvLogLogger.pBuffers[i] != NULL)
{
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[i];
if ((pNvLogBuffer->tag == tag) &&
(DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance) &&
FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
(pNvLogBuffer->pos >= pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
{
return NV_TRUE;
}
}
}
return NV_FALSE;
@@ -1897,19 +1897,27 @@ NvBool isLibosPreserveLogBufferFull(LIBOS_LOG_DECODE *pLogDecode, NvU32 gpuInsta
static NvBool findPreservedNvlogBuffer(NvU32 tag, NvU32 gpuInstance, NVLOG_BUFFER_HANDLE *pHandle)
{
NVLOG_BUFFER_HANDLE handle = 0;
NV_STATUS status = nvlogGetBufferHandleFromTag(tag, &handle);
NvU64 i;
if (status != NV_OK)
return NV_FALSE;
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[handle];
if (FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance &&
(pNvLogBuffer->pos < pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
//
// Cannot use nvlogGetBufferHandleFromTag here since in multi GPU case,
// we can have multiple buffers with exact same tag, only differentiable
// from gpuInstance
//
for (i = 0; i < NVLOG_MAX_BUFFERS; i++)
{
*pHandle = handle;
return NV_TRUE;
if (NvLogLogger.pBuffers[i] != NULL)
{
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[i];
if ((pNvLogBuffer->tag == tag) &&
(DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance) &&
FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
(pNvLogBuffer->pos < pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
{
*pHandle = i;
return NV_TRUE;
}
}
}
return NV_FALSE;
@@ -2247,6 +2255,7 @@ void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSiz
);
NvLogLogger.pBuffers[pLog->hNvLogWrap]->pos = NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) + sizeof(NvU64); // offset to account for LIBOS buffer header and put pointer
}
else
{
@@ -2447,6 +2456,7 @@ void libosLogUpdateTimerDelta(LIBOS_LOG_DECODE *logDecode, NvU64 localToGlobalTi
pNoWrapBuf->localToGlobalTimerDelta = localToGlobalTimerDelta;
pWrapBuf->localToGlobalTimerDelta = localToGlobalTimerDelta;
#endif
logDecode->log[i].localToGlobalTimerDelta = localToGlobalTimerDelta;
}