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This commit is contained in:
Maneet Singh
2025-09-30 12:52:14 -07:00
parent 87c0b12473
commit 2b436058a6
147 changed files with 56986 additions and 55176 deletions
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30
src/common/sdk/nvidia/inc/class/cl0050.h
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@@ -45,31 +45,37 @@ typedef struct NV0050_ALLOCATION_PARAMETERS {
// Whether the CeUtils will allocate everything with RM client or external client
#define NV0050_CEUTILS_FLAGS_EXTERNAL 0:0
#define NV0050_CEUTILS_FLAGS_EXTERNAL_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_EXTERNAL_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_EXTERNAL_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_EXTERNAL_TRUE (0x00000001)
// Whether CeUtils will use virtual copy
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE 1:1
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_TRUE (0x00000001)
// Whether the CeUtils is using fifo lite mode. Has to be internal
#define NV0050_CEUTILS_FLAGS_FIFO_LITE 2:2
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_TRUE (0x00000001)
// Whether the CeUtils will use BAR1 or BAR2 for data copy
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE 3:3
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_TRUE (0x00000001)
// Force a specific CE engine to be used be setting forceCeId
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID 4:4
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_TRUE (0x00000001)
// Use a CC secure channel
#define NV0050_CEUTILS_FLAGS_CC_SECURE 5:5
#define NV0050_CEUTILS_FLAGS_CC_SECURE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_CC_SECURE_TRUE (0x00000001)
#define NV0050_CEUTILS_FLAGS_CC_SECURE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_CC_SECURE_TRUE (0x00000001)
// Enable callbacks at work completion
#define NV0050_CEUTILS_FLAGS_ENABLE_COMPLETION_CB 6:6
#define NV0050_CEUTILS_FLAGS_ENABLE_COMPLETION_CB_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_ENABLE_COMPLETION_CB_TRUE (0x00000001)

211
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
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@@ -1672,4 +1672,215 @@ typedef struct NV0073_CTRL_DFP_SET_FORCE_BLACK_PIXELS_PARAMS {
NvBool bForceBlack;
} NV0073_CTRL_DFP_SET_FORCE_BLACK_PIXELS_PARAMS;
/*
* NV0073_CTRL_CMD_DFP_GET_DISP_PHY_INFO
*
* Return a high-level DISP PHY description that is independent of raw register
* encodings. Tools or firmware can use the information to reason about link
* routing and data-rate policy, etc.
*
* Parameters
* subDeviceInstance (in)
* Sub-device instance within NV04_DISPLAY_COMMON.
*
* edpClkSrc (out) enum NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC
* edpPllFreq (out) enum NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL
*
* padLink[4] (out) One entry per DP Pad-Link (DP0...DP3):
* sorSel enum NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL
* mode enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE
* cableOrient enum NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT
* modeStatusDone NvBool (Alt-mode exit / entry finished)
* safeMode enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE
*
* tpllForceVal enum NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL
* tpllForceEn NvBool (DA_XTP_LN_TPLL_SEL[16])
* pllPwrSeqEn NvBool (DP_PHY_DIG_PLL_CTL_0[0])
* pllPwrSeqState enum NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE
* bitRateSel enum NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL
* pdCableIdA NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO
* structured view of TOP_TYPEC_IPMUX_PD_CABLE_ID_A
* (DP-rate capability, pin sets, UHBR13.5 support,
* active component type, DP-AM version, ...)
*
* pdCableIdB NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO
* structured view of TOP_TYPEC_IPMUX_PD_CABLE_ID_B
* (VCONN source indication)
*
* Status values
* NV_OK
* NV_ERR_INVALID_ARGUMENT invalid subDeviceInstance
* NV_ERR_NOT_SUPPORTED device doesn't have a display
*/
#define NV0073_CTRL_DFP_DISP_DP_PADLINK_COUNT 4U
// eDP clock source selection (EDP_PHY_DIG_MISC[3:0])
typedef enum NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC {
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_NONE = 0,
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR0 = 1,
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR1 = 2,
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR2 = 4,
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC_SOR3 = 8,
} NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC;
// eDP PLL frequency selector (EDP_PHY_DIG_BIT_RATE[3:0])
typedef enum NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL {
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_1_62GHZ = 1,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_2_16GHZ = 2,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_2_43GHZ = 3,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_2_70GHZ = 4,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_3_24GHZ = 5,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_4_32GHZ = 6,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_5_40GHZ = 7,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_6_75GHZ = 8,
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_8_10GHZ = 9,
} NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL;
// DP bit-rate selector (DP_PHY_DIG_BIT_RATE[2:0])
typedef enum NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL {
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_1_62GHZ = 0,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_2_70GHZ = 1,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_5_40GHZ = 2,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_8_10GHZ = 3,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_10_00GHZ = 4,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_13_50GHZ = 5,
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_20_00GHZ = 6,
} NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL;
// DP_PHY_DIG_MISC[3:0]
typedef enum NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL {
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_NONE = 0,
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR0 = 1,
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR1 = 2,
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR2 = 3,
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL_SOR3 = 4,
} NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL;
// Type-C mux operating mode (TOP_TYPEC_IPMUX_CTRL[1:0])
typedef enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE {
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_USB4_2T2R = 0,
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_USB3_2T2R = 1,
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_DP_4T = 2,
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE_DP_2T_USB3_1T1R = 3,
} NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE;
// Cable orientation (TOP_TYPEC_IPMUX_CTRL[2])
typedef enum NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT {
NV0073_CTRL_DFP_DISP_PHY_ORIENT_UNFLIPPED = 0,
NV0073_CTRL_DFP_DISP_PHY_ORIENT_FLIPPED = 1,
} NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT;
// Safe-mode control (TOP_TYPEC_IPMUX_CTRL[3])
typedef enum NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE {
NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE_ENABLED = 0, // IP-MUX held in Safe-Mode
NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE_ALT = 1, // Safe-Mode disabled so Alt-Mode allowed
} NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE;
// TPLL force-value codes (DA_XTP_LN_TPLL_SEL[15:8])
typedef enum NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL {
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_RBR_UHBR13_5 = 57, // RBR / UHBR13.5
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_HBR_HBR2 = 89, // HBR / HBR2
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_HBR3 = 121, // HBR3
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_UHBR10_UHBR20 = 26, // UHBR10 / UHBR20
} NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL;
// PLL power-sequence state (DP_PHY_DIG_PLL_CTL_0[2:1])
typedef enum NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE {
NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_PD = 0,
NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_BIAS_ON = 1,
NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_PLL_ON = 2,
NV0073_CTRL_DFP_DISP_PHY_PLL_STATE_LANE_ON = 3,
} NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE;
// Supported DisplayPort data-rate capability (bits 5:2)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_NONE = 0,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_HBR3 = 1,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UHBR10_0 = 2,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_UHBR10_0 = 3,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UHBR20_0 = 4,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_HBR3_UHBR20_0 = 5,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UHBR10_0_UHBR20_0 = 6,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT_UPTO_UHBR20_0 = 7,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT;
// SRC / SINK pin-sets advertised by the cable (bits 15:8 / 23:16)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CD = 12,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_E = 16,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP;
// UHBR13.5 support is Boolean, using NvBool
// Active-component type (bits 29:28)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_COMP {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_PASSIVE = 0,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_RETIMER = 1,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_REDRIVER = 2,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_OPTICAL = 3,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_COMP;
// DP Alt-Mode version supported by the cable (bits 31:30)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS_UPTO_2_0 = 0,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS_2_1_OR_LATER = 1,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS;
// VCONN source indication (Cable-ID-B bit 0)
typedef enum NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC_DPTX = 0,
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC_DPRX = 1,
} NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC;
typedef struct NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DP_PROT dpProt;
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP srcPinSet;
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_PIN_CAP sinkPinSet;
NvBool bUhbr13_5; // bit 26
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_ACTIVE_COMP activeComp; // bits 29:28
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_DPAM_VERS dpamVers; // bits 31:30
} NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO;
typedef struct NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO {
NV0073_CTRL_DFP_DISP_PHY_PD_CBL_VCONN_SRC vconnSrc; // bit 0
} NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO;
typedef struct NV0073_CTRL_DFP_DISP_PHY_PADLINK_INFO {
// SOR routing
NV0073_CTRL_DFP_DISP_PHY_DP_SOR_SEL sorSel;
// Type-C mux status
NV0073_CTRL_DFP_DISP_PHY_TYPEC_MODE mode; // USB4_2T2R, etc
NV0073_CTRL_DFP_DISP_PHY_CABLE_ORIENT cableOrient;
NvBool bModeStatusDone; // Type-C IP-MUX has finished its mode-change power-down / power-up sequence when entering or exiting an alternate mode
NV0073_CTRL_DFP_DISP_PHY_TYPEC_SAFE_MODE safeMode;
// Data-rate / PLL settings
NV0073_CTRL_DFP_DISP_PHY_TPLL_FORCE_VAL tpllForceVal;
NvBool bTpllForceEn; // 0 = let hardware pick the appropriate TPLL settings automatically, 1 = force the TPLL to use tpllForceVal.
NvBool bPllPwrSeqEn; // 0 = normal automatic power-sequencer operation, 1 = override; the PHY obeys the explicit power state given in pllPwrSeqState.
NV0073_CTRL_DFP_DISP_PHY_PLL_PWR_STATE pllPwrSeqState;
NV0073_CTRL_DFP_DISP_PHY_DP_BIT_RATE_SEL bitRateSel;
// USB-PD cable identification
NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_A_INFO pdCableIdA;
NV0073_CTRL_DFP_DISP_PHY_PD_CABLE_ID_B_INFO pdCableIdB;
} NV0073_CTRL_DFP_DISP_PHY_PADLINK_INFO;
#define NV0073_CTRL_CMD_DFP_GET_DISP_PHY_INFO (0x731180U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS_MESSAGE_ID (0x80U)
typedef struct NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS {
NvU32 subDeviceInstance;
// eDP-wide settings
NV0073_CTRL_DFP_DISP_PHY_EDP_CLK_SRC edpClkSrc;
NV0073_CTRL_DFP_DISP_PHY_EDP_PLL_FREQ_SEL edpPllFreq;
// Per-Pad-Link (DP0...DP3) information
NV0073_CTRL_DFP_DISP_PHY_PADLINK_INFO padLink[NV0073_CTRL_DFP_DISP_DP_PADLINK_COUNT];
} NV0073_CTRL_DFP_GET_DISP_PHY_INFO_PARAMS;
/* _ctrl0073dfp_h_ */

53
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
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@@ -1351,6 +1351,10 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS {
* bLtSkipped
* The flag returned indicating whether link training is skipped or not.
* TRUE if link training is skipped due to the link config is not changed.
* bLinkAssessmentOnly
* The flag as input to this command. It indicates that the client is doing
* link training only for the link assessment, no FRL video transmission is
* intended.
*
* Possible status values returned include:
* NV_OK -
@@ -1374,16 +1378,51 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS {
NvU32 data;
NvBool bFakeLt;
NvBool bLtSkipped;
NvBool bLinkAssessmentOnly;
} NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS;
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE 2:0
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE (0x00000000U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G (0x00000001U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G (0x00000002U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G (0x00000003U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G (0x00000004U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G (0x00000005U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G (0x00000006U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_NONE (0x00000000U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_3G (0x00000001U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_3LANES_6G (0x00000002U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_6G (0x00000003U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_8G (0x00000004U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_10G (0x00000005U)
#define NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G (0x00000006U)
/*
* NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE
*
* This command is used to enable flush mode on given HDMI displayId in
* preparation for FRL link training. The flush mode can be enabled only if HDMI
* display is active and driven by FRL protocol. If display is not active then
* this control command does nothing.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
* displayID
* This parameter specifies the displayID for the display output resource to
* configure.
* bEnable
* This parameter is an inputto this command.
*
* Possible status values returned include:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* If any argument is invalid for this control call, NV_ERR_INVALID_ARGUMENT
* status will be returned.
*/
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE (0x73029bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS_MESSAGE_ID (0x9BU)
typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvBool bEnable;
} NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_FLUSH_MODE_PARAMS;

4
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -68,7 +68,7 @@ typedef struct NV0080_CTRL_MSENC_GET_CAPS_PARAMS {
/* size in bytes of MSENC caps table */
#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 4
#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 5
/*
* NV0080_CTRL_CMD_MSENC_GET_CAPS_V2

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
View File

@@ -430,6 +430,8 @@ typedef enum NV2080_CTRL_CE_LCE_TYPE {
*
* [in] lceType
* LCE type. Should be one of NV2080_CTRL_CE_LCE_TYPE_* values.
* [in] metadataForLceType
* Metadata for LCE type.
* [out] numPces
* Number of PCEs supported per LCE
* [out] numLces
@@ -450,6 +452,7 @@ typedef enum NV2080_CTRL_CE_LCE_TYPE {
typedef struct NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS {
NV2080_CTRL_CE_LCE_TYPE lceType;
NvU32 metadataForLceType;
NvU32 numPces;
NvU32 numLces;
NvU32 supportedPceMask;

27
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -3714,5 +3714,32 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS {
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS;
/*
* NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME
* NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME
*
* These commands store/retrieve a 64 char null-terminated ASCII string which is
* treated by the NVLINK firmware as the node's hostname for fabric reporting
* purposes.
*/
typedef struct NV2080_CTRL_NVLINK_NODE_HOSTNAME {
NvU8 name[64];
} NV2080_CTRL_NVLINK_NODE_HOSTNAME;
#define NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS_MESSAGE_ID (0x9AU)
typedef struct NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS {
NV2080_CTRL_NVLINK_NODE_HOSTNAME hostname;
} NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SAVE_NODE_HOSTNAME (0x2080309aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS_MESSAGE_ID (0x9BU)
typedef struct NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS {
NV2080_CTRL_NVLINK_NODE_HOSTNAME hostname;
} NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_SAVED_NODE_HOSTNAME (0x2080309bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS_MESSAGE_ID" */
/* _ctrl2080nvlink_h_ */

1
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
View File

@@ -113,6 +113,7 @@ typedef struct NVA081_CTRL_VGPU_INFO {
NvU32 encoderCapacity;
NV_DECLARE_ALIGNED(NvU64 bar1Length, 8);
NvU32 frlEnable;
NvU16 vgpuSsvid;
NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH];
NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH];
NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];

4
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -109,7 +109,7 @@
#define ROBUST_CHANNEL_NVJPG5_ERROR (103)
#define ROBUST_CHANNEL_NVJPG6_ERROR (104)
#define ROBUST_CHANNEL_NVJPG7_ERROR (105)
#define DESTINATION_FLA_TRANSLATION_ERROR (108)
#define NVLINK_REMOTE_TRANSLATION_ERROR (108)
#define SEC_FAULT_ERROR (110)
#define GSP_RPC_TIMEOUT (119)
#define GSP_ERROR (120)
@@ -129,7 +129,7 @@
#define ROBUST_CHANNEL_CE18_ERROR (134)
#define ROBUST_CHANNEL_CE19_ERROR (135)
#define ALI_TRAINING_FAIL (136)
#define NVLINK_FLA_PRIV_ERR (137)
#define NVLINK_PRIV_ERR (137)
#define ROBUST_CHANNEL_DLA_ERROR (138)
#define ROBUST_CHANNEL_OFA1_ERROR (139)
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)