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This commit is contained in:
Andy Ritger
2026-03-09 13:13:35 -07:00
parent 2ccbad25e1
commit 2c7bfb4706
1210 changed files with 436452 additions and 437093 deletions
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19
src/common/displayport/inc/dp_auxdefs.h
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@@ -34,16 +34,6 @@
#define DPCD_MESSAGEBOX_SIZE 48
//
// This definitions are being used for orin Hdcp opensourcing. Ideally this
// should be replaced with build flags. Bug ID: 200733434
//
#define DP_OPTION_HDCP_SUPPORT_ENABLE 1 /* HDCP Enable */
#define DP_OPTION_HDCP_12_ENABLED 1 /* DP1.2 HDCP ENABLE */
#define DP_OPTION_QSE_ENABLED 1 /* Remove here when QSE p4r check-in */
//
// If a message is outstanding for at least 4 seconds
// assume no reply is coming through
@@ -77,6 +67,9 @@
#define HDCP_AUTHENTICATION_COOLDOWN_HPD 3000// 3 sec for first stream Add
#define HDCP_CPIRQ_RXSTATUS_COOLDOWN 20 // 20ms between attempts
#define HDCP_QSEANDSETECF_RETRIES 6 // 6 retries as authentication retires
#define HDCP_QSEANDSETECF_COOLDOWN 3000// 3 sec between attempts as authentication period
// Need to re-submit Stream Validation request to falcon microcontroller after 1 sec if current request fails
#define HDCP_STREAM_VALIDATION_RESUBMIT_COOLDOWN 1000
@@ -86,6 +79,12 @@
//
#define HDCP_STREAM_VALIDATION_REQUEST_COOLDOWN 8000
//
// Wait till 1 sec to check if still have active QSE message then send QSE message or queue
// to check next time. 1sec should be enough that sink reply QSE request.
//
#define HDCP_SEND_QSE_MESSAGE_COOLDOWN 1000
#define DPCD_OUI_NVIDIA 0x00044B
//

12
src/common/displayport/inc/dp_configcaps.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -742,7 +742,11 @@ namespace DisplayPort
//
bool linkStatusDirtied;
} laneStatusIntr;
struct
{
bool receiverPort0InSync;
bool receiverPort1InSync;
} sinkStatus; // DPCD offset 205
struct
{
bool testRequestTraining; // DPCD offset 218
@@ -1130,7 +1134,7 @@ namespace DisplayPort
void readLTTPRLinkStatus(NvS32 rxIndex, NvU8 *buffer);
void resetIntrLaneStatus();
void fetchLinkStatusESI();
virtual void fetchLinkStatusESI();
void fetchLinkStatusLegacy();
virtual bool readTraining(NvU8* voltageSwingLane, NvU8* preemphasisLane,
@@ -1504,7 +1508,7 @@ namespace DisplayPort
bool clearDpTunnelingEstimatedBwStatus();
bool clearDpTunnelingBwAllocationCapStatus();
virtual AuxRetry::status notifySDPErrDetectionCapability() { return AuxRetry::ack; }
virtual AuxRetry::status notifySDPErrDetectionCapability() { return AuxRetry::ack; }
virtual bool isDp2xChannelCodingCapable() { return false; }
virtual void setIgnoreCableIdCaps(bool bIgnore) { return; }
virtual void overrideCableIdCap(LinkRate linkRate, bool bEnable) { return; }

17
src/common/displayport/inc/dp_configcaps2x.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2024-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -73,7 +73,7 @@ namespace DisplayPort
bool bUHBR_20GSupported;
} dpInTunnelingCaps;
/*
/*
* Cable capabilities determined on the sink end
* read by source via DPCD
*/
@@ -86,7 +86,7 @@ namespace DisplayPort
bool bHandshakeCompleted;
} rxCableCaps;
/*
/*
* Cable capabilities determined on the source end
*/
struct
@@ -117,6 +117,13 @@ namespace DisplayPort
//
NvU32 sqNum; // DPCD offset 249
} testPhyCompliance2x;
struct
{
bool streamRegenerated;
bool interhopAuxReply;
} sinkStatus2x; // DPCD offset 205
} interrupts2x;
virtual AuxRetry::status notifySDPErrDetectionCapability();
@@ -130,6 +137,8 @@ namespace DisplayPort
virtual void setGpuDPSupportedVersions(NvU32 _gpuDPSupportedVersions);
virtual bool isDp2xChannelCodingCapable();
virtual void parseAndReadCaps();
virtual void fetchLinkStatusESI();
virtual LinkRate getMaxLinkRate();
virtual NvU32 getUHBRSupported();
virtual void setIgnoreCableIdCaps(bool bIgnore){ bIgnoreCableIdCaps = bIgnore; }
@@ -162,7 +171,7 @@ namespace DisplayPort
bool bIgnoreCableIdCaps;
bool bConnectorIsTypeC;
bool bCableVconnSourceUnknown;
virtual void initialize()
{
setIgnoreCableIdCaps(false);

22
src/common/displayport/inc/dp_connector.h
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@@ -105,6 +105,14 @@ namespace DisplayPort
connectorVGA
};
typedef enum
{
// Read DID2x first, then read EDID regardless of DID2x availability.
DISPLAYID2_MST_POLICY_DID2X_THEN_EDID = 0,
// Read DID2x first, then read EDID only if DID2x is not available.
DISPLAYID2_MST_POLICY_DID2X_ONLY = 1,
} DISPLAYID2_MST_POLICY;
typedef struct portMap
{
NvU16 validMap; // port i is valid = bit i is high
@@ -230,6 +238,8 @@ namespace DisplayPort
// Copies RawEDID into client buffer. Fails if the buffer is too small
virtual bool getRawEDID(char * buffer, unsigned size) const = 0;
virtual unsigned getDisplayId2xSize() const = 0;
virtual bool getDisplayId2x(char * buffer, unsigned size) const = 0;
virtual bool getPCONCaps(PCONCaps *pPCONCaps) = 0;
virtual bool isFallbackEdid() = 0; // is the device edid a fallback one?
@@ -384,6 +394,7 @@ namespace DisplayPort
virtual void destroy() = 0; // Destroy the group object
// Toggles the encryption status for the stream.
virtual bool hdcpSetEncrypted(bool encrypted, NvU8 streamType = NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_0, NvBool bForceClear = NV_FALSE, NvBool bAddStreamBack = NV_FALSE) = 0;
// Returns whether encryption is currently enabled.
virtual bool hdcpGetEncrypted() = 0;
@@ -669,6 +680,15 @@ namespace DisplayPort
//
virtual void setPolicyForceLTAtNAB(bool enabled) = 0;
//
// Set the policy of reading DID2x on MST devices.
// Valid values are 0-1.
// 0 - DID2x then EDID. - DPLib will read DID2x then EDID before reporting device to client.
// 1 - DID2x only. - DPLib will only read DID2x and ignore EDID.
// Default value is 0.
// All other values are reserved.
//
virtual void setDisplayId2MSTPolicy(DISPLAYID2_MST_POLICY policy) = 0;
//
// There are cases where OS does not detach heads from connector immediately after hot-unplug,
// on next hot-plug there is no guarantee that newly connected sink is capable to drive existing
@@ -722,6 +742,8 @@ namespace DisplayPort
virtual void resetDp11ProtocolForced() = 0;
virtual bool isDp11ProtocolForced() = 0;
// Operates at the Link Level. Causes reauthentication of the entire link.
virtual void hdcpRenegotiate(NvU64 cN, NvU64 cKsv) = 0;
virtual bool getHDCPAbortCodesDP12(NvU32 &hdcpAbortCodesDP12) = 0;
virtual bool getOuiSink(unsigned &ouiId, unsigned char * modelName,

64
src/common/displayport/inc/dp_connectorimpl.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -42,8 +42,11 @@
#include "dp_discovery.h"
#include "dp_groupimpl.h"
#include "dp_deviceimpl.h"
#include "dp_qse.h"
#include "./dptestutil/dp_testmessage.h"
#include "dp_displayid2.h"
// HDCP abort codes
#define HDCP_FLAGS_ABORT_DEVICE_REVOKED 0x00000800 // Abort due to a revoked device in DP1.2 topology
#define HDCP_FLAGS_ABORT_DEVICE_INVALID 0x00080000 // Abort due to an invalid device in DP1.2 topology
@@ -72,6 +75,8 @@ static inline unsigned getDataClockMultiplier(NvU64 linkRate, NvU64 laneCount)
namespace DisplayPort
{
class QSENonceGenerator;
typedef enum
{
DP_TRANSPORT_MODE_INIT = 0,
@@ -137,6 +142,7 @@ namespace DisplayPort
bool bPConConnected; // HDMI2.1-Protocol Converter (Support SRC control mode) connected.
bool bSkipAssessLinkForPCon; // Skip assessLink() for PCON. DD will call assessFRLLink later.
bool bHdcpAuthOnlyOnDemand; // True if only initiate Hdcp authentication on demand and MST won't auto-trigger authenticate at device attach.
bool bMstRestoreHdcpStateAtAttach; // True if restore previous HDCP state at attach
bool bHdcpStrmEncrEnblOnlyOnDemand; // True if only initiate Hdcp Stream Encryption Enable on demand and MST won't auto-trigger.
bool bReassessMaxLink; // Retry assessLink() if the first assessed link config is lower than the panel max config.
@@ -252,8 +258,20 @@ namespace DisplayPort
List pendingEdidReads; // List of DevicePendingEDIDRead structures.
// This list tracks the currently in progress MST Edid Reads
List pendingDid2Reads; // List of DevicePendingDID2Read structures.
// This list tracks the currently in progress MST Did2 Reads
Device * lastDeviceSetForVbios;
QSENonceGenerator * qseNonceGenerator;
// Tells whether requests made by library to Downstream Device (i.e QSE messages sent to Branch Device) and RM
// (i.e KSV validation and Stream Validation requests sent by library to RM after getting QSE message reply from Downstream)
// during querying stream status is valid or not.
bool bValidQSERequest;
ListElement * message; // Outstanding QSE message pointer for which Stream Validation submission failed.
NvU8 * clientId; // ClientId of the group for which Stream Validation submission failed.
// Flag which gets set when ACPI init is done. DD calls notifyAcpiInitDone to tell client that ACPI init is completed
// & client can now initiate DDC EDID read for a device which supports EDID through SBIOS
bool bAcpiInitDone;
@@ -261,12 +279,6 @@ namespace DisplayPort
// Flag to check if the system is UEFI.
bool bIsUefiSystem;
//
// Flag to enable accounting available DP tunnelling BW while generating PPS
// for the mode
//
bool bOptimizeDscBppForTunnellingBw;
//
// Flag to minimize link config for SST if it is 128b/132b.
// Enables gR-3336 if set.
@@ -342,6 +354,12 @@ namespace DisplayPort
//
bool bForceHeadShutdownOnModeTransition;
// Use max DSC compression for MST topologies
bool bUseMaxDSCCompressionMST;
// Flag to tell whether to send QSE after stream encryption on
bool bIsEncryptionQseValid;
bool bReportDeviceLostBeforeNew;
bool bDisableSSC;
bool bEnableFastLT;
@@ -362,9 +380,6 @@ namespace DisplayPort
bool bForceHeadShutdownPerMonitor;
// Use max DSC compression for MST topologies
bool bUseMaxDSCCompressionMST;
// Enable stats collection for compoundQueryAttach()
bool bEnableCqaStatsCollection;
NvU64 cqaStatsMinUs = static_cast<NvU64>(-1);
@@ -417,6 +432,9 @@ namespace DisplayPort
// Use regkey DP_DSC_DEVID_WAR to toggle this flag.
bool bEnableDevId;
// To skip NLP similar to fakeMuxDevice on non-DSC DDS
bool bIgnoreUnplugUnlessRequested;
Group *perHeadAttachedGroup[NV_MAX_HEADS];
NvU32 inTransitionHeadMask;
@@ -426,15 +444,24 @@ namespace DisplayPort
void setPolicyForceLTAtNAB(bool enabled);
void setPolicyAssessLinkSafely(bool enabled);
void setDisplayId2MSTPolicy(DISPLAYID2_MST_POLICY policy) { return; };
virtual void discoveryNewDevice(const DiscoveryManager::Device &device);
bool bDisableNativeDisplayId2xSupport;
void discoveryDetectComplete();
void discoveryNewDevice(const DiscoveryManager::Device &device);
void discoveryLostDevice(const Address &address);
void processNewDevice(const DiscoveryManager::Device &device,
const Edid &edid,
bool isMultistream,
DwnStreamPortType portType,
DwnStreamPortAttribute portAttribute,
bool isCompliance = false);
struct ProcessNewDeviceParams {
const DiscoveryManager::Device &device;
const Edid &edid;
const DisplayID2x &displayId2x;
bool isMultistream;
DwnStreamPortType portType;
DwnStreamPortAttribute portAttribute;
bool isCompliance;
};
void processNewDevice(const ProcessNewDeviceParams &params);
void applyEdidWARs(Edid &edid, DiscoveryManager::Device &device);
virtual void handleEdidWARs(Edid &edid, DiscoveryManager::Device &device){};
@@ -564,6 +591,7 @@ namespace DisplayPort
char tagHDCPReauthentication;
char tagDelayedHdcpCapRead;
char tagDelayedHDCPCPIrqHandling;
char tagSendQseMessage;
char tagDpBwAllocationChanged;
char tagHDCPStreamEncrEnable;
@@ -706,6 +734,8 @@ namespace DisplayPort
virtual bool allocateTimeslice(GroupImpl * targetGroup);
void freeTimeslice(GroupImpl * targetGroup);
void flushTimeslotsToHardware();
void hdcpRenegotiate(NvU64 cN, NvU64 cKsv);
void hdcpActiveGroupsSetECF();
bool getHDCPAbortCodesDP12(NvU32 &hdcpAbortCodesDP12);
bool getOuiSink(unsigned &ouiId, unsigned char * modelName, size_t modelNameBufferSize, NvU8 &chipRevision);
bool hdcpValidateKsv(const NvU8 *ksv, NvU32 Size);

34
src/common/displayport/inc/dp_connectorimpl2x.h
View File

@@ -96,7 +96,16 @@ namespace DisplayPort
bool bMstTimeslotBug4968411;
bool bApplyManualTimeslotBug4968411;
//
// Set the policy of reading DID2x on MST devices.
// Valid values are 0-1.
// 0 - DID2X then EDID. (Read DID2x first, then read EDID regardless of DID2x availability before reporting device to client.)
// 1 - DID2X only. (Read DID2x first, then read EDID only if DID2x is not available.)
// Default value is 0.
//
DISPLAYID2_MST_POLICY displayId2MSTPolicy;
void discoveryNewDevice(const DiscoveryManager::Device &device) override;
bool bApplyStuffDummySymbolsWAR;
bool bStuffDummySymbolsFor128b132b;
bool bStuffDummySymbolsFor8b10b;
@@ -150,12 +159,31 @@ namespace DisplayPort
}
virtual ~WatermarkCacheElement() = default;
unsigned int hash() const override;
bool isEqual(const HashMapElement *other) const override;
unsigned int hash() const override;
bool isEqual(const HashMapElement *other) const override;
};
HashMap m_watermarkCache;
};
//
// New devices may not get a DeviceImpl created until after the Did2 read has completed.
// This object is used to track the necessary state.
//
struct DevicePendingDID2Read : protected DID2ReadMultistream::DID2ReadMultistreamEventSink, public ListElement
{
ConnectorImpl2x * parent;
DiscoveryManager::Device device;
DID2ReadMultistream reader;
void mstDid2Completed(DID2ReadMultistream * from);
void mstDid2ReadFailed(DID2ReadMultistream * from);
public:
DevicePendingDID2Read(ConnectorImpl2x * _parent, MessageManager * manager, DiscoveryManager::Device dev)
: parent(_parent), device(dev), reader(_parent->timer, manager, this, dev.address)
{
}
};
}
#endif //INCLUDED_DP_CONNECTORIMPL2X_H

7
src/common/displayport/inc/dp_deviceimpl.h
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@@ -34,7 +34,9 @@
#include "dp_edid.h"
#include "dp_list.h"
#include "dp_auxdefs.h"
#include "dp_qse.h"
#include "dp_vrr.h"
#include "dp_displayid2.h"
namespace DisplayPort
{
@@ -121,6 +123,8 @@ namespace DisplayPort
Edid rawEDID;
Edid processedEdid;
Edid ddcEdid;
DisplayID2x displayId2x;
DPCDHAL * hal;
GroupImpl * activeGroup;
ConnectorImpl * connector;
@@ -202,6 +206,7 @@ namespace DisplayPort
TriState bSdpExtCapable;
TriState bAsyncSDPCapable;
bool bMSAOverMSTCapable;
bool bDscPassThroughColorFormatWar;
@@ -219,6 +224,8 @@ namespace DisplayPort
virtual unsigned getRawEDIDSize() const;
virtual bool getRawEDID(char * buffer, unsigned size) const;
virtual unsigned getDisplayId2xSize() const;
virtual bool getDisplayId2x(char * buffer, unsigned size) const;
virtual bool getPCONCaps(PCONCaps *pPCONCaps);
virtual Group * getOwningGroup()

5
src/common/displayport/inc/dp_discovery.h
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@@ -34,6 +34,8 @@
#include "dp_list.h"
#include "dp_messages.h"
#include "dp_messagecodings.h"
#include "dp_edid.h"
#include "dp_displayid2.h"
namespace DisplayPort
{
@@ -57,6 +59,9 @@ namespace DisplayPort
bool videoSink; // Should be true when a video sink is supported
NvU64 maxTmdsClkRate;
DisplayID2x displayId2x;
Edid edid;
Device():peerDevice(None),SDPStreams(0),SDPStreamSinks(0),dirty(false),videoSink(false),maxTmdsClkRate(0)
{
portMap.validMap = portMap.inputMap = portMap.internalMap = 0;

186
src/common/displayport/inc/dp_displayid2.h Normal file
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@@ -0,0 +1,186 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort *******************************\
* *
* Module: dp_did2.h *
* reading DisplayID2x from SST/MST Device *
* *
\***************************************************************************/
#ifndef INCLUDED_DP_DID2_H
#define INCLUDED_DP_DID2_H
#include "dp_buffer.h"
#include "dp_auxbus.h"
#include "dp_timer.h"
#include "dp_messages.h"
#include "dp_messagecodings.h"
#define NV_DISPLAYID2_BLOCK_SIZE 0x80
#define NV_DISPLAYID2_MAX_RETRIES 0x03
#define NV_DISPLAYID2_DDC_ADDRESS 0xA4
#define NV_DISPLAYID2_DDC_SEG_SELECTOR_OFFSET 0x60
#define NV_DISPLAYID2_MAX_BLOCK_COUNT 16
#define NV_DISPLAYID2_IDX_STRUCTURE_VERSION 0x00
#define NV_DISPLAYID2_STRUCTURE_VERSION_V20 0x20
#define NV_DISPLAYID2_IDX_BYTES_IN_SECTION 0x01
#define NV_DISPLAYID2_SECTION_SIZE_MIN 0x05
#define NV_DISPLAYID2_SECTION_SIZE_MAX 0x100
#define NV_DISPLAYID2_BYTES_IN_SECTION_MIN 0x00
#define NV_DISPLAYID2_BYTES_IN_SECTION_MAX 0xFB
#define NV_DISPLAYID2_IDX_EXTENSION_COUNT 0x03
#define NV_DISPLAYID2_EXTENSION_COUNT_RESERVED 0x00
#define NV_DISPLAYID2_EXTENSION_COUNT_MIN 0x00
#define NV_DISPLAYID2_EXTENSION_COUNT_MAX 0xFF
#define IS_VALID_DISPLAYID2_VERSION(pSection) \
(pSection[NV_DISPLAYID2_IDX_STRUCTURE_VERSION] == \
NV_DISPLAYID2_STRUCTURE_VERSION_V20)
#define GET_DISPLAYID2_SECTION_LENGTH(pSection) \
(NV_DISPLAYID2_SECTION_SIZE_MIN + \
pSection[NV_DISPLAYID2_IDX_BYTES_IN_SECTION])
#define GET_DISPLAYID2_EXTENSION_COUNT(pSection) \
(pSection[NV_DISPLAYID2_IDX_EXTENSION_COUNT])
namespace DisplayPort
{
class DisplayID2x
{
public:
DisplayID2x();
~DisplayID2x();
NvU32 getDisplayId2xSize() const { return displayId2xSize; }
void setDisplayId2xSize(NvU32 length) { displayId2xSize = length; }
NvU8 getBlockCount() const { return blockCount; }
void setBlockCount(NvU8 count) { blockCount = count; }
Buffer * getBuffer() const { return &buffer; }
bool operator== (const DisplayID2x & other)
{
return (buffer == other.buffer);
}
bool operator!= (const DisplayID2x & other)
{
return !(buffer == other.buffer);
}
private:
mutable Buffer buffer;
NvU8 blockCount;
NvU32 displayId2xSize;
};
bool DisplayId2ReadSST(DisplayID2x & displayId2x, AuxBus * aux, Timer * timer, MainLink *main = NULL);
bool DisplayId2ReadMST(DisplayID2x & displayId2x, AuxBus * aux, Timer * timer, MainLink *main = NULL);
NvU8 getDID2BlockChecksum(NvU8 * buffer, NvU8 size);
const NvU8 NV_DISPLAYID2_READ_RETRY_MS = 100;
const NvU8 NV_DISPLAYID2_MAX_AUX_RETRIES = 10;
const NvU8 NV_DISPLAYID2_AUX_WAIT_TIME = 1;
//
// MST DID2x Read API
//
class DID2ReadMultistream : public Object, protected MessageManager::Message::MessageEventSink, Timer::TimerCallback
{
public:
class DID2ReadMultistreamEventSink // Connector will inherit from this
{
public:
virtual void mstDid2Completed(DID2ReadMultistream * from) = 0;
virtual void mstDid2ReadFailed(DID2ReadMultistream * from) = 0;
};
DID2ReadMultistream(Timer * timer, MessageManager * manager, DID2ReadMultistream::DID2ReadMultistreamEventSink * sink, Address topologyAddress)
: topologyAddress(topologyAddress), manager(manager),
retries(0), timer(timer), sink(sink), stream(displayId2x.getBuffer())
{
startReadingDid2();
}
DisplayID2x displayId2x;
Address topologyAddress;
~DID2ReadMultistream();
private:
void startReadingDid2();
MessageManager * manager;
RemoteI2cReadMessage remoteI2cRead;
unsigned retries;
Timer * timer;
void readNextBlock();
bool readNextRequest();
void failedToReadDid2();
void expired(const void * tag);
DID2ReadMultistreamEventSink * sink;
virtual void messageFailed(MessageManager::Message * from, NakData * nakData);
virtual void messageCompleted(MessageManager::Message * from);
void did2AttemptDone(bool succeeded);
Stream stream;
// Number of times the sections are read. Note the section might not be aligned to 128 bytes.
NvU8 loop;
// Number of bytes already read but not yet processed.
NvU32 remainingBytes;
// Pointer to the current section of the DisplayID2x
NvU8 *pSection;
// Length of the current section of the DisplayID2x
NvU8 sectionLength;
// Number of extension blocks. Only valid for the base section.
NvU8 extensionCount;
// Size of the DisplayID2x blocks that are already completed.
NvU32 displayId2xSize;
bool retried;
};
}
#endif

8
src/common/displayport/inc/dp_evoadapter.h
View File

@@ -181,6 +181,7 @@ namespace DisplayPort
unsigned maxNumHztSlices;
unsigned lineBufferBitDepth;
}_DSC;
NV0073_CTRL_SPECIFIC_HDCP_CTRL_PARAMS paramsHdcpCtrl;
void initializeRegkeyDatabase();
void applyRegkeyOverrides();
@@ -371,6 +372,13 @@ namespace DisplayPort
virtual bool dscCrcTransaction(NvBool bEnable, gpuDscCrc *data, NvU16 *headIndex);
void triggerACT();
void configureAndTriggerECF(NvU64 ecf, NvBool bForceClearEcf = NV_FALSE, NvBool bAddStreamBack = NV_FALSE); // This function program as well as trigger ECF on branch devices.
virtual void disableAlternateScramblerReset();
void configureHDCPDisableAuthentication();
void configureHDCPAbortAuthentication(AbortAuthReason abortAuthReason);
bool setStreamType(unsigned streamIndex, NvU8 streamType, bool * bNeedReNegotiate);
void configureHDCPValidateLink(HDCPValidateData &hdcpValidateData, NvU64 cN = HDCP_DUMMY_CN, NvU64 cKsv = HDCP_DUMMY_CKSV);
void forwardPendingKsvListReady(NvBool bKsvListReady);
void configureHDCPRenegotiate(NvU64 cN = HDCP_DUMMY_CN, NvU64 cKsv = HDCP_DUMMY_CKSV, bool bForceReAuth = false,
bool bRxIDMsgPending = false);
void configureHDCPGetHDCPState(HDCPState &hdcpState);

3
src/common/displayport/inc/dp_evoadapter2x.h
View File

@@ -107,7 +107,6 @@ namespace DisplayPort
bool bSupportUHBR2_50; // Support UHBR2.5 for internal testing.
bool bSupportUHBR2_70; // Support UHBR2.7 for internal testing.
bool bSupportUHBR5_00; // Support UHBR5.0 for internal testing.
bool bEnable5147205Fix; // Enable 5147205 fix.
bool bConnectorIsUSBTypeC;
bool bCableVconnSourceUnknown;
@@ -149,7 +148,7 @@ namespace DisplayPort
virtual bool clearFlushMode(FlushModePhase phase, NvU32 attachFailedHeadMask = 0, NvU32 headIndex = 0);
virtual bool isRgFlushSequenceUsed() {return bUseRgFlushSequence;}
void applyDP2xRegkeyOverrides();
virtual NvU32 headToStream(NvU32 head, bool bSidebandMessageSupported,
virtual NvU32 headToStream(NvU32 head, bool bSidebandMessageSupported,
DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
// Link Rate will return the value with 10M convention!

21
src/common/displayport/inc/dp_groupimpl.h
View File

@@ -37,11 +37,14 @@
namespace DisplayPort
{
class StreamEncryptionStatusDetection;
struct GroupImpl : public Group, ListElement, Timer::TimerCallback
{
ConnectorImpl * parent;
LinkedList<Device> members;
StreamEncryptionStatusDetection * streamEncryptionStatusDetection;
NvU8 clientId[CLIENT_ID_SIZE];
List elements;
unsigned headIndex;
unsigned streamIndex;
@@ -50,6 +53,7 @@ namespace DisplayPort
bool bIsHeadShutdownNeeded; // Set if head shutdown is requested during modeset
bool hdcpEnabled;
bool hdcpPreviousStatus;
bool qseEncryptionStatusMismatch;
bool bWaitForDeAllocACT;
bool bDeferredPayloadAlloc;
ModesetInfo lastModesetInfo;
@@ -75,6 +79,7 @@ namespace DisplayPort
bIsHeadShutdownNeeded(true),
hdcpEnabled(false),
hdcpPreviousStatus(false),
qseEncryptionStatusMismatch(false),
bWaitForDeAllocACT(false),
dscModeRequest(DSC_MODE_NONE),
dscModeActive(DSC_MODE_NONE),
@@ -82,11 +87,22 @@ namespace DisplayPort
singleHeadMultiStreamMode(DP_SINGLE_HEAD_MULTI_STREAM_MODE_NONE),
headAttached(false), timeslotAllocated(false)
{
if (isFirmwareGroup)
streamEncryptionStatusDetection = 0;
else
{
streamEncryptionStatusDetection = new StreamEncryptionStatusDetection(this, parent);
}
timeslot.count = 0;
}
~GroupImpl()
{
if (streamEncryptionStatusDetection)
{
delete streamEncryptionStatusDetection;
streamEncryptionStatusDetection = 0;
}
}
virtual void insert(Device * dev);
@@ -104,9 +120,14 @@ namespace DisplayPort
char tagHDCPReauthentication;
char tagStreamValidation;
char tagMSTQSEandSetECF;
unsigned QSESetECFRetries; // Retry counter for MST QSE and set ECF.
virtual void hdcpMSTQSEandSetECF();
unsigned authRetries; // Retry counter for the authentication.
virtual void expired(const void * tag);
virtual bool hdcpSetEncrypted(bool encrypted, NvU8 streamType = NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_0, NvBool bForceClear = NV_FALSE, NvBool bAddStreamBack = NV_FALSE);
virtual bool hdcpGetEncrypted();
virtual void destroy();
void cancelHdcpCallbacks();

3
src/common/displayport/inc/dp_linkconfig.h
View File

@@ -242,6 +242,9 @@ namespace DisplayPort
struct HDCPValidateData
{
NvU8 vP[NV0073_CTRL_HDCP_VPRIME_SIZE];
NvU64 aN;
NvU64 mP;
};
typedef enum

12
src/common/displayport/inc/dp_mainlink.h
View File

@@ -226,6 +226,18 @@ namespace DisplayPort
// HDCP Renegotiate and trigger ACT.
//
virtual void configureHDCPRenegotiate(NvU64 cN = HDCP_DUMMY_CN, NvU64 cKsv = HDCP_DUMMY_CKSV, bool bForceReAuth = false, bool bRxIDMsgPending = false) = 0;
// HDCP set ECF
virtual void configureAndTriggerECF(NvU64 ecf, NvBool bForceClearEcf = NV_FALSE, NvBool bAddStreamBack = NV_FALSE) = 0;
//
// Enable of disable alternate scrambler SR (ASSR)
//
// (used for embedded displayport)
virtual void disableAlternateScramblerReset() = 0;
virtual void configureHDCPDisableAuthentication() = 0;
virtual void configureHDCPAbortAuthentication(AbortAuthReason abortAuthReason) = 0;
virtual bool setStreamType(unsigned streamIndex, NvU8 streamType, bool * bNeedReNegotiate) = 0;
virtual void configureHDCPValidateLink(HDCPValidateData &hdcpValidateData, NvU64 cN = HDCP_DUMMY_CN, NvU64 cKsv = HDCP_DUMMY_CKSV) = 0;
virtual void forwardPendingKsvListReady(NvBool bKsvListReady) = 0;
virtual void triggerACT() = 0;
virtual void configureHDCPGetHDCPState(HDCPState &hdcpState) = 0;

100
src/common/displayport/inc/dp_messagecodings.h
View File

@@ -133,6 +133,7 @@ namespace DisplayPort
{
StreamUnconnected = 0,
NonAuthLegacyDevice = 1, // TV or CRT
Non12CPOrNonQSE = 2, // DVI/HDMI or DP 1.1 sink/repeater
DP_MST = 4
}OutputSinkType;
@@ -558,6 +559,105 @@ namespace DisplayPort
SinkEventNotifyMessage(MessageReceiverEventSink * sink, unsigned requestId);
};
//
// QUERY_STREAM_ENCRYPTION_STATUS 0x38
//
class QueryStreamEncryptionMessage : public MessageManager::Message
{
virtual ParseResponseStatus parseResponseAck(EncodedMessage * message,
BitStreamReader * reader);
private:
struct QSES_REPLY
{
StreamState streamState;
bool repeaterFuncPresent;
bool encryption;
bool authentication;
OutputSinkType sinkType;
OutputCPType cpType;
bool signedLPrime;
NvU8 streamId;
} reply;
bool bIsHdcp22Qse;
public:
QueryStreamEncryptionMessage() :
Message(NV_DP_SBMSG_REQUEST_ID_QUERY_STREAM_ENCRYPTION_STATUS,
NV_DP_SBMSG_PRIORITY_LEVEL_DEFAULT)
{
dpMemZero(&reply, sizeof(reply));
bIsHdcp22Qse = false;
}
void set(const Address & target,
unsigned streamId,
NvU8* clientId,
StreamEvent streamEvent,
bool streamEventMask,
StreamBehavior streamBehavior,
bool streamBehaviorMask);
NvU8 getStreamId()
{
return reply.streamId;
}
void getReply(void *p)
{
*(struct QSES_REPLY *)p = reply;
}
NvU16 getStreamStatus()
{
NvU16 streamStatus = 0;
streamStatus = (NvU16)reply.streamState;
if (reply.repeaterFuncPresent)
streamStatus |= 1 << (1 ? NV_DP_HDCP_STREAM_REPEATER);
if (reply.encryption)
streamStatus |= 1 << (1 ? NV_DP_HDCP_STREAM_ENCRYPTION);
if (reply.authentication)
streamStatus |= 1 << (1 ? NV_DP_HDCP_STREAM_AUTHENTICATION);
if (reply.sinkType != StreamUnconnected)
{
if (reply.sinkType & DP_MST)
{
streamStatus |= 1 << (1 ? NV_DP_HDCP_STREAM_OUTPUT_SINK_MULTI);
}
if (reply.sinkType & Non12CPOrNonQSE)
{
streamStatus |= 1 << (1 ? NV_DP_HDCP_STREAM_OUTPUT_SINK_NON_DP1_2_CP);
}
if (reply.sinkType & NonAuthLegacyDevice)
{
streamStatus |= 1 << (1 ? NV_DP_HDCP_STREAM_OUTPUT_SINK_LEGACY);
}
}
if (reply.cpType == HDCP1x)
{
streamStatus |= 1 << (1 ? NV_DP_HDCP_STREAM_OUTPUT_CP_TYPE_HDCP1X);
}
else if (reply.cpType == HDCP2x)
{
streamStatus |= 1 << (1 ? NV_DP_HDCP_STREAM_OUTPUT_CP_TYPE_HDCP2X);
}
return streamStatus;
}
void setHdcp22Qse(bool bHdcp22Qse)
{
bIsHdcp22Qse = bHdcp22Qse;
}
};
}
#endif //INCLUDED_DP_MESSAGECODINGS_H

52
src/common/displayport/inc/dp_messages.h
View File

@@ -153,6 +153,58 @@ namespace DisplayPort
mergerDownReply.mailboxInterrupt();
}
void clearNotYetSentQSEDownRequest()
{
for (ListElement * i = notYetSentDownRequest.begin(); i!=notYetSentDownRequest.end(); )
{
Message * m = (Message *)i;
i = i->next; // Do this first since we may unlink the current node
if (m->requestIdentifier ==
NV_DP_SBMSG_REQUEST_ID_QUERY_STREAM_ENCRYPTION_STATUS)
{
notYetSentDownRequest.remove(m);
m->parent = 0;
}
}
}
bool isAnyAwaitingQSEReplyDownRequest()
{
bool bQSEAwaiting = false;
for (ListElement * i = awaitingReplyDownRequest.begin(); i!=awaitingReplyDownRequest.end(); )
{
Message * m = (Message *)i;
i = i->next; // Do this first since we may unlink the current node
if (m->requestIdentifier ==
NV_DP_SBMSG_REQUEST_ID_QUERY_STREAM_ENCRYPTION_STATUS)
{
// We break because there could be only one outstanding QSE message at any time.
bQSEAwaiting = true;
break;
}
}
return bQSEAwaiting;
}
void clearAwaitingQSEReplyDownRequest()
{
for (ListElement * i = awaitingReplyDownRequest.begin(); i!=awaitingReplyDownRequest.end(); )
{
Message * m = (Message *)i;
i = i->next; // Do this first since we may unlink the current node
if (m->requestIdentifier ==
NV_DP_SBMSG_REQUEST_ID_QUERY_STREAM_ENCRYPTION_STATUS)
{
awaitingReplyDownRequest.remove(m);
m->parent = 0;
break;
}
}
}
MessageManager(DPCDHAL * hal, Timer * timer)
: timer(timer), hal(hal),
splitterDownRequest(hal, timer),

73
src/common/displayport/inc/dp_qse.h
View File

@@ -33,4 +33,77 @@
#include "dp_messagecodings.h"
#include "dp_auxdefs.h"
namespace DisplayPort
{
#define CLIENT_ID_SIZE 7
struct CLIENTID
{
NvU8 data[CLIENT_ID_SIZE];
CLIENTID()
{
dpMemZero(&data, sizeof(data));
}
};
enum QSE_REASON
{
qseReason_Generic,
qseReason_Ssc
};
class QSENonceGenerator: public Object
{
NvU32 previousRandomLSB;
NvU32 previousRandomMSB;
//
// Linear congruential random number generator
// Seed values chosen from numerical methods
//
NvU64 random();
public:
QSENonceGenerator():previousRandomLSB(0),previousRandomMSB(0)
{}
void clientIdBuilder(NvU64 aN);
// For every clientId generation we need to call makeClientId
void makeClientId(CLIENTID & clientId);
};
struct GroupImpl;
struct ConnectorImpl;
class StreamEncryptionStatusDetection : public Object, public MessageManager::Message::MessageEventSink, Timer::TimerCallback
{
GroupImpl * parent;
ConnectorImpl * connector;
QueryStreamEncryptionMessage qseMessage;
unsigned retriesSendQSEMessage;
QSE_REASON reason;
bool bIsHdcp22Qse;
bool bIsRepeater;
public:
StreamEncryptionStatusDetection(GroupImpl * parent, ConnectorImpl * connector):
parent(parent), connector(connector), retriesSendQSEMessage(0), bIsHdcp22Qse(false), bIsRepeater(false)
{}
~StreamEncryptionStatusDetection();
void sendQSEMessage(GroupImpl * group, QSE_REASON reasonId = qseReason_Generic);
void handleQSEDownReply();
void messageFailed(MessageManager::Message * from, NakData * nakData);
void messageCompleted(MessageManager::Message * from);
void expired(const void * tag);
bool handleQSEReplyValidation();
void resetQseMessageState();
void setHdcp22Qse(bool bHdcp22Qse);
};
struct DeviceImpl;
}
#endif // INCLUDED_DP_QSE_H

18
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,6 +34,7 @@
#include "dp_auxdefs.h"
// Regkey Names
#define NV_DP_REGKEY_DISABLE_QSES "DISABLE_QSES"
#define NV_DP_REGKEY_OVERRIDE_DPCD_REV "OVERRIDE_DPCD_REV"
#define NV_DP_REGKEY_DISABLE_SSC "DISABLE_SSC" // SSC (Stream Status Changed)
#define NV_DP_REGKEY_ENABLE_FAST_LINK_TRAINING "ENABLE_FAST_LINK_TRAINING"
@@ -48,6 +49,7 @@
#define NV_DP_REGKEY_DISABLE_DSC "DISABLE_DSC"
#define NV_DP_REGKEY_SKIP_ASSESSLINK_FOR_EDP "HP_WAR_2189772"
#define NV_DP_REGKEY_MST_AUTO_HDCP_AUTH_AT_ATTACH "DP_MST_AUTO_HDCP_AUTH_AT_ATTACH"
#define NV_DP_REGKEY_MST_RESTORE_HDCP_AT_ATTACH_SKIPPED "DP_MST_RESTORE_HDCP_AT_ATTACH_SKIPPED"
#define NV_DP_REGKEY_ENABLE_MSA_OVER_MST "ENABLE_MSA_OVER_MST"
#define NV_DP_REGKEY_DISABLE_DOWNSPREAD "DISABLE_DOWNSPREAD"
@@ -98,7 +100,6 @@
// Bug 4793112 : On eDP panel, do not cache source OUI if it reads zero
#define NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE "DP_SKIP_ZERO_OUI_CACHE"
#define NV_DP_REGKEY_ENABLE_FIX_FOR_5147205 "DP_ENABLE_5147205_FIX"
// Bug 5088957 : Force head shutdown in DpLib
#define NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN "DP_WAR_5088957"
@@ -112,12 +113,11 @@
#define NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC "DP_IGNORE_CAPS_AND_FORCE_HIGHEST_LC_WAR"
// This regkey ensures DP IMP takes DP tunnelling BW into account while calculating DSC BPP
#define NV_DP_REGKEY_OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW "OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW"
// This regkey disables GR-3336 that disables minimizing link config if it is 128b/132b.
#define NV_DP_REGKEY_ENABLE_128b132b_DSC_LNK_CFG_REDUCTION "ENABLE_128b132b_DSC_LNK_CFG_REDUCTION"
#define NV_DP_REGKEY_ENABLE_128b132b_DSC_LNK_CFG_REDUCTION "ENABLE_128b132b_DSC_LNK_CFG_REDUCTION"
#define NV_DP_REGKEY_DISABLE_NATIVE_DISPLAYID2X_SUPPORT "DISABLE_NATIVE_DISPLAYID2X_SUPPORT"
#define NV_DP_REGKEY_FORCE_NLPIGNORE_DDS "DP_FORCE_NLPIGNORE_DDS"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -129,6 +129,7 @@ struct DP_REGKEY_DATABASE
{
bool bInitialized; // set to true after the first EvoMainLink instance is constructed
// Below are regkey values
bool bQsesDisabled;
NvU32 dpcdRevOveride;
bool bSscDisabled;
bool bFastLinkTrainingEnabled;
@@ -142,6 +143,7 @@ struct DP_REGKEY_DATABASE
bool bDscDisabled;
bool bAssesslinkForEdpSkipped;
bool bMstAutoHdcpAuthAtAttach;
bool bMstRestoreHdcpAtAttachSkipped;
bool bMsaOverMstEnabled;
bool bOptLinkKeptAlive;
bool bOptLinkKeptAliveMst;
@@ -159,14 +161,14 @@ struct DP_REGKEY_DATABASE
bool bDisableAvoidHBR3War;
bool bCableVconnSourceUnknownWar;
bool bSkipZeroOuiCache;
bool bEnable5147205Fix;
bool bForceHeadShutdown;
bool bEnableDevId;
bool bEnableCqaStatsCollection;
bool bIgnoreCapsAndForceHighestLc;
bool bOptimizeDscBppForTunnellingBw;
bool bEnable128b132bDSCLnkCfgReduction;
bool bDisableNativeDisplayId2xSupport;
bool bUseMaxDSCCompressionMST;
bool bIgnoreUnplugUnlessRequested;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;

68
src/common/displayport/inc/dptestutil/dp_testmessage.h
View File

@@ -31,6 +31,9 @@
#include "dp_auxdefs.h"
#define DP_TESTMESSAGE_QSES 0x38
#include "dp_qse.h"
#include "dp_connector.h"
#define DP_LPRIME_SIZE 20
@@ -48,8 +51,59 @@ namespace DisplayPort
// Request type enum.
typedef enum
{
DP_TESTMESSAGE_REQUEST_TYPE_QSES, // TestMessage from DPTestUtil.
} DP_TESTMESSAGE_REQUEST_TYPE;
//
// NVAPI QSES reply message struct.
// Do NOT inherit any class, need keep consist with definition with Nvapi part,
// which is C STRUCT
//
typedef struct
{
StreamState streamState;
bool repeaterFuncPresent;
bool encryption;
bool authentication;
OutputSinkType sinkType;
OutputCPType cpType;
bool signedLPrime;
NvU8 streamId;
NvU8 LPrime[DP_LPRIME_SIZE];
} DP_TESTMESSAGE_REQUEST_QSES_OUTPUT;
//
// Version of QSES_OUTPUT that consistent with struct in dp_messageencodings.h
// ( without QSES Lprime).
//
// Considering nvapi backward compatibility, don't modify DP_TESTMESSAGE_REQUEST_QSES_OUTPUT
// definition but has internal version to sync up with dplib implementation.
//
// DPLib message implementation is using this version for now. TestMessage
// need this structure to safely copy info from QSES message structure.
//
typedef struct
{
StreamState streamState;
bool repeaterFuncPresent;
bool encryption;
bool authentication;
OutputSinkType sinkType;
OutputCPType cpType;
bool signedLPrime;
NvU8 streamId;
} DP_TESTMESSAGE_REQUEST_QSES_OUTPUT_V2;
typedef struct
{
// indicated what status to get, for DP, user need fill this
DP_TESTMESSAGE_REQUEST_TYPE requestType;
// stream id for QSES to get, user need file this
NvU32 streamID;
// replay buffer
DP_TESTMESSAGE_REQUEST_QSES_OUTPUT reply;
} DP_TESTMESSAGE_REQUEST_QSES_INPUT;
class TestMessage;
struct ConnectorImpl;
@@ -83,6 +137,10 @@ namespace DisplayPort
{
switch (requestType)
{
case DP_TESTMESSAGE_REQUEST_TYPE_QSES:
{
return structSize == sizeof(DP_TESTMESSAGE_REQUEST_QSES_INPUT) ? true : false;
}
default:
return false;
}
@@ -92,8 +150,10 @@ namespace DisplayPort
// Data Structure for Generic Message.
NvU32 replyBytes;
void sendTestMsgQSES(void *pBuffer);
public:
DP_TESTMESSAGE_REQUEST_QSES_OUTPUT_V2 qsesReply;
DP_TESTMESSAGE_REQUEST_STATUS testMessageStatus;
@@ -103,6 +163,14 @@ namespace DisplayPort
pConnector = 0;
pMsgManager = 0;
replyBytes = 0;
qsesReply.streamState = DoesNotExist;
qsesReply.repeaterFuncPresent = 0;
qsesReply.encryption = 0;
qsesReply.authentication = 0;
qsesReply.sinkType = StreamUnconnected;
qsesReply.cpType = HDCP1x;
qsesReply.signedLPrime = 0;
qsesReply.streamId = '\0';
}
DP_TESTMESSAGE_STATUS sendDPTestMessage(void *pBuffer,
NvU32 requestSize,

36
src/common/displayport/src/dp_configcaps.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1321,7 +1321,7 @@ AuxRetry::status DPCDHALImpl::setMessagingEnable(bool _uprequestEnable, bool _up
if (!bMultistream)
return AuxRetry::ack;
}
mstmCtrl = 0;
if (bMultistream)
@@ -1677,7 +1677,7 @@ void DPCDHALImpl::fetchLinkStatusESI()
{
NvU8 buffer[16] = {0};
NvS32 rxIndex;
MainLinkChannelCoding mainLinkChannelCoding = getMainLinkChannelCoding();
// LINK_STATUS_ESI from 0x200C to 0x200E
int bytesToRead = 3;
@@ -1687,9 +1687,6 @@ void DPCDHALImpl::fetchLinkStatusESI()
{
if (rxIndex != NV0073_CTRL_DP_DATA_TARGET_SINK)
{
// Ignore LTTPR Link Status for 128b/132b
if (mainLinkChannelCoding == ChannelCoding128B132B)
continue;
readLTTPRLinkStatus(rxIndex, &buffer[0xC]);
}
else
@@ -2136,17 +2133,12 @@ void DPCDHALImpl::payloadTableClearACT()
bool DPCDHALImpl::payloadWaitForACTReceived()
{
NvU8 byte = 0;
int retries = 0;
NvU8 byte = 0;
NvU8 timeoutSeconds = 1;
while (true)
Timeout timeout(timer, timeoutSeconds * 1000);
do
{
if (++retries > 40)
{
DP_PRINTF(DP_ERROR, "DPHAL> ACT Not received by sink device!");
return false;
}
if (AuxRetry::ack == bus.read(NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS, &byte, sizeof byte))
{
if (FLD_TEST_DRF(_DPCD, _PAYLOAD_TABLE_UPDATE_STATUS, _ACT_HANDLED, _YES, byte))
@@ -2155,7 +2147,19 @@ bool DPCDHALImpl::payloadWaitForACTReceived()
return true;
}
}
}
else
{
DP_PRINTF(DP_ERROR, "DPHAL> Read NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS failed.");
if (!auxAccessAvailable())
{
DP_PRINTF(DP_ERROR, "DPHAL> AUX access not available, cannot wait for ACT.");
return false;
}
}
timer->sleep(1); // 1ms
} while (timeout.valid());
return false;
}
bool DPCDHALImpl::payloadAllocate(unsigned streamId, unsigned begin, unsigned count)

74
src/common/displayport/src/dp_configcaps2x.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2024-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -896,3 +896,75 @@ MainLinkChannelCoding DPCDHALImpl2x::getMainLinkChannelCoding()
return ChannelCoding8B10B;
}
void DPCDHALImpl2x::fetchLinkStatusESI()
{
NvU8 buffer[16] = {0};
NvS32 rxIndex;
MainLinkChannelCoding mainLinkChannelCoding = getMainLinkChannelCoding();
// LINK_STATUS_ESI from 0x200C to 0x200F
int bytesToRead = 4;
// Reset all laneStatus to true.
resetIntrLaneStatus();
for (rxIndex = caps.phyRepeaterCount; rxIndex >= (NvS32) NV0073_CTRL_DP_DATA_TARGET_SINK; rxIndex--)
{
if (rxIndex != NV0073_CTRL_DP_DATA_TARGET_SINK)
{
// Ignore LTTPR Link Status for 128b/132b
if (mainLinkChannelCoding == ChannelCoding128B132B)
continue;
readLTTPRLinkStatus(rxIndex, &buffer[0xC]);
}
else
{
bus.read(NV_DPCD_LANE0_1_STATUS_ESI, &buffer[0xC], bytesToRead);
}
for (int lane = 0; lane < 4; lane++)
{
// lane0/1: buffer[0xC], lane2/3: buffer[0xD]
unsigned laneBits = buffer[0xC+lane/2];
if (lane % 2 == 0)
{
// lane0/2: _LANEX_XPLUS1_STATUS_ESI_LANEX
interrupts.laneStatusIntr.laneStatus[lane].clockRecoveryDone &=
FLD_TEST_DRF(_DPCD, _LANEX_XPLUS1_STATUS_ESI_LANEX, _CR_DONE, _YES, laneBits);
interrupts.laneStatusIntr.laneStatus[lane].channelEqualizationDone &=
FLD_TEST_DRF(_DPCD, _LANEX_XPLUS1_STATUS_ESI_LANEX, _CHN_EQ_DONE, _YES, laneBits);
interrupts.laneStatusIntr.laneStatus[lane].symbolLocked &=
FLD_TEST_DRF(_DPCD, _LANEX_XPLUS1_STATUS_ESI_LANEX, _SYMBOL_LOCKED, _YES, laneBits);
}
else
{
// lane1/3: _LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1
interrupts.laneStatusIntr.laneStatus[lane].clockRecoveryDone &=
FLD_TEST_DRF(_DPCD, _LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1, _CR_DONE, _YES, laneBits);
interrupts.laneStatusIntr.laneStatus[lane].channelEqualizationDone &=
FLD_TEST_DRF(_DPCD, _LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1, _CHN_EQ_DONE, _YES, laneBits);
interrupts.laneStatusIntr.laneStatus[lane].symbolLocked &=
FLD_TEST_DRF(_DPCD, _LANEX_XPLUS1_STATUS_ESI_LANEXPLUS1, _SYMBOL_LOCKED, _YES, laneBits);
}
}
// Buffer[0xE]: NV_DPCD_LANE_ALIGN_STATUS_UPDATED_ESI
interrupts.laneStatusIntr.interlaneAlignDone &=
FLD_TEST_DRF(_DPCD, _LANE_ALIGN_STATUS_UPDATED_ESI, _INTERLANE_ALIGN_DONE, _YES, buffer[0xE]);
interrupts.laneStatusIntr.downstmPortChng &=
FLD_TEST_DRF(_DPCD, _LANE_ALIGN_STATUS_UPDATED_ESI, _DOWNSTRM_PORT_STATUS_DONE, _YES, buffer[0xE]);
interrupts.laneStatusIntr.linkStatusUpdated &=
FLD_TEST_DRF(_DPCD, _LANE_ALIGN_STATUS_UPDATED_ESI, _LINK_STATUS_UPDATED, _YES, buffer[0xE]);
}
// Buffer[0xF]: NV_DPCD_SINK_STATUS_ESI
interrupts.sinkStatus.receiverPort0InSync =
FLD_TEST_DRF(_DPCD, _SINK_STATUS, _RECEIVE_PORT_0_STATUS, _IN_SYNC_YES, buffer[0xF]);
interrupts.sinkStatus.receiverPort1InSync =
FLD_TEST_DRF(_DPCD, _SINK_STATUS, _RECEIVE_PORT_1_STATUS, _IN_SYNC_YES, buffer[0xF]);
interrupts2x.sinkStatus2x.streamRegenerated =
FLD_TEST_DRF(_DPCD20, _SINK_STATUS, _STREAM_REGENERATED, _YES, buffer[0xF]);
interrupts2x.sinkStatus2x.interhopAuxReply =
FLD_TEST_DRF(_DPCD20, _SINK_STATUS, _INTRA_HOP_AUX_REPLY, _LTTPR, buffer[0xF]);
this->setDirtyLinkStatus(false);
}

720
src/common/displayport/src/dp_connectorimpl.cpp
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File diff suppressed because it is too large Load Diff

139
src/common/displayport/src/dp_connectorimpl2x.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -113,9 +113,7 @@ void ConnectorImpl2x::applyDP2xRegkeyOverrides()
this->bSupportUHBR5_00 = dpRegkeyDatabase.supportInternalUhbrOnFpga & NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_5_0G;
this->maxLinkRateFromRegkey = dpRegkeyDatabase.applyMaxLinkRateOverrides;
bSupportInternalUhbrOnFpga = dpRegkeyDatabase.supportInternalUhbrOnFpga;
// Disabling watermark caching by default on 590 irrespective of the regkey
// TODO: Set it back to read regkey value while fixing the issues on 595
this->bDisableWatermarkCaching = true;
this->bDisableWatermarkCaching = dpRegkeyDatabase.bDisableWatermarkCaching;
if (dpRegkeyDatabase.bIgnoreCableIdCaps)
{
hal->setIgnoreCableIdCaps(true);
@@ -154,9 +152,6 @@ bool ConnectorImpl2x::getValidLowestLinkConfig
{
// Get next entry.
lowestSelected = this->allPossibleLinkCfgs[i+1];
// Update enhancedFraming/bDisableDownspread/bEnableFEC for target config
lowestSelected.enhancedFraming = lConfig.enhancedFraming;
lowestSelected.bDisableDownspread = lConfig.bDisableDownspread;
lowestSelected.enableFEC(lConfig.bEnableFEC);
}
}
@@ -885,6 +880,13 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
}
}
// Clean up: Clearing ECF
if (linkUseMultistream() || (activeLinkConfig.bIs128b132bChannelCoding))
{
targetImpl->hdcpSetEncrypted(false, NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_0, NV_TRUE, NV_FALSE);
targetImpl->hdcpEnabled = false;
}
if (linkUseMultistream())
{
unsigned symbolSize = GET_SYMBOL_SIZE(activeLinkConfig.bIs128b132bChannelCoding);
@@ -1036,18 +1038,42 @@ void ConnectorImpl2x::notifyAttachEnd(bool modesetCancelled)
// For DP1.1, let the upstream to turn it back.
// For DP1.2, we should turn the modeset back if it was on.
// The authentication will be called off during the modeset.
// see Bug 5633477
//
HDCPState hdcpState = {0};
main->configureHDCPGetHDCPState(hdcpState);
if ((!hdcpState.HDCP_State_Authenticated) && (isHDCPAuthOn == true)
&& (currentModesetDeviceGroup->hdcpEnabled))
if ((!hdcpState.HDCP_State_Authenticated)
&& (currentModesetDeviceGroup->hdcpPreviousStatus))
{
if (!this->linkUseMultistream())
{
currentModesetDeviceGroup->hdcpEnabled = isHDCPAuthOn = false;
}
else if (bMstRestoreHdcpStateAtAttach)
{
currentModesetDeviceGroup->cancelHdcpCallbacks();
if (isDP12AuthCap && !isHopLimitExceeded && !isHDCPReAuthPending)
{
isHDCPReAuthPending = true;
timer->queueCallback(this, &tagHDCPReauthentication, HDCP_AUTHENTICATION_COOLDOWN_HPD);
}
}
}
//
// RM has the requirement of Head being ARMed to do authentication.
// Postpone the authentication until the NAE to do the authentication for DP1.2 as solution.
//
if (isDP12AuthCap && !isHopLimitExceeded && !isHDCPReAuthPending &&
!bHdcpAuthOnlyOnDemand)
{
isHDCPReAuthPending = true;
timer->queueCallback(this, &tagHDCPReauthentication, HDCP_AUTHENTICATION_COOLDOWN_HPD);
}
hdcpCapsRetries = 0U;
timer->queueCallback(this, &tagDelayedHdcpCapRead, 2000);
fireEvents();
}
@@ -1408,6 +1434,12 @@ void ConnectorImpl2x::notifyDetachBegin(Group *target)
DP_PRINTF(DP_ERROR, "Failed to Disable the WAR for bug4949066!");
}
}
if(!linkUseMultistream() && activeLinkConfig.bIs128b132bChannelCoding)
{
group->hdcpPreviousStatus = group->hdcpEnabled;
group->hdcpSetEncrypted(false, NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_0, NV_TRUE, NV_FALSE);
group->hdcpEnabled = false;
}
return ConnectorImpl::notifyDetachBegin(target);
}
@@ -1500,6 +1532,20 @@ void ConnectorImpl2x::notifyDetachEnd(bool bKeepOdAlive)
//
else
{
//
// - if EDP; disable ASSR after switching off the stream from head
// to prevent corruption (bug 926360)
// - disable ASSR before power down link (bug 1641174)
//
if (main->isEDP())
{
bool bPanelPowerOn;
// if eDP's power has been shutdown here, don't disable ASSR, else it will be turned on by LT.
if (main->getEdpPowerData(&bPanelPowerOn, NULL) && bPanelPowerOn)
{
main->disableAlternateScramblerReset();
}
}
//
// Power down the links as we have switched away from the monitor.
// For shared SOR case, we need this to keep SW stats in DP instances in sync.
@@ -1909,9 +1955,84 @@ ConnectorImpl2x::ConnectorImpl2x(MainLink * main, AuxBus * auxBus, Timer * timer
{
bFlushSkipped = false;
bDisableDownspread = false;
displayId2MSTPolicy = DISPLAYID2_MST_POLICY_DID2X_THEN_EDID;
applyDP2xRegkeyOverrides();
}
void ConnectorImpl2x::discoveryNewDevice(const DiscoveryManager::Device & device)
{
//
// We're guaranteed that there isn't already a device on the list with the same
// address. If we receive the same device announce again - it is considered
// a notification that the device underlying may have seen an HPD.
//
// We're going to queue a DID2x read, and remember which device we did it on.
// If the DID2x comes back different we'll have mark the old device object
// as disconnected - and create a new one. This is required because
// DID2x is one of the fields considered to be immutable.
//
NvBool bReadDID2x = false;
if (!device.branch)
{
if (!device.videoSink)
{
// Don't read DID2x and EDID on a device having no videoSink
processNewDevice({device, Edid(), DisplayID2x(), false, DISPLAY_PORT, RESERVED});
return;
}
// Only read DID2x if the device is version 1.4 or higher and native DisplayID2x support is enabled
bReadDID2x = !bDisableNativeDisplayId2xSupport &&
(device.dpcdRevisionMajor > 1 || device.dpcdRevisionMinor >= 4);
if (bReadDID2x)
{
pendingDid2Reads.insertBack(new DevicePendingDID2Read(this, messageManager, device));
}
else
{
pendingEdidReads.insertBack(new DevicePendingEDIDRead(this, messageManager, device));
}
}
else
{
// Don't try to read the DID2x and EDID on a branch device
processNewDevice({device, Edid(), DisplayID2x(), true, DISPLAY_PORT, RESERVED});
}
}
void DisplayPort::DevicePendingDID2Read::mstDid2Completed(DID2ReadMultistream * from)
{
Address::StringBuffer sb;
DP_USED(sb);
DP_PRINTF(DP_NOTICE, "DP-CONN> DID2 read complete: %s",
from->topologyAddress.toString(sb));
ConnectorImpl2x * connector = parent;
if (connector->displayId2MSTPolicy == DISPLAYID2_MST_POLICY_DID2X_ONLY)
{
parent->processNewDevice({device, Edid(), from->displayId2x, true, DISPLAY_PORT, RESERVED});
delete this;
connector->discoveryDetectComplete();
}
else
{
device.displayId2x = from->displayId2x;
connector->pendingEdidReads.insertBack(new DevicePendingEDIDRead(connector, connector->messageManager, device));
delete this;
}
}
void DisplayPort::DevicePendingDID2Read::mstDid2ReadFailed(DID2ReadMultistream * from)
{
Address::StringBuffer sb;
DP_USED(sb);
DP_PRINTF(DP_ERROR, "DP-CONN> DID2 read failed: %s - read EDID instead",
from->topologyAddress.toString(sb));
ConnectorImpl2x * connector = parent;
connector->pendingEdidReads.insertBack(new DevicePendingEDIDRead(connector, connector->messageManager, device));
delete this;
}
bool ConnectorImpl2x::getDp2xLaneConfig(NvU32 *numLanes, NvU32 *data)
{
return (main->getDp2xLaneData(numLanes, data));

72
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1384,6 +1384,24 @@ TriState DeviceImpl::hdcpAvailable()
{
return this->hdcpAvailableHop();
}
else
{
DeviceImpl *targetDevice = this;
while (targetDevice)
{
if (!targetDevice->hdcpAvailableHop())
{
return False;
}
else if (targetDevice->hdcpAvailableHop() == Indeterminate)
{
return Indeterminate;
}
targetDevice = targetDevice->parent;
}
return True;
}
return False;
}
@@ -1632,7 +1650,19 @@ bool DeviceImpl::getRawEDID(char * buffer, unsigned size) const
dpMemCopy(buffer, rawEDID.getBuffer()->getData(), rawEDID.getEdidSize());
return true;
}
unsigned DeviceImpl::getDisplayId2xSize() const
{
return displayId2x.getDisplayId2xSize();
}
bool DeviceImpl::getDisplayId2x(char * buffer, unsigned size) const
{
if (size < displayId2x.getDisplayId2xSize())
return false;
dpMemCopy(buffer, displayId2x.getBuffer()->getData(), displayId2x.getDisplayId2xSize());
return true;
}
bool DeviceImpl::startVrrEnablement()
{
bool ret = false;
@@ -2622,6 +2652,18 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent)
this->bDSCPossible = true;
this->devDoingDscDecompression = this;
}
else
{
//
// This condition takes care of sink devices not capable of DSC
// but parent is capable of DSC decompression.
//
if (this->parent && this->parent->isDSCDecompressionSupported())
{
this->bDSCPossible = true;
this->devDoingDscDecompression = this->parent;
}
}
}
else
{
@@ -3352,9 +3394,7 @@ DeviceHDCPDetection::start()
}
else
{
parent->isHDCPCap = False;
waivePendingHDCPCapDoneNotification();
return;
goto NativeDPCDHDCPCAPRead;
}
NativeDPCDHDCPCAPRead:
@@ -3380,8 +3420,8 @@ NativeDPCDHDCPCAPRead:
waivePendingHDCPCapDoneNotification();
return;
}
else
{
else
{
parent->hal->getBCaps(bCaps, parent->BCAPS);
*(parent->nvBCaps) = *(parent->BCAPS);
if (bCaps.HDCPCapable)
@@ -3406,8 +3446,16 @@ NativeDPCDHDCPCAPRead:
}
else
{
parent->isHDCPCap = False;
waivePendingHDCPCapDoneNotification();
parent->isHDCPCap = Indeterminate;
Address parentAddress = parent->address.parent();
//For DP1.4 atomic messaging, HDCP detection can be delayed, so lowering the priority.
remote22BCapsReadMessage.setMessagePriority(NV_DP_SBMSG_PRIORITY_LEVEL_DEFAULT);
remote22BCapsReadMessage.set(parentAddress, parent->address.tail(), NV_DPCD_HDCP22_BCAPS_OFFSET, HDCP22_BCAPS_SIZE);
bCapsReadCompleted = false;
bBCapsReadMessagePending = true;
messageManager->post(&remote22BCapsReadMessage, this);
if (parent->connector)
parent->connector->incPendingRemoteHdcpDetection();
}
}
@@ -3444,7 +3492,8 @@ DeviceHDCPDetection::readRemoteHdcp1xCaps
bCapsReadCompleted = false;
bBCapsReadMessagePending = true;
messageManager->post(&remoteBCapsReadMessage, this);
}
}
void
DeviceHDCPDetection::handleRemoteDpcdReadDownReply
@@ -3716,7 +3765,7 @@ DeviceHDCPDetection::messageFailed
// any other reason like NakNoResources/NakUndefined/NakDpcdFail etc
// then reset the bBCapsReadMessagePending flag and try to read HDCP1X
// capability
//
//
Address::StringBuffer sb;
DP_USED(sb);
DP_PRINTF(DP_ERROR, "DP-QM> Message REMOTE_DPC_READ(22BCaps) {%p} at '%s' failed.",
@@ -3724,7 +3773,7 @@ DeviceHDCPDetection::messageFailed
bBCapsReadMessagePending = false;
tryRemote1XCaps = true;
timer->queueCallback(this, "22BCaps-Try1X", DPCD_REMOTE_DPCD_READ_MESSAGE_COOLDOWN_BKSV);
return;
return;
}
}
@@ -3845,7 +3894,6 @@ DeviceHDCPDetection::expired
tryRemote1XCaps = false;
readRemoteHdcp1xCaps();
}
}
DeviceHDCPDetection::~DeviceHDCPDetection()

47
src/common/displayport/src/dp_displayid2.cpp Normal file
View File

@@ -0,0 +1,47 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort *******************************\
* *
* Module: dp_displayid2.c *
* Implementation DisplayID2x reads *
* *
\***************************************************************************/
#include "dp_buffer.h"
#include "dp_auxbus.h"
#include "dp_internal.h"
#include "dp_edid.h"
#include "dp_printf.h"
#include "dp_displayid2.h"
using namespace DisplayPort;
DisplayID2x::DisplayID2x(): buffer()
{
buffer.memZero();
blockCount = 0;
displayId2xSize = 0;
}
DisplayID2x::~DisplayID2x()
{
}

329
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,6 +31,7 @@
#include "dp_internal.h"
#include "dp_evoadapter.h"
#include "dp_auxdefs.h"
#include "dp_qse.h"
#include "dp_tracing.h"
#include "dp_vrr.h"
#include "dp_printf.h"
@@ -76,6 +77,7 @@ const struct
DP_REG_VAL_TYPE valueType;
} DP_REGKEY_TABLE [] =
{
{NV_DP_REGKEY_DISABLE_QSES, &dpRegkeyDatabase.bQsesDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_OVERRIDE_DPCD_REV, &dpRegkeyDatabase.dpcdRevOveride, DP_REG_VAL_U32},
{NV_DP_REGKEY_DISABLE_SSC, &dpRegkeyDatabase.bSscDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FAST_LINK_TRAINING, &dpRegkeyDatabase.bFastLinkTrainingEnabled, DP_REG_VAL_BOOL},
@@ -89,6 +91,7 @@ const struct
{NV_DP_REGKEY_DISABLE_DSC, &dpRegkeyDatabase.bDscDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ASSESSLINK_FOR_EDP, &dpRegkeyDatabase.bAssesslinkForEdpSkipped, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_AUTO_HDCP_AUTH_AT_ATTACH, &dpRegkeyDatabase.bMstAutoHdcpAuthAtAttach, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_RESTORE_HDCP_AT_ATTACH_SKIPPED, &dpRegkeyDatabase.bMstRestoreHdcpAtAttachSkipped, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_MSA_OVER_MST, &dpRegkeyDatabase.bMsaOverMstEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE, &dpRegkeyDatabase.bOptLinkKeptAlive, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_MST, &dpRegkeyDatabase.bOptLinkKeptAliveMst, DP_REG_VAL_BOOL},
@@ -106,14 +109,14 @@ const struct
{NV_DP_REGKEY_DISABLE_DOWNSPREAD, &dpRegkeyDatabase.bDownspreadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_AVOID_HBR3_WAR, &dpRegkeyDatabase.bDisableAvoidHBR3War, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FIX_FOR_5147205, &dpRegkeyDatabase.bEnable5147205Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_EXPOSE_DSC_DEVID_WAR, &dpRegkeyDatabase.bEnableDevId, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_CQA_STATS_COLLECTION, &dpRegkeyDatabase.bEnableCqaStatsCollection, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_IGNORE_CAPS_AND_FORCE_HIGHEST_LC, &dpRegkeyDatabase.bIgnoreCapsAndForceHighestLc, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_OPTIMIZE_DSC_BPP_FOR_TUNNELLING_BW, &dpRegkeyDatabase.bOptimizeDscBppForTunnellingBw, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_128b132b_DSC_LNK_CFG_REDUCTION, &dpRegkeyDatabase.bEnable128b132bDSCLnkCfgReduction, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_USE_MAX_DSC_COMPRESSION_MST, &dpRegkeyDatabase.bUseMaxDSCCompressionMST, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_DISABLE_NATIVE_DISPLAYID2X_SUPPORT, &dpRegkeyDatabase.bDisableNativeDisplayId2xSupport, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_USE_MAX_DSC_COMPRESSION_MST, &dpRegkeyDatabase.bUseMaxDSCCompressionMST, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_NLPIGNORE_DDS, &dpRegkeyDatabase.bIgnoreUnplugUnlessRequested, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :
@@ -137,6 +140,7 @@ EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :
dpMemZero(&_DSC, sizeof(_DSC));
dpMemZero(&dfpParams, sizeof(dfpParams));
dpMemZero(&dpParams, sizeof(dpParams));
dpMemZero(&paramsHdcpCtrl, sizeof(paramsHdcpCtrl));
//
// Tell RM to hands off on the DisplayPort hardware
@@ -336,14 +340,288 @@ void EvoMainLink::triggerACT()
}
}
void EvoMainLink::configureHDCPRenegotiate(NvU64 cN, NvU64 cKSV, bool bForceReAuth, bool bRxIDMsgPending) {}
void EvoMainLink::configureAndTriggerECF(NvU64 ecf, NvBool bForceClearEcf, NvBool bAddStreamBack)
{
NV0073_CTRL_CMD_DP_SET_ECF_PARAMS params = {0};
params.subDeviceInstance = this->subdeviceIndex;
params.sorIndex = provider->getSorIndex();
params.ecf = ecf;
//
// ForceClearECF will delete DP MST Time slots along with ECF from GA10X and Later
// if ADD Stream Back is set then it will add back same time slots after clearing ECF
// bForceClear = TRUE should be set to have significance for bAddStreamBack
// bForceClear will be only set in case of Detach Stream/Flush mode
// bAddStream will also be set only in case of QSES error scenario
// In all other cases these are set to FALSE
//
params.bForceClearEcf = bForceClearEcf;
params.bAddStreamBack = bAddStreamBack;
NvU32 ret = provider->rmControl0073(NV0073_CTRL_CMD_DP_SET_ECF, &params, sizeof params);
if (ret != NVOS_STATUS_SUCCESS)
{
DP_PRINTF(DP_ERROR, "Set EFC failed!");
}
triggerACT();
// Wait for 1 link frame time for ECF to take effect i.e
// Wait Time = 1024 MTPs * 64 clocks/MTP * (1/162MHz) = 404.5 us.
// As the minimum time available for timer->sleep() is 1 ms hence taking that time
timer->sleep(1);
}
//TODO: we need to re-arch this code to remove from dp library
void EvoMainLink::configureHDCPRenegotiate(NvU64 cN, NvU64 cKSV, bool bForceReAuth, bool bRxIDMsgPending)
{
dpMemZero(&paramsHdcpCtrl, sizeof(paramsHdcpCtrl));
paramsHdcpCtrl.subDeviceInstance = this->subdeviceIndex;
paramsHdcpCtrl.displayId = this->displayId;
paramsHdcpCtrl.cN = cN;
paramsHdcpCtrl.cKsv = cKSV;
if (bForceReAuth)
{
paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_FORCE_REAUTH, _YES);
}
else
{
paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_FORCE_REAUTH, _NO);
}
if (bRxIDMsgPending)
{
paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_RXIDMSG_PENDING, _YES);
}
else
{
paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_RXIDMSG_PENDING, _NO);
}
paramsHdcpCtrl.cmd |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _CMD, _RENEGOTIATE);
NvU32 ret = provider->rmControl0073(NV0073_CTRL_CMD_SPECIFIC_HDCP_CTRL, &paramsHdcpCtrl, sizeof paramsHdcpCtrl);
if (ret != NVOS_STATUS_SUCCESS)
{
DP_PRINTF(DP_ERROR, "configureHDCPRenegotiate failed!");
}
}
void EvoMainLink::configureHDCPDisableAuthentication()
{
dpMemZero(&paramsHdcpCtrl, sizeof(paramsHdcpCtrl));
paramsHdcpCtrl.subDeviceInstance = this->subdeviceIndex;
paramsHdcpCtrl.displayId = this->displayId;
paramsHdcpCtrl.cmd |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _CMD, _DISABLE_AUTHENTICATION);
NvU32 ret = provider->rmControl0073(NV0073_CTRL_CMD_SPECIFIC_HDCP_CTRL, &paramsHdcpCtrl, sizeof paramsHdcpCtrl);
if (ret != NVOS_STATUS_SUCCESS)
{
DP_PRINTF(DP_ERROR, "configureHDCPDisableAuthentication failed!");
}
}
void EvoMainLink::configureHDCPAbortAuthentication(AbortAuthReason abortAuthReason)
{
dpMemZero(&paramsHdcpCtrl, sizeof(paramsHdcpCtrl));
paramsHdcpCtrl.subDeviceInstance = this->subdeviceIndex;
paramsHdcpCtrl.displayId = this->displayId;
paramsHdcpCtrl.cN = HDCP_DUMMY_CN;
paramsHdcpCtrl.cKsv = HDCP_DUMMY_CKSV;
switch (abortAuthReason)
{
case UNTRUST: paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_ABORT, _UNTRUST); break; //Abort due to Kp mismatch
case UNRELBL: paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_ABORT, _UNRELBL); break; //Abort due to repeated link failure
case KSV_LEN: paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_ABORT, _KSV_LEN); break; //Abort due to KSV length
case KSV_SIG: paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_ABORT, _KSV_SIG); break; //Abort due to KSV signature
case SRM_SIG: paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_ABORT, _SRM_SIG); break; //Abort due to SRM signature
case SRM_REV: paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_ABORT, _SRM_REV); break; //Abort due to SRM revocation
case NORDY: paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_ABORT, _NORDY); break; //Abort due to repeater not ready
case KSVTOP: paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_ABORT, _KSVTOP); break; //Abort due to KSV topology error
case BADBKSV: paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_ABORT, _BADBKSV); break; //Abort due to invalid Bksv
default: paramsHdcpCtrl.flags |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _FLAGS_ABORT, _NONE); break; // Default value;
}
paramsHdcpCtrl.cmd |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _CMD, _ABORT_AUTHENTICATION);
NvU32 ret = provider->rmControl0073(NV0073_CTRL_CMD_SPECIFIC_HDCP_CTRL, &paramsHdcpCtrl, sizeof paramsHdcpCtrl);
if (ret != NVOS_STATUS_SUCCESS)
{
DP_PRINTF(DP_ERROR, "configureHDCPAbortAuthentication failed!");
}
}
void EvoMainLink::configureHDCPValidateLink(HDCPValidateData &hdcpValidateData, NvU64 cN, NvU64 cKsv)
{
dpMemZero(&paramsHdcpCtrl, sizeof(paramsHdcpCtrl));
paramsHdcpCtrl.subDeviceInstance = this->subdeviceIndex;
paramsHdcpCtrl.displayId = this->displayId;
paramsHdcpCtrl.linkCount = 1;
paramsHdcpCtrl.cN = cN;
paramsHdcpCtrl.cKsv = cKsv;
paramsHdcpCtrl.cmd |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _CMD, _VALIDATE_LINK);
NvU32 ret = provider->rmControl0073(NV0073_CTRL_CMD_SPECIFIC_HDCP_CTRL, &paramsHdcpCtrl, sizeof paramsHdcpCtrl);
if (ret != NVOS_STATUS_SUCCESS)
{
DP_PRINTF(DP_ERROR, "configureHDCPValidateLink(): HDCP_CTRL failed!");
}
for (unsigned i = 0; i < NV0073_CTRL_HDCP_VPRIME_SIZE; i++)
{
hdcpValidateData.vP[i] = paramsHdcpCtrl.vP[i];
}
hdcpValidateData.aN = paramsHdcpCtrl.aN[0]; // Only primary link An for DP use.
hdcpValidateData.mP = paramsHdcpCtrl.mP;
}
void EvoMainLink::configureHDCPGetHDCPState(HDCPState &hdcpState)
{
// HDCP Not Supported
hdcpState.HDCP_State_Repeater_Capable = false;
hdcpState.HDCP_State_22_Capable = false;
hdcpState.HDCP_State_Encryption = false;
hdcpState.HDCP_State_Authenticated = false;
NV0073_CTRL_SPECIFIC_GET_HDCP_STATE_PARAMS params = {0};
params.subDeviceInstance = this->subdeviceIndex;
params.displayId = this->displayId;
// Set CACHED to False, it will cause a hdcpStatusRead which gating the eng.
// params.flags = FLD_SET_DRF(0073_CTRL_SPECIFIC, _HDCP_STATE, _ENCRYPTING_CACHED, _TRUE, 0);
NvU32 ret = provider->rmControl0073(NV0073_CTRL_CMD_SPECIFIC_GET_HDCP_STATE, &params, sizeof params);
if (ret != NVOS_STATUS_SUCCESS)
{
DP_PRINTF(DP_ERROR, "configureHDCPGetHDCPState(): Get HDCP state failed!");
}
hdcpState.HDCP_State_1X_Capable = FLD_TEST_DRF(0073_CTRL_SPECIFIC,
_HDCP_STATE, _RECEIVER_CAPABLE, _YES, params.flags) ? true : false;
if (FLD_TEST_DRF(0073_CTRL_SPECIFIC, _HDCP_STATE, _REPEATER_CAPABLE,
_YES, params.flags) ||
FLD_TEST_DRF(0073_CTRL_SPECIFIC, _HDCP_STATE, _HDCP22_REPEATER_CAPABLE,
_YES, params.flags))
{
hdcpState.HDCP_State_Repeater_Capable = true;
}
else
{
hdcpState.HDCP_State_Repeater_Capable = false;
}
if (FLD_TEST_DRF(0073_CTRL_SPECIFIC, _HDCP_STATE, _HDCP22_RECEIVER_CAPABLE,
_YES, params.flags) ||
FLD_TEST_DRF(0073_CTRL_SPECIFIC, _HDCP_STATE, _HDCP22_REPEATER_CAPABLE,
_YES, params.flags))
{
hdcpState.HDCP_State_22_Capable = true;
}
else
{
hdcpState.HDCP_State_22_Capable = false;
}
if (hdcpState.HDCP_State_22_Capable)
{
if (FLD_TEST_DRF(0073_CTRL_SPECIFIC, _HDCP_STATE, _HDCP22_ENCRYPTING,_YES, params.flags))
{
hdcpState.HDCP_State_Encryption = true;
}
else
{
hdcpState.HDCP_State_Encryption = false;
}
}
else
{
if (FLD_TEST_DRF(0073_CTRL_SPECIFIC, _HDCP_STATE,_ENCRYPTING, _YES, params.flags))
{
hdcpState.HDCP_State_Encryption = true;
}
else
{
hdcpState.HDCP_State_Encryption = false;
}
}
if (FLD_TEST_DRF(0073_CTRL_SPECIFIC, _HDCP_STATE, _AUTHENTICATED,
_YES, params.flags))
{
hdcpState.HDCP_State_Authenticated = true;
}
else
{
hdcpState.HDCP_State_Authenticated = false;
}
}
void EvoMainLink::disableAlternateScramblerReset()
{
NV0073_CTRL_DP_ASSR_CTRL_PARAMS assrParams;
dpMemZero(&assrParams, sizeof(assrParams));
assrParams.subDeviceInstance = subdeviceIndex;
assrParams.displayId = displayId;
assrParams.cmd = DRF_DEF(0073_CTRL, _DP, _ASSR_CMD, _DISABLE);
NvU32 code = provider->rmControl0073(NV0073_CTRL_CMD_DP_ASSR_CTRL, &assrParams, sizeof(assrParams));
if (code != NVOS_STATUS_SUCCESS || assrParams.err)
{
DP_ASSERT(0 && "Unable to change scrambler reset");
}
}
bool EvoMainLink::setStreamType(unsigned streamIndex, NvU8 streamType, bool * bNeedReNegotiate)
{
dpMemZero(&paramsHdcpCtrl, sizeof(paramsHdcpCtrl));
paramsHdcpCtrl.subDeviceInstance = this->subdeviceIndex;
paramsHdcpCtrl.displayId = this->displayId;
paramsHdcpCtrl.streamIndex = streamIndex;
paramsHdcpCtrl.streamType = streamType;
//
// According to spec, Type1 content cannot be transmitted to repeater HDCP1.X downstream device.
// Thus RM provides option for client that force to type0 instead repeater blank the output with type1.
// TODO: check Playready/HWDRM behavior with this,
// 1. Will it stop engaging HWDRM with this fix ?
// 2. VPR blanking gets applied and blanks repeater display as well
//
paramsHdcpCtrl.bEnforceType0Hdcp1xDS = (streamType == NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_1);
paramsHdcpCtrl.cmd |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _CMD,
_SET_TYPE);
*bNeedReNegotiate = false;
if (!provider->rmControl0073(NV0073_CTRL_CMD_SPECIFIC_HDCP_CTRL,
&paramsHdcpCtrl, sizeof paramsHdcpCtrl))
{
if (FLD_TEST_DRF(0073_CTRL_SPECIFIC, _HDCP_CTRL_FLAGS, _TYPE_CHANGED,
_YES, paramsHdcpCtrl.flags))
{
*bNeedReNegotiate = true;
}
return true;
}
else
{
DP_PRINTF(DP_ERROR, "DP_EVO> set stream type cmd failed!");
return false;
}
}
void EvoMainLink::forwardPendingKsvListReady(NvBool bKsvListReady)
{
dpMemZero(&paramsHdcpCtrl, sizeof(paramsHdcpCtrl));
paramsHdcpCtrl.subDeviceInstance = this->subdeviceIndex;
paramsHdcpCtrl.displayId = this->displayId;
paramsHdcpCtrl.bPendingKsvListReady = bKsvListReady;
paramsHdcpCtrl.cmd |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _CMD,
_FORWARD_KSVLIST_READY);
NvU32 ret = provider->rmControl0073(NV0073_CTRL_CMD_SPECIFIC_HDCP_CTRL, &paramsHdcpCtrl,
sizeof paramsHdcpCtrl);
if (ret != NVOS_STATUS_SUCCESS)
{
DP_PRINTF(DP_ERROR, "configureSingleHeadMultiStreamMode failed!");
}
}
void EvoMainLink::configureSingleStream(NvU32 head,
@@ -992,9 +1270,16 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
bool isPostLtAdjRequestGranted, unsigned phyRepeaterCount)
{
NvU32 targetIndex;
NvU32 ltCounter = retLink->getLTCounter();
bool bTrainPhyRepeater =
(!link.bDisableLTTPR) && (_isLTPhyRepeaterSupported);
NvU32 ltCounter = retLink->getLTCounter();
bool bTrainPhyRepeater = (!link.bDisableLTTPR) && (_isLTPhyRepeaterSupported);
NvU32 bNotifyLT = NVOS_STATUS_SUCCESS;
NV0073_CTRL_DP_NOTIFY_LT_PARAMS notifyParams;
dpMemZero(&notifyParams, sizeof(notifyParams));
notifyParams.subDeviceInstance = subdeviceIndex;
notifyParams.displayId = displayId;
notifyParams.bLTInProgress = NV_FALSE;
if (provider->getSorIndex() == DP_INVALID_SOR_INDEX)
{
@@ -1063,6 +1348,12 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
//
NvU32 crHighRateFallbackCount = 0;
if (link.lanes != 0)
{
notifyParams.bLTInProgress = NV_TRUE;
bNotifyLT = provider->rmControl0073(NV0073_CTRL_CMD_DP_NOTIFY_LT, &notifyParams, sizeof(notifyParams));
}
//
// The rate and lane count we send to RM might be different than what client
// sent to us since fallback might happen.
@@ -1093,6 +1384,11 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
if (requestRmLC.lanes != 0)
{
DP_ASSERT(0 && "Unknown rate");
if (bNotifyLT == NVOS_STATUS_SUCCESS)
{
notifyParams.bLTInProgress = NV_FALSE;
provider->rmControl0073(NV0073_CTRL_CMD_DP_NOTIFY_LT, &notifyParams, sizeof(notifyParams));
}
return false;
}
break;
@@ -1117,7 +1413,7 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
dpCtrlCmd = FLD_SET_DRF(0073_CTRL, _DP_CMD, _FALLBACK_CONFIG, _FALSE, dpCtrlCmd);
do
{
NV0073_CTRL_DP_CTRL_PARAMS params;
NV0073_CTRL_DP_CTRL_PARAMS params;
dpMemZero(&params, sizeof(params));
params.subDeviceInstance = subdeviceIndex;
@@ -1272,6 +1568,11 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
}
} while (crHighRateFallbackCount < NV_DP_RBR_FALLBACK_MAX_TRIES);
if (bNotifyLT == NVOS_STATUS_SUCCESS)
{
notifyParams.bLTInProgress = NV_FALSE;
provider->rmControl0073(NV0073_CTRL_CMD_DP_NOTIFY_LT, &notifyParams, sizeof(notifyParams));
}
//
// Result should be checked for only the control call status. 'err'
// doesn't represent failure in LT - some compliance tests such as 700.1.1.2

18
src/common/displayport/src/dp_evoadapter2x.cpp
View File

@@ -109,8 +109,7 @@ void EvoMainLink2x::applyDP2xRegkeyOverrides()
this->bSupportUHBR2_50 = dpRegkeyDatabase.supportInternalUhbrOnFpga & NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_2_5G;
this->bSupportUHBR2_70 = dpRegkeyDatabase.supportInternalUhbrOnFpga & NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_2_7G;
this->bSupportUHBR5_00 = dpRegkeyDatabase.supportInternalUhbrOnFpga & NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_5_0G;
this->bEnable5147205Fix = dpRegkeyDatabase.bEnable5147205Fix;
this->bCableVconnSourceUnknown = dpRegkeyDatabase.bCableVconnSourceUnknownWar;
this->bCableVconnSourceUnknown = dpRegkeyDatabase.bCableVconnSourceUnknownWar;
}
NvU32 EvoMainLink2x::headToStream(NvU32 head, bool bSidebandMessageSupported,
@@ -484,10 +483,23 @@ bool EvoMainLink2x::train(const LinkConfiguration & link, bool force,
// Check if the link is capable to train with 128b/132b
if (requestRmLC.bIs128b132bChannelCoding)
{
NV0073_CTRL_DP_NOTIFY_LT_PARAMS notifyParams;
dpMemZero(&notifyParams, sizeof(notifyParams));
notifyParams.subDeviceInstance = subdeviceIndex;
notifyParams.displayId = displayId;
notifyParams.bLTInProgress = NV_TRUE;
NvU32 bNotifyLT = provider->rmControl0073(NV0073_CTRL_CMD_DP_NOTIFY_LT, &notifyParams, sizeof(notifyParams));
ltStatus = trainDP2xChannelCoding(requestRmLC, force, linkTrainingType,
retLink, bSkipLt,
isPostLtAdjRequestGranted,
phyRepeaterCount);
if (bNotifyLT == NVOS_STATUS_SUCCESS)
{
notifyParams.bLTInProgress = NV_FALSE;
provider->rmControl0073(NV0073_CTRL_CMD_DP_NOTIFY_LT, &notifyParams, sizeof(notifyParams));
}
}
else
{
@@ -1115,7 +1127,7 @@ bool EvoMainLink2x::resetDPRXLink(DP2XResetParam resetParam)
ltRmParams.cmd |= DRF_DEF(0073_CTRL, _DP2X_CMD, _FAKE_LINK_TRAINING, _DONOT_TOGGLE_TRANSMISSION);
}
if (resetParam.bSkipLt && bEnable5147205Fix)
if (resetParam.bSkipLt)
{
ltRmParams.cmd |= DRF_DEF(0073_CTRL, _DP2X_CMD, _SKIP_HW_PROGRAMMING, _YES);
}

401
src/common/displayport/src/dp_groupimpl.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -155,8 +155,51 @@ void GroupImpl::insert(Device * dev)
members.insertFront(di);
update(dev, true);
NvBool bIs128b132bChannelCoding = false;
LinkConfiguration linkConfig = parent->getActiveLinkConfig();
bIs128b132bChannelCoding = linkConfig.bIs128b132bChannelCoding;
// Is HDCP on for this group?
// YES? Disable HDCP (ECF)
if (this->hdcpEnabled)
{
NvU64 ecf = 0x0;
NvU64 countOnes = 0x0;
NvU64 mask = 0x0;
// Get the MASK for the all active groups which is ECF enabled.
for (ListElement * i = parent->activeGroups.begin(); i != parent->activeGroups.end(); i = i->next)
{
GroupImpl * group = (GroupImpl *)i;
if (group->hdcpEnabled)
{
countOnes = (((NvU64)1) << group->timeslot.count) - 1;
if (bIs128b132bChannelCoding && (group->timeslot.count == 64))
{
countOnes = (NvU64)0xFFFFFFFFFFFFFFFF;
}
mask = countOnes << group->timeslot.begin;
ecf |= mask;
}
}
countOnes = (((NvU64)1) << this->timeslot.count) - 1;
if (bIs128b132bChannelCoding && (this->timeslot.count == 64))
{
countOnes = (NvU64)0xFFFFFFFFFFFFFFFF;
}
mask = countOnes << this->timeslot.begin;
ecf &= ~mask;
parent->main->configureAndTriggerECF(ecf);
this->hdcpEnabled = false;
}
update(dev, true);
}
void GroupImpl::remove(Device * dev)
@@ -195,6 +238,11 @@ void GroupImpl::destroy()
// Cancel any queue the auth callback.
cancelHdcpCallbacks();
if (streamEncryptionStatusDetection)
{
delete streamEncryptionStatusDetection;
streamEncryptionStatusDetection = 0;
}
parent = this->parent;
if (parent)
@@ -247,6 +295,8 @@ void GroupImpl::cancelHdcpCallbacks()
parent->timer->cancelCallback(this, &tagHDCPReauthentication);
parent->timer->cancelCallback(this, &tagStreamValidation);
QSESetECFRetries = 0;
parent->timer->cancelCallback(this, &tagMSTQSEandSetECF);
}
Device * GroupImpl::enumDevices(Device * previousDevice)
@@ -294,12 +344,215 @@ void GroupImpl::expired(const void * tag)
DP_ASSERT(0 && "DP> Didn't get final notification." );
}
}
else if (tag == &tagMSTQSEandSetECF)
{
if (QSESetECFRetries < HDCP_QSEANDSETECF_RETRIES)
{
HDCPState hdcpState = {0};
parent->main->configureHDCPGetHDCPState(hdcpState);
this->hdcpEnabled = parent->isHDCPAuthOn = hdcpState.HDCP_State_Authenticated;
// Wait till authenticated then enable QSE and set ECF.
if (parent->isHDCPAuthOn)
{
QSESetECFRetries = 0;
parent->timer->cancelCallback(this, &tagMSTQSEandSetECF);
hdcpMSTQSEandSetECF();
}
else
{
QSESetECFRetries++;
parent->timer->queueCallback(this, &tagMSTQSEandSetECF,
HDCP_QSEANDSETECF_COOLDOWN);
}
}
else
{
DP_ASSERT(0 && "MST HDCP not authenticated within timeout and fail to set ECF." );
}
}
}
// bForceClear stands for bForceClearECF.
bool GroupImpl::hdcpSetEncrypted(bool encrypted, NvU8 streamType, NvBool bForceClear, NvBool bAddStreamBack)
{
LinkConfiguration linkConfig = parent->getActiveLinkConfig();
if (encrypted == true)
{
bool bNeedReNegotiate = false;
HDCPState hdcpState = {0};
DP_PRINTF(DP_NOTICE, "DP-GRP: enable encryption with type=%d.", streamType);
// enumerate the displays in the group and see if they are hdcp capable.
Device * d = 0;
bool isHdcpCapable = false;
for (d = ((Group*)this)->enumDevices(0); d != 0; d = ((Group*)this)->enumDevices(d))
{
NvU8 Bcaps = (NvU8)(((DeviceImpl*)d)->nvBCaps[0]);
if ((FLD_TEST_DRF(_DPCD, _HDCP_BCAPS_OFFSET, _HDCP_CAPABLE, _YES, Bcaps)) &&
(((DeviceImpl*)d)->isHDCPCap == True))
{
isHdcpCapable = true;
break;
}
}
if (isHdcpCapable == false)
{
DP_PRINTF(DP_ERROR, "DP-GRP: group does not contain a hdcp capable device.");
return false;
}
parent->main->configureHDCPGetHDCPState(hdcpState);
// Clear dplib authentication state if RM reports not authenticated.
if (!hdcpState.HDCP_State_Authenticated)
{
parent->isHDCPAuthOn = this->hdcpEnabled = false;
}
// Update stream content type and trigger negotiation if need.
if ((hdcpState.HDCP_State_22_Capable) &&
(false == parent->main->setStreamType(streamIndex, streamType, &bNeedReNegotiate)))
{
DP_PRINTF(DP_ERROR, "DP-GRP: group set stream type failed.");
return false;
}
if(!parent->isHDCPAuthOn || bNeedReNegotiate)
{
cancelHdcpCallbacks();
parent->main->configureHDCPRenegotiate();
parent->main->configureHDCPGetHDCPState(hdcpState);
if (hdcpState.HDCP_State_Encryption)
{
parent->isHDCPAuthOn = this->hdcpEnabled = true;
}
else
{
parent->isHDCPAuthOn = this->hdcpEnabled = false;
parent->timer->queueCallback(this, &tagHDCPReauthentication, HDCP_AUTHENTICATION_COOLDOWN);
}
}
else
{
// SST and non128b/132b is done when it's authenticated.
if (!(parent->linkUseMultistream())
&& !linkConfig.bIs128b132bChannelCoding
)
return true;
}
if (parent->linkUseMultistream()
|| linkConfig.bIs128b132bChannelCoding
)
{
// Check if authenticated else wait it's authenticated then assigning ECF.
if(!parent->isHDCPAuthOn || bNeedReNegotiate)
{
parent->timer->queueCallback(this, &tagMSTQSEandSetECF, HDCP_QSEANDSETECF_COOLDOWN);
return true;
}
else
{
parent->timer->cancelCallback(this, &tagMSTQSEandSetECF);
hdcpMSTQSEandSetECF();
}
}
}
else
{
if (parent->isHDCPAuthOn)
{
if (!(parent->linkUseMultistream())
&& !linkConfig.bIs128b132bChannelCoding
)
{
parent->main->configureHDCPDisableAuthentication();
parent->isHDCPAuthOn = this->hdcpEnabled = false;
}
else
{
NvU64 ecf = 0x0;
NvU64 countOnes = 0x0;
NvU64 mask = 0x0;
// Get the MASK for the all active groups which is ECF enabled.
for (ListElement * i = parent->activeGroups.begin(); i != parent->activeGroups.end(); i = i->next)
{
GroupImpl * group = (GroupImpl *)i;
if (group->hdcpEnabled)
{
countOnes = (((NvU64)1) << group->timeslot.count) - 1;
if (linkConfig.bIs128b132bChannelCoding && (group->timeslot.count == 64))
{
countOnes = (NvU64)0xFFFFFFFFFFFFFFFF;
}
mask = countOnes << group->timeslot.begin;
ecf |= mask;
}
}
//Just clear the ECF not turn off the auth.
for (ListElement * i = parent->activeGroups.begin(); i != parent->activeGroups.end(); i = i->next)
{
GroupImpl * group = (GroupImpl *)i;
if (this->headIndex == group->headIndex)
{
countOnes = (((NvU64)1) << group->timeslot.count) - 1;
if (linkConfig.bIs128b132bChannelCoding && (group->timeslot.count == 64))
{
countOnes = (NvU64)0xFFFFFFFFFFFFFFFF;
}
mask = countOnes << group->timeslot.begin;
ecf &= ~mask;
}
}
parent->main->configureAndTriggerECF(ecf, bForceClear, bAddStreamBack);
for (ListElement * i = parent->activeGroups.begin(); i != parent->activeGroups.end(); i = i->next)
{
GroupImpl * group = (GroupImpl *)i;
if (this->headIndex == group->headIndex)
{
group->hdcpEnabled = false;
{ // Inform ConnectorEventSink that we have disabled HDCP on this Device
Device * d = 0;
for (d = ((Group*)this)->enumDevices(0); d != 0; d = ((Group*)this)->enumDevices(d))
{
if (((DeviceImpl*)d)->isHDCPCap == True)
{
parent->sink->notifyHDCPCapDone(d, False);
}
}
}
}
}
}
}
else
return true;
}
return true;
}
//DP_OPTION_HDCP_SUPPORT_ENABLE
bool GroupImpl::hdcpGetEncrypted()
{
//
// Returns whether encryption is currently enabled
// After the setECFencyption we just set the flag for this group and make the default as false.
//
if (parent->isHDCPAuthOn)
{
@@ -311,6 +564,150 @@ bool GroupImpl::hdcpGetEncrypted()
}
}
void GroupImpl::hdcpMSTQSEandSetECF()
{
NvBool bIs128b132bChannelCoding = false;
LinkConfiguration linkConfig = parent->getActiveLinkConfig();
bIs128b132bChannelCoding = linkConfig.bIs128b132bChannelCoding;
//
// We become passive and wait for the Stream_Status_Change coming.
// Otherwise, we might not have the change to get the update KSVlist to
// validate it. Before, Naresh's Stream_Status_Change p4r in.
// We just simple turn it on. (which can be the option for non-QSE
// (AKA intel/AMD plan) branch.)
//
//
// Enable sending QSES message only when regkey 'DISABLE_QSES' set to 0
// in DD's path.
// This is added to provide driver for ST and not to be productized.
//
if ((parent->bIsEncryptionQseValid) &&
(!parent->main->getRegkeyValue(NV_DP_REGKEY_DISABLE_QSES))
&& (!bIs128b132bChannelCoding)
)
{
for (ListElement * i = parent->activeGroups.begin();
i != parent->activeGroups.end(); i = i->next)
{
GroupImpl * group = (GroupImpl *)i;
if (this->headIndex == group->headIndex)
{
HDCPValidateData hdcpValidateData = {0};
parent->main->configureHDCPValidateLink(hdcpValidateData);
parent->qseNonceGenerator->clientIdBuilder(hdcpValidateData.aN);
}
}
}
//
// Turn on the ECF set ECF on according to the group's active stream.
// Set flag for the goup for later getting status using.
//
NvU64 ecf = 0x0;
NvU64 countOnes = 0x0;
NvU64 mask = 0x0;
// Get the MASK for the all active groups which is ECF enabled.
for (ListElement * i = parent->activeGroups.begin();
i != parent->activeGroups.end(); i = i->next)
{
GroupImpl * group = (GroupImpl *)i;
if (group->hdcpEnabled)
{
countOnes = (((NvU64)1) << group->timeslot.count) - 1;
if (bIs128b132bChannelCoding && (group->timeslot.count == 64))
{
countOnes = (NvU64)0xFFFFFFFFFFFFFFFF;
}
mask = countOnes << group->timeslot.begin;
ecf |= mask;
}
}
for (ListElement * i = parent->activeGroups.begin();
i != parent->activeGroups.end(); i = i->next)
{
GroupImpl * group = (GroupImpl *)i;
if (this->headIndex == group->headIndex)
{
countOnes = (((NvU64)1) << group->timeslot.count) - 1;
if (bIs128b132bChannelCoding && (group->timeslot.count == 64))
{
countOnes = (NvU64)0xFFFFFFFFFFFFFFFF;
}
mask = countOnes << group->timeslot.begin;
ecf |= mask;
}
}
// Set the ECF with new added group.
parent->main->configureAndTriggerECF(ecf);
//
// Enable sending QSES message only when regkey 'DISABLE_QSES' set to 0 in
// DD's path.
// This is added to provide driver for ST and not to be productized.
//
if ((parent->bIsEncryptionQseValid) &&
(!parent->main->getRegkeyValue(NV_DP_REGKEY_DISABLE_QSES))
&& (!bIs128b132bChannelCoding)
)
{
for (ListElement * i = parent->activeGroups.begin();
i != parent->activeGroups.end(); i = i->next)
{
GroupImpl * group = (GroupImpl *)i;
if (this->headIndex == group->headIndex)
{
if (NULL == group->streamEncryptionStatusDetection)
{
group->streamEncryptionStatusDetection =
new StreamEncryptionStatusDetection(group, parent);
}
if (group->streamEncryptionStatusDetection)
{
parent->bValidQSERequest = true;
group->streamEncryptionStatusDetection->sendQSEMessage(group);
parent->timer->queueCallback(group,
&(group->tagStreamValidation),
HDCP_STREAM_VALIDATION_REQUEST_COOLDOWN);
}
}
}
}
for (ListElement * i = parent->activeGroups.begin();
i != parent->activeGroups.end(); i = i->next)
{
GroupImpl * group = (GroupImpl *)i;
if (this->headIndex == group->headIndex)
{
group->hdcpEnabled = true;
{ // Inform ConnectorEventSink that we have enabled HDCP on this Device
Device * d = 0;
for (d = ((Group*)this)->enumDevices(0); d != 0; d = ((Group*)this)->enumDevices(d))
{
if (((DeviceImpl*)d)->isHDCPCap == True)
{
parent->sink->notifyHDCPCapDone(d, True);
}
}
}
}
}
}
void GroupImpl::updateVbiosScratchRegister(Device * lastDev)
{
if (!parent->bDisableVbiosScratchRegisterUpdate &&

57
src/common/displayport/src/dp_messagecodings.cpp
View File

@@ -669,6 +669,63 @@ bool SinkEventNotifyMessage::processByType(EncodedMessage * message, BitStreamRe
}
//
// QUERY_STREAM_ENCRYPTION_STATUS 0x38
// Follow the SCR DP1.2 Query Stream Encryption Status Definition v0.4
//
void QueryStreamEncryptionMessage::set
(
const Address & target,
unsigned streamId,
NvU8* clientId,
StreamEvent streamEvent,
bool streamEventMask,
StreamBehavior streamBehavior,
bool streamBehaviorMask
)
{
clear();
BitStreamWriter writer(&encodedMessage.buffer, 0);
// Write request identifier
writer.write(0/*zero*/, 1);
writer.write(requestIdentifier, 7);
// Write message request body
writer.write(streamId, 8);
for (unsigned i=0; i<7; i++)
{
writer.write(clientId[i], 8);
}
writer.write(streamEvent, 2);
writer.write(streamEventMask?1:0, 1);
writer.write(streamBehavior, 2);
writer.write(streamBehaviorMask?1:0, 1);
writer.write(0 /*zeroes*/, 2);
encodedMessage.isPathMessage = false;
encodedMessage.isBroadcast = false;
encodedMessage.address = target;
}
ParseResponseStatus QueryStreamEncryptionMessage::parseResponseAck(EncodedMessage * message, BitStreamReader * reader)
{
reply.streamState = (StreamState)reader->readOrDefault(2 /*Stream_State*/, 0x0);
reply.repeaterFuncPresent = !!reader->readOrDefault(1 /*Stream_Repeater_Function*/, 0x0);
reply.encryption = !!reader->readOrDefault(1 /*Stream_Encryption */, 0x0);
reply.authentication = !!reader->readOrDefault(1 /*Stream_Authentication */, 0x0);
reader->readOrDefault(3 /*zero*/, 0);
reply.sinkType = (OutputSinkType)reader->readOrDefault(3 /*Stream_Output_Sink_Type*/, 0x0);
reply.cpType = (OutputCPType)reader->readOrDefault(2 /*Stream_Output_CP_Type*/, 0x0);
reader->readOrDefault(2 /*zeroes*/, 0);
reply.signedLPrime = !!reader->readOrDefault(1 /*Signed*/, 0x0);
reply.streamId = (NvU8)reader->readOrDefault(8/*Stream_ID*/, 0x0);
return ParseResponseSuccess;
}
I2cWriteTransaction::I2cWriteTransaction
(
unsigned WriteI2cDeviceId,

252
src/common/displayport/src/dp_mst_displayid2.cpp Normal file
View File

@@ -0,0 +1,252 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort *******************************\
* *
* Module: dp_mst_displayid2.c *
* Implementation Multi Stream DisplayID20 reads *
* *
\***************************************************************************/
#include "dp_internal.h"
#include "dp_displayid2.h"
#include "dp_address.h"
#include "dp_messagecodings.h"
#include "dp_messages.h"
#include "dp_printf.h"
using namespace DisplayPort;
DID2ReadMultistream::~DID2ReadMultistream()
{
timer->cancelCallbacks(this);
}
void DID2ReadMultistream::startReadingDid2()
{
NvU8 offset = 0;
NvU8 nWriteTransactions = 0;
I2cWriteTransaction i2cWriteTransactions[2];
Address::StringBuffer buffer;
DP_USED(buffer);
DP_PRINTF(DP_NOTICE, "%s(): start for %s", __FUNCTION__, topologyAddress.toString(buffer));
// Initialize the variables
remainingBytes = 0;
loop = 0;
sectionLength = 0;
extensionCount = 0;
displayId2xSize = 0;
// Reset the offset only.
i2cWriteTransactions[0] = I2cWriteTransaction(NV_DISPLAYID2_DDC_ADDRESS >> 1,
sizeof(offset), &offset, true);
nWriteTransactions = 1;
remoteI2cRead.set(topologyAddress.parent(), // topology Address
nWriteTransactions, // number of write transactions
topologyAddress.tail(), // port of Device
i2cWriteTransactions, // list of write transactions
NV_DISPLAYID2_DDC_ADDRESS >> 1, // right shifted DDC Address (request identifier in spec)
NV_DISPLAYID2_BLOCK_SIZE); // requested size
manager->post(&remoteI2cRead, this);
}
void DID2ReadMultistream::messageCompleted(MessageManager::Message * from)
{
RemoteI2cReadMessage* I2CReadMessage = (RemoteI2cReadMessage*)from;
unsigned char * data = 0;
unsigned numBytesRead;
Address::StringBuffer buffer;
DP_USED(buffer);
DP_PRINTF(DP_NOTICE, "- for %s", topologyAddress.toString(buffer));
data = I2CReadMessage->replyGetI2CData(&numBytesRead);
DP_ASSERT(data);
remainingBytes += numBytesRead;
stream.write(data, numBytesRead);
bool bNotFinished = readNextRequest();
if (bNotFinished)
{
loop++;
readNextBlock();
}
else
{
// Did20 read is finished or failed.
sink->mstDid2Completed(this);
}
}
void DID2ReadMultistream::expired(const void * tag)
{
Address::StringBuffer buffer;
DP_USED(buffer);
DP_PRINTF(DP_NOTICE, "%s on %s", __FUNCTION__, topologyAddress.toString(buffer));
startReadingDid2();
}
void DID2ReadMultistream::messageFailed(MessageManager::Message * from, NakData * nakData)
{
Address::StringBuffer buffer;
DP_USED(buffer);
DP_PRINTF(DP_NOTICE, "%s on %s", __FUNCTION__, topologyAddress.toString(buffer));
if (nakData->reason == NakDefer || nakData->reason == NakTimeout)
{
if (retries < NV_DISPLAYID2_MAX_RETRIES)
{
++retries;
timer->queueCallback(this, "DID2", NV_DISPLAYID2_READ_RETRY_MS);
}
else
sink->mstDid2ReadFailed(this);
}
else
{
sink->mstDid2ReadFailed(this);
}
}
/*!
* @brief Check if there is more blocks to read.
*
* @param[in/out] seg The segment of the display sink.
* @param[in/out] offset The offset of the display sink.
*
* @return true if there is more blocks to read, false otherwise.
*
*/
bool DID2ReadMultistream::readNextRequest()
{
Buffer * buffer = displayId2x.getBuffer();
pSection = buffer->getData() + displayId2xSize;
if (!IS_VALID_DISPLAYID2_VERSION(pSection))
{
DP_PRINTF(DP_ERROR, "Invalid DisplayID2 version");
return false;
}
sectionLength = GET_DISPLAYID2_SECTION_LENGTH(pSection);
if (loop == 0)
{
// Only read the total extension count from Base section.
extensionCount = GET_DISPLAYID2_EXTENSION_COUNT(pSection);
if (extensionCount > 0)
{
NvU32 maxSize = sectionLength + extensionCount * NV_DISPLAYID2_BLOCK_SIZE;
if (!buffer->resize(maxSize))
{
DP_PRINTF(DP_ERROR, "Failed to resize buffer");
return false;
}
}
}
if (sectionLength > remainingBytes)
{
// the current section is not complete, and we don't have enough bytes already.
return true;
}
// Check if we need to read more bytes.
if (sectionLength <= remainingBytes)
{
if (getDID2BlockChecksum(pSection, sectionLength))
{
// Something went wrong! Let's retry.
if (retried)
{
DP_PRINTF(DP_ERROR, "Checksum validation still failed after retries");
return false;
}
DP_PRINTF(DP_ERROR, "Checksum validation failed, retrying...");
retried = true;
return true;
}
//
// The displayId2xSize is not 0 means that we're parsing
// the extension section, so we need to decrease the counter
// when the checksum validation is done.
//
if (displayId2xSize != 0)
extensionCount--;
//
// Update the total size of VESA DisplayID structure, and
// other variables for parsing next section if needed.
//
displayId2xSize += sectionLength;
remainingBytes -= sectionLength;
pSection = buffer->getData() + displayId2xSize;
sectionLength = 0;
}
displayId2x.setDisplayId2xSize(displayId2xSize);
return (extensionCount != 0);
}
void DID2ReadMultistream::readNextBlock()
{
NvU8 seg = loop >> 1;
NvU8 offset = (loop & 0x1) * NV_DISPLAYID2_BLOCK_SIZE;
I2cWriteTransaction i2cWriteTransactions[2];
Address::StringBuffer buffer;
DP_USED(buffer);
// ensure that init function for i2cWriteTranscation for segment and offset won't break
DP_ASSERT(sizeof(seg) == 1);
DP_ASSERT(sizeof(offset) == 1);
DP_PRINTF(DP_NOTICE, "DID2ReadMultistream::readNextBlock(): for %s (seg/offset) = %d/%d",
topologyAddress.toString(buffer),
seg, offset);
unsigned nWriteTransactions = 2;
// select segment
i2cWriteTransactions[0] = I2cWriteTransaction(NV_DISPLAYID2_DDC_SEG_SELECTOR_OFFSET >> 1,
1, &seg, true);
// set offset within segment
i2cWriteTransactions[1] = I2cWriteTransaction(NV_DISPLAYID2_DDC_ADDRESS >> 1,
1, &offset, true);
remoteI2cRead.set(topologyAddress.parent(), // topology Address
nWriteTransactions, // number of write transactions
topologyAddress.tail(), // port of Device
i2cWriteTransactions, // list of write transactions
NV_DISPLAYID2_DDC_ADDRESS >> 1, // right shifted DDC Address (request identifier in spec)
NV_DISPLAYID2_BLOCK_SIZE); // requested size
manager->post(&remoteI2cRead, this, false);
}

261
src/common/displayport/src/dp_qse.cpp
View File

@@ -30,3 +30,264 @@
#include "dp_auxdefs.h"
#include "dp_qse.h"
#include "dp_internal.h"
#include "dp_deviceimpl.h"
#include "dp_connectorimpl.h"
#include "dp_printf.h"
#include <nvmisc.h>
using namespace DisplayPort;
NvU64
QSENonceGenerator::random()
{
NvU64 randomNumber;
previousRandomLSB = static_cast<NvU32>(((NvU64)1664525 * previousRandomLSB + 1013904223));
previousRandomMSB = static_cast<NvU32>(((NvU64)1664525 * previousRandomMSB + 1013904223));
randomNumber = ((NvU64)previousRandomMSB << 32) | previousRandomLSB ;
return randomNumber;
}
void
QSENonceGenerator::clientIdBuilder
(
NvU64 aN
)
{
previousRandomMSB = (NvU32)(aN >> 32) ;
previousRandomLSB = (NvU32)(aN & 0xFFFFFFFF);
}
void
QSENonceGenerator::makeClientId
(
CLIENTID &clientId
)
{
// Generate 56 bit nonce
NvU64 rnd = random();
clientId.data[0] = static_cast<NvU8>( rnd & 0xFF);
clientId.data[1] = static_cast<NvU8>((rnd >> 8) & 0xFF);
clientId.data[2] = static_cast<NvU8>((rnd >> 16) & 0xFF);
clientId.data[3] = static_cast<NvU8>((rnd >> 24) & 0xFF);
clientId.data[4] = static_cast<NvU8>((rnd >> 32) & 0xFF);
clientId.data[5] = static_cast<NvU8>((rnd >> 40) & 0xFF);
clientId.data[6] = static_cast<NvU8>((rnd >> 48) & 0xFF);
}
StreamEncryptionStatusDetection::~StreamEncryptionStatusDetection()
{
connector->timer->cancelCallbacks(this);
}
void
StreamEncryptionStatusDetection::messageFailed
(
MessageManager::Message *from,
NakData *nakData
)
{
if (from == &qseMessage)
{
connector->messageManager->clearAwaitingQSEReplyDownRequest();
if ((retriesSendQSEMessage < DPCD_QUERY_STREAM_MESSAGE_RETRIES) &&
(nakData->reason == NakDefer || nakData->reason == NakTimeout))
{
connector->timer->cancelCallback(parent, &(parent->tagStreamValidation));
retriesSendQSEMessage++;
sendQSEMessage(parent);
connector->timer->queueCallback(parent, &(parent->tagStreamValidation), HDCP_STREAM_VALIDATION_REQUEST_COOLDOWN);
return;
}
//
// If message failed is called after all retries have expired then
// we should disable the HDCP.
//
else
{
DP_PRINTF(DP_ERROR, "DP-QSE> Downstream failed to handle %s QSES message",
reason == qseReason_Ssc ? "SSC" : "generic");
//
// Non-QSE supported branch would get HDCP off if we honor QSES's result even w/o SSC from it.
// So to improve compatibility, we honor QSES's result to have HDCP off only if it's fired for SSC.
//
if (reason == qseReason_Ssc)
{
for (ListElement * i = connector->activeGroups.begin(); i != connector->activeGroups.end(); i = i->next)
{
GroupImpl * group = (GroupImpl *)i;
if (group->hdcpEnabled)
{
//
// In case of MST, time slots will be deleted and add back for clearing ECF
// This will lead to blank screen momentarily
// Similarly for all other QSES errors
//
group->hdcpSetEncrypted(false, NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_0, NV_TRUE, NV_TRUE);
}
}
connector->main->configureHDCPAbortAuthentication(KSV_SIG);
connector->main->configureHDCPDisableAuthentication();
// Clear HDCP cap for groups and connector and devices.
connector->isHDCPAuthOn = false;
}
else
{
connector->bIsEncryptionQseValid = false;
}
retriesSendQSEMessage = 0;
parent->streamValidationDone = true;
//Reset the MessageManager pointer state
resetQseMessageState();
}
}
}
void
StreamEncryptionStatusDetection::expired(
const void * tag
)
{
// Not required as of now.
}
void
StreamEncryptionStatusDetection::handleQSEDownReply()
{
if ((connector->bValidQSERequest) && (handleQSEReplyValidation()))
{
parent->streamValidationDone = true;
}
else
{
connector->bValidQSERequest = true;
parent->streamValidationDone = true;
}
}
void
StreamEncryptionStatusDetection::messageCompleted
(
MessageManager::Message *from
)
{
if (from == &qseMessage)
{
handleQSEDownReply();
//Reset the MessageManager pointer state
resetQseMessageState();
}
}
void
StreamEncryptionStatusDetection::sendQSEMessage
(
GroupImpl *group,
QSE_REASON reasonId
)
{
Address address(0);
CLIENTID clientId;
HDCPState hdcpState = {0};
// Get hdcp version to see if hdcp22 QSE or not.
connector->main->configureHDCPGetHDCPState(hdcpState);
setHdcp22Qse(hdcpState.HDCP_State_22_Capable);
// Check whether repeater or not.
bIsRepeater = hdcpState.HDCP_State_Repeater_Capable;
//Generate the Pseudo Random number
connector->qseNonceGenerator->makeClientId(clientId);
for (unsigned i = 0 ; i < CLIENT_ID_SIZE; i++)
{
group->clientId[i] = clientId.data[i];
}
this->reason = reasonId;
group->streamValidationDone = false;
qseMessage.set( address,
group->streamIndex,
clientId.data,
CP_IRQ_ON,
STREAM_EVENT_MASK_ON,
Force_Reauth,
STREAM_BEHAVIOUR_MASK_ON);
connector->messageManager->post(&qseMessage, this);
}
bool
StreamEncryptionStatusDetection::handleQSEReplyValidation()
{
if (parent->streamIndex != qseMessage.getStreamId())
{
DP_PRINTF(DP_ERROR, "DP-QSE> Query the active Stream ID %d, but reply Stream ID %d mismatch.", parent->streamIndex, qseMessage.getStreamId());
parent->hdcpSetEncrypted(false, NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_0, NV_TRUE, NV_TRUE);
return false;
}
NvU16 streamStatus = 0;
streamStatus = qseMessage.getStreamStatus();
DP_PRINTF(DP_NOTICE, "DP-QSE> Query the active Stream ID %d. The reply streamStatus: %d", parent->streamIndex, streamStatus);
NvU16 streamState = DRF_VAL(_DP, _HDCP, _STREAM_STATE, streamStatus);
if ((streamState == NV_DP_HDCP_STREAM_STATE_NO_EXIST) ||
(streamState == NV_DP_HDCP_STREAM_STATE_ERROR))
{
DP_PRINTF(DP_ERROR, "DP-QSE> Query the active Stream ID %d, but reply as Stream does not exist or Error/Reserved", parent->streamIndex);
parent->hdcpSetEncrypted(false, NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_0, NV_TRUE, NV_TRUE);
return false;
}
else if (streamState == NV_DP_HDCP_STREAM_STATE_NOT_ACTIVE)
{
DP_PRINTF(DP_ERROR, "DP-QSE> Query the active Stream ID %d, but reply as Stream not active", parent->streamIndex);
parent->hdcpSetEncrypted(false, NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_0, NV_TRUE, NV_TRUE);
return false;
}
NvU16 streamAuth = DRF_VAL(_DP, _HDCP, _STREAM_AUTHENTICATION, streamStatus);
if (streamAuth == NV_DP_HDCP_STREAM_AUTHENTICATION_OFF)
{
DP_PRINTF(DP_ERROR, "DP-QSE> Query the Stream ID %d, reply as failed authentication all the way down", parent->streamIndex);
parent->hdcpSetEncrypted(false, NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_0, NV_TRUE, NV_TRUE);
return false;
}
// Watch here for not over reacting encryption policy here.
NvU16 streamEncrypt = DRF_VAL(_DP, _HDCP, _STREAM_ENCRYPTION, streamStatus);
if (streamEncrypt == NV_DP_HDCP_STREAM_ENCRYPTION_OFF)
{
if (parent->hdcpEnabled)
{
DP_PRINTF(DP_ERROR, "DP-QSE> Query the Stream ID %d, reply as not encryption all the way down", parent->streamIndex);
parent->qseEncryptionStatusMismatch = parent->hdcpEnabled;
parent->hdcpSetEncrypted(false, NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_0, NV_TRUE, NV_TRUE);
}
else
return false;
}
return true;
}
void
StreamEncryptionStatusDetection::resetQseMessageState()
{
qseMessage.clear();
}
void
StreamEncryptionStatusDetection::setHdcp22Qse(bool bHdcp22Qse)
{
bIsHdcp22Qse = bHdcp22Qse;
qseMessage.setHdcp22Qse(bHdcp22Qse);
}

365
src/common/displayport/src/dp_sst_displayid2.cpp Normal file
View File

@@ -0,0 +1,365 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort *******************************\
* *
* Module: dp_sst_displayid2.c *
* Implementation Single Stream DisplayID2x reads *
* *
\***************************************************************************/
#include "dp_internal.h"
#include "dp_displayid2.h"
#include "dp_printf.h"
using namespace DisplayPort;
/*!
* @brief Read a 128-byte data block from display sink.
* Note this might not be aligned with DID2 section since DID2 section length is not fixed.
*
* @param[in] aux The auxiliary bus instance.
* @param[in] timer The timer instance.
* @param[in] segment The segment of the display sink.
* @param[in] offset The offset of the display sink.
* @param[in/out] buffer The buffer to store the data.
*
* @return true if the data is read successfully, false otherwise.
*
*/
static bool sstReadDid2Block
(
AuxBus *auxBus,
Timer *timer,
NvU8 segment,
NvU8 offset,
Buffer *buffer
)
{
AuxBus::Type type = AuxBus::i2cMot;
AuxBus::status auxStatus;
unsigned retries = 0;
unsigned sizeRequested;
unsigned sizeCompleted;
unsigned transactionSize = auxBus->transactionSize();
unsigned totalRead = 0;
DP_ASSERT(auxBus);
DP_ASSERT(transactionSize > 0);
// ASSERT if displayId2x offset wasn't increased in block len sizes
DP_ASSERT(offset == 0 || offset == NV_DISPLAYID2_BLOCK_SIZE);
NvU32 totalSizeRequired = NV_DISPLAYID2_BLOCK_SIZE * segment * 2 + offset + NV_DISPLAYID2_BLOCK_SIZE;
NvU32 startOffset = NV_DISPLAYID2_BLOCK_SIZE * segment * 2 + offset;
if ((buffer->capacity < totalSizeRequired) && !(buffer->resize(totalSizeRequired)))
{
return false;
}
DP_ASSERT(sizeof(segment) == 1);
DP_ASSERT(sizeof(offset) == 1);
// start DID2 read by specifying appropriate DID2 segment id
for (unsigned retry = 0; retry < NV_DISPLAYID2_MAX_RETRIES; retry++)
{
auxStatus = auxBus->transaction(AuxBus::write, AuxBus::i2cMot, NV_DISPLAYID2_DDC_SEG_SELECTOR_OFFSET >> 1,
&segment, sizeof(segment), &sizeCompleted);
if (auxStatus == AuxBus::success)
break;
// If deferred due to timeout
if (auxStatus == AuxBus::defer)
{
// Wait for sometime between retries
timer->sleep(NV_DISPLAYID2_AUX_WAIT_TIME);
continue;
}
return false;
}
auxStatus = AuxBus::nack;
for (retries = 0; totalRead < NV_DISPLAYID2_BLOCK_SIZE;)
{
//
// For retry, rewrite the Offset for the internal read pointer
// except when the previous Read auxstatus was an Aux::defer
// since in that case, the offset was never incremented by sink
//
if ((auxStatus != AuxBus::success) && (auxStatus != AuxBus::defer))
{
// start from this offset, need to verify with display with multiple edid blocks
for (unsigned retry = 0; retry < NV_DISPLAYID2_MAX_AUX_RETRIES; retry++)
{
auxStatus = auxBus->transaction(AuxBus::write, AuxBus::i2cMot, NV_DISPLAYID2_DDC_ADDRESS >> 1,
(NvU8*)(&offset), sizeof(offset), &sizeCompleted);
if (auxStatus == AuxBus::success)
break;
// If deferred due to timeout
if (auxStatus == AuxBus::defer)
{
// Wait for sometime between retries
timer->sleep(NV_DISPLAYID2_AUX_WAIT_TIME);
continue;
}
return false;
}
// if retries exceed NV_DISPLAYID2_MAX_AUX_RETRIES, give up
if (auxStatus != AuxBus::success)
{
return false;
}
}
// need to change to I2C (not MOT) to read just one last part of EDID block
if (totalRead + transactionSize >= NV_DISPLAYID2_BLOCK_SIZE)
type = AuxBus::i2c;
sizeRequested = DP_MIN(transactionSize, NV_DISPLAYID2_BLOCK_SIZE - totalRead);
auxStatus = auxBus->transaction(AuxBus::read, type, NV_DISPLAYID2_DDC_ADDRESS >> 1,
&(buffer->data[startOffset + totalRead]), sizeRequested, &sizeCompleted);
if (AuxBus::success != auxStatus || (sizeRequested && (sizeCompleted == 0)))
{
if (retries >= NV_DISPLAYID2_MAX_AUX_RETRIES)
return false;
DP_PRINTF(DP_WARNING, "DisplayPort: %s: Retrying at totalRead 0x%08x (replyType %x, size %x)",
__FUNCTION__, totalRead, auxStatus, sizeRequested);
// Wait for sometime between retries
timer->sleep(NV_DISPLAYID2_AUX_WAIT_TIME);
retries++;
continue;
}
// Assert when size mismatches and it is not last block
if ((sizeRequested != sizeCompleted) &&
(totalRead + transactionSize < NV_DISPLAYID2_BLOCK_SIZE))
{
DP_PRINTF(DP_ERROR, "DisplayPort: %s: dpAux returned edid block smaller than expected. Read from totalRead 0x%08x (replyType %x, size %x)",
__FUNCTION__, totalRead, auxStatus, sizeRequested);
DP_ASSERT(0);
}
retries = 0; // reset the number of retries
totalRead += sizeCompleted;
offset += (NvU8)sizeCompleted;
}
return true;
}
static bool sstReadDid2(DisplayID2x & did2x, AuxBus * aux, Timer * timer, MainLink *main)
{
NvU32 vesaDisplayIdSize = 0;
NvU32 sectionLength = 0;
NvU8 extensionCount = 0;
NvU8 loop = 0;
NvU8 segment = 0;
NvU8 offset = 0;
unsigned retries = 0;
bool status = false;
bool bReadNextBlock = false;
NvU32 remainingBytes = 0;
NvU8 *pSection = 0;
Buffer *buffer = did2x.getBuffer();
const NvU8 blockSize = NV_DISPLAYID2_BLOCK_SIZE;
do
{
// Reset these variables before starting to read data.
loop = 0;
remainingBytes = 0;
sectionLength = 0;
extensionCount = 0;
vesaDisplayIdSize = 0;
// The main loop for reading all sections of a VESA DisplayID structure.
do
{
//
// The sub loop for doing i2c-over-dpAux sequential read transcation, and the
// default size per transcation is a 128-byte block here. Although
// the data size of each transcation is implementation-specific,
// assuming a 128-byte block here like what we do for EDID increases
// interoperability with most display sinks.
//
do
{
if ((remainingBytes <= NV_DISPLAYID2_BYTES_IN_SECTION_MIN) ||
(remainingBytes < sectionLength))
{
segment = loop >> 1;
offset = (loop & 0x1) * blockSize;
status = sstReadDid2Block(aux, timer, segment, offset, buffer);
if (!status)
break;
// Increase the bytes read and loop count.
remainingBytes += blockSize;
loop++;
}
// Point to the current section of VESA DisplayID data structure.
pSection = buffer->data + vesaDisplayIdSize;
// Check the VESA DisplayID structure signature/version.
if (!IS_VALID_DISPLAYID2_VERSION(pSection))
{
status = false;
DP_PRINTF(DP_ERROR, "Invalid DisplayID2 version");
break;
}
// Read the bytes in section of this section.
sectionLength = GET_DISPLAYID2_SECTION_LENGTH(pSection);
// Only read the total extension count from Base section.
if ((segment == 0) && (offset == 0))
{
extensionCount = GET_DISPLAYID2_EXTENSION_COUNT(pSection);
//
// The initial buffer size sets to a 256-byte data section,
// so we're enlarging it to fit the worst-case here.
//
if (extensionCount > 0)
{
NvU32 maxSize = sectionLength +
extensionCount * NV_DISPLAYID2_BLOCK_SIZE;
status = buffer->resize(maxSize);
if (!status)
{
DP_PRINTF(DP_ERROR, "Failed to resize buffer");
return status;
}
// Base block + extension blocks
did2x.setBlockCount(extensionCount + 1);
}
}
// Check if we need to read more bytes.
if (sectionLength <= remainingBytes)
{
if (getDID2BlockChecksum(pSection, sectionLength))
{
status = false;
DP_PRINTF(DP_ERROR, "Checksum validation failed");
break;
}
//
// The vesaDisplayIdSize is not 0 means that we're parsing
// the extension section, so we need to decrease the counter
// when the checksum validation is done.
//
if (vesaDisplayIdSize != 0)
extensionCount--;
//
// Update the total size of VESA DisplayID structure, and
// other variables for parsing next section if needed.
//
vesaDisplayIdSize += sectionLength;
remainingBytes -= sectionLength;
sectionLength = 0;
//
// Once this section is validated, set flag to exit current
// loop and move to the next section.
//
bReadNextBlock = false;
}
else
{
// We don't have a whole section. Let's read another block.
bReadNextBlock = true;
}
} while (bReadNextBlock);
// Something went wrong! Let's retry.
if (!status)
break;
} while (extensionCount > 0);
retries++;
} while ((!status) &&
(retries <= NV_DISPLAYID2_MAX_RETRIES));
if (status)
{
status = buffer->resize(vesaDisplayIdSize);
did2x.setDisplayId2xSize(vesaDisplayIdSize);
}
return status;
}
bool DisplayPort::DisplayId2ReadSST(DisplayID2x & did2x, AuxBus * aux, Timer * timer, MainLink *main)
{
bool status = false;
NvU8 retries = 0;
Buffer *buffer = did2x.getBuffer();
if (!buffer->resize(NV_DISPLAYID2_BLOCK_SIZE))
{
return false;
}
if ((aux == NULL) || (timer == NULL))
{
DP_PRINTF(DP_ERROR, "DP-DID2> Invalid parameters for SST read. aux: %p, timer: %p", aux, timer);
return false;
}
do {
status = sstReadDid2(did2x, aux, timer, main);
} while ((!status) &&
((retries++) <= NV_DISPLAYID2_MAX_RETRIES));
return status;
}
NvU8 DisplayPort::getDID2BlockChecksum(NvU8 * buffer, NvU8 blockSize)
{
unsigned chksum = 0;
for (unsigned i = 0; i < blockSize; i++)
{
chksum += buffer[i];
}
chksum = chksum & 0xFF;
return (NvU8)chksum;
}

2
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -631,7 +631,7 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
}
else if (ProductID == 0x5CA7 || ProductID == 0x9E9D || ProductID == 0x9EA0 || ProductID == 0x9EA5 || ProductID == 0x5CB7 ||
ProductID == 0x9EA8 || ProductID == 0x9EAF || ProductID == 0x7846 || ProductID == 0x7849 || ProductID == 0x5CB5 ||
ProductID == 0x77E0 || ProductID == 0x9EB9)
ProductID == 0x77E0 || ProductID == 0x9EB9 || ProductID == 0x5BBF)
{
this->WARFlags.bForceHeadShutdownOnModeTransition = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Force head shutdown on Mode transition.");

78
src/common/displayport/src/dptestutil/dp_testmessage.cpp
View File

@@ -39,6 +39,11 @@ void DPTestMessageCompletion::messageFailed(MessageManager::Message * from, NakD
{
parent->testMessageStatus = DP_TESTMESSAGE_REQUEST_STATUS_DONE;
if (from->getMsgType() == NV_DP_SBMSG_REQUEST_ID_QUERY_STREAM_ENCRYPTION_STATUS)
{
delete (QueryStreamEncryptionMessage *)from;
}
else
{
{
DP_ASSERT(0 && "unknown msg type when msg failed");
@@ -50,6 +55,12 @@ void DPTestMessageCompletion::messageCompleted(MessageManager::Message * from)
{
parent->testMessageStatus = DP_TESTMESSAGE_REQUEST_STATUS_DONE;
if (from->getMsgType() == NV_DP_SBMSG_REQUEST_ID_QUERY_STREAM_ENCRYPTION_STATUS)
{
((QueryStreamEncryptionMessage *)from)->getReply(&parent->qsesReply);
delete (QueryStreamEncryptionMessage *)from;
}
else
{
{
DP_ASSERT(0 && "unknown msg type when msg complete");
@@ -62,6 +73,31 @@ MessageManager * TestMessage::getMessageManager()
return pMsgManager;
}
//pBuffer should point to a DP_TESTMESSAGE_REQUEST_QSES_INPUT structure
void TestMessage::sendTestMsgQSES(void *pBuffer)
{
//Generate the Pseudo Random number
QSENonceGenerator qseNonceGenerator;
//for qses, send to the root branch
Address address(0);
CLIENTID clientId;
QueryStreamEncryptionMessage *pQseMessage = new QueryStreamEncryptionMessage();
DP_TESTMESSAGE_REQUEST_QSES_INPUT *pQSES =
(DP_TESTMESSAGE_REQUEST_QSES_INPUT *)pBuffer;
pQseMessage->set(address,
pQSES->streamID,
clientId.data,
CP_IRQ_ON,
STREAM_EVENT_MASK_ON,
Force_Reauth,
STREAM_BEHAVIOUR_MASK_ON);
pMsgManager->post(pQseMessage, &diagCompl);
}
//
// The function request that the request struct size should be check first to ensure the right structure is used and
// no BSOD will happen.
@@ -88,7 +124,45 @@ DP_TESTMESSAGE_STATUS TestMessage::sendDPTestMessage
if (!isValidStruct(type, requestSize))
return DP_TESTMESSAGE_STATUS_ERROR_INVALID_PARAM;
*pDpStatus = DP_TESTMESSAGE_REQUEST_STATUS_ERROR;
return DP_TESTMESSAGE_STATUS_ERROR;
switch (type)
{
case DP_TESTMESSAGE_REQUEST_TYPE_QSES:
// new request, try send message
if (*pDpStatus == DP_TESTMESSAGE_REQUEST_STATUS_NEWREQUEST)
{
//there is still processing request, new one not allow now
if (testMessageStatus == DP_TESTMESSAGE_REQUEST_STATUS_PENDING)
{
*pDpStatus = DP_TESTMESSAGE_REQUEST_STATUS_ERROR;
return DP_TESTMESSAGE_STATUS_ERROR;
}
else
{
sendTestMsgQSES(pBuffer);
//need change the DP lib status accordingly
*pDpStatus = DP_TESTMESSAGE_REQUEST_STATUS_PENDING;
testMessageStatus = DP_TESTMESSAGE_REQUEST_STATUS_PENDING;
}
}
//old request, check if request finished
else if(*pDpStatus == DP_TESTMESSAGE_REQUEST_STATUS_PENDING)
{
//already finished, fill in the data
if (testMessageStatus == DP_TESTMESSAGE_REQUEST_STATUS_DONE)
{
DP_TESTMESSAGE_REQUEST_QSES_INPUT *p =
(DP_TESTMESSAGE_REQUEST_QSES_INPUT *)pBuffer;
p->reply = *(DP_TESTMESSAGE_REQUEST_QSES_OUTPUT *)&qsesReply;
*pDpStatus = DP_TESTMESSAGE_REQUEST_STATUS_DONE;
}
//otherwise, just return and ask the user try again
}
break;
default:
*pDpStatus = DP_TESTMESSAGE_REQUEST_STATUS_ERROR;
return DP_TESTMESSAGE_STATUS_ERROR;
}
return DP_TESTMESSAGE_STATUS_SUCCESS;
}

5
src/common/inc/displayport/dpcd20.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -180,6 +180,9 @@
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_SINK_STATUS (0x00000205) /* R-XUR */
#define NV_DPCD20_SINK_STATUS_STREAM_REGENERATED 2:2 /* R-XUF */
#define NV_DPCD20_SINK_STATUS_STREAM_REGENERATED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_SINK_STATUS_STREAM_REGENERATED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_SINK_STATUS_INTRA_HOP_AUX_REPLY 3:3 /* R-XUF */
#define NV_DPCD20_SINK_STATUS_INTRA_HOP_AUX_REPLY_DPRX (0x00000000) /* R-XUV */
#define NV_DPCD20_SINK_STATUS_INTRA_HOP_AUX_REPLY_LTTPR (0x00000001) /* R-XUV */

2
src/common/inc/hdmi_spec.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

6
src/common/inc/nvBinSegment.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2012-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,6 +21,10 @@
* DEALINGS IN THE SOFTWARE.
*/
/** @file nvBinSegment.h
* @brief <TBA>
*/
#ifndef NVBINSEGMENT_H
#define NVBINSEGMENT_H

22
src/common/inc/nvBldVer.h
View File

@@ -36,26 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r591_47
#define NV_BUILD_BRANCH VK595_35
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r591_47
#define NV_PUBLIC_BRANCH VK595_35
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r590/r591_47-174"
#define NV_BUILD_CHANGELIST_NUM (37007394)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r595/VK595_35-123"
#define NV_BUILD_CHANGELIST_NUM (37461308)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r590/r591_47-174"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37007394)
#define NV_BUILD_NAME "rel/gpu_drv/r595/VK595_35-123"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37461308)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r591_47-1"
#define NV_BUILD_CHANGELIST_NUM (37007394)
#define NV_BUILD_BRANCH_VERSION "VK595_35-6"
#define NV_BUILD_CHANGELIST_NUM (37461308)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "591.51"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37007394)
#define NV_BUILD_BRANCH_BASE_VERSION R590
#define NV_BUILD_NAME "595.84"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37461308)
#define NV_BUILD_BRANCH_BASE_VERSION R595
#endif
// End buildmeister python edited section

21
src/common/inc/nvPNPVendorIds.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009 - 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -19,19 +19,16 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* This header file contains the 3-character Plug and Play Vendor IDs and
* their translation into Vendor names.
*/
/** @file nvPNPVendorIds.h
* @brief Contains the 3-character Plug and Play Vendor IDs and their translation into Vendor names.
*
* If the includer defines NV_PNP_VENDOR_IDS_USE_TCHAR, then
* PNPVendorID::vendorName will have type const TCHAR*; otherwise, it will have
* type const char*.
* If the includer defines NV_PNP_VENDOR_IDS_USE_TCHAR, then PNPVendorID::vendorName will have type const TCHAR*;
* otherwise, it will have type const char*.
*
* References:
* https://uefi.org/pnp_id_list
*
*/
* References: https://uefi.org/pnp_id_list
*/
#ifndef __NV_PNP_VENDOR_IDS_H__
#define __NV_PNP_VENDOR_IDS_H__

2
src/common/inc/nvUnixVersion.h
View File

@@ -5,7 +5,7 @@
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) || \
defined(NV_DCECORE)
#define NV_VERSION_STRING "590.48.01"
#define NV_VERSION_STRING "595.44.02"
#else

2
src/common/inc/nvVer.h
View File

@@ -3,7 +3,7 @@
#define NV_COMPANY_NAME_STRING_SHORT "NVIDIA"
#define NV_COMPANY_NAME_STRING_FULL "NVIDIA Corporation"
#define NV_COMPANY_NAME_STRING NV_COMPANY_NAME_STRING_FULL
#define NV_COPYRIGHT_YEAR "2025"
#define NV_COPYRIGHT_YEAR "2026"
#define NV_COPYRIGHT "(C) " NV_COPYRIGHT_YEAR " NVIDIA Corporation. All rights reserved." // Please do not use the non-ascii copyright symbol for (C).
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \

7
src/common/inc/nvlog_defs.h
View File

@@ -65,6 +65,11 @@ typedef struct _NVLOG_RING_BUFFER_EXTRA_FIELDS
} NVLOG_RING_BUFFER_EXTRA_FIELDS;
// For offline tools
#if !defined(PORT_IS_KERNEL_BUILD) || PORT_IS_KERNEL_BUILD == 0
#define PORT_ATOMIC volatile
#endif
/**
* @brief Struct representing a buffer in NvLog
*
@@ -90,7 +95,7 @@ struct _NVLOG_BUFFER
/** Position of the next available byte in the buffer */
NvU32 pos;
/** Number of threads currently writing to this buffer */
volatile NvS32 threadCount;
PORT_ATOMIC NvS32 threadCount;
/** Specific buffer types will define their fields here */
union
{

20
src/common/inc/swref/published/ampere/ga100/dev_ce.h → src/common/inc/swref/published/ampere/ga100/dev_ce_base.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,13 +21,13 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_ce_h__
#define __ga100_dev_ce_h__
#define NV_CE_PCE_MAP 0x00104028 /* R--4R */
#define NV_CE_PCE2LCE_CONFIG__SIZE_1 18 /* */
#define NV_CE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE 0x0000000f /* RW--V */
#define NV_CE_GRCE_CONFIG__SIZE_1 2 /* */
#define NV_CE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#define NV_CE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#ifndef __ga100_dev_ce_base_h__
#define __ga100_dev_ce_base_h__
#define NV_CE_BASE_PCE_MAP 0x00000028 /* R--4R */
#define NV_CE_BASE_PCE2LCE_CONFIG__SIZE_1 18 /* */
#define NV_CE_BASE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE 0x0000000f /* RW--V */
#define NV_CE_BASE_GRCE_CONFIG__SIZE_1 2 /* */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#define NV_CE_BASE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#endif

26
src/common/inc/swref/published/ampere/ga102/dev_ce.h → src/common/inc/swref/published/ampere/ga102/dev_ce_base.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,16 +21,16 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_ce_h__
#define __ga102_dev_ce_h__
#define NV_CE_PCE_MAP 0x00104028 /* R--4R */
#define NV_CE_PCE_MAP_VALUE 23:0 /* R-XVF */
#define NV_CE_HSH_PCE_MASK 0x0010404c /* C--4R */
#define NV_CE_HSH_PCE_MASK_VALUE 23:0 /* C--VF */
#define NV_CE_PCE2LCE_CONFIG__SIZE_1 6 /* */
#define NV_CE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE 0x0000000f /* RW--V */
#define NV_CE_GRCE_CONFIG__SIZE_1 2 /* */
#define NV_CE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#define NV_CE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#ifndef __ga102_dev_ce_base_h__
#define __ga102_dev_ce_base_h__
#define NV_CE_BASE_PCE_MAP 0x00000028 /* R--4R */
#define NV_CE_BASE_PCE_MAP_VALUE 23:0 /* R-XVF */
#define NV_CE_BASE_HSH_PCE_MASK 0x0000004c /* C--4R */
#define NV_CE_BASE_HSH_PCE_MASK_VALUE 23:0 /* C--VF */
#define NV_CE_BASE_PCE2LCE_CONFIG__SIZE_1 6 /* */
#define NV_CE_BASE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE 0x0000000f /* RW--V */
#define NV_CE_BASE_GRCE_CONFIG__SIZE_1 2 /* */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#define NV_CE_BASE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#endif

5
src/common/inc/swref/published/ampere/ga102/dev_fbif_v4.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,9 +27,12 @@
#define NV_PFALCON_FBIF_TRANSCFG(i) (0x00000000+(i)*4) /* RW-4A */
#define NV_PFALCON_FBIF_TRANSCFG__SIZE_1 8 /* */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_LOCAL_FB 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_ENGINE_ID_FLAG 16:16 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_ENGINE_ID_FLAG_BAR2_FN0 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_CTL 0x00000024 /* RW-4R */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */

2
src/common/inc/swref/published/blackwell/gb100/dev_boot_zb.h
View File

@@ -35,5 +35,7 @@
#define NV_PMC_ZB_ENABLE_PDISP 30:30 /* RWBVF */
#define NV_PMC_ZB_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ZB_ENABLE_PDISP_ENABLED 0x00000001 /* RWB-V */
#define NV_PMC_ZB_BOOT_42 0x00000A00 /* R--4R */
#define NV_PMC_ZB_BOOT_0 0x00000000 /* R--4R */
#endif // __gb100_dev_boot_zb_h__

6
src/common/inc/swref/published/blackwell/gb100/dev_bus_addendum.h
View File

@@ -24,6 +24,12 @@
#ifndef gb100_dev_nv_bus_addendum_h
#define gb100_dev_nv_bus_addendum_h
//
// This register is used report GSP errors
//
#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR NV_PBUS_SW_SCRATCH(0x37)
#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_CODE 31:0
/*!
* @defgroup FRTS_INSECURE_SCRATCH_REGISTERS
*

32
src/common/inc/swref/published/blackwell/gb100/dev_bus_zb.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_bus_zb_h__
#define __gb100_dev_bus_zb_h__
#define NV_PBUS_ZB_SW_SCRATCH(i) (0x00000400+(i)*4) /* RW-4A */
#define NV_PBUS_ZB_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_ZB_SW_SCRATCH_FIELD 31:0 /* RWBVF */
#define NV_PBUS_ZB_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWB-V */
#endif // __gb100_dev_bus_zb_h__

43
src/common/inc/swref/published/blackwell/gb100/dev_esched_pbdma.h Normal file
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@@ -0,0 +1,43 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_esched_pbdma_h__
#define __gb100_dev_esched_pbdma_h__
#define NV_PBDMA 0x000007ff:0x00000000 /* RW--D */
#define NV_PBDMA_GP_BASE 0x090 /* RW-4R */
#define NV_PBDMA_GP_BASE_RSVD 2:0 /* RWXUF */
#define NV_PBDMA_GP_BASE_RSVD_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_BASE_HI 0x094 /* RW-4R */
#define NV_PBDMA_GP_BASE_HI_OFFSET 24:0 /* RWXUF */
#define NV_PBDMA_GP_BASE_HI_OFFSET_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_MISC_FETCH_STATE 0x0b4 /* RW-4R */
#define NV_PBDMA_MISC_FETCH_STATE_GP_INFO_LIMIT2 28:24 /* RWXUF */
#define NV_PBDMA_MISC_FETCH_STATE_GP_INFO_LIMIT2_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_SEGMENT_EXTENDED_BASE 0x05C /* RW-4R */
#define NV_PBDMA_PB_SEGMENT_EXTENDED_BASE_VALUE 24:8 /* RWXUF */
#define NV_PBDMA_PB_SEGMENT_EXTENDED_BASE_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_SEGMENT_EXTENDED_BASE_RSVD 31:25 /* RWXUF */
#define NV_PBDMA_PB_SEGMENT_EXTENDED_BASE_RSVD_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_SEGMENT_EXTENDED_BASE_RSVD2 7:0 /* RWXUF */
#define NV_PBDMA_PB_SEGMENT_EXTENDED_BASE_RSVD2_ZERO 0x00000000 /* RW--V */
#endif // __gb100_dev_esched_pbdma_h__

21
src/common/inc/swref/published/turing/tu102/dev_ce.h → src/common/inc/swref/published/blackwell/gb100/dev_fb.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,11 +21,14 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __tu102_dev_ce_h__
#define __tu102_dev_ce_h__
#define NV_CE_PCE2LCE_CONFIG__SIZE_1 4 /* */
#define NV_CE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE 0x0000000f /* RW--V */
#define NV_CE_GRCE_CONFIG__SIZE_1 2 /* */
#define NV_CE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#endif // __tu102_dev_ce_h__
#ifndef __gb100_dev_fb_h_
#define __gb100_dev_fb_h_
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE 0x001FA3E0 /* RW-4R */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE__PRIV_LEVEL_MASK 0x001FA7C4 /* */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_SCALE 3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_SCALE_INIT 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_MAG 27:4 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_MAG_INIT 0x00000000 /* RWE-V */
#endif // __gb100_dev_fb_h_

31
src/common/inc/swref/published/blackwell/gb100/dev_gc6_island.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_gc6_island_h__
#define __gb100_dev_gc6_island_h__
#define NV_PGC6_BSI_SECURE_SCRATCH_12 0x001180f0 /* RW-4R */
#define NV_PGC6_BSI_SECURE_SCRATCH_12_DATA 31:0 /* RWIVF */
#define NV_PGC6_BSI_SECURE_SCRATCH_12_DATA_INIT 0x00000000 /* RWI-V */
#endif // __gb100_dev_gc6_island_h__

29
src/common/inc/swref/published/blackwell/gb100/dev_gc6_island_addendum.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_gc6_island_addendum_h__
#define __gb100_dev_gc6_island_addendum_h__
#define NV_PGC6_BSI_SECURE_SCRATCH_MMU_LOCAL_MEMORY_RANGE NV_PGC6_BSI_SECURE_SCRATCH_12
#endif // __gb100_dev_gc6_island_addendum_h__

5
src/common/inc/swref/published/blackwell/gb100/dev_hshub.h
View File

@@ -25,6 +25,9 @@
#define __gb100_dev_hshub_h__
// Needed to boot GSP before we get the whole device info table.
#define NV_PFB_HSHUB0 0x00870fff:0x00870000
// Derived from NV_PFB_HSHUB0
// HW provides these define in hwproject.h in chips after Blackwell
#define NV_HSHUB0_PRIV_BASE 0x870000
#define NV_HSHUB_PRIV_STRIDE 0x1000
#endif // __gb100_dev_hshub_h__

43
src/common/inc/swref/published/blackwell/gb100/dev_hshub_base.h
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@@ -1,43 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_hshub_base_h__
#define __gb100_dev_hshub_base_h__
#define NV_PFB_HSHUB 0x00000FFF:0x00000000 /* RW--D */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO 0x00000E50 /* RW-4R */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xFFFFFF00 /* ----V */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00000E54 /* RW-4R */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO 0x000006C0 /* RW-4R */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xFFFFFF00 /* ----V */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI 0x000006C4 /* RW-4R */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#endif // __gb100_dev_hshub_base_h__

43
src/common/inc/swref/published/blackwell/gb100/dev_hshub_zb.h Normal file
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@@ -0,0 +1,43 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_hshub_zb_h__
#define __gb100_dev_hshub_zb_h__
#define NV_PFB_HSHUB_ZB 0x00000FFF:0x00000000 /* RW--D */
#define NV_PFB_HSHUB_ZB_PCIE_FLUSH_SYSMEM_ADDR_LO 0x00000E50 /* RW-4R */
#define NV_PFB_HSHUB_ZB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_ZB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_ZB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xFFFFFF00 /* ----V */
#define NV_PFB_HSHUB_ZB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00000E54 /* RW-4R */
#define NV_PFB_HSHUB_ZB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_ZB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_ZB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#define NV_PFB_HSHUB_ZB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO 0x000006C0 /* RW-4R */
#define NV_PFB_HSHUB_ZB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_ZB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_ZB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xFFFFFF00 /* ----V */
#define NV_PFB_HSHUB_ZB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI 0x000006C4 /* RW-4R */
#define NV_PFB_HSHUB_ZB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_ZB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_ZB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#endif // __gb100_dev_hshub_zb_h__

97
src/common/inc/swref/published/blackwell/gb100/dev_hubmmu_base.h Normal file
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@@ -0,0 +1,97 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_hubmmu_base_h__
#define __gb100_dev_hubmmu_base_h__
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS 0x0000A560 /* RW-4R */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS 0:0 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_CLEAR 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_SET 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT 1:1 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_RESET 0x00000000 /* RWE-V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_CLEAR 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_SET 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS 2:2 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_CLEAR 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_SET 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT 3:3 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_RESET 0x00000000 /* RWE-V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_CLEAR 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_SET 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS 4:4 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_CLEAR 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_SET 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT 5:5 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_RESET 0x00000000 /* RWE-V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_CLEAR 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_SET 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS 6:6 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_CLEAR 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_SET 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT 7:7 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_RESET 0x00000000 /* RWE-V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_CLEAR 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_SET 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_REPLAYABLE 8:8 /* R-EVF */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_REPLAYABLE_RESET 0x00000000 /* R-E-V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_REPLAYABLE_SET 0x00000001 /* R---V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_VALID 31:31 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_VALID_RESET 0x00000000 /* RWE-V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_VALID_CLEAR 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_STATUS_VALID_SET 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_HI_VIRT(i,j) (0x2004+((i)*128)+((j)*20)) /* RW-4A */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_HI_VIRT__SIZE_1 64 /* */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_HI_VIRT__SIZE_2 2 /* */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_HI_VIRT__PRIV_LEVEL_MASK 0xaa70 /* */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_HI_VIRT_ADDR 31:0 /* RW-VF */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_LO_VIRT(i,j) (0x2000+((i)*128)+((j)*20)) /* RW-4A */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_LO_VIRT__SIZE_1 64 /* */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_LO_VIRT__SIZE_2 2 /* */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_LO_VIRT__PRIV_LEVEL_MASK 0xaa70 /* */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_LO_VIRT_ADDR_MODE 0:0 /* R--VF */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_LO_VIRT_PHYS_APERTURE 2:1 /* RW-VF */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_LO_VIRT_PHYS_VOL 3:3 /* RW-VF */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_LO_VIRT_ADDR 31:12 /* RW-VF */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */
#define NV_HUBMMU_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_HUBMMU_PRI_MMU_WPR1_ADDR_LO 0xa81c /* RW-4R */
#define NV_HUBMMU_PRI_MMU_WPR1_ADDR_LO_VAL 31:4 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_WPR1_ADDR_LO_ALIGNMENT 0x0000000c /* */
#define NV_HUBMMU_PRI_MMU_WPR1_ADDR_HI 0xa820 /* RW-4R */
#define NV_HUBMMU_PRI_MMU_WPR1_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_WPR1_ADDR_HI_ALIGNMENT 0x0000000c /* */
#define NV_HUBMMU_PRI_MMU_WPR2_ADDR_LO 0xa824 /* RW-4R */
#define NV_HUBMMU_PRI_MMU_WPR2_ADDR_LO_VAL 31:4 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_WPR2_ADDR_LO_ALIGNMENT 0x0000000c /* */
#define NV_HUBMMU_PRI_MMU_WPR2_ADDR_HI 0xa828 /* RW-4R */
#define NV_HUBMMU_PRI_MMU_WPR2_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_HUBMMU_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT 0x0000000c /* */
#endif // __gb100_dev_hubmmu_base_h__

10
src/common/inc/swref/published/blackwell/gb100/pri_nv_xal_ep_p2p.h → src/common/inc/swref/published/blackwell/gb100/dev_nv_xal_ep_p2p_zb.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,8 +21,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_pri_nv_xal_ep_p2p_h__
#define __gb100_pri_nv_xal_ep_p2p_h__
#ifndef __gb100_dev_nv_xal_ep_p2p_zb__h__
#define __gb100_dev_nv_xal_ep_p2p_zb__h__
#define NV_XAL_EP_P2P 0x00827fff:0x00826000 /* RW--D */
#define NV_XAL_EP_P2P_REG_STRIDE 64
@@ -33,7 +33,7 @@
#define NV_XAL_EP_P2P_WMBOX_ADDR_DIS 0:0 /* RWIUF */
#define NV_XAL_EP_P2P_WMBOX_ADDR_DIS_DISABLED 0x1 /* RWI-V */
#define NV_XAL_EP_P2P_WMBOX_ADDR_DIS_ENABLED 0x0 /* RW--V */
#define NV_XAL_EP_P2P_WMBOX_ADDR_ADDR 23:1 /* RWIUF */
#define NV_XAL_EP_P2P_ZB_WMBOX_ADDR_ADDR 23:1 /* RWIUF */
#define NV_XAL_EP_P2P_WMBOX_ADDR_ADDR_INIT 0x03ffff /* RWI-V */
#define NV_XAL_EP_P2P_WREQMB_L(i) (0x00826200+(i)*64) /* R--4A */
#define NV_XAL_EP_P2P_WREQMB_L__SIZE_1 8 /* */
@@ -46,4 +46,4 @@
#define NV_XAL_EP_P2P_WREQMB_H_REQ_ATTR 4:0 /* R-IUF */
#define NV_XAL_EP_P2P_WREQMB_H_REQ_ATTR_INIT 0x00 /* R-I-V */
#endif // __gb100_pri_nv_xal_ep_p2p_h__
#endif // __gb100_dev_nv_xal_ep_p2p_zb__h__

18
src/common/inc/swref/published/blackwell/gb100/pri_nv_xal_ep.h → src/common/inc/swref/published/blackwell/gb100/dev_nv_xal_ep_zb.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,10 +21,10 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_pri_nv_xal_ep_h__
#define __gb100_pri_nv_xal_ep_h__
#ifndef __gb100_dev_nv_xal_ep_zb__h__
#define __gb100_dev_nv_xal_ep_zb__h__
#define NV_XAL_EP_INTR_0 0x0010f100 /* RW-4R */
#define NV_XAL_EP_ZB_INTR_0 0x00000100 /* RW-4R */
#define NV_XAL_EP_INTR_0_PRI_FECSERR 1:1 /* RWIVF */
#define NV_XAL_EP_INTR_0_PRI_FECSERR_PENDING 0x1 /* R---V */
#define NV_XAL_EP_INTR_0_PRI_REQ_TIMEOUT 2:2 /* RWIVF */
@@ -33,12 +33,12 @@
#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT_PENDING 0x1 /* R---V */
#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT 5:5 /* RWIVF */
#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT_PENDING 0x1 /* R---V */
#define NV_XAL_EP_INTR_0_TRS_TIMEOUT 24:24 /* RWIVF */
#define NV_XAL_EP_INTR_0_TRS_TIMEOUT_PENDING 0x1 /* R---V */
#define NV_XAL_EP_ZB_INTR_0_TRS_TIMEOUT 24:24 /* RWIVF */
#define NV_XAL_EP_ZB_INTR_0_TRS_TIMEOUT_PENDING 0x1 /* R---V */
#define NV_XAL_EP_SCPM_PRI_DUMMY_DATA_PATTERN_INIT 0xbadf0200 /* RWI-V */
#define NV_XAL_EP_BAR0_WINDOW 0x0010fd40 /* RW-4R */
#define NV_XAL_EP_BAR0_WINDOW_BASE 22:0 /* RWIUF */
#define NV_XAL_EP_ZB_BAR0_WINDOW 0x00000d40 /* RW-4R */
#define NV_XAL_EP_ZB_BAR0_WINDOW_BASE 22:0 /* RWIUF */
#define NV_XAL_EP_BAR0_WINDOW_BASE_0 0x000000 /* RWI-V */
#define NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT 0x000010 /* */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS 0x0010f808 /* R--4R */
@@ -60,4 +60,4 @@
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS_IDLE 0x0 /* R-I-V */
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS_BUSY 0x1 /* R---V */
#endif // __gb100_pri_nv_xal_ep_h__
#endif // __gb100_dev_nv_xal_ep_zb__h__

40
src/common/inc/swref/published/blackwell/gb100/dev_pcfg_pf0.h
View File

@@ -120,7 +120,6 @@
#define NV_PF0_SUBSYSTEM_ID_AND_VENDOR_ID 0x0000002c /* R--4R */
#define NV_PF0_LINK_CONTROL_AND_STATUS 0x00000050 /* RW-4R */
#define NV_PF0_REVISION_ID_AND_CLASS_CODE_BASE_CLASS_CODE_3D 0 /* */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS 20:20 /* RWCVF */
#define NV_PF0_BASE_ADDRESS_REGISTERS_5 0x00000024 /* RW-4R */
#define NV_PF0_VF_BAR_0 0x00000324 /* RW-4R */
#define NV_PF0_LINK_CAPABILITIES 0x0000004c /* R--4R */
@@ -167,6 +166,8 @@
#define NV_PF0_DEVICE_VENDOR_ID_VENDOR_ID_DEFAULT 0x000010de /* R-E-V */
#define NV_PF0_DEVICE_CONTROL_AND_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:8 /* RWIVF */
#define NV_PF0_DEVICE_CONTROL_2 0x00000068 /* RW-4R */
#define NV_PF0_DEVICE_CONTROL_2_LTR_MECHANISM_ENABLE 10:10 /* RWIVF */
#define NV_PF0_DEVICE_CONTROL_2_LTR_MECHANISM_ENABLE_DEFAULT 0x00000000 /* RWI-V */
#define NV_PF0_DEVICE_CAPABILITIES_FUNCTION_LEVEL_RESET_CAPABILITY 28:28 /* R-IVF */
#define NV_PF0_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS 0:0 /* RWCVF */
#define NV_PF0_REVISION_ID_AND_CLASS_CODE_SUB_CLASS_CODE 23:16 /* R-IVF */
@@ -174,6 +175,43 @@
#define NV_PF0_BASE_ADDRESS_REGISTERS_0_ADDR_TYPE_64BIT 2 /* */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS 0x0000014c /* RW-4R */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS 4:4 /* RWCVF */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS 20:20 /* RWCVF */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_IDE_CHECK_FAILED_STATUS 28:28 /* RWCVF */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_IDE_CHECK_FAILED_STATUS_DEFAULT 0x00000000 /* RWC-V */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_MISROUTED_IDE_TLP_STATUS 29:29 /* RWCVF */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_MISROUTED_IDE_TLP_STATUS_DEFAULT 0x00000000 /* RWC-V */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_PCRC_CHECK_FAILED_STATUS 30:30 /* RWCVF */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_PCRC_CHECK_FAILED_STATUS_DEFAULT 0x00000000 /* RWC-V */
#define NV_PF0_UNCORRECTABLE_ERROR_MASK 0x00000150 /* RW-4R */
#define NV_PF0_UNCORRECTABLE_ERROR_MASK_IDE_CHECK_FAILED_MASK 28:28 /* RWCVF */
#define NV_PF0_UNCORRECTABLE_ERROR_MASK_IDE_CHECK_FAILED_MASK_DEFAULT 0x00000000 /* RWC-V */
#define NV_PF0_UNCORRECTABLE_ERROR_MASK_MISROUTED_IDE_TLP_MASK 29:29 /* RWCVF */
#define NV_PF0_UNCORRECTABLE_ERROR_MASK_MISROUTED_IDE_TLP_MASK_DEFAULT 0x00000000 /* RWC-V */
#define NV_PF0_UNCORRECTABLE_ERROR_MASK_PCRC_CHECK_FAILED_MASK 30:30 /* RWCVF */
#define NV_PF0_UNCORRECTABLE_ERROR_MASK_PCRC_CHECK_FAILED_MASK_DEFAULT 0x00000000 /* RWC-V */
#define NV_PF0_UNCORRECTABLE_ERROR_SEVERITY 0x00000154 /* RW-4R */
#define NV_PF0_UNCORRECTABLE_ERROR_SEVERITY_IDE_CHECK_FAILED_SEVERITY 28:28 /* RWCVF */
#define NV_PF0_UNCORRECTABLE_ERROR_SEVERITY_IDE_CHECK_FAILED_SEVERITY_DEFAULT 0x00000001 /* RWC-V */
#define NV_PF0_UNCORRECTABLE_ERROR_SEVERITY_MISROUTED_IDE_TLP_SEVERITY 29:29 /* RWCVF */
#define NV_PF0_UNCORRECTABLE_ERROR_SEVERITY_MISROUTED_IDE_TLP_SEVERITY_DEFAULT 0x00000000 /* RWC-V */
#define NV_PF0_UNCORRECTABLE_ERROR_SEVERITY_PCRC_CHECK_FAILED_SEVERITY 30:30 /* RWCVF */
#define NV_PF0_UNCORRECTABLE_ERROR_SEVERITY_PCRC_CHECK_FAILED_SEVERITY_DEFAULT 0x00000000 /* RWC-V */
#define NV_PF0_IDE_CONTROL 0x000003f0 /* R--4R */
#define NV_PF0_IDE_CONTROL_FLOW_THROUGH_IDE_STREAM_ENABLED 2:2 /* R-IVF */
#define NV_PF0_IDE_CONTROL_FLOW_THROUGH_IDE_STREAM_ENABLED_DEFAULT 0x00000000 /* R-I-V */
#define NV_PF0_LINK_IDE_STREAM_CONTROL_0 0x000003f4 /* RW-4R */
#define NV_PF0_LINK_IDE_STREAM_CONTROL_0_LINK_IDE_STREAM_ENABLE 0:0 /* RWIVF */
#define NV_PF0_LINK_IDE_STREAM_CONTROL_0_LINK_IDE_STREAM_ENABLE_DEFAULT 0x00000000 /* RWI-V */
#define NV_PF0_LINK_IDE_STREAM_STATUS_0 0x000003f8 /* RW-4R */
#define NV_PF0_LINK_IDE_STREAM_STATUS_0_LINK_IDE_STREAM_STATE 3:0 /* R-IVF */
#define NV_PF0_LINK_IDE_STREAM_STATUS_0_LINK_IDE_STREAM_STATE_DEFAULT 0x00000000 /* R-I-V */
#define NV_PF0_SELECTIVE_IDE_STREAM_CONTROL(i) (0x00000400+(i)*104) /* RW-4A */
#define NV_PF0_SELECTIVE_IDE_STREAM_CONTROL_SELECTIVE_IDE_STREAM_ENABLE 0:0 /* RWIVF */
#define NV_PF0_SELECTIVE_IDE_STREAM_CONTROL_SELECTIVE_IDE_STREAM_ENABLE_DEFAULT 0x00000000 /* RWI-V */
#define NV_PF0_SELECTIVE_IDE_STREAM_STATUS(i) (0x00000404+(i)*104) /* RW-4A */
#define NV_PF0_SELECTIVE_IDE_STREAM_STATUS__SIZE_1 16 /* */
#define NV_PF0_SELECTIVE_IDE_STREAM_STATUS_SELECTIVE_IDE_STREAM_STATE 3:0 /* R-IVF */
#define NV_PF0_SELECTIVE_IDE_STREAM_STATUS_SELECTIVE_IDE_STREAM_STATE_DEFAULT 0x00000000 /* R-I-V */
#define NV_PF0_STATUS_COMMAND 0x00000004 /* RW-4R */
#define NV_PF0_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS 13:13 /* RWCVF */
#define NV_PF0_STATUS_COMMAND_IO_SPACE_ENABLE_ENABLE 1 /* */

38
src/common/inc/swref/published/blackwell/gb100/dev_ram.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_ram_h__
#define __gb100_dev_ram_h__
#define NV_RAMFC /* ----G */
#define NV_RAMFC_PB_SEGMENT_EXTENDED_BASE (23*32+31):(23*32+0) /* RW-UF */
#define NV_RAMFC_GP_BASE (36*32+31):(36*32+0) /* RW-UF */
#define NV_RAMFC_GP_BASE_HI (37*32+31):(37*32+0) /* RW-UF */
#define NV_RAMFC_GP_GET (38*32+31):(38*32+0) /* RW-UF */
#define NV_RAMFC_MISC_FETCH_STATE (45*32+31):(45*32+0) /* RW-UF */
#define NV_RAMFC_DEBUG_STATE(i) (((i)+48)*32+31):(((i)+48)*32+0) /* RW-UF */
#define NV_RAMFC_DEBUG_STATE__SIZE_1 4 /* */
#define NV_RAMFC_DEBUG_STATE_RAMFC_INDEX_gp_put 0x00000000 /* */
#define NV_RAMFC_DEBUG_STATE_RAMFC_INDEX_gp_peek 0x00000001 /* */
#define NV_RAMFC_DEBUG_STATE_RAMFC_INDEX_gp_fetch 0x00000002 /* */
#define NV_RAMFC_DEBUG_STATE_RAMFC_INDEX_hdr_shadow 0x00000003 /* */
#endif // __gb100_dev_ram_h__

4
src/common/inc/swref/published/blackwell/gb100/dev_top_zb.h
View File

@@ -25,5 +25,7 @@
#define __gb100_dev_top_zb__h__
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_TMR 0x1f /* */
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_PBUS 0x33 /* */
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_HUBMMU 0x35 /* */
#endif // __gb100_dev_top_zb__h__
#endif // __gb100_dev_top_zb_h__

4
src/common/inc/swref/published/blackwell/gb100/hwproject.h
View File

@@ -32,5 +32,9 @@
#define NV_LTC_PRI_BASE 0x140000
#define NV_LTC_PRI_STRIDE 0x2000
#define NV_LTS_PRI_STRIDE 0x200
#define NV_PBUS0_PRI_BASE 0x1000
#define NV_HUBMMU0_PRI_BASE 0x880000
#define NV_PGRAPH_BASE 0x400000
#define NV_PTIMER0_PRI_BASE 0x9000
#endif // __gb100_hwproject_h__

6
src/common/inc/swref/published/blackwell/gb102/dev_bus_addendum.h
View File

@@ -24,6 +24,12 @@
#ifndef gb100_dev_nv_bus_addendum_h
#define gb100_dev_nv_bus_addendum_h
//
// This register is used report GSP errors
//
#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR NV_PBUS_SW_SCRATCH(0x37)
#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_CODE 31:0
/*!
* @defgroup FRTS_INSECURE_SCRATCH_REGISTERS
*

11
src/common/inc/swref/published/blackwell/gb202/pri_nv_xal_ep.h → src/common/inc/swref/published/blackwell/gb10b/dev_fuse.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,10 +21,9 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_pri_nv_xal_ep_h__
#define __gb202_pri_nv_xal_ep_h__
#ifndef __gb10b_dev_fuse_h__
#define __gb10b_dev_fuse_h__
#define NV_XAL_EP_BAR0_WINDOW 0x0010fd40 /* RW-4R */
#endif // __gb202_pri_nv_xal_ep_h__
#define NV_FUSE_STATUS_OPT_GPC 0x00820c1c /* R--4R */
#endif // __gb10b_dev_fuse_h__

14
src/common/inc/swref/published/blackwell/gb10b/dev_nv_xal_ep_zb.h
View File

@@ -20,8 +20,14 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_nv_xal_ep_zb_h__
#define __gb10b_dev_nv_xal_ep_zb_h__
#define NV_XAL_EP_ZB 0x00000FFF:0x00000000 /* RW--D */
#endif // __gb10b_dev_nv_xal_ep_zb_h__
#ifndef __gb10b_dev_nv_xal_ep_zb__h__
#define __gb10b_dev_nv_xal_ep_zb__h__
#define NV_XAL_EP_ZB 0x00000FFF:0x00000000 /* RW--D */
#define NV_XAL_EP_ZB_BAR0_WINDOW 0x00000d40 /* RW-4R */
#define NV_XAL_EP_ZB_BAR0_WINDOW_BASE 24:0 /* RWIUF */
#define NV_XAL_EP_BAR0_WINDOW_BASE_0 0x0000000 /* RWI-V */
#define NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT 0x0000010 /* */
#endif // __gb10b_dev_nv_xal_ep_zb__h__

29
src/common/inc/swref/published/blackwell/gb10b/dev_xtl_ep_pri.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_xtl_ep_pri_h__
#define __gb10b_dev_xtl_ep_pri_h__
#define NV_XTL_EP_PRI 0x00EFF:0x00000 /* RW--D */
#endif // __gb10b_dev_xtl_ep_pri_h__

5
src/common/inc/swref/published/blackwell/gb202/dev_ce_base.h
View File

@@ -23,9 +23,14 @@
#ifndef __gb202_dev_ce_base_h__
#define __gb202_dev_ce_base_h__
#define NV_CE_BASE_GRCE_CONFIG__SIZE_1 4
#define NV_CE_BASE_PCE2LCE_CONFIG__SIZE_1 4
#define NV_CE_BASE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#define NV_CE_BASE_GRCE_MASK 0x000000d8 /* C--4R */
#define NV_CE_BASE_GRCE_MASK_VALUE 9:0 /* C--VF */
#define NV_CE_BASE_GRCE_MASK_VALUE_INIT 0x00f /* C---V */
#endif // __gb202_dev_ce_base_h__

30
src/common/inc/swref/published/blackwell/gb202/dev_nv_xal_ep_zb.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_nv_xal_ep_zb__h__
#define __gb202_dev_nv_xal_ep_zb__h__
#define NV_XAL_EP_ZB_BAR0_WINDOW 0x00000d40 /* RW-4R */
#endif // __gb202_dev_nv_xal_ep_zb__h__

29
src/common/inc/swref/published/blackwell/gb202/dev_top_zb.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_top_zb__h__
#define __gb202_dev_top_zb__h__
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_LCE 0x13 /* */
#endif // __gb202_dev_top_zb__h__

29
src/common/inc/swref/published/blackwell/gb202/dev_xtl_ep_pri.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_xtl_ep_pri_h__
#define __gb202_dev_xtl_ep_pri_h__
#define NV_XTL_EP_PRI 0x01FFF:0x00000 /* RW--D */
#endif // __gb202_dev_xtl_ep_pri_h__

31
src/common/inc/swref/published/blackwell/gb202/hwproject.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_hwproject_h__
#define __gb202_hwproject_h__
#define NV_PMC0_PRI_BASE 0x0
#define NV_XTL_BASE_ADDRESS 0x8A000
#endif // __gb202_hwproject_h__

32
src/common/inc/swref/published/blackwell/gb20b/dev_bus_zb.h Normal file
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@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_bus_h__
#define __gb20b_dev_bus_h__
#define NV_PBUS_ZB_SW_SCRATCH(i) (0x00000400+(i)*4) /* RW-4A */
#define NV_PBUS_ZB_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_ZB_SW_SCRATCH_FIELD 31:0 /* RWBVF */
#define NV_PBUS_ZB_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWB-V */
#endif // __gb20b_dev_bus_h__

29
src/common/inc/swref/published/blackwell/gb20b/dev_top_zb.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_top_zb_h__
#define __gb20b_dev_top_zb_h__
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_PBUS 0x33 /* */
#endif // __gb20b_dev_top_zb_h__

6
src/common/inc/swref/published/hopper/gh100/dev_bus_addendum.h
View File

@@ -24,6 +24,12 @@
#ifndef gh100_dev_nv_bus_addendum_h
#define gh100_dev_nv_bus_addendum_h
//
// This register is used report GSP-FMC errors
//
#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR NV_PBUS_SW_SCRATCH(0x37)
#define NV_PBUS_SW_SCRATCH_GSP_FMC_ERROR_CODE 31:0
/*!
* @defgroup FRTS_INSECURE_SCRATCH_REGISTERS
*

16
src/common/inc/swref/published/hopper/gh100/dev_ce.h → src/common/inc/swref/published/hopper/gh100/dev_ce_base.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -20,10 +20,10 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_ce_h__
#define __gh100_dev_ce_h__
#define NV_CE_PCE2LCE_CONFIG__SIZE_1 16
#define NV_CE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#define NV_CE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#endif // __gh100_dev_ce_h__
#ifndef __gh100_dev_ce_base_h__
#define __gh100_dev_ce_base_h__
#define NV_CE_BASE_PCE2LCE_CONFIG__SIZE_1 16
#define NV_CE_BASE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#endif // __gh100_dev_ce_base_h__

37
src/common/inc/swref/published/hopper/gh100/dev_esched_pbdma.h Normal file
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@@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_esched_pbdma_h__
#define __gh100_dev_esched_pbdma_h__
#define NV_PBDMA 0x000007ff:0x00000000 /* RW--D */
#define NV_PBDMA_GP_BASE_RSVD 2:0 /* RWXUF */
#define NV_PBDMA_GP_BASE_RSVD_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_BASE_HI 0x04c /* RW-4R */
#define NV_PBDMA_GP_BASE_HI_OFFSET 24:0 /* RWXUF */
#define NV_PBDMA_GP_BASE_HI_OFFSET_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_INFO 0x0a4 /* RW-4R */
#define NV_PBDMA_GP_INFO_PB_SEGMENT_EXTENDED_BASE 24:8 /* RWXUF */
#define NV_PBDMA_GP_INFO_PB_SEGMENT_EXTENDED_BASE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_INFO_LIMIT2 4:0 /* RWXUF */
#define NV_PBDMA_GP_INFO_LIMIT2_ZERO 0x00000000 /* RW--V */
#endif // __gh100_dev_esched_pbdma_h__

19
src/common/inc/swref/published/hopper/gh100/dev_nv_xal_ep_p2p_zb.h
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@@ -20,7 +20,18 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_nv_xal_ep_p2p_zb_h__
#define __gh100_dev_nv_xal_ep_p2p_zb_h__
#define NV_XAL_EP_P2P_ZB 0x00001fff:0x00000000 /* RW--D */
#endif // __gh100_dev_nv_xal_ep_p2p_zb_h__
#ifndef __gh100_dev_nv_xal_ep_p2p_zb__h__
#define __gh100_dev_nv_xal_ep_p2p_zb__h__
#define NV_XAL_EP_P2P_ZB 0x00001fff:0x00000000
#define NV_XAL_EP_P2P_ZB_WMBOX_ADDR_ADDR 22:1
#define NV_XAL_EP_P2P_ZB_WREQMB_L(i) (0x00000200+(i)*64) /* R--4A */
#define NV_XAL_EP_P2P_ZB_WREQMB_L__SIZE_1 8 /* */
#define NV_XAL_EP_P2P_ZB_WREQMB_L__PRIV_LEVEL_MASK 0x00000900 /* */
#define NV_XAL_EP_P2P_WREQMB_L_PAGE_ADDR 21:0 /* R-IUF */
#define NV_XAL_EP_P2P_WREQMB_L_PAGE_ADDR_INIT 0x000000 /* R-I-V */
#define NV_XAL_EP_P2P_ZB_WREQMB_H(i) (0x00000204+(i)*64) /* R--4A */
#define NV_XAL_EP_P2P_ZB_WREQMB_H__SIZE_1 8 /* */
#define NV_XAL_EP_P2P_ZB_WREQMB_H__PRIV_LEVEL_MASK 0x00000900 /* */
#define NV_XAL_EP_P2P_WREQMB_H_REQ_ATTR 31:0 /* R-IUF */
#define NV_XAL_EP_P2P_WREQMB_H_REQ_ATTR_INIT 0x00000000 /* R-I-V */
#endif // __gh100_dev_nv_xal_ep_p2p_zb__h__

58
src/common/inc/swref/published/hopper/gh100/dev_nv_xal_ep_zb.h
View File

@@ -20,8 +20,58 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_nv_xal_ep_zb_h__
#define __gh100_dev_nv_xal_ep_zb_h__
#define NV_XAL_EP_ZB 0x00000FFF:0x00000000 /* RW--D */
#endif // __gh100_dev_nv_xal_ep_zb_h__
#ifndef __gh100_dev_nv_xal_ep_zb__h__
#define __gh100_dev_nv_xal_ep_zb__h__
#define NV_XAL_EP_ZB 0x00000FFF:0x00000000 /* RW--D */
#define NV_XAL_EP_ZB_BAR0_WINDOW_BASE_SHIFT 0x000010
#define NV_XAL_EP_ZB_BAR0_WINDOW_BASE 21:0
#define NV_XAL_EP_ZB_BAR0_WINDOW 0x00000d40
#define NV_XAL_EP_ZB_UFLUSH_L2_FLUSH_DIRTY 0x00000810
#define NV_XAL_EP_ZB_UFLUSH_L2_FLUSH_DIRTY_TOKEN 30:0
#define NV_XAL_EP_ZB_UFLUSH_L2_FLUSH_DIRTY_COMPLETED 0x00000814
#define NV_XAL_EP_ZB_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_TOKEN 30:0
#define NV_XAL_EP_ZB_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS 31:31
#define NV_XAL_EP_ZB_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS_BUSY 0x1
#define NV_XAL_EP_ZB_UFLUSH_FB_FLUSH 0x00000800 /* R--4R */
#define NV_XAL_EP_ZB_UFLUSH_FB_FLUSH_TOKEN 30:0 /* R-IUF */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_XAL_EP_ZB_UFLUSH_FB_FLUSH_COMPLETED 0x00000804 /* R--4R */
#define NV_XAL_EP_ZB_UFLUSH_FB_FLUSH_COMPLETED_TOKEN 30:0 /* R-IUF */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_XAL_EP_ZB_UFLUSH_FB_FLUSH_COMPLETED_STATUS 31:31 /* R-IUF */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_STATUS_IDLE 0x0 /* R-I-V */
#define NV_XAL_EP_ZB_UFLUSH_FB_FLUSH_COMPLETED_STATUS_BUSY 0x1 /* R---V */
#define NV_XAL_EP_ZB_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED 0x0000080c
#define NV_XAL_EP_ZB_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_TOKEN 30:0
#define NV_XAL_EP_ZB_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS 31:31
#define NV_XAL_EP_ZB_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS_BUSY 0x1
#define NV_XAL_EP_ZB_UFLUSH_L2_CLEAN_COMPTAGS 0x00000808
#define NV_XAL_EP_ZB_UFLUSH_L2_CLEAN_COMPTAGS_TOKEN 30:0
#define NV_XAL_EP_ZB_ZEROS 0x00000900 /* C--4R */
#define NV_XAL_EP_ZEROS_DATA 31:0 /* C--VF */
#define NV_XAL_EP_ZEROS_DATA_ZEROS 0x00000000 /* C---V */
#define NV_XAL_EP_ZB_INTR_0 0x00000100
#define NV_XAL_EP_ZB_INTR_0_FB_ACK_TIMEOUT 5:5
#define NV_XAL_EP_ZB_INTR_0_FB_ACK_TIMEOUT_PENDING 0x1
#define NV_XAL_EP_ZB_INTR_0_PRI_FECSERR 1:1
#define NV_XAL_EP_ZB_INTR_0_PRI_FECSERR_PENDING 0x1
#define NV_XAL_EP_ZB_INTR_0_PRI_REQ_TIMEOUT 2:2
#define NV_XAL_EP_ZB_INTR_0_PRI_REQ_TIMEOUT_PENDING 0x1
#define NV_XAL_EP_ZB_INTR_0_PRI_RSP_TIMEOUT 3:3
#define NV_XAL_EP_ZB_INTR_0_PRI_RSP_TIMEOUT_PENDING 0x1
#define NV_XAL_EP_ZB_SCPM_PRI_DUMMY_DATA_PATTERN_INIT 0xbadf0200
#define NV_XAL_EP_ZB_REORDER_ECC_UNCORRECTED_ERR_COUNT 0x00000364 /* RW-4R */
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIUF */
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
#define NV_XAL_EP_ZB_REORDER_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIUF */
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#define NV_XAL_EP_ZB_P2PREQ_ECC_UNCORRECTED_ERR_COUNT 0x0000037c /* RW-4R */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIUF */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
#define NV_XAL_EP_ZB_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIUF */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#endif // __gh100_dev_nv_xal_ep_zb__h__

10
src/common/inc/swref/published/hopper/gh100/dev_nv_xal_addendum.h → src/common/inc/swref/published/hopper/gh100/dev_nv_xal_zb_addendum.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,11 +21,11 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_nv_xal_addendum_h__
#define __gh100_dev_nv_xal_addendum_h__
#ifndef __gh100_dev_nv_xal_zb_addendum_h__
#define __gh100_dev_nv_xal_zb_addendum_h__
#define NV_XAL_EP_MEMOP_TOKEN_SIZE 31
#define NV_XAL_EP_MEMOP_TOKEN_MAX_ISSUED 4
#define NV_XAL_EP_MEMOP_MAX_OUTSTANDING 140
#define NV_XAL_EP_ZB_MEMOP_MAX_OUTSTANDING 140
#endif // __gh100_dev_nv_xal_addendum_h__
#endif // __gh100_dev_nv_xal_zb_addendum_h__

8
src/common/inc/swref/published/hopper/gh100/dev_ram.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,4 +26,10 @@
#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_LO (31+0*32):(8+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI_HW (19+1*32):(0+1*32) /* RWXUF */
#define NV_RAMFC /* ----G */
#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) /* RW-UF */
#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) /* RW-UF */
#define NV_RAMFC_GP_INFO (41*32+31):(41*32+0) /* RW-UF */
#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) /* RW-UF */
#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) /* RW-UF */
#endif // __gh100_dev_ram_h__

4
src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pri.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,7 +24,7 @@
#ifndef __gh100_dev_xtl_ep_pri_h__
#define __gh100_dev_xtl_ep_pri_h__
#define NV_EP_PCFGM 0x92FFF:0x92000 /* RW--D */
#define NV_XTL_EP_PRI 0x00FFF:0x00000 /* RW--D */
#define NV_XTL_EP_PRI_DED_ERROR_STATUS 0x0000043C /* RW-4R */
#define NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS 0x000003C8 /* RW-4R */
#endif // __gh100_dev_xtl_ep_pri_h__

75
src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h
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@@ -1,75 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_pri_nv_xal_ep_h__
#define __gh100_pri_nv_xal_ep_h__
#define NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT 0x000010
#define NV_XAL_EP_BAR0_WINDOW_BASE 21:0
#define NV_XAL_EP_BAR0_WINDOW 0x0010fd40
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY 0x0010f810
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_TOKEN 30:0
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED 0x0010f814
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_TOKEN 30:0
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS 31:31
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS_BUSY 0x1
#define NV_XAL_EP_UFLUSH_FB_FLUSH 0x0010f800 /* R--4R */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_TOKEN 30:0 /* R-IUF */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED 0x0010f804 /* R--4R */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_TOKEN 30:0 /* R-IUF */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_STATUS 31:31 /* R-IUF */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_STATUS_IDLE 0x0 /* R-I-V */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_STATUS_BUSY 0x1 /* R---V */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED 0x0010f80c
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_TOKEN 30:0
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS 31:31
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS_BUSY 0x1
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS 0x0010f808
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_TOKEN 30:0
#define NV_XAL_EP_ZEROS 0x0010f900 /* C--4R */
#define NV_XAL_EP_ZEROS_DATA 31:0 /* C--VF */
#define NV_XAL_EP_ZEROS_DATA_ZEROS 0x00000000 /* C---V */
#define NV_XAL_EP_INTR_0 0x0010f100
#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT 5:5
#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT_PENDING 0x1
#define NV_XAL_EP_INTR_0_PRI_FECSERR 1:1
#define NV_XAL_EP_INTR_0_PRI_FECSERR_PENDING 0x1
#define NV_XAL_EP_INTR_0_PRI_REQ_TIMEOUT 2:2
#define NV_XAL_EP_INTR_0_PRI_REQ_TIMEOUT_PENDING 0x1
#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT 3:3
#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT_PENDING 0x1
#define NV_XAL_EP_SCPM_PRI_DUMMY_DATA_PATTERN_INIT 0xbadf0200
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT 0x0010f364 /* RW-4R */
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIUF */
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIUF */
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT 0x0010f37c /* RW-4R */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIUF */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIUF */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#endif // __gh100_pri_nv_xal_ep_h__

37
src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep_p2p.h
View File

@@ -1,37 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_pri_nv_xal_ep_p2p_h__
#define __gh100_pri_nv_xal_ep_p2p_h__
#define NV_XAL_EP_P2P 0x00827fff:0x00826000
#define NV_XAL_EP_P2P_WMBOX_ADDR_ADDR 22:1
#define NV_XAL_EP_P2P_WREQMB_L(i) (0x00826200+(i)*64) /* R--4A */
#define NV_XAL_EP_P2P_WREQMB_L__SIZE_1 8 /* */
#define NV_XAL_EP_P2P_WREQMB_L__PRIV_LEVEL_MASK 0x00826900 /* */
#define NV_XAL_EP_P2P_WREQMB_L_PAGE_ADDR 21:0 /* R-IUF */
#define NV_XAL_EP_P2P_WREQMB_L_PAGE_ADDR_INIT 0x000000 /* R-I-V */
#define NV_XAL_EP_P2P_WREQMB_H(i) (0x00826204+(i)*64) /* R--4A */
#define NV_XAL_EP_P2P_WREQMB_H__SIZE_1 8 /* */
#define NV_XAL_EP_P2P_WREQMB_H__PRIV_LEVEL_MASK 0x00826900 /* */
#define NV_XAL_EP_P2P_WREQMB_H_REQ_ATTR 31:0 /* R-IUF */
#define NV_XAL_EP_P2P_WREQMB_H_REQ_ATTR_INIT 0x00000000 /* R-I-V */
#endif // __gh100_pri_nv_xal_ep_p2p_h__

35
src/common/inc/swref/published/maxwell/gm107/dev_esched_pbdma.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_pbdma_zero__
#define __gm107_dev_pbdma_zero__
#define NV_PBDMA 0x0001ffff:0x00000000 /* RW--D */
#define NV_PBDMA_GP_BASE_RSVD 2:0 /* RW-UF */
#define NV_PBDMA_GP_BASE_RSVD_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_BASE_HI(i) (0x0000004C+(i)*8192) /* RW-4A */
#define NV_PBDMA_GP_BASE_HI__SIZE_1 2 /* */
#define NV_PBDMA_GP_BASE_HI_OFFSET 7:0 /* RW-UF */
#define NV_PBDMA_GP_BASE_HI_OFFSET_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_BASE_HI_LIMIT2 20:16 /* RW-UF */
#define NV_PBDMA_GP_BASE_HI_LIMIT2_ZERO 0x00000000 /* RW--V */
#endif // __gm107_dev_pbdma_zero__

4
src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h
View File

@@ -162,6 +162,10 @@
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_CYA_2 0x00000704 /* RW-4R */
#define NV_XVE_DEVICE_CONTROL_STATUS_2 0x000000A0 /* RWI4R */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_LTR_ENABLE 10:10 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_DISABLED 0x00000000 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1 0x00000260 /* RW-4R */
#define NV_XVE_SW_RESET 0x00000718 /* RW-4R */
#define NV_XVE_SW_RESET_RESET 0:0 /* RWCVF */

7
src/common/inc/swref/published/maxwell/gm107/dev_ram.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -66,4 +66,9 @@
#define NV_RAMIN_PAGE_DIR_BASE_HI (129*32+7):(129*32+0) /* RWXUF */
#define NV_RAMIN_ADR_LIMIT_LO (130*32+31):(130*32+12) /* RWXUF */
#define NV_RAMIN_ADR_LIMIT_HI (131*32+7):(131*32+0) /* RWXUF */
#define NV_RAMFC /* ----G */
#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) /* RWXUF */
#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) /* RWXUF */
#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) /* RWXUF */
#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) /* RWXUF */
#endif // __gm107_dev_ram_h__

19
src/common/inc/swref/published/blackwell/gb10b/pri_nv_xal_ep.h → src/common/inc/swref/published/turing/tu102/dev_ce_base.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,12 +21,11 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_pri_nv_xal_ep_h__
#define __gb10b_pri_nv_xal_ep_h__
#define NV_XAL_EP_BAR0_WINDOW 0x0010fd40 /* RW-4R */
#define NV_XAL_EP_BAR0_WINDOW_BASE 24:0 /* RWIUF */
#define NV_XAL_EP_BAR0_WINDOW_BASE_0 0x0000000 /* RWI-V */
#define NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT 0x0000010 /* */
#endif // __gb10b_pri_nv_xal_ep_h__
#ifndef __tu102_dev_ce_base_h__
#define __tu102_dev_ce_base_h__
#define NV_CE_BASE_PCE2LCE_CONFIG__SIZE_1 4 /* */
#define NV_CE_BASE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE 0x0000000f /* RW--V */
#define NV_CE_BASE_GRCE_CONFIG__SIZE_1 2 /* */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#endif // __tu102_dev_ce_base_h__

29
src/common/inc/swref/published/turing/tu102/dev_fb.h
View File

@@ -31,6 +31,11 @@
#define NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_REPLAYABLE 64 /* R---V */
#define NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_NON_REPLAYABLE 132 /* R---V */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL 0x00100CF8 /* RW-4R */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER 1:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_ALL 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_NONE 0x00000003 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO 0x001FA824 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO_ALIGNMENT 0x0000000c /* */
@@ -38,6 +43,30 @@
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET(i) (0x00100E2C+(i)*20) /* RW-4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET__SIZE_1 2 /* */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR 19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR_RESET 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED 30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_NO 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_YES 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_CLEAR 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW 31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_NO 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_YES 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_CLEAR 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT(i) (0x00100E30+(i)*20) /* R--4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT__SIZE_1 2 /* */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_PTR 19:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_PTR_RESET 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED 30:30 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_NO 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_YES 0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW 31:31 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_NO 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */

4
src/common/inc/swref/published/turing/tu102/dev_fbif_v4.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,9 @@
#define NV_PFALCON_FBIF_TRANSCFG(i) (0x00000000+(i)*4) /* RW-4A */
#define NV_PFALCON_FBIF_TRANSCFG__SIZE_1 8 /* */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_LOCAL_FB 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_INSTBLK 0x00000020 /* R--4R */

6
src/common/inc/swref/published/turing/tu102/dev_ltc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -25,9 +25,5 @@
#define __tu102_dev_ltc_h_
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001404f8 /* RW-4R */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#endif // __tu102_dev_ltc_h_

17
src/common/inc/swref/published/blackwell/gb202/dev_ce.h → src/common/inc/swref/published/turing/tu102/dev_ltc_zb.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,9 +21,12 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_ce_h__
#define __gb202_dev_ce_h__
#define NV_CE_GRCE_MASK 0x001040d8 /* C--4R */
#define NV_CE_GRCE_MASK_VALUE 9:0 /* C--VF */
#define NV_CE_GRCE_MASK_VALUE_INIT 0x00f /* C---V */
#endif // __gb202_dev_ce_h__
#ifndef __tu102_dev_ltc_zb_h_
#define __tu102_dev_ltc_zb_h_
#define NV_PLTC_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
#define NV_PLTC_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
#define NV_PLTC_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
#define NV_PLTC_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#endif // __tu102_dev_ltc_zb_h_

6
src/common/modeset/hdmipacket/nvhdmi_frlInterface.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,7 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/** @file nvhdmi_frlInterface.h
/** @file nvhdmi_frlInterface.h
* @brief This file provides FRL related interfaces between client and HDMI lib
*/
@@ -180,7 +180,7 @@ typedef struct tagHDMI_FRL_CONFIG
NvU32 dscHActiveBytes;
NvU32 dscHActiveTriBytes;
NvU32 dscHBlankTriBytes;
NvU32 dscTBlankToTTotalRatioX1k;
NvU32 dscTBlankToTTotalRatioX1k;
} dscInfo;
} HDMI_FRL_CONFIG;

27
src/common/modeset/hdmipacket/nvhdmipkt.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2012-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -19,10 +19,10 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* File: nvhdmipkt.c
*
* Purpose: Provide initialization functions for HDMI library
*/
/** @file nvhdmipkt.c
** @brief Provide initialization functions for HDMI library
*/
#include <stddef.h>
@@ -611,6 +611,14 @@ NvHdmiPkt_CallConstructors(NVHDMIPKT_CLASS_ID const thisClassId,
return NV_TRUE;
}
static void
NvHdmiPkt_NullPrint(NvHdmiPkt_CBHandle handle,
const char *format, ...)
{
// Noop implementation. Avoids having to check for NULL on every call.
}
/******************************** HDMI Library Init functions ***********************************/
/*
* NvHdmiPkt_InitializeLibrary
@@ -712,7 +720,14 @@ NvHdmiPkt_InitializeLibrary(NvU32 const hwClass,
pClass->callback.checkTimeout = pCallbacks->checkTimeout;
#endif
pClass->callback.print = pCallbacks->print;
if (pCallbacks->print == NULL)
{
pClass->callback.print = NvHdmiPkt_NullPrint;
}
else
{
pClass->callback.print = pCallbacks->print;
}
#if defined (DEBUG)
pClass->callback.assert = pCallbacks->assert;

10
src/common/modeset/hdmipacket/nvhdmipkt.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2012-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -19,10 +19,10 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* File: nvhdmipkt.h
*
* Purpose: This file is a common header for all HDMI Library Clients
*/
/** @file nvhdmipkt.h
** @brief This file is a common header for all HDMI Library Clients
*/
#ifndef _NVHDMIPKT_H_

10
src/common/modeset/hdmipacket/nvhdmipkt_0073.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -19,10 +19,10 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* File: nvhdmipkt_0073.c
*
* Purpose: Provides infoframe write functions for HDMI library for Pre-KEPLER chips
*/
/** @file nvhdmipkt_0073.c
* @brief Provides infoframe write functions for HDMI library for pre-KEPLER chips
*/
#include "nvhdmipkt_common.h"

10
src/common/modeset/hdmipacket/nvhdmipkt_9171.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -19,10 +19,10 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* File: nvhdmipkt_9171.c
*
* Purpose: Provides packet write functions for HDMI library for KEPLER + chips
*/
/** @file nvhdmipkt_9171.c
* @brief Provides packet write functions for HDMI library for KEPLER+ chips
*/
#include "nvlimits.h"

10
src/common/modeset/hdmipacket/nvhdmipkt_9271.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -19,10 +19,10 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* File: nvhdmipkt_9271.c
*
* Purpose: Provides packet write functions for HDMI library for KEPLER + chips
*/
/** @file nvhdmipkt_9271.c
* @brief Provides packet write functions for HDMI library for KEPLER+ chips
*/
#include "nvhdmipkt_common.h"

10
src/common/modeset/hdmipacket/nvhdmipkt_9471.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -19,10 +19,10 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* File: nvhdmipkt_9471.c
*
* Purpose: Provides packet write functions for HDMI library for Maxwell + chips
*/
/** @file nvhdmipkt_9471.c
* @brief Provides packet write functions for HDMI library for Maxwell+ chips
*/
#include "nvhdmipkt_common.h"

10
src/common/modeset/hdmipacket/nvhdmipkt_9571.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -19,10 +19,10 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* File: nvhdmipkt_9571.c
*
* Purpose: Provides packet write functions for HDMI library for Maxwell + chips
*/
/** @file nvhdmipkt_9571.c
* @brief Provides packet write functions for HDMI library for Maxwell+ chips
*/
#include "nvhdmipkt_common.h"

10
src/common/modeset/hdmipacket/nvhdmipkt_C371.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2016-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -19,10 +19,10 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* File: nvhdmipkt_C371.c
*
* Purpose: Provides packet write functions for HDMI library for Volta+ chips
*/
/** @file nvhdmipkt_C371.c
* @brief Provides packet write functions for HDMI library for Volta+ chips
*/
#include "nvhdmipkt_common.h"

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