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550.107.02

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This commit is contained in:
Bernhard Stoeckner
2024-07-29 10:22:58 +02:00
parent caa2dd11a0
commit 2cca8b3fd5
66 changed files with 1016 additions and 447 deletions
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1
src/common/displayport/inc/dp_connector.h
View File

@@ -282,6 +282,7 @@ namespace DisplayPort
virtual void markDeviceForDeletion() = 0;
virtual bool getRawDscCaps(NvU8 *buffer, NvU32 bufferSize) = 0;
virtual bool setRawDscCaps(NvU8 *buffer, NvU32 bufferSize) = 0;
// This interface is still nascent. Please don't use it. Read size limit is 16 bytes.
virtual AuxBus::status getDpcdData(unsigned offset, NvU8 * buffer,

2
src/common/displayport/inc/dp_deviceimpl.h
View File

@@ -44,6 +44,7 @@ namespace DisplayPort
#define HDCP_BCAPS_DDC_EN_BIT 0x80
#define HDCP_BCAPS_DP_EN_BIT 0x01
#define HDCP_I2C_CLIENT_ADDR 0x74
#define DSC_CAPS_SIZE 16
struct GroupImpl;
struct ConnectorImpl;
@@ -421,6 +422,7 @@ namespace DisplayPort
virtual void markDeviceForDeletion() {bisMarkedForDeletion = true;};
virtual bool isMarkedForDeletion() {return bisMarkedForDeletion;};
virtual bool getRawDscCaps(NvU8 *buffer, NvU32 bufferSize);
virtual bool setRawDscCaps(NvU8 *buffer, NvU32 bufferSize);
virtual AuxBus::status dscCrcControl(NvBool bEnable, gpuDscCrc *dataGpu, sinkDscCrc *dataSink);

9
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -472,6 +472,15 @@ bool DeviceImpl::getRawDscCaps(NvU8 *buffer, NvU32 bufferSize)
return true;
}
bool DeviceImpl::setRawDscCaps(NvU8 *buffer, NvU32 bufferSize)
{
if (bufferSize < sizeof(rawDscCaps))
return false;
dpMemCopy(&rawDscCaps, buffer, sizeof(rawDscCaps));
return parseDscCaps(&rawDscCaps[0], sizeof(rawDscCaps));
}
AuxBus::status DeviceImpl::transaction(Action action, Type type, int address,
NvU8 * buffer, unsigned sizeRequested,
unsigned * sizeCompleted,

22
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r550_00
#define NV_BUILD_BRANCH r552_86
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r550_00
#define NV_PUBLIC_BRANCH r552_86
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r550_00-326"
#define NV_BUILD_CHANGELIST_NUM (34471492)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r552_86-355"
#define NV_BUILD_CHANGELIST_NUM (34618165)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r550/r550_00-326"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34471492)
#define NV_BUILD_NAME "rel/gpu_drv/r550/r552_86-355"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34618165)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r550_00-324"
#define NV_BUILD_CHANGELIST_NUM (34468048)
#define NV_BUILD_TYPE "Nightly"
#define NV_BUILD_NAME "r550_00-240627"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34454921)
#define NV_BUILD_BRANCH_VERSION "r552_86-1"
#define NV_BUILD_CHANGELIST_NUM (34615400)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "552.87"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34615400)
#define NV_BUILD_BRANCH_BASE_VERSION R550
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "550.100"
#define NV_VERSION_STRING "550.107.02"
#else

2
src/common/inc/swref/published/ampere/ga102/dev_falcon_v4.h
View File

@@ -57,7 +57,9 @@
#define NV_PFALCON_FALCON_DMATRFCMD 0x00000118 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */
#define NV_PFALCON_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMATRFCMD_FULL_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IDLE_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMATRFCMD_SEC 3:2 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */

10
src/common/nvswitch/common/inc/rmsoecmdif.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -49,6 +49,7 @@
#include "soe/soeifsmbpbi.h"
#include "soe/soeifcore.h"
#include "soe/soeifchnmgmt.h"
#include "soe/soeiftnvl.h"
#include "soe/soeifcci.h"
#include "soe/soeifheartbeat.h"
@@ -71,6 +72,7 @@ typedef struct
RM_SOE_BIF_CMD bif;
RM_SOE_CORE_CMD core;
RM_SOE_CHNMGMT_CMD chnmgmt;
RM_SOE_TNVL_CMD tnvl;
RM_SOE_CCI_CMD cci;
} cmd;
} RM_FLCN_CMD_SOE,
@@ -126,8 +128,9 @@ typedef struct
#define RM_SOE_TASK_ID_CCI 0x0D
#define RM_SOE_TASK_ID_FSPMGMT 0x0E
#define RM_SOE_TASK_ID_HEARTBEAT 0x0F
#define RM_SOE_TASK_ID_TNVL 0x10
// Add new task ID here...
#define RM_SOE_TASK_ID__END 0x10
#define RM_SOE_TASK_ID__END 0x11
/*!
* Unit-identifiers:
@@ -151,8 +154,9 @@ typedef struct
#define RM_SOE_UNIT_CHNMGMT (0x0D)
#define RM_SOE_UNIT_CCI (0x0E)
#define RM_SOE_UNIT_HEARTBEAT (0x0F)
#define RM_SOE_UNIT_TNVL (0x10)
// Add new unit ID here...
#define RM_SOE_UNIT_END (0x10)
#define RM_SOE_UNIT_END (0x11)
#endif // _RMSOECMDIF_H_

76
src/common/nvswitch/common/inc/soe/soeiftnvl.h Normal file
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@@ -0,0 +1,76 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _SOEIFTNVL_H_
#define _SOEIFTNVL_H_
/*!
* @file soeiftnvl.h
* @brief SOE TNVL Command Queue
*
* The TNVL unit ID will be used for sending and recieving
* Command Messages between driver and TNVL unit of SOE
*/
/*!
* Commands offered by the SOE Tnvl Interface.
*/
enum
{
/*
* Issue register write command
*/
RM_SOE_TNVL_CMD_ISSUE_REGISTER_WRITE = 0x0,
/*
* Issue pre-lock sequence
*/
RM_SOE_TNVL_CMD_ISSUE_PRE_LOCK_SEQUENCE = 0x1,
};
/*!
* TNVL queue command payload
*/
typedef struct
{
NvU8 cmdType;
NvU32 offset;
NvU32 data;
} RM_SOE_TNVL_CMD_REGISTER_WRITE;
typedef struct
{
NvU8 cmdType;
} RM_SOE_TNVL_CMD_PRE_LOCK_SEQUENCE;
typedef union
{
NvU8 cmdType;
RM_SOE_TNVL_CMD_REGISTER_WRITE registerWrite;
RM_SOE_TNVL_CMD_PRE_LOCK_SEQUENCE preLockSequence;
} RM_SOE_TNVL_CMD;
#endif // _SOEIFTNVL_H_

14
src/common/nvswitch/kernel/cci/cci_nvswitch.c
View File

@@ -325,9 +325,17 @@ cciInit
NvU32 pci_device_id
)
{
nvswitch_task_create(device, _nvswitch_cci_poll_callback,
NVSWITCH_INTERVAL_1SEC_IN_NS / NVSWITCH_CCI_POLLING_RATE_HZ,
0);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_task_create(device, _nvswitch_cci_poll_callback,
NVSWITCH_INTERVAL_1SEC_IN_NS / NVSWITCH_CCI_POLLING_RATE_HZ,
0);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping CCI background task when TNVL is enabled\n");
}
return NVL_SUCCESS;
}

2
src/common/nvswitch/kernel/inc/haldef_nvswitch.h
View File

@@ -295,6 +295,8 @@
_op(NvlStatus, nvswitch_tnvl_get_attestation_report, (nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params), _arch) \
_op(NvlStatus, nvswitch_tnvl_send_fsp_lock_config, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_tnvl_get_status, (nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params), _arch) \
_op(NvlStatus, nvswitch_send_tnvl_prelock_cmd, (nvswitch_device *device), _arch) \
_op(void, nvswitch_tnvl_disable_interrupts, (nvswitch_device *device), _arch) \
NVSWITCH_HAL_FUNCTION_LIST_FEATURE_0(_op, _arch) \
#define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \

1
src/common/nvswitch/kernel/inc/lr10/lr10.h
View File

@@ -710,4 +710,5 @@ NvlStatus nvswitch_fsp_error_code_to_nvlstatus_map_lr10(nvswitch_device *device,
NvlStatus nvswitch_tnvl_get_attestation_certificate_chain_lr10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS *params);
NvlStatus nvswitch_tnvl_get_attestation_report_lr10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params);
NvlStatus nvswitch_tnvl_get_status_lr10(nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params);
void nvswitch_tnvl_disable_interrupts_lr10(nvswitch_device *device);
#endif //_LR10_H_

9
src/common/nvswitch/kernel/inc/ls10/ls10.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -188,7 +188,9 @@
#define SOE_VBIOS_VERSION_MASK 0xFF0000
#define SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR 0x370000
#define SOE_VBIOS_REVLOCK_ISSUE_INGRESS_STOP 0x440000
#define SOE_VBIOS_REVLOCK_ISSUE_INGRESS_STOP 0x4C0000
#define SOE_VBIOS_REVLOCK_ISSUE_REGISTER_WRITE 0x580000
#define SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND 0x600000
// LS10 Saved LED state
#define ACCESS_LINK_LED_STATE CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED
@@ -1058,6 +1060,9 @@ NvlStatus nvswitch_tnvl_get_attestation_certificate_chain_ls10(nvswitch_device *
NvlStatus nvswitch_tnvl_get_attestation_report_ls10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params);
NvlStatus nvswitch_tnvl_send_fsp_lock_config_ls10(nvswitch_device *device);
NvlStatus nvswitch_tnvl_get_status_ls10(nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params);
void nvswitch_tnvl_reg_wr_32_ls10(nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast, NvU32 eng_instance, NvU32 base_addr, NvU32 offset, NvU32 data);
NvlStatus nvswitch_send_tnvl_prelock_cmd_ls10(nvswitch_device *device);
void nvswitch_tnvl_disable_interrupts_ls10(nvswitch_device *device);
NvlStatus nvswitch_ctrl_get_soe_heartbeat_ls10(nvswitch_device *device, NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p);
NvlStatus nvswitch_cci_enable_iobist_ls10(nvswitch_device *device, NvU32 linkNumber, NvBool bEnable);

5
src/common/nvswitch/kernel/inc/ls10/soe_ls10.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -50,5 +50,6 @@ void nvswitch_heartbeat_soe_callback_ls10(nvswitch_device *device, RM_FLCN_
NvlStatus nvswitch_soe_set_nport_interrupts_ls10(nvswitch_device *device, NvU32 nport, NvBool bEnable);
void nvswitch_soe_disable_nport_fatal_interrupts_ls10(nvswitch_device *device, NvU32 nport,
NvU32 nportIntrEnable, NvU8 nportIntrType);
NvlStatus nvswitch_soe_issue_ingress_stop_ls10(nvswitch_device *device, NvU32 nport, NvBool bStop);
NvlStatus nvswitch_soe_reg_wr_32_ls10(nvswitch_device *device, NvU32 offset, NvU32 data);
#endif //_SOE_LS10_H_

8
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
View File

@@ -272,8 +272,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9,
0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd,
0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f,
0x9fa00499, 0x0005ecdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0,
0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0x9fa00499, 0x0005ecdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0,
0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d,
0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01,
0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x294f2cc2, 0x883a9d68, 0x493e2990, 0xc8e27d59,
0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x8fc5fac6, 0xe1f366be, 0x1ec159bf, 0x352ff984,
0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x1de66f4b, 0x98838b38, 0xce342fcf, 0x31422bca,
0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x154ee848, 0x4d419617, 0xc10ab5e0, 0x5570cfeb,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

8
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
View File

@@ -272,8 +272,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9,
0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd,
0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f,
0x9fa00499, 0x0005ecdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0,
0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0x9fa00499, 0x0005ecdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0,
0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d,
0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01,
0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x294f2cc2, 0x883a9d68, 0x493e2990, 0xc8e27d59,
0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x8fc5fac6, 0xe1f366be, 0x1ec159bf, 0x352ff984,
0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x1de66f4b, 0x98838b38, 0xce342fcf, 0x31422bca,
0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x154ee848, 0x4d419617, 0xc10ab5e0, 0x5570cfeb,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

11
src/common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c
View File

@@ -212,8 +212,15 @@ _inforom_nvlink_start_correctable_error_recording
pNvlinkState->bCallbackPending = NV_FALSE;
nvswitch_task_create(device, &_nvswitch_nvlink_1hz_callback,
NVSWITCH_INTERVAL_1SEC_IN_NS, 0);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_task_create(device, &_nvswitch_nvlink_1hz_callback,
NVSWITCH_INTERVAL_1SEC_IN_NS, 0);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping NVLINK heartbeat task when TNVL is enabled\n");
}
}
NvlStatus

18
src/common/nvswitch/kernel/lr10/lr10.c
View File

@@ -8186,6 +8186,24 @@ nvswitch_tnvl_get_status_lr10
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus
nvswitch_send_tnvl_prelock_cmd_lr10
(
nvswitch_device *device
)
{
return -NVL_ERR_NOT_SUPPORTED;
}
void
nvswitch_tnvl_disable_interrupts_lr10
(
nvswitch_device *device
)
{
return;
}
//
// This function auto creates the lr10 HAL connectivity from the NVSWITCH_INIT_HAL
// macro in haldef_nvswitch.h

7
src/common/nvswitch/kernel/ls10/cci_ls10.c
View File

@@ -386,6 +386,13 @@ nvswitch_is_cci_supported_ls10
nvswitch_device *device
)
{
// Skip CCI on TNVL mode
if (nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT(device, INFO, "CCI is not supported on TNVL mode\n");
return NV_FALSE;
}
if (FLD_TEST_DRF(_SWITCH_REGKEY, _CCI_CONTROL, _ENABLE, _FALSE,
device->regkeys.cci_control))
{

48
src/common/nvswitch/kernel/ls10/intr_ls10.c
View File

@@ -5928,11 +5928,18 @@ nvswitch_create_deferred_link_state_check_task_ls10
pErrorReportParams->nvlipt_instance = nvlipt_instance;
pErrorReportParams->link = link;
status = nvswitch_task_create_args(device, (void*)pErrorReportParams,
&_nvswitch_deferred_link_state_check_ls10,
NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS,
NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE |
NVSWITCH_TASK_TYPE_FLAGS_VOID_PTR_ARGS);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
status = nvswitch_task_create_args(device, (void*)pErrorReportParams,
&_nvswitch_deferred_link_state_check_ls10,
NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS,
NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE |
NVSWITCH_TASK_TYPE_FLAGS_VOID_PTR_ARGS);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping Deferred link state background task when TNVL is enabled\n");
}
}
if (status == NVL_SUCCESS)
@@ -6013,11 +6020,14 @@ _nvswitch_create_deferred_link_errors_task_ls10
pErrorReportParams->nvlipt_instance = nvlipt_instance;
pErrorReportParams->link = link;
status = nvswitch_task_create_args(device, (void*)pErrorReportParams,
&_nvswitch_deferred_link_errors_check_ls10,
NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS,
NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE |
NVSWITCH_TASK_TYPE_FLAGS_VOID_PTR_ARGS);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
status = nvswitch_task_create_args(device, (void*)pErrorReportParams,
&_nvswitch_deferred_link_errors_check_ls10,
NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS,
NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE |
NVSWITCH_TASK_TYPE_FLAGS_VOID_PTR_ARGS);
}
}
if (status == NVL_SUCCESS)
@@ -7416,7 +7426,7 @@ nvswitch_lib_service_interrupts_ls10
// 3. Run leaf specific interrupt handler
//
val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_NON_FATAL);
val = DRF_NUM(_CTRL, _CPU_INTR_NVLW_NON_FATAL, _MASK, val);
val = DRF_VAL(_CTRL, _CPU_INTR_NVLW_NON_FATAL, _MASK, val);
if (val != 0)
{
NVSWITCH_PRINT(device, INFO, "%s: NVLW NON_FATAL interrupts pending = 0x%x\n",
@@ -7438,7 +7448,7 @@ nvswitch_lib_service_interrupts_ls10
}
val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_FATAL);
val = DRF_NUM(_CTRL, _CPU_INTR_NVLW_FATAL, _MASK, val);
val = DRF_VAL(_CTRL, _CPU_INTR_NVLW_FATAL, _MASK, val);
if (val != 0)
{
NVSWITCH_PRINT(device, INFO, "%s: NVLW FATAL interrupts pending = 0x%x\n",
@@ -7462,7 +7472,7 @@ nvswitch_lib_service_interrupts_ls10
}
val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_CORRECTABLE);
val = DRF_NUM(_CTRL, _CPU_INTR_NVLW_CORRECTABLE, _MASK, val);
val = DRF_VAL(_CTRL, _CPU_INTR_NVLW_CORRECTABLE, _MASK, val);
if (val != 0)
{
NVSWITCH_PRINT(device, ERROR, "%s: NVLW CORRECTABLE interrupts pending = 0x%x\n",
@@ -7472,7 +7482,7 @@ nvswitch_lib_service_interrupts_ls10
// Check NPG
val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NPG_FATAL);
val = DRF_NUM(_CTRL, _CPU_INTR_NPG_FATAL, _MASK, val);
val = DRF_VAL(_CTRL, _CPU_INTR_NPG_FATAL, _MASK, val);
if (val != 0)
{
NVSWITCH_PRINT(device, INFO, "%s: NPG FATAL interrupts pending = 0x%x\n",
@@ -7494,7 +7504,7 @@ nvswitch_lib_service_interrupts_ls10
}
val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NPG_NON_FATAL);
val = DRF_NUM(_CTRL, _CPU_INTR_NPG_NON_FATAL, _MASK, val);
val = DRF_VAL(_CTRL, _CPU_INTR_NPG_NON_FATAL, _MASK, val);
if (val != 0)
{
NVSWITCH_PRINT(device, INFO, "%s: NPG NON_FATAL interrupts pending = 0x%x\n",
@@ -7516,7 +7526,7 @@ nvswitch_lib_service_interrupts_ls10
}
val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NPG_CORRECTABLE);
val = DRF_NUM(_CTRL, _CPU_INTR_NPG_CORRECTABLE, _MASK, val);
val = DRF_VAL(_CTRL, _CPU_INTR_NPG_CORRECTABLE, _MASK, val);
if (val != 0)
{
NVSWITCH_PRINT(device, ERROR, "%s: NPG CORRECTABLE interrupts pending = 0x%x\n",
@@ -7526,7 +7536,7 @@ nvswitch_lib_service_interrupts_ls10
// Check NXBAR
val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NXBAR_FATAL);
val = DRF_NUM(_CTRL, _CPU_INTR_NXBAR_FATAL, _MASK, val);
val = DRF_VAL(_CTRL, _CPU_INTR_NXBAR_FATAL, _MASK, val);
if (val != 0)
{
NVSWITCH_PRINT(device, INFO, "%s: NXBAR FATAL interrupts pending = 0x%x\n",
@@ -7605,9 +7615,9 @@ nvswitch_lib_service_interrupts_ls10
NVSWITCH_PRINT(device, ERROR, "%s: Problem servicing SOE",
__FUNCTION__);
return_status = status;
}
}
}
}
}
}
// step 4 -- retrigger engine interrupts

23
src/common/nvswitch/kernel/ls10/ls10.c
View File

@@ -2979,13 +2979,6 @@ nvswitch_is_soe_supported_ls10
NVSWITCH_PRINT(device, WARN, "SOE can not be disabled via regkey.\n");
}
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, INFO,
"SOE is not supported when TNVL mode is locked\n");
return NV_FALSE;
}
return NV_TRUE;
}
@@ -3033,13 +3026,6 @@ nvswitch_is_inforom_supported_ls10
return NV_FALSE;
}
if (nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT(device, INFO,
"INFOROM is not supported when TNVL mode is enabled\n");
return NV_FALSE;
}
if (!nvswitch_is_soe_supported(device))
{
NVSWITCH_PRINT(device, INFO,
@@ -4421,7 +4407,14 @@ nvswitch_eng_wr_ls10
return;
}
nvswitch_reg_write_32(device, base_addr + offset, data);
if (nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_tnvl_reg_wr_32_ls10(device, eng_id, eng_bcast, eng_instance, base_addr, offset, data);
}
else
{
nvswitch_reg_write_32(device, base_addr + offset, data);
}
#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS)
{

158
src/common/nvswitch/kernel/ls10/soe_ls10.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -559,6 +559,76 @@ nvswitch_soe_disable_nport_fatal_interrupts_ls10
}
}
/*
* @Brief : Perform register writes in SOE during TNVL
*
* @param[in] device
* @param[in] offset
* @param[in] data
*/
NvlStatus
nvswitch_soe_reg_wr_32_ls10
(
nvswitch_device *device,
NvU32 offset,
NvU32 data
)
{
FLCN *pFlcn;
NvU32 cmdSeqDesc = 0;
NV_STATUS status;
RM_FLCN_CMD_SOE cmd;
NVSWITCH_TIMEOUT timeout;
RM_SOE_TNVL_CMD_REGISTER_WRITE *pRegisterWrite;
NVSWITCH_GET_BIOS_INFO_PARAMS params = { 0 };
if (!nvswitch_is_soe_supported(device))
{
NVSWITCH_PRINT(device, INFO,
"%s: SOE is not supported\n",
__FUNCTION__);
return NVL_SUCCESS; // -NVL_ERR_NOT_SUPPORTED
}
status = device->hal.nvswitch_ctrl_get_bios_info(device, &params);
if ((status != NVL_SUCCESS) || ((params.version & SOE_VBIOS_VERSION_MASK) <
SOE_VBIOS_REVLOCK_ISSUE_REGISTER_WRITE))
{
nvswitch_reg_write_32(device, offset, data);
return NVL_SUCCESS;
}
pFlcn = device->pSoe->pFlcn;
nvswitch_os_memset(&cmd, 0, sizeof(cmd));
cmd.hdr.unitId = RM_SOE_UNIT_TNVL;
cmd.hdr.size = RM_SOE_CMD_SIZE(TNVL, REGISTER_WRITE);
pRegisterWrite = &cmd.cmd.tnvl.registerWrite;
pRegisterWrite->cmdType = RM_SOE_TNVL_CMD_ISSUE_REGISTER_WRITE;
pRegisterWrite->offset = offset;
pRegisterWrite->data = data;
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&cmd,
NULL, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to send REGISTER_WRITE command to SOE, offset = 0x%x, data = 0x%x\n",
__FUNCTION__, offset, data);
return -NVL_ERR_GENERIC;
}
return NVL_SUCCESS;
}
/*
* @Brief : Init sequence for SOE FSP RISCV image
*
@@ -609,14 +679,21 @@ nvswitch_init_soe_ls10
}
// Register SOE callbacks
status = nvswitch_soe_register_event_callbacks(device);
if (status != NVL_SUCCESS)
if (!nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE,
"Failed to register SOE events\n");
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP,
"SOE init failed(2)\n");
return status;
status = nvswitch_soe_register_event_callbacks(device);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE,
"Failed to register SOE events\n");
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP,
"SOE init failed(2)\n");
return status;
}
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping registering SOE callbacks since TNVL is enabled\n");
}
// Sanity the command and message queues as a final check
@@ -1363,6 +1440,71 @@ _soeI2CAccess_LS10
return ret;
}
/*
* @Brief : Send TNVL Pre Lock command to SOE
*
* @param[in] device
*/
NvlStatus
nvswitch_send_tnvl_prelock_cmd_ls10
(
nvswitch_device *device
)
{
FLCN *pFlcn;
NvU32 cmdSeqDesc = 0;
NV_STATUS status;
RM_FLCN_CMD_SOE cmd;
NVSWITCH_TIMEOUT timeout;
RM_SOE_TNVL_CMD_PRE_LOCK_SEQUENCE *pTnvlPreLock;
NVSWITCH_GET_BIOS_INFO_PARAMS params = { 0 };
if (!nvswitch_is_soe_supported(device))
{
NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported\n",
__FUNCTION__);
return -NVL_ERR_NOT_SUPPORTED;
}
status = device->hal.nvswitch_ctrl_get_bios_info(device, &params);
if ((status != NVL_SUCCESS) || ((params.version & SOE_VBIOS_VERSION_MASK) <
SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND))
{
NVSWITCH_PRINT(device, INFO,
"%s: Skipping TNVL_CMD_PRE_LOCK_SEQUENCE command to SOE. Update firmware "
"from .%02X to .%02X\n",
__FUNCTION__, (NvU32)((params.version & SOE_VBIOS_VERSION_MASK) >> 16),
SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND);
return -NVL_ERR_NOT_SUPPORTED;
}
pFlcn = device->pSoe->pFlcn;
nvswitch_os_memset(&cmd, 0, sizeof(cmd));
cmd.hdr.unitId = RM_SOE_UNIT_TNVL;
cmd.hdr.size = RM_SOE_CMD_SIZE(TNVL, PRE_LOCK_SEQUENCE);
pTnvlPreLock = &cmd.cmd.tnvl.preLockSequence;
pTnvlPreLock->cmdType = RM_SOE_TNVL_CMD_ISSUE_PRE_LOCK_SEQUENCE;
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&cmd,
NULL, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to send PRE_LOCK_SEQUENCE command to SOE, status 0x%x\n",
__FUNCTION__, status);
return -NVL_ERR_GENERIC;
}
return NVL_SUCCESS;
}
/**
* @brief set hal function pointers for functions defined in LR10 (i.e. this file)
*

126
src/common/nvswitch/kernel/ls10/tnvl_ls10.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,9 +26,14 @@
#include "common_nvswitch.h"
#include "haldef_nvswitch.h"
#include "ls10/ls10.h"
#include "ls10/soe_ls10.h"
#include "nvswitch/ls10/dev_nvlsaw_ip.h"
#include "nvswitch/ls10/dev_nvlsaw_ip_addendum.h"
#include "nvswitch/ls10/dev_ctrl_ip.h"
#include "nvswitch/ls10/dev_ctrl_ip_addendum.h"
#include "nvswitch/ls10/dev_cpr_ip.h"
#include "nvswitch/ls10/dev_npg_ip.h"
#include <stddef.h>
@@ -947,6 +952,9 @@ nvswitch_detect_tnvl_mode_ls10
val = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _TNVL_MODE);
if (FLD_TEST_DRF(_NVLSAW, _TNVL_MODE, _STATUS, _ENABLED, val))
{
NVSWITCH_PRINT(device, ERROR,
"%s: TNVL Mode Detected\n",
__FUNCTION__);
device->tnvl_mode = NVSWITCH_DEVICE_TNVL_MODE_ENABLED;
}
@@ -1048,3 +1056,119 @@ nvswitch_tnvl_get_status_ls10
params->status = device->tnvl_mode;
return NVL_SUCCESS;
}
static NvBool
_nvswitch_reg_cpu_write_allow_list_ls10
(
nvswitch_device *device,
NVSWITCH_ENGINE_ID eng_id,
NvU32 offset
)
{
switch (eng_id)
{
case NVSWITCH_ENGINE_ID_SOE:
case NVSWITCH_ENGINE_ID_GIN:
case NVSWITCH_ENGINE_ID_FSP:
return NV_TRUE;
case NVSWITCH_ENGINE_ID_SAW:
{
if (offset == NV_NVLSAW_DRIVER_ATTACH_DETACH)
return NV_TRUE;
break;
}
case NVSWITCH_ENGINE_ID_NPG:
{
if ((offset == NV_NPG_INTR_RETRIGGER(0)) ||
(offset == NV_NPG_INTR_RETRIGGER(1)))
return NV_TRUE;
break;
}
case NVSWITCH_ENGINE_ID_CPR:
{
if ((offset == NV_CPR_SYS_INTR_RETRIGGER(0)) ||
(offset == NV_CPR_SYS_INTR_RETRIGGER(1)))
return NV_TRUE;
break;
}
default :
return NV_FALSE;
}
return NV_FALSE;
}
void
nvswitch_tnvl_reg_wr_32_ls10
(
nvswitch_device *device,
NVSWITCH_ENGINE_ID eng_id,
NvU32 eng_bcast,
NvU32 eng_instance,
NvU32 base_addr,
NvU32 offset,
NvU32 data
)
{
if (!nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s: TNVL mode is not enabled\n",
__FUNCTION__);
NVSWITCH_ASSERT(0);
return;
}
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s: TNVL mode is locked\n",
__FUNCTION__);
NVSWITCH_ASSERT(0);
return;
}
if (_nvswitch_reg_cpu_write_allow_list_ls10(device, eng_id, offset))
{
nvswitch_reg_write_32(device, base_addr + offset, data);
}
else
{
if (nvswitch_soe_reg_wr_32_ls10(device, base_addr + offset, data) != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
"%s: SOE ENG_WR failed for 0x%x[%d] %s @0x%08x+0x%06x = 0x%08x\n",
__FUNCTION__,
eng_id, eng_instance,
(
(eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_UNICAST) ? "UC" :
(eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_BCAST) ? "BC" :
(eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_MULTICAST) ? "MC" :
"??"
),
base_addr, offset, data);
NVSWITCH_ASSERT(0);
}
}
}
void
nvswitch_tnvl_disable_interrupts_ls10
(
nvswitch_device *device
)
{
//
// In TNVL locked disable non-fatal NVLW, NPG, and legacy interrupt,
// disable additional non-fatals on those partitions.
//
NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX),
0xFFFF);
NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
0xFFFF);
NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_UNITS_IDX),
0xFFFFFFFF);
}

78
src/common/nvswitch/kernel/nvswitch.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1021,6 +1021,15 @@ _nvswitch_ctrl_get_tnvl_status
return device->hal.nvswitch_tnvl_get_status(device, params);
}
void
nvswitch_tnvl_disable_interrupts
(
nvswitch_device *device
)
{
device->hal.nvswitch_tnvl_disable_interrupts(device);
}
static NvlStatus
_nvswitch_construct_soe
(
@@ -1860,9 +1869,16 @@ nvswitch_lib_initialize_device
(void)device->hal.nvswitch_read_oob_blacklist_state(device);
(void)device->hal.nvswitch_write_fabric_state(device);
nvswitch_task_create(device, &nvswitch_fabric_state_heartbeat,
NVSWITCH_HEARTBEAT_INTERVAL_NS,
NVSWITCH_TASK_TYPE_FLAGS_RUN_EVEN_IF_DEVICE_NOT_INITIALIZED);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_task_create(device, &nvswitch_fabric_state_heartbeat,
NVSWITCH_HEARTBEAT_INTERVAL_NS,
NVSWITCH_TASK_TYPE_FLAGS_RUN_EVEN_IF_DEVICE_NOT_INITIALIZED);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping Fabric state heartbeat background task when TNVL is enabled\n");
}
//
// Blacklisted devices return successfully in order to preserve the fabric state heartbeat
@@ -1966,12 +1982,26 @@ nvswitch_lib_initialize_device
if (device->regkeys.latency_counter == NV_SWITCH_REGKEY_LATENCY_COUNTER_LOGGING_ENABLE)
{
nvswitch_task_create(device, &nvswitch_internal_latency_bin_log,
nvswitch_get_latency_sample_interval_msec(device) * NVSWITCH_INTERVAL_1MSEC_IN_NS * 9/10, 0);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_task_create(device, &nvswitch_internal_latency_bin_log,
nvswitch_get_latency_sample_interval_msec(device) * NVSWITCH_INTERVAL_1MSEC_IN_NS * 9/10, 0);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping Internal latency background task when TNVL is enabled\n");
}
}
nvswitch_task_create(device, &nvswitch_ecc_writeback_task,
(60 * NVSWITCH_INTERVAL_1SEC_IN_NS), 0);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_task_create(device, &nvswitch_ecc_writeback_task,
(60 * NVSWITCH_INTERVAL_1SEC_IN_NS), 0);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping ECC writeback background task when TNVL is enabled\n");
}
if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device))
{
@@ -1981,8 +2011,15 @@ nvswitch_lib_initialize_device
}
else
{
nvswitch_task_create(device, &nvswitch_monitor_thermal_alert,
100*NVSWITCH_INTERVAL_1MSEC_IN_NS, 0);
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_task_create(device, &nvswitch_monitor_thermal_alert,
100*NVSWITCH_INTERVAL_1MSEC_IN_NS, 0);
}
else
{
NVSWITCH_PRINT(device, INFO, "Skipping Thermal alert background task when TNVL is enabled\n");
}
}
device->nvlink_device->initialized = 1;
@@ -5968,6 +6005,15 @@ nvswitch_tnvl_send_fsp_lock_config
return device->hal.nvswitch_tnvl_send_fsp_lock_config(device);
}
NvlStatus
nvswitch_send_tnvl_prelock_cmd
(
nvswitch_device *device
)
{
return device->hal.nvswitch_send_tnvl_prelock_cmd(device);
}
static NvlStatus
_nvswitch_ctrl_set_device_tnvl_lock
(
@@ -6001,8 +6047,18 @@ _nvswitch_ctrl_set_device_tnvl_lock
//
// Disable non-fatal and legacy interrupts
// Disable commands to SOE
//
nvswitch_tnvl_disable_interrupts(device);
//
//
// Send Pre-Lock sequence command to SOE
//
status = nvswitch_send_tnvl_prelock_cmd(device);
if (status != NVL_SUCCESS)
{
return status;
}
// Send lock-config command to FSP
status = nvswitch_tnvl_send_fsp_lock_config(device);

14
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
View File

@@ -155,24 +155,24 @@ typedef struct NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS {
} NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS;
/*
* NV0000_CTRL_CMD_VGPU_VFIO_UNREGISTER_STATUS
* NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS
*
* This command informs RM the status vgpu-vfio unregister for a GPU.
* This command informs RM the status of vgpu-vfio GPU operations such as probe and unregister.
*
* returnStatus [IN]
* This parameter provides the status vgpu-vfio unregister operation.
* This parameter provides the status of vgpu-vfio GPU operation.
*
* gpuPciId [IN]
* This parameter provides the gpu id of the GPU
*/
#define NV0000_CTRL_CMD_VGPU_VFIO_UNREGISTER_STATUS (0xc05) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_VFIO_UNREGISTER_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS (0xc05) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_VGPU_VFIO_UNREGISTER_STATUS_PARAMS_MESSAGE_ID (0x5U)
#define NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0000_CTRL_VGPU_VFIO_UNREGISTER_STATUS_PARAMS {
typedef struct NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS {
NvU32 returnStatus;
NvU32 gpuId;
} NV0000_CTRL_VGPU_VFIO_UNREGISTER_STATUS_PARAMS;
} NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS;
/* _ctrl0000vgpu_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h
View File

@@ -108,6 +108,8 @@
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE 0
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV 1
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX 2
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV_SNP 3
#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SNP_VTOM 4
#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE 0
#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM 1