NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-01-30 13:09:47 +00:00
Code Issues Packages Projects Releases Wiki Activity

590.48.01

Browse Source
This commit is contained in:
Maneet Singh
2025-12-18 09:16:33 -08:00
parent a5bfb10e75
commit 2ccbad25e1
51 changed files with 2054 additions and 359 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r591_37
#define NV_BUILD_BRANCH r591_47
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r591_37
#define NV_PUBLIC_BRANCH r591_47
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r590/r591_37-155"
#define NV_BUILD_CHANGELIST_NUM (36926008)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r590/r591_47-174"
#define NV_BUILD_CHANGELIST_NUM (37007394)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r590/r591_37-155"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36926008)
#define NV_BUILD_NAME "rel/gpu_drv/r590/r591_47-174"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37007394)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r591_37-1"
#define NV_BUILD_CHANGELIST_NUM (36926008)
#define NV_BUILD_BRANCH_VERSION "r591_47-1"
#define NV_BUILD_CHANGELIST_NUM (37007394)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "591.38"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36926008)
#define NV_BUILD_NAME "591.51"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37007394)
#define NV_BUILD_BRANCH_BASE_VERSION R590
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -5,7 +5,7 @@
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) || \
defined(NV_DCECORE)
#define NV_VERSION_STRING "590.44.01"
#define NV_VERSION_STRING "590.48.01"
#else

23
src/common/inc/swref/published/ampere/ga102/dev_riscv_pri.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,10 +27,31 @@
#define NV_FALCON2_GSP_BASE 0x00111000
#define NV_PRISCV_RISCV_IRQMASK 0x00000528 /* R-I4R */
#define NV_PRISCV_RISCV_IRQDEST 0x0000052c /* RW-4R */
#define NV_PRISCV_RISCV_IRQDELEG 0x00000534 /* RWI4R */
#define NV_PRISCV_RISCV_RPC 0x000003ec /* R--4R */
#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RWI4R */
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */
#define NV_PRISCV_RISCV_ICD_CMD 0x000003d0 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_ADDR0 0x000003d4 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_ADDR1 0x000003d8 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_RDATA0 0x000003e4 /* R--4R */
#define NV_PRISCV_RISCV_ICD_RDATA1 0x000003e8 /* R--4R */
#define NV_PRISCV_RISCV_TRACECTL 0x00000400 /* RW-4R */
#define NV_PRISCV_RISCV_TRACECTL_FULL 30:30 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX 0x00000404 /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_RDIDX_RDIDX 7:0 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX_MAXIDX 23:16 /* R-IVF */
#define NV_PRISCV_RISCV_TRACE_WTIDX 0x00000408 /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_WTIDX_WTIDX 31:24 /* RWIVF */
#define NV_PRISCV_RISCV_TRACEPC_HI 0x00000410 /* RW-4R */
#define NV_PRISCV_RISCV_TRACEPC_LO 0x0000040c /* RW-4R */
#define NV_PRISCV_RISCV_PRIV_ERR_STAT 0x00000500 /* RWI4R */
#define NV_PRISCV_RISCV_PRIV_ERR_INFO 0x00000504 /* R-I4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR 0x00000508 /* R-I4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI 0x0000050c /* R-I4R */
#define NV_PRISCV_RISCV_HUB_ERR_STAT 0x00000510 /* RWI4R */
#define NV_PRISCV_RISCV_BCR_CTRL 0x00000668 /* RWI4R */
#define NV_PRISCV_RISCV_BCR_CTRL_VALID 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_BCR_CTRL_VALID_TRUE 0x00000001 /* R---V */

38
src/common/inc/swref/published/blackwell/gb202/dev_riscv_pri.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_riscv_pri_h__
#define __gb202_dev_riscv_pri_h__
#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RW-4R */
#define NV_PRISCV_RISCV_RPC 0x000003ec /* R--4R */
#define NV_PRISCV_RISCV_IRQDELEG 0x00000534 /* RW-4R */
#define NV_PRISCV_RISCV_IRQDEST 0x0000052c /* RW-4R */
#define NV_PRISCV_RISCV_IRQMASK 0x00000528 /* R--4R */
#define NV_PRISCV_RISCV_PRIV_ERR_STAT 0x00000420 /* RW-4R */
#define NV_PRISCV_RISCV_PRIV_ERR_INFO 0x00000424 /* R--4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR 0x00000428 /* R--4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI 0x0000042c /* R--4R */
#define NV_PRISCV_RISCV_HUB_ERR_STAT 0x00000430 /* RW-4R */
#endif // __gb202_dev_riscv_pri_h__

1
src/common/inc/swref/published/turing/tu102/dev_falcon_v4.h
View File

@@ -33,6 +33,7 @@
#define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-XVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMODE 0x0000000c /* RW-4R */
#define NV_PFALCON_FALCON_IRQMSET 0x00000010 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMCLR 0x00000014 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */

7
src/common/inc/swref/published/turing/tu102/dev_fbif_v4.h
View File

@@ -30,8 +30,15 @@
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_INSTBLK 0x00000020 /* R--4R */
#define NV_PFALCON_FBIF_CTL 0x00000024 /* RW-4R */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_THROTTLE 0x0000002c /* RW-4R */
#define NV_PFALCON_FBIF_ACHK_BLK(i) (0x00000030+(i)*8) /* RW-4A */
#define NV_PFALCON_FBIF_ACHK_BLK__SIZE_1 2 /* */
#define NV_PFALCON_FBIF_ACHK_CTL(i) (0x00000034+(i)*8) /* RW-4A */
#define NV_PFALCON_FBIF_ACHK_CTL__SIZE_1 2 /* */
#define NV_PFALCON_FBIF_CG1 0x00000074 /* RW-4R */
#endif // __tu102_dev_fbif_v4_h__

35
src/common/inc/swref/published/turing/tu102/dev_riscv_pri.h
View File

@@ -28,7 +28,42 @@
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS 0x00000240 /* R-I4R */
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS_ACTIVE_STAT 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_CPUCTL 0x00000268 /* RWI4R */
#define NV_PRISCV_RISCV_IRQMASK 0x000002b4 /* R-I4R */
#define NV_PRISCV_RISCV_IRQDEST 0x000002b8 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_CMD 0x00000300 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_CMD_OPC 4:0 /* RW-VF */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_STOP 0x00000000 /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RCSR 0x00000010 /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RPC 0x00000012 /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_SZ 7:6 /* RW-VF */
#define NV_PRISCV_RISCV_ICD_CMD_IDX 12:8 /* RW-VF */
#define NV_PRISCV_RISCV_ICD_CMD_ERROR 14:14 /* R-IVF */
#define NV_PRISCV_RISCV_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_ICD_CMD_ERROR_FALSE 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_ICD_CMD_BUSY 15:15 /* R-IVF */
#define NV_PRISCV_RISCV_ICD_CMD_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_ICD_CMD_BUSY_TRUE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_ICD_CMD_PARM 31:16 /* RW-VF */
#define NV_PRISCV_RISCV_ICD_RDATA0 0x0000030c /* R--4R */
#define NV_PRISCV_RISCV_ICD_RDATA1 0x00000318 /* R--4R */
#define NV_PRISCV_RISCV_ICD_ADDR0 0x00000304 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_ADDR1 0x00000310 /* RW-4R */
#define NV_PRISCV_RISCV_TRACECTL 0x00000344 /* RW-4R */
#define NV_PRISCV_RISCV_TRACECTL_FULL 30:30 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX 0x00000348 /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_RDIDX_RDIDX 7:0 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX_MAXIDX 23:16 /* R-IVF */
#define NV_PRISCV_RISCV_TRACE_WTIDX 0x0000034c /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_WTIDX_WTIDX 31:24 /* RWIVF */
#define NV_PRISCV_RISCV_TRACEPC_HI 0x00000350 /* RW-4R */
#define NV_PRISCV_RISCV_TRACEPC_LO 0x00000354 /* RW-4R */
#define NV_PRISCV_RISCV_PRIV_ERR_STAT 0x00000360 /* RWI4R */
#define NV_PRISCV_RISCV_PRIV_ERR_INFO 0x00000364 /* R-I4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR 0x00000368 /* R-I4R */
#define NV_PRISCV_RISCV_HUB_ERR_STAT 0x0000036c /* RWI4R */
#endif // __tu102_dev_riscv_pri_h__

37
src/common/modeset/hdmipacket/nvhdmipkt_C671.c
View File

@@ -1136,17 +1136,9 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
NvU32 bppMinX16Itr, bppMaxX16Itr;
NvBool bHasPreCalcFRLData = NV_FALSE;
NvBool forceFRLRateDSC = pClientCtrl->forceFRLRate;
HDMI_FRL_DATA_RATE requestedFRLRate = pClientCtrl->frlRate;
#if defined(NVHDMIPKT_NVKMS)
NvU32 rr = (pVidTransInfo->pTiming->pclk * (NvU64)10000) /
(pVidTransInfo->pTiming->HTotal * (NvU64)pVidTransInfo->pTiming->VTotal);
if (!pVidTransInfo->pTiming->interlaced && (rr >= 480)) {
forceFRLRateDSC = NV_TRUE;
requestedFRLRate = dscMaxFRLRate;
}
NvU32 hVisible, vVisible, rr;
NvBool clampBpp;
#endif
// DSC_All_bpp = 1:
@@ -1256,16 +1248,16 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
frlParams.compressionInfo.hSlices = NV_UNSIGNED_DIV_CEIL(pVidTransInfo->pTiming->HVisible, pClientCtrl->sliceWidth);
}
if (forceFRLRateDSC)
if (pClientCtrl->forceFRLRate)
{
if (requestedFRLRate > dscMaxFRLRate)
if (pClientCtrl->frlRate > dscMaxFRLRate)
{
result = NVHDMIPKT_FAIL;
goto frlQuery_fail;
}
minFRLRateItr = requestedFRLRate;
maxFRLRateItr = requestedFRLRate;
minFRLRateItr = pClientCtrl->frlRate;
maxFRLRateItr = pClientCtrl->frlRate;
}
if (pClientCtrl->forceBppx16)
@@ -1274,6 +1266,23 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
bppMaxX16Itr = pClientCtrl->bitsPerPixelX16;
}
#if defined(NVHDMIPKT_NVKMS)
hVisible = pVidTransInfo->pTiming->HVisible;
vVisible = pVidTransInfo->pTiming->VVisible;
rr = (pVidTransInfo->pTiming->pclk * (NvU64)10000) /
(pVidTransInfo->pTiming->HTotal * (NvU64)pVidTransInfo->pTiming->VTotal);
clampBpp = ((rr >= 480) || ((rr >= 165) && (hVisible == 5120) && (vVisible == 2160))) &&
(!pVidTransInfo->pTiming->interlaced) &&
(bppMinX16Itr <= 8 * 16) &&
(bppMaxX16Itr >= 8 * 16);
if (clampBpp) {
bppMaxX16Itr = 8 * 16;
}
#endif
// Determine Primary Compressed Format
// First determine the FRL rate at which video transport is possible even at bppMin
// Then iterate over bppTarget - start at max n decrement until we hit bppMin. The max bpp for which

4
src/common/modeset/timing/nvt_gtf.c
View File

@@ -103,6 +103,7 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
// A proper way to calculate fixed HTotal*VTotal*Rr/10000
pT->pclk = axb_div_c(dwHTCells*dwVTotal, dwRefreshRate, 10000/NVT_GTF_CELL_GRAN);
pT->pclk1khz = pT->pclk * 10;
pT->HSyncPol = NVT_H_SYNC_NEGATIVE;
pT->VSyncPol = NVT_V_SYNC_POSITIVE;
@@ -111,7 +112,7 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
// fill in the extra timing info
pT->etc.flag = 0;
pT->etc.rr = (NvU16)rr;
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk, (NvU32)10000*(NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal);
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk1khz, (NvU32)1000*(NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal);
pT->etc.aspect = 0;
pT->etc.rep = 0x1;
pT->etc.status = NVT_STATUS_GTF;
@@ -128,6 +129,7 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
pT->interlaced = NVT_INTERLACED_NO_EXTRA_VBLANK_ON_FIELD2;
pT->pclk >>= 1;
pT->pclk1khz >>= 1;
pT->VTotal >>= 1;
pT->VVisible = (pT->VVisible + 1) / 2;
}

4
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -813,6 +813,9 @@ typedef struct NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS {
* productId (in)
* Specifies the product ID of panel obtained from the EDID. This
* parameter is expected to be non-zero only in case of internal panel.
* tconId (out)
* RM provides an enumerated TCON specific value to help the client
* identify the panel TCON. Clients can refer to the enum from sdk/nvidia/inc/dds_tcon_db.h
*
* Possible status values returned are:
* NV_OK
@@ -830,6 +833,7 @@ typedef struct NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS {
NvU32 displayId;
NvU16 manfId;
NvU16 productId;
NvU16 tconId;
} NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS;

2
src/nvidia/arch/nvalloc/unix/src/osapi.c
View File

@@ -1330,7 +1330,7 @@ RmDmabufVerifyMemHandle(
}
// Check if hMemory belongs to the same pGpu
if ((pMemDesc->pGpu != pGpu) &&
if ((pMemDesc->pGpu != pGpu) ||
(pSrcMemory->pGpu != pGpu))
{
return NV_ERR_INVALID_OBJECT_PARENT;

2
src/nvidia/generated/g_gpu_nvoc.c
View File

@@ -2282,7 +2282,7 @@ static void __nvoc_init_funcTable_OBJGPU_2(OBJGPU *pThis) {
pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_3dd2c9;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x60000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000006UL) )) /* ChipHal: GB100 | GB102 | GB110 | GB112 */
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: GB100 | GB102 | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_GB100;
}

214
src/nvidia/generated/g_kernel_falcon_nvoc.c
View File

@@ -695,6 +695,214 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, GpuHalspec
}
}
// kflcnRiscvIcdWaitForIdle -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0ffe0UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnRiscvIcdWaitForIdle__ = &kflcnRiscvIcdWaitForIdle_TU102;
}
// default
else
{
pThis->__kflcnRiscvIcdWaitForIdle__ = &kflcnRiscvIcdWaitForIdle_46f6a7;
}
// kflcnRiscvIcdReadMem -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0ffe0UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnRiscvIcdReadMem__ = &kflcnRiscvIcdReadMem_TU102;
}
// default
else
{
pThis->__kflcnRiscvIcdReadMem__ = &kflcnRiscvIcdReadMem_46f6a7;
}
// kflcnRiscvIcdReadReg -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0ffe0UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnRiscvIcdReadReg__ = &kflcnRiscvIcdReadReg_TU102;
}
// default
else
{
pThis->__kflcnRiscvIcdReadReg__ = &kflcnRiscvIcdReadReg_46f6a7;
}
// kflcnRiscvIcdRcsr -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0ffe0UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnRiscvIcdRcsr__ = &kflcnRiscvIcdRcsr_TU102;
}
// default
else
{
pThis->__kflcnRiscvIcdRcsr__ = &kflcnRiscvIcdRcsr_46f6a7;
}
// kflcnRiscvIcdRstat -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0ffe0UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnRiscvIcdRstat__ = &kflcnRiscvIcdRstat_TU102;
}
// default
else
{
pThis->__kflcnRiscvIcdRstat__ = &kflcnRiscvIcdRstat_46f6a7;
}
// kflcnRiscvIcdRpc -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0ffe0UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnRiscvIcdRpc__ = &kflcnRiscvIcdRpc_TU102;
}
// default
else
{
pThis->__kflcnRiscvIcdRpc__ = &kflcnRiscvIcdRpc_46f6a7;
}
// kflcnRiscvIcdHalt -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0ffe0UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnRiscvIcdHalt__ = &kflcnRiscvIcdHalt_TU102;
}
// default
else
{
pThis->__kflcnRiscvIcdHalt__ = &kflcnRiscvIcdHalt_46f6a7;
}
// kflcnIcdReadCmdReg -- halified (3 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */
{
pThis->__kflcnIcdReadCmdReg__ = &kflcnIcdReadCmdReg_TU102;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0f800UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnIcdReadCmdReg__ = &kflcnIcdReadCmdReg_GA102;
}
// default
else
{
pThis->__kflcnIcdReadCmdReg__ = &kflcnIcdReadCmdReg_4a4dee;
}
// kflcnRiscvIcdReadRdata -- halified (3 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */
{
pThis->__kflcnRiscvIcdReadRdata__ = &kflcnRiscvIcdReadRdata_TU102;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0f800UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnRiscvIcdReadRdata__ = &kflcnRiscvIcdReadRdata_GA102;
}
// default
else
{
pThis->__kflcnRiscvIcdReadRdata__ = &kflcnRiscvIcdReadRdata_4a4dee;
}
// kflcnRiscvIcdWriteAddress -- halified (3 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */
{
pThis->__kflcnRiscvIcdWriteAddress__ = &kflcnRiscvIcdWriteAddress_TU102;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0f800UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnRiscvIcdWriteAddress__ = &kflcnRiscvIcdWriteAddress_GA102;
}
// default
else
{
pThis->__kflcnRiscvIcdWriteAddress__ = &kflcnRiscvIcdWriteAddress_b3696a;
}
// kflcnIcdWriteCmdReg -- halified (3 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */
{
pThis->__kflcnIcdWriteCmdReg__ = &kflcnIcdWriteCmdReg_TU102;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0f800UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnIcdWriteCmdReg__ = &kflcnIcdWriteCmdReg_GA102;
}
// default
else
{
pThis->__kflcnIcdWriteCmdReg__ = &kflcnIcdWriteCmdReg_b3696a;
}
// kflcnCoreDumpPc -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0f800UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnCoreDumpPc__ = &kflcnCoreDumpPc_GA102;
}
// default
else
{
pThis->__kflcnCoreDumpPc__ = &kflcnCoreDumpPc_46f6a7;
}
// kflcnDumpCoreRegs -- halified (4 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */
{
pThis->__kflcnDumpCoreRegs__ = &kflcnDumpCoreRegs_TU102;
}
else if (( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe0UL) )) /* ChipHal: GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnDumpCoreRegs__ = &kflcnDumpCoreRegs_GB202;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0f800UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000006UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 */
{
pThis->__kflcnDumpCoreRegs__ = &kflcnDumpCoreRegs_GA102;
}
// default
else
{
pThis->__kflcnDumpCoreRegs__ = &kflcnDumpCoreRegs_b3696a;
}
// kflcnDumpTracepc -- halified (3 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */
{
pThis->__kflcnDumpTracepc__ = &kflcnDumpTracepc_TU102;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0f800UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnDumpTracepc__ = &kflcnDumpTracepc_GA102;
}
// default
else
{
pThis->__kflcnDumpTracepc__ = &kflcnDumpTracepc_b3696a;
}
// kflcnDumpPeripheralRegs -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xf1f0ffe0UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe6UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB110 | GB112 | GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
{
pThis->__kflcnDumpPeripheralRegs__ = &kflcnDumpPeripheralRegs_TU102;
}
// default
else
{
pThis->__kflcnDumpPeripheralRegs__ = &kflcnDumpPeripheralRegs_b3696a;
}
// kflcnGetEccInterruptMask -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x60000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000006UL) )) /* ChipHal: GB100 | GB102 | GB110 | GB112 */
@@ -739,13 +947,13 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, GpuHalspec
// kflcnGetWFL0Offset -- virtual halified (2 hals) inherited (kcrashcatEngine) base (kcrashcatEngine)
pThis->__kflcnGetWFL0Offset__ = &__nvoc_up_thunk_KernelCrashCatEngine_kflcnGetWFL0Offset;
} // End __nvoc_init_funcTable_KernelFalcon_1 with approximately 88 basic block(s).
} // End __nvoc_init_funcTable_KernelFalcon_1 with approximately 125 basic block(s).
// Initialize vtable(s) for 38 virtual method(s).
// Initialize vtable(s) for 53 virtual method(s).
void __nvoc_init_funcTable_KernelFalcon(KernelFalcon *pThis, GpuHalspecOwner *pGpuhalspecowner, RmHalspecOwner *pRmhalspecowner) {
// Initialize vtable(s) with 28 per-object function pointer(s).
// Initialize vtable(s) with 43 per-object function pointer(s).
__nvoc_init_funcTable_KernelFalcon_1(pThis, pGpuhalspecowner, pRmhalspecowner);
}

247
src/nvidia/generated/g_kernel_falcon_nvoc.h
View File

@@ -51,6 +51,7 @@ extern "C" {
#include "core/core.h"
#include "gpu/falcon/falcon_common.h"
#include "gpu/falcon/kernel_falcon_core_dump.h"
#include "gpu/falcon/kernel_crashcat_engine.h"
#include "gpu/intr/intr_service.h"
@@ -119,7 +120,7 @@ struct KernelFalcon {
struct KernelCrashCatEngine *__nvoc_pbase_KernelCrashCatEngine; // kcrashcatEngine super
struct KernelFalcon *__nvoc_pbase_KernelFalcon; // kflcn
// Vtable with 28 per-object function pointers
// Vtable with 43 per-object function pointers
NvU32 (*__kflcnRegRead__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU32); // virtual halified (3 hals) override (kcrashcatEngine) base (kcrashcatEngine) body
void (*__kflcnRegWrite__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU32, NvU32); // virtual halified (3 hals) override (kcrashcatEngine) base (kcrashcatEngine) body
NvU32 (*__kflcnRiscvRegRead__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU32); // halified (3 hals) body
@@ -142,6 +143,21 @@ struct KernelFalcon {
void (*__kflcnIntrRetrigger__)(struct OBJGPU *, struct KernelFalcon * /*this*/); // halified (3 hals) body
NvU32 (*__kflcnMaskImemAddr__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU32); // halified (4 hals) body
NvU32 (*__kflcnMaskDmemAddr__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU32); // virtual halified (4 hals) override (kcrashcatEngine) base (kcrashcatEngine) body
NV_STATUS (*__kflcnRiscvIcdWaitForIdle__)(struct OBJGPU *, struct KernelFalcon * /*this*/); // halified (2 hals) body
NV_STATUS (*__kflcnRiscvIcdReadMem__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU64, NvU64, NvU64 *); // halified (2 hals) body
NV_STATUS (*__kflcnRiscvIcdReadReg__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU32, NvU64 *); // halified (2 hals) body
NV_STATUS (*__kflcnRiscvIcdRcsr__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU32, NvU64 *); // halified (2 hals) body
NV_STATUS (*__kflcnRiscvIcdRstat__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU32, NvU64 *); // halified (2 hals) body
NV_STATUS (*__kflcnRiscvIcdRpc__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU64 *); // halified (2 hals) body
NV_STATUS (*__kflcnRiscvIcdHalt__)(struct OBJGPU *, struct KernelFalcon * /*this*/); // halified (2 hals) body
NvU32 (*__kflcnIcdReadCmdReg__)(struct OBJGPU *, struct KernelFalcon * /*this*/); // halified (3 hals) body
NvU64 (*__kflcnRiscvIcdReadRdata__)(struct OBJGPU *, struct KernelFalcon * /*this*/); // halified (3 hals) body
void (*__kflcnRiscvIcdWriteAddress__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU64); // halified (3 hals) body
void (*__kflcnIcdWriteCmdReg__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU32); // halified (3 hals) body
NV_STATUS (*__kflcnCoreDumpPc__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU64 *); // halified (2 hals) body
void (*__kflcnDumpCoreRegs__)(struct OBJGPU *, struct KernelFalcon * /*this*/, CoreDumpRegs *); // halified (4 hals) body
void (*__kflcnDumpTracepc__)(struct OBJGPU *, struct KernelFalcon * /*this*/, CoreDumpRegs *); // halified (3 hals) body
void (*__kflcnDumpPeripheralRegs__)(struct OBJGPU *, struct KernelFalcon * /*this*/, CoreDumpRegs *); // halified (2 hals) body
NvU32 (*__kflcnGetEccInterruptMask__)(struct OBJGPU *, struct KernelFalcon * /*this*/); // halified (2 hals) body
NV_STATUS (*__kflcnGetFatalHwErrorStatus__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU32 *); // halified (2 hals) body
const char * (*__kflcnFatalHwErrorCodeToString__)(struct OBJGPU *, struct KernelFalcon * /*this*/, NvU32, NvBool); // halified (2 hals)
@@ -224,6 +240,26 @@ static inline void kflcnConfigureEngine(struct OBJGPU *pGpu, struct KernelFalcon
#define kflcnConfigureEngine(pGpu, pKernelFalcon, pFalconConfig) kflcnConfigureEngine_IMPL(pGpu, pKernelFalcon, pFalconConfig)
#endif // __nvoc_kernel_falcon_h_disabled
NV_STATUS kflcnCoreDumpNondestructive_IMPL(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 verbosity);
#ifdef __nvoc_kernel_falcon_h_disabled
static inline NV_STATUS kflcnCoreDumpNondestructive(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 verbosity) {
NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_kernel_falcon_h_disabled
#define kflcnCoreDumpNondestructive(pGpu, pKernelFlcn, verbosity) kflcnCoreDumpNondestructive_IMPL(pGpu, pKernelFlcn, verbosity)
#endif // __nvoc_kernel_falcon_h_disabled
NV_STATUS kflcnCoreDumpDestructive_IMPL(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn);
#ifdef __nvoc_kernel_falcon_h_disabled
static inline NV_STATUS kflcnCoreDumpDestructive(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) {
NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else // __nvoc_kernel_falcon_h_disabled
#define kflcnCoreDumpDestructive(pGpu, pKernelFlcn) kflcnCoreDumpDestructive_IMPL(pGpu, pKernelFlcn)
#endif // __nvoc_kernel_falcon_h_disabled
NvU32 kflcnGetPendingHostInterrupts_IMPL(struct OBJGPU *arg1, struct KernelFalcon *arg_this);
#ifdef __nvoc_kernel_falcon_h_disabled
static inline NvU32 kflcnGetPendingHostInterrupts(struct OBJGPU *arg1, struct KernelFalcon *arg_this) {
@@ -327,6 +363,51 @@ struct KernelFalcon * kflcnGetKernelFalconForEngine_IMPL(struct OBJGPU *pGpu, EN
#define kflcnMaskDmemAddr_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnMaskDmemAddr__
#define kflcnMaskDmemAddr(pGpu, pKernelFlcn, addr) kflcnMaskDmemAddr_DISPATCH(pGpu, pKernelFlcn, addr)
#define kflcnMaskDmemAddr_HAL(pGpu, pKernelFlcn, addr) kflcnMaskDmemAddr_DISPATCH(pGpu, pKernelFlcn, addr)
#define kflcnRiscvIcdWaitForIdle_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnRiscvIcdWaitForIdle__
#define kflcnRiscvIcdWaitForIdle(pGpu, pKernelFlcn) kflcnRiscvIcdWaitForIdle_DISPATCH(pGpu, pKernelFlcn)
#define kflcnRiscvIcdWaitForIdle_HAL(pGpu, pKernelFlcn) kflcnRiscvIcdWaitForIdle_DISPATCH(pGpu, pKernelFlcn)
#define kflcnRiscvIcdReadMem_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnRiscvIcdReadMem__
#define kflcnRiscvIcdReadMem(pGpu, pKernelFlcn, address, size, pValue) kflcnRiscvIcdReadMem_DISPATCH(pGpu, pKernelFlcn, address, size, pValue)
#define kflcnRiscvIcdReadMem_HAL(pGpu, pKernelFlcn, address, size, pValue) kflcnRiscvIcdReadMem_DISPATCH(pGpu, pKernelFlcn, address, size, pValue)
#define kflcnRiscvIcdReadReg_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnRiscvIcdReadReg__
#define kflcnRiscvIcdReadReg(pGpu, pKernelFlcn, reg, pValue) kflcnRiscvIcdReadReg_DISPATCH(pGpu, pKernelFlcn, reg, pValue)
#define kflcnRiscvIcdReadReg_HAL(pGpu, pKernelFlcn, reg, pValue) kflcnRiscvIcdReadReg_DISPATCH(pGpu, pKernelFlcn, reg, pValue)
#define kflcnRiscvIcdRcsr_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnRiscvIcdRcsr__
#define kflcnRiscvIcdRcsr(pGpu, pKernelFlcn, csr, pValue) kflcnRiscvIcdRcsr_DISPATCH(pGpu, pKernelFlcn, csr, pValue)
#define kflcnRiscvIcdRcsr_HAL(pGpu, pKernelFlcn, csr, pValue) kflcnRiscvIcdRcsr_DISPATCH(pGpu, pKernelFlcn, csr, pValue)
#define kflcnRiscvIcdRstat_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnRiscvIcdRstat__
#define kflcnRiscvIcdRstat(pGpu, pKernelFlcn, index, pValue) kflcnRiscvIcdRstat_DISPATCH(pGpu, pKernelFlcn, index, pValue)
#define kflcnRiscvIcdRstat_HAL(pGpu, pKernelFlcn, index, pValue) kflcnRiscvIcdRstat_DISPATCH(pGpu, pKernelFlcn, index, pValue)
#define kflcnRiscvIcdRpc_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnRiscvIcdRpc__
#define kflcnRiscvIcdRpc(pGpu, pKernelFlcn, pValue) kflcnRiscvIcdRpc_DISPATCH(pGpu, pKernelFlcn, pValue)
#define kflcnRiscvIcdRpc_HAL(pGpu, pKernelFlcn, pValue) kflcnRiscvIcdRpc_DISPATCH(pGpu, pKernelFlcn, pValue)
#define kflcnRiscvIcdHalt_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnRiscvIcdHalt__
#define kflcnRiscvIcdHalt(pGpu, pKernelFlcn) kflcnRiscvIcdHalt_DISPATCH(pGpu, pKernelFlcn)
#define kflcnRiscvIcdHalt_HAL(pGpu, pKernelFlcn) kflcnRiscvIcdHalt_DISPATCH(pGpu, pKernelFlcn)
#define kflcnIcdReadCmdReg_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnIcdReadCmdReg__
#define kflcnIcdReadCmdReg(pGpu, pKernelFlcn) kflcnIcdReadCmdReg_DISPATCH(pGpu, pKernelFlcn)
#define kflcnIcdReadCmdReg_HAL(pGpu, pKernelFlcn) kflcnIcdReadCmdReg_DISPATCH(pGpu, pKernelFlcn)
#define kflcnRiscvIcdReadRdata_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnRiscvIcdReadRdata__
#define kflcnRiscvIcdReadRdata(pGpu, pKernelFlcn) kflcnRiscvIcdReadRdata_DISPATCH(pGpu, pKernelFlcn)
#define kflcnRiscvIcdReadRdata_HAL(pGpu, pKernelFlcn) kflcnRiscvIcdReadRdata_DISPATCH(pGpu, pKernelFlcn)
#define kflcnRiscvIcdWriteAddress_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnRiscvIcdWriteAddress__
#define kflcnRiscvIcdWriteAddress(pGpu, pKernelFlcn, address) kflcnRiscvIcdWriteAddress_DISPATCH(pGpu, pKernelFlcn, address)
#define kflcnRiscvIcdWriteAddress_HAL(pGpu, pKernelFlcn, address) kflcnRiscvIcdWriteAddress_DISPATCH(pGpu, pKernelFlcn, address)
#define kflcnIcdWriteCmdReg_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnIcdWriteCmdReg__
#define kflcnIcdWriteCmdReg(pGpu, pKernelFlcn, value) kflcnIcdWriteCmdReg_DISPATCH(pGpu, pKernelFlcn, value)
#define kflcnIcdWriteCmdReg_HAL(pGpu, pKernelFlcn, value) kflcnIcdWriteCmdReg_DISPATCH(pGpu, pKernelFlcn, value)
#define kflcnCoreDumpPc_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnCoreDumpPc__
#define kflcnCoreDumpPc(pGpu, pKernelFlcn, pc) kflcnCoreDumpPc_DISPATCH(pGpu, pKernelFlcn, pc)
#define kflcnCoreDumpPc_HAL(pGpu, pKernelFlcn, pc) kflcnCoreDumpPc_DISPATCH(pGpu, pKernelFlcn, pc)
#define kflcnDumpCoreRegs_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnDumpCoreRegs__
#define kflcnDumpCoreRegs(pGpu, pKernelFlcn, pCore) kflcnDumpCoreRegs_DISPATCH(pGpu, pKernelFlcn, pCore)
#define kflcnDumpCoreRegs_HAL(pGpu, pKernelFlcn, pCore) kflcnDumpCoreRegs_DISPATCH(pGpu, pKernelFlcn, pCore)
#define kflcnDumpTracepc_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnDumpTracepc__
#define kflcnDumpTracepc(pGpu, pKernelFlcn, pCode) kflcnDumpTracepc_DISPATCH(pGpu, pKernelFlcn, pCode)
#define kflcnDumpTracepc_HAL(pGpu, pKernelFlcn, pCode) kflcnDumpTracepc_DISPATCH(pGpu, pKernelFlcn, pCode)
#define kflcnDumpPeripheralRegs_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnDumpPeripheralRegs__
#define kflcnDumpPeripheralRegs(pGpu, pKernelFlcn, pCore) kflcnDumpPeripheralRegs_DISPATCH(pGpu, pKernelFlcn, pCore)
#define kflcnDumpPeripheralRegs_HAL(pGpu, pKernelFlcn, pCore) kflcnDumpPeripheralRegs_DISPATCH(pGpu, pKernelFlcn, pCore)
#define kflcnGetEccInterruptMask_FNPTR(pKernelFlcn) pKernelFlcn->__kflcnGetEccInterruptMask__
#define kflcnGetEccInterruptMask(pGpu, pKernelFlcn) kflcnGetEccInterruptMask_DISPATCH(pGpu, pKernelFlcn)
#define kflcnGetEccInterruptMask_HAL(pGpu, pKernelFlcn) kflcnGetEccInterruptMask_DISPATCH(pGpu, pKernelFlcn)
@@ -458,6 +539,66 @@ static inline NvU32 kflcnMaskDmemAddr_DISPATCH(struct OBJGPU *pGpu, struct Kerne
return pKernelFlcn->__kflcnMaskDmemAddr__(pGpu, pKernelFlcn, addr);
}
static inline NV_STATUS kflcnRiscvIcdWaitForIdle_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) {
return pKernelFlcn->__kflcnRiscvIcdWaitForIdle__(pGpu, pKernelFlcn);
}
static inline NV_STATUS kflcnRiscvIcdReadMem_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 address, NvU64 size, NvU64 *pValue) {
return pKernelFlcn->__kflcnRiscvIcdReadMem__(pGpu, pKernelFlcn, address, size, pValue);
}
static inline NV_STATUS kflcnRiscvIcdReadReg_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 reg, NvU64 *pValue) {
return pKernelFlcn->__kflcnRiscvIcdReadReg__(pGpu, pKernelFlcn, reg, pValue);
}
static inline NV_STATUS kflcnRiscvIcdRcsr_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 csr, NvU64 *pValue) {
return pKernelFlcn->__kflcnRiscvIcdRcsr__(pGpu, pKernelFlcn, csr, pValue);
}
static inline NV_STATUS kflcnRiscvIcdRstat_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 index, NvU64 *pValue) {
return pKernelFlcn->__kflcnRiscvIcdRstat__(pGpu, pKernelFlcn, index, pValue);
}
static inline NV_STATUS kflcnRiscvIcdRpc_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 *pValue) {
return pKernelFlcn->__kflcnRiscvIcdRpc__(pGpu, pKernelFlcn, pValue);
}
static inline NV_STATUS kflcnRiscvIcdHalt_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) {
return pKernelFlcn->__kflcnRiscvIcdHalt__(pGpu, pKernelFlcn);
}
static inline NvU32 kflcnIcdReadCmdReg_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) {
return pKernelFlcn->__kflcnIcdReadCmdReg__(pGpu, pKernelFlcn);
}
static inline NvU64 kflcnRiscvIcdReadRdata_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) {
return pKernelFlcn->__kflcnRiscvIcdReadRdata__(pGpu, pKernelFlcn);
}
static inline void kflcnRiscvIcdWriteAddress_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 address) {
pKernelFlcn->__kflcnRiscvIcdWriteAddress__(pGpu, pKernelFlcn, address);
}
static inline void kflcnIcdWriteCmdReg_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 value) {
pKernelFlcn->__kflcnIcdWriteCmdReg__(pGpu, pKernelFlcn, value);
}
static inline NV_STATUS kflcnCoreDumpPc_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 *pc) {
return pKernelFlcn->__kflcnCoreDumpPc__(pGpu, pKernelFlcn, pc);
}
static inline void kflcnDumpCoreRegs_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, CoreDumpRegs *pCore) {
pKernelFlcn->__kflcnDumpCoreRegs__(pGpu, pKernelFlcn, pCore);
}
static inline void kflcnDumpTracepc_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, CoreDumpRegs *pCode) {
pKernelFlcn->__kflcnDumpTracepc__(pGpu, pKernelFlcn, pCode);
}
static inline void kflcnDumpPeripheralRegs_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, CoreDumpRegs *pCore) {
pKernelFlcn->__kflcnDumpPeripheralRegs__(pGpu, pKernelFlcn, pCore);
}
static inline NvU32 kflcnGetEccInterruptMask_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) {
return pKernelFlcn->__kflcnGetEccInterruptMask__(pGpu, pKernelFlcn);
}
@@ -686,6 +827,110 @@ static inline NvU32 kflcnMaskDmemAddr_474d46(struct OBJGPU *pGpu, struct KernelF
NV_ASSERT_OR_RETURN_PRECOMP(0, 0);
}
NV_STATUS kflcnRiscvIcdWaitForIdle_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn);
static inline NV_STATUS kflcnRiscvIcdWaitForIdle_46f6a7(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS kflcnRiscvIcdReadMem_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 address, NvU64 size, NvU64 *pValue);
static inline NV_STATUS kflcnRiscvIcdReadMem_46f6a7(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 address, NvU64 size, NvU64 *pValue) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS kflcnRiscvIcdReadReg_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 reg, NvU64 *pValue);
static inline NV_STATUS kflcnRiscvIcdReadReg_46f6a7(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 reg, NvU64 *pValue) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS kflcnRiscvIcdRcsr_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 csr, NvU64 *pValue);
static inline NV_STATUS kflcnRiscvIcdRcsr_46f6a7(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 csr, NvU64 *pValue) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS kflcnRiscvIcdRstat_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 index, NvU64 *pValue);
static inline NV_STATUS kflcnRiscvIcdRstat_46f6a7(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 index, NvU64 *pValue) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS kflcnRiscvIcdRpc_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 *pValue);
static inline NV_STATUS kflcnRiscvIcdRpc_46f6a7(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 *pValue) {
return NV_ERR_NOT_SUPPORTED;
}
NV_STATUS kflcnRiscvIcdHalt_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn);
static inline NV_STATUS kflcnRiscvIcdHalt_46f6a7(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) {
return NV_ERR_NOT_SUPPORTED;
}
NvU32 kflcnIcdReadCmdReg_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn);
NvU32 kflcnIcdReadCmdReg_GA102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn);
static inline NvU32 kflcnIcdReadCmdReg_4a4dee(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) {
return 0;
}
NvU64 kflcnRiscvIcdReadRdata_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn);
NvU64 kflcnRiscvIcdReadRdata_GA102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn);
static inline NvU64 kflcnRiscvIcdReadRdata_4a4dee(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) {
return 0;
}
void kflcnRiscvIcdWriteAddress_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 address);
void kflcnRiscvIcdWriteAddress_GA102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 address);
static inline void kflcnRiscvIcdWriteAddress_b3696a(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 address) {
return;
}
void kflcnIcdWriteCmdReg_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 value);
void kflcnIcdWriteCmdReg_GA102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 value);
static inline void kflcnIcdWriteCmdReg_b3696a(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 value) {
return;
}
NV_STATUS kflcnCoreDumpPc_GA102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 *pc);
static inline NV_STATUS kflcnCoreDumpPc_46f6a7(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU64 *pc) {
return NV_ERR_NOT_SUPPORTED;
}
void kflcnDumpCoreRegs_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, CoreDumpRegs *pCore);
void kflcnDumpCoreRegs_GA102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, CoreDumpRegs *pCore);
void kflcnDumpCoreRegs_GB202(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, CoreDumpRegs *pCore);
static inline void kflcnDumpCoreRegs_b3696a(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, CoreDumpRegs *pCore) {
return;
}
void kflcnDumpTracepc_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, CoreDumpRegs *pCode);
void kflcnDumpTracepc_GA102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, CoreDumpRegs *pCode);
static inline void kflcnDumpTracepc_b3696a(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, CoreDumpRegs *pCode) {
return;
}
void kflcnDumpPeripheralRegs_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, CoreDumpRegs *pCore);
static inline void kflcnDumpPeripheralRegs_b3696a(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, CoreDumpRegs *pCore) {
return;
}
NvU32 kflcnGetEccInterruptMask_GB100(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn);
static inline NvU32 kflcnGetEccInterruptMask_4a4dee(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) {

2
src/nvidia/generated/g_kernel_graphics_nvoc.c
View File

@@ -278,7 +278,7 @@ void __nvoc_init_dataField_KernelGraphics(KernelGraphics *pThis, GpuHalspecOwner
pThis->bOverrideContextBuffersToGpuCached = NV_FALSE;
// Hal field -- bPeFiroBufferEnabled
if (( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000fe0UL) )) /* ChipHal: GB202 | GB203 | GB205 | GB206 | GB207 | GB20B | GB20C */
if (( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: GB202 | GB203 | GB205 | GB206 | GB207 */
{
pThis->bPeFiroBufferEnabled = NV_TRUE;
}

23
src/nvidia/generated/g_kernel_gsp_nvoc.c
View File

@@ -1117,6 +1117,23 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, GpuHalspecOwner
}
}
// kgspDumpMailbox -- halified (3 hals) body
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
{
pThis->__kgspDumpMailbox__ = &kgspDumpMailbox_f2d351;
}
else
{
if (( ((chipHal_HalVarIdx >> 5) == 3UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000a000UL) )) /* ChipHal: T234D | T264D */
{
pThis->__kgspDumpMailbox__ = &kgspDumpMailbox_f2d351;
}
else
{
pThis->__kgspDumpMailbox__ = &kgspDumpMailbox_TU102;
}
}
// kgspService -- halified (3 hals) body
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
{
@@ -1893,13 +1910,13 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, GpuHalspecOwner
// kgspGetWFL0Offset -- virtual halified (2 hals) inherited (kcrashcatEngine) base (kflcn)
pThis->__kgspGetWFL0Offset__ = &__nvoc_up_thunk_KernelCrashCatEngine_kgspGetWFL0Offset;
} // End __nvoc_init_funcTable_KernelGsp_1 with approximately 259 basic block(s).
} // End __nvoc_init_funcTable_KernelGsp_1 with approximately 262 basic block(s).
// Initialize vtable(s) for 92 virtual method(s).
// Initialize vtable(s) for 93 virtual method(s).
void __nvoc_init_funcTable_KernelGsp(KernelGsp *pThis, GpuHalspecOwner *pGpuhalspecowner, RmHalspecOwner *pRmhalspecowner) {
// Initialize vtable(s) with 66 per-object function pointer(s).
// Initialize vtable(s) with 67 per-object function pointer(s).
__nvoc_init_funcTable_KernelGsp_1(pThis, pGpuhalspecowner, pRmhalspecowner);
}

16
src/nvidia/generated/g_kernel_gsp_nvoc.h
View File

@@ -420,7 +420,7 @@ struct KernelGsp {
struct KernelFalcon *__nvoc_pbase_KernelFalcon; // kflcn super
struct KernelGsp *__nvoc_pbase_KernelGsp; // kgsp
// Vtable with 66 per-object function pointers
// Vtable with 67 per-object function pointers
void (*__kgspConfigureFalcon__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (4 hals) body
NvBool (*__kgspIsDebugModeEnabled__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (5 hals) body
NV_STATUS (*__kgspAllocBootArgs__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (4 hals) body
@@ -443,6 +443,7 @@ struct KernelGsp {
NvU32 (*__kgspReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelGsp * /*this*/, NvU32); // halified (5 hals) body
NV_STATUS (*__kgspResetHw__)(struct OBJGPU *, struct KernelGsp * /*this*/); // virtual halified (5 hals) override (kflcn) base (kflcn) body
NvBool (*__kgspHealthCheck__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (3 hals) body
void (*__kgspDumpMailbox__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (3 hals) body
NvU32 (*__kgspService__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (3 hals) body
void (*__kgspServiceFatalHwError__)(struct OBJGPU *, struct KernelGsp * /*this*/, NvU32); // halified (3 hals) body
void (*__kgspEccServiceEvent__)(struct OBJGPU *, struct KernelGsp * /*this*/); // halified (3 hals) body
@@ -930,6 +931,9 @@ static inline void kgspPrintGspBinBuildId(struct OBJGPU *pGpu, struct KernelGsp
#define kgspHealthCheck_FNPTR(pKernelGsp) pKernelGsp->__kgspHealthCheck__
#define kgspHealthCheck(pGpu, pKernelGsp) kgspHealthCheck_DISPATCH(pGpu, pKernelGsp)
#define kgspHealthCheck_HAL(pGpu, pKernelGsp) kgspHealthCheck_DISPATCH(pGpu, pKernelGsp)
#define kgspDumpMailbox_FNPTR(pKernelGsp) pKernelGsp->__kgspDumpMailbox__
#define kgspDumpMailbox(pGpu, pKernelGsp) kgspDumpMailbox_DISPATCH(pGpu, pKernelGsp)
#define kgspDumpMailbox_HAL(pGpu, pKernelGsp) kgspDumpMailbox_DISPATCH(pGpu, pKernelGsp)
#define kgspService_FNPTR(pKernelGsp) pKernelGsp->__kgspService__
#define kgspService(pGpu, pKernelGsp) kgspService_DISPATCH(pGpu, pKernelGsp)
#define kgspService_HAL(pGpu, pKernelGsp) kgspService_DISPATCH(pGpu, pKernelGsp)
@@ -1214,6 +1218,10 @@ static inline NvBool kgspHealthCheck_DISPATCH(struct OBJGPU *pGpu, struct Kernel
return pKernelGsp->__kgspHealthCheck__(pGpu, pKernelGsp);
}
static inline void kgspDumpMailbox_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
pKernelGsp->__kgspDumpMailbox__(pGpu, pKernelGsp);
}
static inline NvU32 kgspService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
return pKernelGsp->__kgspService__(pGpu, pKernelGsp);
}
@@ -1710,6 +1718,12 @@ static inline NvBool kgspHealthCheck_86b752(struct OBJGPU *pGpu, struct KernelGs
NV_ASSERT_OR_RETURN_PRECOMP(0, NV_FALSE);
}
void kgspDumpMailbox_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp);
static inline void kgspDumpMailbox_f2d351(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
NV_ASSERT_PRECOMP(0);
}
NvU32 kgspService_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp);
static inline NvU32 kgspService_474d46(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {

6
src/nvidia/generated/g_nv_name_released.h
View File

@@ -149,7 +149,6 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1E93, 0x1089, 0x1d05, "NVIDIA GeForce RTX 2080 Super with Max-Q Design" },
{ 0x1EB0, 0x0000, 0x0000, "Quadro RTX 5000" },
{ 0x1EB1, 0x0000, 0x0000, "Quadro RTX 4000" },
{ 0x1EB1, 0x12a0, 0x15c3, "EIZO Quadro MED-XN92" },
{ 0x1EB5, 0x0000, 0x0000, "Quadro RTX 5000" },
{ 0x1EB5, 0x1375, 0x1025, "Quadro RTX 5000 with Max-Q Design" },
{ 0x1EB5, 0x1401, 0x1025, "Quadro RTX 5000 with Max-Q Design" },
@@ -796,9 +795,13 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2BB1, 0x204b, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
{ 0x2BB1, 0x204b, 0x17aa, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
{ 0x2BB3, 0x204d, 0x1028, "NVIDIA RTX PRO 5000 Blackwell" },
{ 0x2BB3, 0x227a, 0x1028, "NVIDIA RTX PRO 5000 72GB Blackwell" },
{ 0x2BB3, 0x204d, 0x103c, "NVIDIA RTX PRO 5000 Blackwell" },
{ 0x2BB3, 0x227a, 0x103c, "NVIDIA RTX PRO 5000 72GB Blackwell" },
{ 0x2BB3, 0x204d, 0x10de, "NVIDIA RTX PRO 5000 Blackwell" },
{ 0x2BB3, 0x227a, 0x10de, "NVIDIA RTX PRO 5000 72GB Blackwell" },
{ 0x2BB3, 0x204d, 0x17aa, "NVIDIA RTX PRO 5000 Blackwell" },
{ 0x2BB3, 0x227a, 0x17aa, "NVIDIA RTX PRO 5000 72GB Blackwell" },
{ 0x2BB4, 0x204c, 0x1028, "NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition" },
{ 0x2BB4, 0x204c, 0x103c, "NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition" },
{ 0x2BB4, 0x204c, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition" },
@@ -845,6 +848,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2DB9, 0x0000, 0x0000, "NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU" },
{ 0x2DD8, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050 Laptop GPU" },
{ 0x2DF9, 0x0000, 0x0000, "NVIDIA RTX PRO 500 Blackwell Embedded GPU" },
{ 0x2E12, 0x21ec, 0x10de, "NVIDIA GB10" },
{ 0x2F04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070" },
{ 0x2F18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },
{ 0x2F38, 0x0000, 0x0000, "NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU" },

57
src/nvidia/inc/kernel/gpu/falcon/kernel_falcon_core_dump.h Normal file
View File

@@ -0,0 +1,57 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef KERNEL_FALCON_CORE_DUMP_H
#define KERNEL_FALCON_CORE_DUMP_H
#include "gpu/falcon/kernel_falcon.h"
#define __RISCV_MAX_UNWIND_DEPTH 32
#define __RISCV_MAX_TRACE_ENTRIES 64
typedef struct CoreDumpRegs
{
NvU32 riscvPc;
NvU32 riscvCpuctl;
NvU32 riscvIrqmask;
NvU32 riscvIrqdest;
NvU32 riscvIrqdeleg;
NvU32 falconMailbox[2];
NvU32 falconIrqstat;
NvU32 falconIrqmode;
NvU32 fbifInstblk;
NvU32 fbifCtl;
NvU32 fbifThrottle;
NvU32 fbifAchkBlk[2];
NvU32 fbifAchkCtl[2];
NvU32 fbifCg1;
// Ampere and above
NvU32 riscvPrivErrStat;
NvU32 riscvPrivErrInfo;
NvU32 riscvPrivErrAddrH;
NvU32 riscvPrivErrAddrL;
NvU32 riscvHubErrStat;
NvU32 tracePCEntries;
NvU64 tracePC[__RISCV_MAX_TRACE_ENTRIES];
} CoreDumpRegs;
#endif

158
src/nvidia/src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,11 +27,13 @@
*/
#include "gpu/falcon/kernel_falcon.h"
#include "gpu/falcon/kernel_falcon_core_dump.h"
#include "os/os.h"
#include "published/ampere/ga102/dev_falcon_v4.h"
#include "published/ampere/ga102/dev_falcon_v4_addendum.h"
#include "published/ampere/ga102/dev_riscv_pri.h"
#include "published/ampere/ga102/dev_fbif_v4.h"
#define PRE_RESET_PRE_SILICON_TIMEOUT_US 300000
@@ -318,3 +320,157 @@ kflcnRiscvReadIntrStatus_GA102
kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_IRQDEST));
}
/*!
* Function to read the ICD_CMD register.
*/
NvU32 kflcnIcdReadCmdReg_GA102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn
)
{
return kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_ICD_CMD);
}
/*!
* Function to read the ICD_RDATA register pair.
*/
NvU64 kflcnRiscvIcdReadRdata_GA102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn
)
{
return (((NvU64)kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_ICD_RDATA1)) << 32) |
kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_ICD_RDATA0);
}
/*!
* Function to write the ICD_ADDR register pair.
*/
void kflcnRiscvIcdWriteAddress_GA102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
NvU64 address
)
{
kflcnRiscvRegWrite_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_ICD_ADDR1, address >> 32);
kflcnRiscvRegWrite_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_ICD_ADDR0, (NvU32) address);
}
/*!
* Function to write the ICD_CMD register.
*/
void kflcnIcdWriteCmdReg_GA102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
NvU32 value
)
{
kflcnRiscvRegWrite_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_ICD_CMD, value);
}
void
kflcnDumpTracepc_GA102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
CoreDumpRegs *pCore
)
{
NvU64 pc;
NvU32 ctl;
NvU32 r, w, size;
NvU32 entry;
NvU32 count;
r = kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACE_RDIDX);
w = kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACE_WTIDX);
if (((r & 0xbadf0000) == 0xbadf0000) &&
((w & 0xbadf0000) == 0xbadf0000))
{
NV_PRINTF(LEVEL_ERROR, "Trace buffer blocked, skipping.\n");
return;
}
size = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _MAXIDX, r);
if (size > __RISCV_MAX_TRACE_ENTRIES)
{
NV_PRINTF(LEVEL_ERROR, "Trace buffer larger than expected. Bailing!\n");
return;
}
r = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, r);
w = DRF_VAL(_PRISCV_RISCV, _TRACE_WTIDX, _WTIDX, w);
ctl = kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACECTL);
if ((w == r) && (DRF_VAL(_PRISCV_RISCV, _TRACECTL, _FULL, ctl) == 0))
{
count = 0;
}
else
{
//
// The number of entries in trace buffer is how far the w (put) pointer
// is ahead of the r (get) pointer. If this value is negative, add
// the size of the circular buffer to bring the element count back into range.
//
count = w > r ? w - r : w - r + size;
}
pCore->tracePCEntries = count;
if (count)
{
for (entry = 0; entry < count; ++entry)
{
if (entry > w)
w += size;
kflcnRiscvRegWrite_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, w - entry);
pc = ((NvU64)kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACEPC_HI) << 32ull) |
kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACEPC_LO);
pCore->tracePC[entry] = pc;
}
}
// Restore original value
kflcnRiscvRegWrite_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, r);
return;
}
NV_STATUS kflcnCoreDumpPc_GA102(OBJGPU *pGpu, KernelFalcon *pKernelFlcn, NvU64 *pc)
{
//
// This code originally handled 0xbadfxxxx values and returned failure,
// however we may want to see badf values so it is now wired to return the read
// register always. We want to also ensure any automated processing will know to
// attempt a soft decode of the lower 32 bits as it is not a complete address.
//
*pc = 0xfa11bacc00000000ull | (NvU64)kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_RPC);
return NV_OK;
}
void
kflcnDumpCoreRegs_GA102(OBJGPU *pGpu, KernelFalcon *pKernelFlcn, CoreDumpRegs *pCore)
{
#define __CORE_DUMP_RISCV_REG(x,y) do { pCore->x = kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, (y)); } while (0)
__CORE_DUMP_RISCV_REG(riscvCpuctl, NV_PRISCV_RISCV_CPUCTL);
__CORE_DUMP_RISCV_REG(riscvIrqmask, NV_PRISCV_RISCV_IRQMASK);
__CORE_DUMP_RISCV_REG(riscvIrqdest, NV_PRISCV_RISCV_IRQDEST);
__CORE_DUMP_RISCV_REG(riscvPc, NV_PRISCV_RISCV_RPC);
__CORE_DUMP_RISCV_REG(riscvIrqdeleg, NV_PRISCV_RISCV_IRQDELEG);
__CORE_DUMP_RISCV_REG(riscvPrivErrStat, NV_PRISCV_RISCV_PRIV_ERR_STAT);
__CORE_DUMP_RISCV_REG(riscvPrivErrInfo, NV_PRISCV_RISCV_PRIV_ERR_INFO);
__CORE_DUMP_RISCV_REG(riscvPrivErrAddrH, NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI);
__CORE_DUMP_RISCV_REG(riscvPrivErrAddrL, NV_PRISCV_RISCV_PRIV_ERR_ADDR);
__CORE_DUMP_RISCV_REG(riscvHubErrStat, NV_PRISCV_RISCV_HUB_ERR_STAT);
#undef __CORE_DUMP_RISCV_REG
}

51
src/nvidia/src/kernel/gpu/falcon/arch/blackwell/kernel_falcon_gb202.c Normal file
View File

@@ -0,0 +1,51 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* Provides the implementation for all GB100+ specific KernelFalcon
* interfaces.
*/
#include "kernel/gpu/gpu.h"
#include "gpu/falcon/kernel_falcon.h"
#include "gpu/falcon/kernel_falcon_core_dump.h"
#include "published/blackwell/gb202/dev_riscv_pri.h"
void
kflcnDumpCoreRegs_GB202(OBJGPU *pGpu, KernelFalcon *pKernelFlcn, CoreDumpRegs *pCore)
{
#define __CORE_DUMP_RISCV_REG(x,y) do { pCore->x = kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, (y)); } while (0)
__CORE_DUMP_RISCV_REG(riscvCpuctl, NV_PRISCV_RISCV_CPUCTL);
__CORE_DUMP_RISCV_REG(riscvIrqmask, NV_PRISCV_RISCV_IRQMASK);
__CORE_DUMP_RISCV_REG(riscvIrqdest, NV_PRISCV_RISCV_IRQDEST);
__CORE_DUMP_RISCV_REG(riscvPc, NV_PRISCV_RISCV_RPC);
__CORE_DUMP_RISCV_REG(riscvIrqdeleg, NV_PRISCV_RISCV_IRQDELEG);
__CORE_DUMP_RISCV_REG(riscvPrivErrStat, NV_PRISCV_RISCV_PRIV_ERR_STAT);
__CORE_DUMP_RISCV_REG(riscvPrivErrInfo, NV_PRISCV_RISCV_PRIV_ERR_INFO);
__CORE_DUMP_RISCV_REG(riscvPrivErrAddrH, NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI);
__CORE_DUMP_RISCV_REG(riscvPrivErrAddrL, NV_PRISCV_RISCV_PRIV_ERR_ADDR);
__CORE_DUMP_RISCV_REG(riscvHubErrStat, NV_PRISCV_RISCV_HUB_ERR_STAT);
#undef __CORE_DUMP_RISCV_REG
}

511
src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,6 +26,7 @@
*/
#include "gpu/falcon/kernel_falcon.h"
#include "gpu/falcon/kernel_falcon_core_dump.h"
#include "os/os.h"
#include "published/turing/tu102/dev_riscv_pri.h"
@@ -426,3 +427,511 @@ kflcnMaskDmemAddr_TU102
return (addr & (DRF_SHIFTMASK(NV_PFALCON_FALCON_DMEMC_OFFS) |
DRF_SHIFTMASK(NV_PFALCON_FALCON_DMEMC_BLK)));
}
/*!
* Function to read the ICD_CMD register.
*/
NvU32 kflcnIcdReadCmdReg_TU102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn
)
{
return kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_ICD_CMD);
}
/*!
* Function to read the ICD_RDATA register pair.
*/
NvU64 kflcnRiscvIcdReadRdata_TU102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn
)
{
return (((NvU64)kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_ICD_RDATA1)) << 32) |
kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_ICD_RDATA0);
}
/*!
* Function to write the ICD_ADDR register pair.
*/
void kflcnRiscvIcdWriteAddress_TU102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
NvU64 address
)
{
kflcnRiscvRegWrite_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_ICD_ADDR1, address >> 32);
kflcnRiscvRegWrite_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_ICD_ADDR0, (NvU32) address);
}
/*!
* Function to write the ICD_CMD register.
*/
void kflcnIcdWriteCmdReg_TU102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
NvU32 value
)
{
kflcnRiscvRegWrite_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_ICD_CMD, value);
}
static NvBool
s_riscvIsIcdNotBusy
(
OBJGPU *pGpu,
void *pVoid
)
{
KernelFalcon *pKernelFlcn = reinterpretCast(pVoid, KernelFalcon *);
NvU32 reg;
reg = kflcnIcdReadCmdReg_HAL(pGpu, pKernelFlcn);
return FLD_TEST_DRF(_PRISCV_RISCV, _ICD_CMD, _BUSY, _FALSE, reg);
}
static NV_STATUS
s_riscvIcdGetValue
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
NvU64 *pValue
)
{
// Wait for ICD to become idle before reading out value.
NV_STATUS status = kflcnRiscvIcdWaitForIdle_HAL(pGpu, pKernelFlcn);
if (status == NV_OK)
{
*pValue = kflcnRiscvIcdReadRdata_HAL(pGpu, pKernelFlcn);
}
else if (status == NV_ERR_INVALID_STATE)
{
return NV_ERR_INVALID_ARGUMENT;
}
else
{
return NV_ERR_INVALID_STATE;
}
return NV_OK;
}
/*!
* Function to wait for the ICD to become idle.
*
* @param[in] pGpu OBJGPU pointer
* @param[in] pKernelFlcn KernelFalcon object pointer
*
* @return 'NV_OK' if idle and no error
* 'NV_ERR_INVALID_STATE' if idle and error; typically bad command.
* 'NV_ERR_TIMEOUT' if busy and timed out. This usually indicates
* a fatal error, eg. core has hung or GPU is off the bus.
*/
NV_STATUS
kflcnRiscvIcdWaitForIdle_TU102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn
)
{
NvU32 icdCmd;
RMTIMEOUT timeout;
gpuSetTimeout(pGpu, 125*1000, &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); // Wait up to 125ms
if (gpuTimeoutCondWait(pGpu, s_riscvIsIcdNotBusy, pKernelFlcn, &timeout) != NV_OK)
{
return NV_ERR_TIMEOUT;
}
icdCmd = kflcnIcdReadCmdReg_HAL(pGpu, pKernelFlcn);
if (FLD_TEST_DRF(_PRISCV_RISCV, _ICD_CMD, _ERROR, _TRUE, icdCmd))
{
return NV_ERR_INVALID_STATE;
}
return NV_OK;
}
/*!
* Function to tell RISCV ICD to read RISCV virtual addresses.
*
* @param[in] pGpu OBJGPU pointer
* @param[in] pKernelFlcn KernelFalcon object pointer
* @param[in] address Address of memory to read.
* @param[in] size Size of access (1-8 bytes, pow2)
* @param[out] pValue register value
*
* @return 'NV_OK' if register value was read
* 'NV_ERR_INVALID_STATE' if core is not booted or didn't halt.
* 'NV_ERR_INVALID_ARGUMENT' if size is invalid
*/
NV_STATUS
kflcnRiscvIcdReadMem_TU102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
NvU64 address,
NvU64 size,
NvU64 *pValue
)
{
NvU32 icdCmd;
// Only pow2 sizes are allowed
if ((size != 1) && (size != 2) && (size != 4) && (size != 8))
{
return NV_ERR_INVALID_ARGUMENT;
}
if ((address & (size - 1))) // Addresses must be aligned to the size. This is a RISCV architecture design decision.
{
return NV_ERR_INVALID_ARGUMENT;
}
NvU32 size_shift = 0;
while (size != 1)
{
size = size >> 1;
size_shift++;
}
if (kflcnIsRiscvActive_HAL(pGpu, pKernelFlcn) &&
(kflcnRiscvIcdWaitForIdle_HAL(pGpu, pKernelFlcn) != NV_ERR_TIMEOUT))
{
icdCmd = DRF_DEF(_PRISCV_RISCV, _ICD_CMD, _OPC, _RDM);
icdCmd = FLD_SET_DRF_NUM(_PRISCV_RISCV, _ICD_CMD, _SZ, size_shift, icdCmd);
icdCmd = FLD_SET_DRF_NUM(_PRISCV_RISCV, _ICD_CMD, _PARM, 1, icdCmd);
kflcnRiscvIcdWriteAddress_HAL(pGpu, pKernelFlcn, address);
kflcnIcdWriteCmdReg_HAL(pGpu, pKernelFlcn, icdCmd);
}
else
{
// RISCV core was not booted, or ICD failed to execute command.
return NV_ERR_INVALID_STATE;
}
return s_riscvIcdGetValue(pGpu, pKernelFlcn, pValue);
}
/*!
* Function to tell RISCV ICD to read RISCV register.
*
* @param[in] pGpu OBJGPU pointer
* @param[in] pKernelFlcn KernelFalcon object pointer
* @param[in] reg which register to read. Valid: 0-31 (0 is x0, so it is skipped)
* @param[out] pValue register value
*
* @return 'NV_OK' if register value was read
* 'NV_ERR_INVALID_STATE' if core is not booted or didn't halt.
* 'NV_ERR_INVALID_ARGUMENT' if register is invalid.
*/
NV_STATUS
kflcnRiscvIcdReadReg_TU102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
NvU32 reg,
NvU64 *pValue
)
{
NvU32 icdCmd;
// x0..x31 are valid RISCV register values.
if (reg >= 32)
{
return NV_ERR_INVALID_ARGUMENT;
}
if (reg == 0)
{
*pValue = 0;
return NV_OK;
}
if (kflcnIsRiscvActive_HAL(pGpu, pKernelFlcn) &&
(kflcnRiscvIcdWaitForIdle_HAL(pGpu, pKernelFlcn) != NV_ERR_TIMEOUT))
{
icdCmd = DRF_DEF(_PRISCV_RISCV, _ICD_CMD, _OPC, _RREG);
icdCmd = FLD_SET_DRF_NUM(_PRISCV_RISCV, _ICD_CMD, _IDX, reg, icdCmd);
kflcnIcdWriteCmdReg_HAL(pGpu, pKernelFlcn, icdCmd);
}
else
{
// RISCV core was not booted, or ICD failed to execute command.
return NV_ERR_INVALID_STATE;
}
return s_riscvIcdGetValue(pGpu, pKernelFlcn, pValue);
}
/*!
* Function to tell RISCV ICD to read RISCV CSR.
*
* @param[in] pGpu OBJGPU pointer
* @param[in] pKernelFlcn KernelFalcon object pointer
* @param[in] csr which CSR register to read. Valid: 0-4095
* @param[out] pValue CSR register value
*
* @return 'NV_OK' if CSR value was read
* 'NV_ERR_INVALID_STATE' if core is not booted or didn't halt.
* 'NV_ERR_INVALID_ARGUMENT' if CSR is invalid.
*/
NV_STATUS
kflcnRiscvIcdRcsr_TU102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
NvU32 csr,
NvU64 *pValue
)
{
NvU32 icdCmd;
// CSR must be between 0 and 4095, inclusive, as this is part of the RISCV spec.
if (csr >= 4096)
{
return NV_ERR_INVALID_ARGUMENT;
}
if (kflcnIsRiscvActive_HAL(pGpu, pKernelFlcn) &&
(kflcnRiscvIcdWaitForIdle_HAL(pGpu, pKernelFlcn) != NV_ERR_TIMEOUT))
{
icdCmd = DRF_DEF(_PRISCV_RISCV, _ICD_CMD, _OPC, _RCSR);
icdCmd = FLD_SET_DRF_NUM(_PRISCV_RISCV, _ICD_CMD, _PARM, csr, icdCmd);
kflcnIcdWriteCmdReg_HAL(pGpu, pKernelFlcn, icdCmd);
}
else
{
// RISCV core was not booted, or ICD failed to read CSR.
return NV_ERR_INVALID_STATE;
}
return s_riscvIcdGetValue(pGpu, pKernelFlcn, pValue);
}
/*!
* Function to tell RISCV ICD to read RSTAT register.
*
* @param[in] pGpu OBJGPU pointer
* @param[in] pKernelFlcn KernelFalcon object pointer
* @param[in] index which RSTAT register to read. Valid: 0 3 4
* @param[out] pValue RSTAT register value
*
* @return 'NV_OK' if RSTAT value was read
* 'NV_ERR_INVALID_STATE' if core is not booted or didn't halt.
* 'NV_ERR_INVALID_ARGUMENT' if invalid RSTAT register was specified.
*/
NV_STATUS
kflcnRiscvIcdRstat_TU102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
NvU32 index,
NvU64 *pValue
)
{
NvU32 icdCmd;
if (kflcnIsRiscvActive_HAL(pGpu, pKernelFlcn) &&
(kflcnRiscvIcdWaitForIdle_HAL(pGpu, pKernelFlcn) != NV_ERR_TIMEOUT))
{
icdCmd = DRF_DEF(_PRISCV_RISCV, _ICD_CMD, _OPC, _RSTAT);
icdCmd = FLD_SET_DRF_NUM(_PRISCV_RISCV, _ICD_CMD, _IDX, index, icdCmd);
kflcnIcdWriteCmdReg_HAL(pGpu, pKernelFlcn, icdCmd);
}
else
{
// RISCV core was not booted, or ICD misbehaved.
return NV_ERR_INVALID_STATE;
}
return s_riscvIcdGetValue(pGpu, pKernelFlcn, pValue);
}
/*!
* Function to tell RISCV ICD to read PC.
*
* @param[in] pGpu OBJGPU pointer
* @param[in] pKernelFlcn KernelFalcon object pointer
* @param[out] pValue PC value
*
* @return 'NV_OK' if RSTAT value was read
* 'NV_ERR_INVALID_STATE' if core is not booted or didn't halt.
* 'NV_ERR_INVALID_ARGUMENT' should not happen.
*/
NV_STATUS
kflcnRiscvIcdRpc_TU102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
NvU64 *pValue
)
{
NvU32 icdCmd;
if (kflcnIsRiscvActive_HAL(pGpu, pKernelFlcn) &&
(kflcnRiscvIcdWaitForIdle_HAL(pGpu, pKernelFlcn) != NV_ERR_TIMEOUT))
{
icdCmd = DRF_DEF(_PRISCV_RISCV, _ICD_CMD, _OPC, _RPC);
kflcnIcdWriteCmdReg_HAL(pGpu, pKernelFlcn, icdCmd);
}
else
{
// RISCV core was not booted, or ICD failed to retrieve PC.
return NV_ERR_INVALID_STATE;
}
return s_riscvIcdGetValue(pGpu, pKernelFlcn, pValue);
}
/*!
* Function to tell RISCV core to enter ICD mode.
*
* @param[in] pGpu OBJGPU pointer
* @param[in] pKernelFlcn KernelFalcon object pointer
*
* @return 'NV_OK' if core has entered ICD
* 'NV_ERR_INVALID_STATE' if core is not booted.
* 'NV_ERR_TIMEOUT' if core did not successfully halt.
*/
NV_STATUS
kflcnRiscvIcdHalt_TU102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn
)
{
NV_STATUS status = NV_OK;
NvU32 icdCmd;
NvU8 tries = 9; // This should be set to allow retries for over a second.
if (kflcnIsRiscvActive_HAL(pGpu, pKernelFlcn))
{
do
{
icdCmd = DRF_DEF(_PRISCV_RISCV, _ICD_CMD, _OPC, _STOP);
kflcnIcdWriteCmdReg_HAL(pGpu, pKernelFlcn, icdCmd);
status = kflcnRiscvIcdWaitForIdle_HAL(pGpu, pKernelFlcn);
if (tries == 0)
break;
tries--;
}
while (status != NV_OK);
}
else // RISCV core was not booted; die immediately.
{
return NV_ERR_INVALID_STATE;
}
return status;
}
void
kflcnDumpTracepc_TU102
(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
CoreDumpRegs *pCore
)
{
NvU64 pc;
NvU32 ctl;
NvU32 r, w, size;
NvU32 entry;
NvU32 count;
r = kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACE_RDIDX);
w = kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACE_WTIDX);
size = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _MAXIDX, r);
if (size > __RISCV_MAX_TRACE_ENTRIES)
{
NV_PRINTF(LEVEL_ERROR, "Trace buffer larger than expected. Bailing!\n");
return;
}
r = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, r);
w = DRF_VAL(_PRISCV_RISCV, _TRACE_WTIDX, _WTIDX, w);
ctl = kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACECTL);
if ((w == r) && (DRF_VAL(_PRISCV_RISCV, _TRACECTL, _FULL, ctl) == 0))
{
count = 0;
}
else
{
//
// The number of entries in trace buffer is how far the w (put) pointer
// is ahead of the r (get) pointer. If this value is negative, add
// the size of the circular buffer to bring the element count back into range.
//
count = w > r ? w - r : w - r + size;
}
pCore->tracePCEntries = count;
if (count)
{
for (entry = 0; entry < count; ++entry)
{
if (entry > w)
w += size;
kflcnRiscvRegWrite_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, w - entry);
pc = ((NvU64)kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACEPC_HI) << 32ull) |
kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACEPC_LO);
pCore->tracePC[entry] = pc;
}
}
// Restore original value
kflcnRiscvRegWrite_HAL(pGpu, pKernelFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, r);
return;
}
void
kflcnDumpCoreRegs_TU102(OBJGPU *pGpu, KernelFalcon *pKernelFlcn, CoreDumpRegs *pCore)
{
#define __CORE_DUMP_RISCV_REG(x,y) do { pCore->x = kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, (y)); } while (0)
__CORE_DUMP_RISCV_REG(riscvCpuctl, NV_PRISCV_RISCV_CPUCTL);
__CORE_DUMP_RISCV_REG(riscvIrqmask, NV_PRISCV_RISCV_IRQMASK);
__CORE_DUMP_RISCV_REG(riscvIrqdest, NV_PRISCV_RISCV_IRQDEST);
__CORE_DUMP_RISCV_REG(riscvPrivErrStat, NV_PRISCV_RISCV_PRIV_ERR_STAT);
__CORE_DUMP_RISCV_REG(riscvPrivErrInfo, NV_PRISCV_RISCV_PRIV_ERR_INFO);
__CORE_DUMP_RISCV_REG(riscvPrivErrAddrL, NV_PRISCV_RISCV_PRIV_ERR_ADDR);
__CORE_DUMP_RISCV_REG(riscvHubErrStat, NV_PRISCV_RISCV_HUB_ERR_STAT);
#undef __CORE_DUMP_RISCV_REG
}
void
kflcnDumpPeripheralRegs_TU102(OBJGPU *pGpu, KernelFalcon *pKernelFlcn, CoreDumpRegs *pCore)
{
#define __CORE_DUMP_REG(x,y) do { pCore->x = kflcnRegRead_HAL(pGpu, pKernelFlcn, (y)); } while (0)
__CORE_DUMP_REG(falconMailbox[0], NV_PFALCON_FALCON_MAILBOX0);
__CORE_DUMP_REG(falconMailbox[1], NV_PFALCON_FALCON_MAILBOX1);
__CORE_DUMP_REG(falconIrqstat, NV_PFALCON_FALCON_IRQSTAT);
__CORE_DUMP_REG(falconIrqmode, NV_PFALCON_FALCON_IRQMODE);
#undef __CORE_DUMP_REG
#define __CORE_DUMP_RAW(x,y) do { pCore->x = GPU_REG_RD32(pGpu, (y)); } while (0)
__CORE_DUMP_RAW(fbifInstblk, pKernelFlcn->fbifBase + NV_PFALCON_FBIF_INSTBLK);
__CORE_DUMP_RAW(fbifCtl, pKernelFlcn->fbifBase + NV_PFALCON_FBIF_CTL);
__CORE_DUMP_RAW(fbifThrottle, pKernelFlcn->fbifBase + NV_PFALCON_FBIF_THROTTLE);
__CORE_DUMP_RAW(fbifAchkBlk[0], pKernelFlcn->fbifBase + NV_PFALCON_FBIF_ACHK_BLK(0));
__CORE_DUMP_RAW(fbifAchkBlk[1], pKernelFlcn->fbifBase + NV_PFALCON_FBIF_ACHK_BLK(1));
__CORE_DUMP_RAW(fbifAchkCtl[0], pKernelFlcn->fbifBase + NV_PFALCON_FBIF_ACHK_CTL(0));
__CORE_DUMP_RAW(fbifAchkCtl[1], pKernelFlcn->fbifBase + NV_PFALCON_FBIF_ACHK_CTL(1));
__CORE_DUMP_RAW(fbifCg1, pKernelFlcn->fbifBase + NV_PFALCON_FBIF_CG1);
#undef __CORE_DUMP_RAW
}

221
src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,6 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "gpu/falcon/kernel_falcon.h"
#include "gpu/falcon/kernel_falcon_core_dump.h"
#include "gpu/sec2/kernel_sec2.h"
#include "gpu/gsp/kernel_gsp.h"
@@ -441,3 +442,221 @@ NV_STATUS gkflcnServiceNotificationInterrupt_IMPL(OBJGPU *pGpu, GenericKernelFal
return NV_OK;
}
NV_STATUS kflcnCoreDumpNondestructive(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn,
NvU32 verbosity
)
{
CoreDumpRegs PeregrineCoreRegisters = { 0 };
kflcnDumpCoreRegs_HAL(pGpu, pKernelFlcn, &PeregrineCoreRegisters);
if (verbosity >= 1)
{
kflcnDumpPeripheralRegs_HAL(pGpu, pKernelFlcn, &PeregrineCoreRegisters);
}
if (verbosity >= 2)
{
kflcnDumpTracepc(pGpu, pKernelFlcn, &PeregrineCoreRegisters);
}
NV_PRINTF(LEVEL_ERROR, "PRI: riscvPc : %08x\n", PeregrineCoreRegisters.riscvPc);
if (verbosity >= 1)
{
NV_PRINTF(LEVEL_ERROR, "PRI: riscvCpuctl : %08x\n", PeregrineCoreRegisters.riscvCpuctl);
NV_PRINTF(LEVEL_ERROR, "PRI: riscvIrqmask : %08x\n", PeregrineCoreRegisters.riscvIrqmask);
NV_PRINTF(LEVEL_ERROR, "PRI: riscvIrqdest : %08x\n", PeregrineCoreRegisters.riscvIrqdest);
NV_PRINTF(LEVEL_ERROR, "PRI: riscvPrivErrStat : %08x\n", PeregrineCoreRegisters.riscvPrivErrStat);
NV_PRINTF(LEVEL_ERROR, "PRI: riscvPrivErrInfo : %08x\n", PeregrineCoreRegisters.riscvPrivErrInfo);
NV_PRINTF(LEVEL_ERROR, "PRI: riscvPrivErrAddr : %016" NvU64_fmtx "\n", (((NvU64)PeregrineCoreRegisters.riscvPrivErrAddrH << 32ull) | PeregrineCoreRegisters.riscvPrivErrAddrL));
NV_PRINTF(LEVEL_ERROR, "PRI: riscvHubErrStat : %08x\n", PeregrineCoreRegisters.riscvHubErrStat);
NV_PRINTF(LEVEL_ERROR, "PRI: falconMailbox : 0:%08x 1:%08x\n", PeregrineCoreRegisters.falconMailbox[0], PeregrineCoreRegisters.falconMailbox[1]);
NV_PRINTF(LEVEL_ERROR, "PRI: falconIrqstat : %08x\n", PeregrineCoreRegisters.falconIrqstat);
NV_PRINTF(LEVEL_ERROR, "PRI: falconIrqmode : %08x\n", PeregrineCoreRegisters.falconIrqmode);
NV_PRINTF(LEVEL_ERROR, "PRI: fbifInstblk : %08x\n", PeregrineCoreRegisters.fbifInstblk);
NV_PRINTF(LEVEL_ERROR, "PRI: fbifCtl : %08x\n", PeregrineCoreRegisters.fbifCtl);
NV_PRINTF(LEVEL_ERROR, "PRI: fbifThrottle : %08x\n", PeregrineCoreRegisters.fbifThrottle);
NV_PRINTF(LEVEL_ERROR, "PRI: fbifAchkBlk : 0:%08x 1:%08x\n", PeregrineCoreRegisters.fbifAchkBlk[0], PeregrineCoreRegisters.fbifAchkBlk[1]);
NV_PRINTF(LEVEL_ERROR, "PRI: fbifAchkCtl : 0:%08x 1:%08x\n", PeregrineCoreRegisters.fbifAchkCtl[0], PeregrineCoreRegisters.fbifAchkCtl[1]);
NV_PRINTF(LEVEL_ERROR, "PRI: fbifCg1 : %08x\n", PeregrineCoreRegisters.fbifCg1);
}
if (verbosity >= 2)
{
for (unsigned int n = 0; n < PeregrineCoreRegisters.tracePCEntries; n++)
{
NV_PRINTF(LEVEL_ERROR, "TRACE: %02u = 0x%016" NvU64_fmtx "\n", n, PeregrineCoreRegisters.tracePC[n]);
}
}
return NV_OK;
}
NV_STATUS kflcnCoreDumpDestructive(
OBJGPU *pGpu,
KernelFalcon *pKernelFlcn
)
{
// Initialise state - nothing succeeded yet.
NvU64 pc = 1;
NvU64 traceRa = 0;
NvU64 traceS0 = 0;
NvU32 unwindDepth = 0;
NvU64 regValue64;
NvU64 riscvCoreRegisters[32];
NvU32 anySuccess = 0;
// Check if PRI is alive / core is booted.
{
if (kflcnIsRiscvActive_HAL(pGpu, pKernelFlcn)) // If core is not booted, abort - nothing to do.
{
NV_PRINTF(LEVEL_ERROR, "ICD: Core is booted.\n");
}
else
{
NV_PRINTF(LEVEL_ERROR, "ICD: [ERROR] Core is not booted.\n");
return NV_OK;
}
}
// Check if ICD RSTAT works.
{
for (int i = 0; i < 8; i++)
{
if (kflcnRiscvIcdRstat_HAL(pGpu, pKernelFlcn, i, &regValue64) == NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "ICD: RSTAT%d 0x%016" NvU64_fmtx "\n", i, regValue64);
anySuccess++;
}
}
if (!anySuccess)
{
NV_PRINTF(LEVEL_ERROR, "ICD: [ERROR] Unable to retrieve any RSTAT register.\n");
return NV_OK; // Failed to read ANY RSTAT value. This means ICD is dead.
}
}
// ATTEMPT ICD HALT, and dump state. Check if ICD commands work.
{
if (kflcnRiscvIcdHalt_HAL(pGpu, pKernelFlcn) != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "ICD: [ERROR] ICD Halt command failed.\n");
return NV_OK; // Failed to halt core. Typical end point for "core is hung" scenario.
}
}
// Dump PC, as much as we can get.
if (kflcnRiscvIcdRpc_HAL(pGpu, pKernelFlcn, &pc) != NV_OK)
{
if (kflcnCoreDumpPc_HAL(pGpu, pKernelFlcn, &pc) != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "ICD: [WARN] Cannot retrieve PC.\n");
}
else
{
NV_PRINTF(LEVEL_ERROR, "ICD: PC = 0x--------%08llx\n", pc & 0xffffffff);
}
}
else
{
NV_PRINTF(LEVEL_ERROR, "ICD: PC = 0x%016" NvU64_fmtx "\n", pc);
}
// Dump registers
for (int a = 0; a < 32; a++)
{
if (kflcnRiscvIcdReadReg_HAL(pGpu, pKernelFlcn, a, &regValue64) == NV_OK)
{
riscvCoreRegisters[a] = regValue64;
// Save off registers needed for unwinding.
if (a == 1)
traceRa = regValue64;
if (a == 8)
traceS0 = regValue64;
}
else
{
NV_PRINTF(LEVEL_ERROR, "ICD: register read failed for x%02d\n", a);
riscvCoreRegisters[a] = 0xbaadbaadbaadbaad;
}
}
NV_PRINTF(LEVEL_ERROR,
"ICD: ra:0x%016" NvU64_fmtx " sp:0x%016" NvU64_fmtx " gp:0x%016" NvU64_fmtx " tp:0x%016" NvU64_fmtx "\n",
riscvCoreRegisters[1], riscvCoreRegisters[2], riscvCoreRegisters[3], riscvCoreRegisters[4]);
NV_PRINTF(LEVEL_ERROR,
"ICD: a0:0x%016" NvU64_fmtx " a1:0x%016" NvU64_fmtx " a2:0x%016" NvU64_fmtx " a3:0x%016" NvU64_fmtx "\n",
riscvCoreRegisters[5], riscvCoreRegisters[6], riscvCoreRegisters[7], riscvCoreRegisters[8]);
NV_PRINTF(LEVEL_ERROR,
"ICD: a4:0x%016" NvU64_fmtx " a5:0x%016" NvU64_fmtx " a6:0x%016" NvU64_fmtx " a7:0x%016" NvU64_fmtx "\n",
riscvCoreRegisters[9], riscvCoreRegisters[10], riscvCoreRegisters[11], riscvCoreRegisters[12]);
NV_PRINTF(LEVEL_ERROR,
"ICD: s0:0x%016" NvU64_fmtx " s1:0x%016" NvU64_fmtx " s2:0x%016" NvU64_fmtx " s3:0x%016" NvU64_fmtx "\n",
riscvCoreRegisters[13], riscvCoreRegisters[14], riscvCoreRegisters[15], riscvCoreRegisters[16]);
NV_PRINTF(LEVEL_ERROR,
"ICD: s4:0x%016" NvU64_fmtx " s5:0x%016" NvU64_fmtx " s6:0x%016" NvU64_fmtx " s7:0x%016" NvU64_fmtx "\n",
riscvCoreRegisters[17], riscvCoreRegisters[18], riscvCoreRegisters[19], riscvCoreRegisters[20]);
NV_PRINTF(LEVEL_ERROR,
"ICD: s8:0x%016" NvU64_fmtx " s9:0x%016" NvU64_fmtx " s10:0x%016" NvU64_fmtx " s11:0x%016" NvU64_fmtx "\n",
riscvCoreRegisters[21], riscvCoreRegisters[22], riscvCoreRegisters[23], riscvCoreRegisters[24]);
NV_PRINTF(LEVEL_ERROR,
"ICD: t0:0x%016" NvU64_fmtx " t1:0x%016" NvU64_fmtx " t2:0x%016" NvU64_fmtx " t3:0x%016" NvU64_fmtx "\n",
riscvCoreRegisters[25], riscvCoreRegisters[26], riscvCoreRegisters[27], riscvCoreRegisters[28]);
NV_PRINTF(LEVEL_ERROR,
"ICD: t4:0x%016" NvU64_fmtx " t5:0x%016" NvU64_fmtx " t6:0x%016" NvU64_fmtx "\n",
riscvCoreRegisters[29], riscvCoreRegisters[30], riscvCoreRegisters[31]);
// Dump CSRs
for (int a = 0; a < 4096; a++)
{
if (kflcnRiscvIcdRcsr_HAL(pGpu, pKernelFlcn, a, &regValue64) == NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "ICD: csr[%03x] = 0x%016" NvU64_fmtx "\n", a, regValue64);
}
}
//
// Attempt core unwind. For various reasons, may fail very early.
// To unwind, we use s0 as the frame pointer and ra as the return address (adding that to the callstack).
// s0[-2] contains the previous stack pointer, and s0[-1] contains the previous return address.
// We continue until the memory is not readable, or we hit some "very definitely wrong" values like zero or
// misaligned stack. If we unwind even once, we declare our unwind a great success and move on.
//
{
if ((!traceRa) || (!traceS0))
return NV_OK; // Fail to unwind - the ra/s0 registers are not valid.
do
{
if ((!traceS0) || // S0 cannot be zero
(!traceRa) || // RA cannot be zero
(traceS0 & 7)) // stack cannot be misaligned
goto abortUnwind;
traceS0 -= 16;
if (kflcnRiscvIcdReadMem_HAL(pGpu, pKernelFlcn, traceS0 + 8, 8, &traceRa) != NV_OK)
goto abortUnwind;
if (kflcnRiscvIcdReadMem_HAL(pGpu, pKernelFlcn, traceS0 + 0, 8, &traceS0) != NV_OK)
goto abortUnwind;
NV_PRINTF(LEVEL_ERROR, "ICD: unwind%02u: 0x%016" NvU64_fmtx "\n", unwindDepth, traceRa);
unwindDepth++;
} while (unwindDepth < __RISCV_MAX_UNWIND_DEPTH);
// Core unwind attempt finished. The call stack was too deep.
NV_PRINTF(LEVEL_ERROR, "ICD: [WARN] unwind greater than max depth...\n");
goto unwindFull;
}
abortUnwind:
// Core unwind attempt finished. No unwind past the register (ra) was possible.
if (unwindDepth == 0)
{
NV_PRINTF(LEVEL_ERROR, "ICD: [WARN] unwind retrieved zero values :(\n");
return NV_OK;
}
// Core unwind attempt finished. Unwind successfully got 1 or more entries.
unwindFull:
NV_PRINTF(LEVEL_ERROR, "ICD: unwind complete.\n");
return NV_OK;
}

17
src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c
View File

@@ -1355,6 +1355,23 @@ exit_fail_cleanup:
return nvStatus;
}
void
kgspDumpMailbox_TU102
(
OBJGPU *pGpu,
KernelGsp *pKernelGsp
)
{
NvU32 idx;
NvU32 data;
for (idx = 0; idx < NV_PGSP_MAILBOX__SIZE_1; idx++)
{
data = GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(idx));
NV_PRINTF(LEVEL_ERROR, "GSP: MAILBOX(%d) = 0x%08X\n", idx, data);
}
}
void
kgspReadEmem_TU102
(

24
src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c
View File

@@ -24,6 +24,7 @@
#include "resserv/rs_server.h"
#include "gpu/gsp/kernel_gsp.h"
#include "gpu/falcon/kernel_falcon.h"
#include "kernel/core/thread_state.h"
#include "kernel/core/locks.h"
@@ -2142,6 +2143,7 @@ _kgspLogXid119
NvU64 duration;
char durationUnitsChar;
KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu);
KernelFalcon *pKernelFlcn = staticCast(pKernelGsp, KernelFalcon);
if (pRpc->timeoutCount == 1)
{
@@ -2186,9 +2188,22 @@ _kgspLogXid119
kgspLogRpcDebugInfo(pGpu, pRpc, GSP_RPC_TIMEOUT, NV_TRUE/*bPollingForRpcResponse*/);
osAssertFailed();
//
// Dump registers / core state, non-destructively here.
// On production boards, ICD dump cannot be done because halt is final.
// Do not print this if we already consider GSP dead (prevents spam overload)
//
kgspDumpMailbox_HAL(pGpu, pKernelGsp);
kflcnCoreDumpNondestructive(pGpu, pKernelFlcn, 2);
NV_PRINTF(LEVEL_ERROR,
"********************************************************************************\n");
}
else
{
kgspDumpMailbox_HAL(pGpu, pKernelGsp); // Always dump mailboxes
kflcnCoreDumpNondestructive(pGpu, pKernelFlcn, 0); // simple version
}
}
static void
@@ -2389,8 +2404,14 @@ _kgspRpcRecvPoll
goto done;
}
//
// Today, we will soldier on if GSP times out. This can cause future issues if the action
// requested never actually occurs.
//
if (timeoutStatus == NV_ERR_TIMEOUT)
{
KernelFalcon *pKernelFlcn = staticCast(pKernelGsp, KernelFalcon);
rpcStatus = timeoutStatus;
_kgspRpcIncrementTimeoutCountAndRateLimitPrints(pGpu, pRpc);
@@ -2408,6 +2429,9 @@ _kgspRpcRecvPoll
gpuMarkDeviceForReset(pGpu);
pKernelGsp->bFatalError = NV_TRUE;
// Do a destructive ICD dump - core is unrecoverable.
kflcnCoreDumpDestructive(pGpu, pKernelFlcn);
// For Windows, if TDR is supported, trigger TDR to recover the system.
if (pGpu->getProperty(pGpu, PDB_PROP_GPU_SUPPORTS_TDR_EVENT))
{

54
src/nvidia/src/kernel/gpu/mig_mgr/arch/blackwell/kmigmgr_gb202.c
View File

@@ -123,6 +123,53 @@ kmigmgrGpuInstanceSupportVgpuTimeslice_GB202
return gfxSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE ? NV_FALSE : NV_TRUE;
}
static NvBool
s_kmigmgrIsSingleSliceConfig_GB202
(
OBJGPU *pGpu,
KernelMIGManager *pKernelMIGManager,
NvU32 gpuInstanceFlag
)
{
NvU32 computeSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, _COMPUTE_SIZE, gpuInstanceFlag);
NvU32 syspipeMask = 0;
NvBool isSingleSliceProfile = NV_FALSE;
NvU32 actualMigCount = 0;
NvU32 i;
for (i = 0; i < RM_ENGINE_TYPE_GR_SIZE; ++i)
{
if (gpuCheckEngine_HAL(pGpu, ENG_GR(i)))
{
syspipeMask |= NVBIT32(i);
}
}
actualMigCount = nvPopCount32(syspipeMask);
switch (computeSizeFlag)
{
case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF:
if (actualMigCount == 2)
{
//
// On 2 slice configurations, MINI_HALF is the smallest available partition
// QUARTER would be hidden by NVML See bug 5592609 for more details.
//
isSingleSliceProfile = NV_TRUE;
}
break;
case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER:
isSingleSliceProfile = NV_TRUE;
break;
default:
// nothing do do. default value is already initialized to NV_FALSE
break;
}
return isSingleSliceProfile;
}
/*!
* @brief Function to determine whether gpu instance flag combinations are valid
* for this GPU
@@ -138,20 +185,17 @@ kmigmgrIsGPUInstanceCombinationValid_GB202
NvU32 memSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, _MEMORY_SIZE, gpuInstanceFlag);
NvU32 computeSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, _COMPUTE_SIZE, gpuInstanceFlag);
NvU32 gfxSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, _GFX_SIZE, gpuInstanceFlag);
NvU32 smallestComputeSizeFlag;
if (!kmigmgrIsGPUInstanceFlagValid_HAL(pGpu, pKernelMIGManager, gpuInstanceFlag))
{
return NV_FALSE;
}
smallestComputeSizeFlag = kmigmgrSmallestComputeProfileSize(pGpu, pKernelMIGManager);
NV_CHECK_OR_RETURN(LEVEL_ERROR, smallestComputeSizeFlag != KMIGMGR_COMPUTE_SIZE_INVALID, NV_FALSE);
// JPG_OFA profile is only available on the smallest available partition
// JPG_OFA profile is only available on single slice GPU Instances
if (FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA, _ENABLE, gpuInstanceFlag))
{
if (computeSizeFlag != smallestComputeSizeFlag)
if (!s_kmigmgrIsSingleSliceConfig_GB202(pGpu, pKernelMIGManager, gpuInstanceFlag))
{
return NV_FALSE;
}

147
src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c
View File

@@ -374,6 +374,92 @@ gisubscriptionCanCopy_IMPL
return NV_TRUE;
}
/*!
* @brief Helper function to allocate and init KERNEL_WATCHDOG under the CI if it's GFX-capable
*/
static NV_STATUS
_gisubscriptionAllocKernelWatchdog
(
OBJGPU *pGpu,
MIG_COMPUTE_INSTANCE *pMIGComputeInstance
)
{
// Allocate watchdog channel for valid GFX-capable CI
if (pMIGComputeInstance->bValid && (pMIGComputeInstance->resourceAllocation.gfxGpcCount > 0))
{
RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
KernelRc *pKernelRc = GPU_GET_KERNEL_RC(pGpu);
RsResourceRef *pKernelWatchdogRef;
KernelWatchdog *pKernelWatchdog;
NV_PRINTF(LEVEL_INFO, "Allocating KERNEL_WATCHDOG object for CI hClient 0x%x, hSubdevice 0x%x, gfxGpcCount(%d)\n",
pMIGComputeInstance->instanceHandles.hClient,
pMIGComputeInstance->instanceHandles.hSubdevice,
pMIGComputeInstance->resourceAllocation.gfxGpcCount);
NV_ASSERT_OK_OR_RETURN(
pRmApi->AllocWithHandle(pRmApi,
pMIGComputeInstance->instanceHandles.hClient,
pMIGComputeInstance->instanceHandles.hSubdevice,
KERNEL_WATCHDOG_OBJECT_ID,
KERNEL_WATCHDOG,
NvP64_NULL,
0));
NV_ASSERT_OK_OR_RETURN(
serverutilGetResourceRefWithType(pMIGComputeInstance->instanceHandles.hClient,
KERNEL_WATCHDOG_OBJECT_ID,
classId(KernelWatchdog),
&pKernelWatchdogRef));
pKernelWatchdog = dynamicCast(pKernelWatchdogRef->pResource, KernelWatchdog);
NV_ASSERT_OR_RETURN(pKernelWatchdog != NULL, NV_ERR_INVALID_STATE);
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, krcWatchdogInit(pGpu, pKernelRc, pKernelWatchdog));
}
return NV_OK;
}
/*!
* @brief Helper function to shutdown and free KERNEL_WATCHDOG under the CI
*/
static NV_STATUS
_gisubscriptionFreeKernelWatchdog
(
OBJGPU *pGpu,
MIG_COMPUTE_INSTANCE *pMIGComputeInstance
)
{
if (pMIGComputeInstance->bValid && (pMIGComputeInstance->resourceAllocation.gfxGpcCount > 0))
{
RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
RsResourceRef *pKernelWatchdogRef;
KernelRc *pKernelRc = GPU_GET_KERNEL_RC(pGpu);
KernelWatchdog *pKernelWatchdog;
NV_PRINTF(LEVEL_INFO, "Freeing KERNEL_WATCHDOG object for CI hClient 0x%x, gfxGpcCount(%d)\n",
pMIGComputeInstance->instanceHandles.hClient,
pMIGComputeInstance->resourceAllocation.gfxGpcCount);
NV_ASSERT_OK_OR_RETURN(
serverutilGetResourceRefWithType(pMIGComputeInstance->instanceHandles.hClient,
KERNEL_WATCHDOG_OBJECT_ID,
classId(KernelWatchdog),
&pKernelWatchdogRef));
pKernelWatchdog = dynamicCast(pKernelWatchdogRef->pResource, KernelWatchdog);
NV_ASSERT_OR_RETURN(pKernelWatchdog != NULL, NV_ERR_INVALID_STATE);
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, krcWatchdogShutdown(pGpu, pKernelRc, pKernelWatchdog));
pRmApi->Free(pRmApi, pMIGComputeInstance->instanceHandles.hClient, KERNEL_WATCHDOG_OBJECT_ID);
}
return NV_OK;
}
//
// gisubscriptionCtrlCmdExecPartitionsCreate
//
@@ -564,36 +650,7 @@ gisubscriptionCtrlCmdExecPartitionsCreate_IMPL
{
for (i = 0; i < pParams->execPartCount; i++)
{
MIG_COMPUTE_INSTANCE *pMIGComputeInstance = &pKernelMIGGpuInstance->MIGComputeInstance[pParams->execPartId[i]];
// Allocate watchdog channel for each valid GFX-capable CI
if (pMIGComputeInstance->bValid && (pMIGComputeInstance->resourceAllocation.gfxGpcCount > 0))
{
RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
KernelRc *pKernelRc = GPU_GET_KERNEL_RC(pGpu);
RsResourceRef *pKernelWatchdogRef;
KernelWatchdog *pKernelWatchdog;
NV_ASSERT_OK_OR_RETURN(
pRmApi->AllocWithHandle(pRmApi,
pMIGComputeInstance->instanceHandles.hClient,
pMIGComputeInstance->instanceHandles.hSubdevice,
KERNEL_WATCHDOG_OBJECT_ID,
KERNEL_WATCHDOG,
NvP64_NULL,
0));
NV_ASSERT_OK_OR_RETURN(
serverutilGetResourceRefWithType(pMIGComputeInstance->instanceHandles.hClient,
KERNEL_WATCHDOG_OBJECT_ID,
classId(KernelWatchdog),
&pKernelWatchdogRef));
pKernelWatchdog = dynamicCast(pKernelWatchdogRef->pResource, KernelWatchdog);
NV_ASSERT_OR_RETURN(pKernelWatchdog != NULL, NV_ERR_INVALID_STATE);
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, krcWatchdogInit(pGpu, pKernelRc, pKernelWatchdog));
}
NV_ASSERT_OK_OR_RETURN(_gisubscriptionAllocKernelWatchdog(pGpu, &pKernelMIGGpuInstance->MIGComputeInstance[pParams->execPartId[i]]));
}
}
@@ -688,31 +745,11 @@ gisubscriptionCtrlCmdExecPartitionsDelete_IMPL
for (execPartIdx = 0; execPartIdx < pParams->execPartCount; ++execPartIdx)
{
KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu);
if (gpuIsClassSupported(pGpu, KERNEL_WATCHDOG) &&
!(IS_GSP_CLIENT(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)))
{
RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
MIG_COMPUTE_INSTANCE *pMIGComputeInstance = &pKernelMIGGpuInstance->MIGComputeInstance[pParams->execPartId[execPartIdx]];
if (pMIGComputeInstance->bValid && (pMIGComputeInstance->resourceAllocation.gfxGpcCount > 0))
{
KernelRc *pKernelRc = GPU_GET_KERNEL_RC(pGpu);
RsResourceRef *pKernelWatchdogRef;
KernelWatchdog *pKernelWatchdog;
NV_ASSERT_OK_OR_RETURN(
serverutilGetResourceRefWithType(pMIGComputeInstance->instanceHandles.hClient,
KERNEL_WATCHDOG_OBJECT_ID,
classId(KernelWatchdog),
&pKernelWatchdogRef));
pKernelWatchdog = dynamicCast(pKernelWatchdogRef->pResource, KernelWatchdog);
NV_ASSERT_OR_RETURN(pKernelWatchdog != NULL, NV_ERR_INVALID_STATE);
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, krcWatchdogShutdown(pGpu, pKernelRc, pKernelWatchdog));
pRmApi->Free(pRmApi, pMIGComputeInstance->instanceHandles.hClient, KERNEL_WATCHDOG_OBJECT_ID);
}
NV_ASSERT_OK_OR_RETURN(_gisubscriptionFreeKernelWatchdog(pGpu, &pKernelMIGGpuInstance->MIGComputeInstance[pParams->execPartId[execPartIdx]]));
}
if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu))
@@ -1078,6 +1115,12 @@ gisubscriptionCtrlCmdExecPartitionsImport_IMPL
}
}
if (gpuIsClassSupported(pGpu, KERNEL_WATCHDOG) &&
!(IS_GSP_CLIENT(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)))
{
NV_ASSERT_OK_OR_GOTO(status, _gisubscriptionAllocKernelWatchdog(pGpu, &pGPUInstance->MIGComputeInstance[pParams->id]), cleanup_rpc);
}
return NV_OK;
cleanup_rpc:

1
src/nvidia/srcs.mk
View File

@@ -478,6 +478,7 @@ SRCS += src/kernel/gpu/external_device/kern_external_device.c
SRCS += src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga100.c
SRCS += src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c
SRCS += src/kernel/gpu/falcon/arch/blackwell/kernel_falcon_gb100.c
SRCS += src/kernel/gpu/falcon/arch/blackwell/kernel_falcon_gb202.c
SRCS += src/kernel/gpu/falcon/arch/turing/kernel_crashcat_engine_tu102.c
SRCS += src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c
SRCS += src/kernel/gpu/falcon/kernel_crashcat_engine.c