NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-05-20 04:19:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

590.48.01

Browse Source
This commit is contained in:
Maneet Singh
2025-12-18 09:16:33 -08:00
parent a5bfb10e75
commit 2ccbad25e1
51 changed files with 2054 additions and 359 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r591_37
#define NV_BUILD_BRANCH r591_47
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r591_37
#define NV_PUBLIC_BRANCH r591_47
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r590/r591_37-155"
#define NV_BUILD_CHANGELIST_NUM (36926008)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r590/r591_47-174"
#define NV_BUILD_CHANGELIST_NUM (37007394)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r590/r591_37-155"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36926008)
#define NV_BUILD_NAME "rel/gpu_drv/r590/r591_47-174"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37007394)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r591_37-1"
#define NV_BUILD_CHANGELIST_NUM (36926008)
#define NV_BUILD_BRANCH_VERSION "r591_47-1"
#define NV_BUILD_CHANGELIST_NUM (37007394)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "591.38"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36926008)
#define NV_BUILD_NAME "591.51"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37007394)
#define NV_BUILD_BRANCH_BASE_VERSION R590
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -5,7 +5,7 @@
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) || \
defined(NV_DCECORE)
#define NV_VERSION_STRING "590.44.01"
#define NV_VERSION_STRING "590.48.01"
#else

23
src/common/inc/swref/published/ampere/ga102/dev_riscv_pri.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,10 +27,31 @@
#define NV_FALCON2_GSP_BASE 0x00111000
#define NV_PRISCV_RISCV_IRQMASK 0x00000528 /* R-I4R */
#define NV_PRISCV_RISCV_IRQDEST 0x0000052c /* RW-4R */
#define NV_PRISCV_RISCV_IRQDELEG 0x00000534 /* RWI4R */
#define NV_PRISCV_RISCV_RPC 0x000003ec /* R--4R */
#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RWI4R */
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */
#define NV_PRISCV_RISCV_ICD_CMD 0x000003d0 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_ADDR0 0x000003d4 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_ADDR1 0x000003d8 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_RDATA0 0x000003e4 /* R--4R */
#define NV_PRISCV_RISCV_ICD_RDATA1 0x000003e8 /* R--4R */
#define NV_PRISCV_RISCV_TRACECTL 0x00000400 /* RW-4R */
#define NV_PRISCV_RISCV_TRACECTL_FULL 30:30 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX 0x00000404 /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_RDIDX_RDIDX 7:0 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX_MAXIDX 23:16 /* R-IVF */
#define NV_PRISCV_RISCV_TRACE_WTIDX 0x00000408 /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_WTIDX_WTIDX 31:24 /* RWIVF */
#define NV_PRISCV_RISCV_TRACEPC_HI 0x00000410 /* RW-4R */
#define NV_PRISCV_RISCV_TRACEPC_LO 0x0000040c /* RW-4R */
#define NV_PRISCV_RISCV_PRIV_ERR_STAT 0x00000500 /* RWI4R */
#define NV_PRISCV_RISCV_PRIV_ERR_INFO 0x00000504 /* R-I4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR 0x00000508 /* R-I4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI 0x0000050c /* R-I4R */
#define NV_PRISCV_RISCV_HUB_ERR_STAT 0x00000510 /* RWI4R */
#define NV_PRISCV_RISCV_BCR_CTRL 0x00000668 /* RWI4R */
#define NV_PRISCV_RISCV_BCR_CTRL_VALID 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_BCR_CTRL_VALID_TRUE 0x00000001 /* R---V */

38
src/common/inc/swref/published/blackwell/gb202/dev_riscv_pri.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_dev_riscv_pri_h__
#define __gb202_dev_riscv_pri_h__
#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RW-4R */
#define NV_PRISCV_RISCV_RPC 0x000003ec /* R--4R */
#define NV_PRISCV_RISCV_IRQDELEG 0x00000534 /* RW-4R */
#define NV_PRISCV_RISCV_IRQDEST 0x0000052c /* RW-4R */
#define NV_PRISCV_RISCV_IRQMASK 0x00000528 /* R--4R */
#define NV_PRISCV_RISCV_PRIV_ERR_STAT 0x00000420 /* RW-4R */
#define NV_PRISCV_RISCV_PRIV_ERR_INFO 0x00000424 /* R--4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR 0x00000428 /* R--4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI 0x0000042c /* R--4R */
#define NV_PRISCV_RISCV_HUB_ERR_STAT 0x00000430 /* RW-4R */
#endif // __gb202_dev_riscv_pri_h__

1
src/common/inc/swref/published/turing/tu102/dev_falcon_v4.h
View File

@@ -33,6 +33,7 @@
#define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-XVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMODE 0x0000000c /* RW-4R */
#define NV_PFALCON_FALCON_IRQMSET 0x00000010 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMCLR 0x00000014 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */

7
src/common/inc/swref/published/turing/tu102/dev_fbif_v4.h
View File

@@ -30,8 +30,15 @@
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_INSTBLK 0x00000020 /* R--4R */
#define NV_PFALCON_FBIF_CTL 0x00000024 /* RW-4R */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_THROTTLE 0x0000002c /* RW-4R */
#define NV_PFALCON_FBIF_ACHK_BLK(i) (0x00000030+(i)*8) /* RW-4A */
#define NV_PFALCON_FBIF_ACHK_BLK__SIZE_1 2 /* */
#define NV_PFALCON_FBIF_ACHK_CTL(i) (0x00000034+(i)*8) /* RW-4A */
#define NV_PFALCON_FBIF_ACHK_CTL__SIZE_1 2 /* */
#define NV_PFALCON_FBIF_CG1 0x00000074 /* RW-4R */
#endif // __tu102_dev_fbif_v4_h__

35
src/common/inc/swref/published/turing/tu102/dev_riscv_pri.h
View File

@@ -28,7 +28,42 @@
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS 0x00000240 /* R-I4R */
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS_ACTIVE_STAT 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_CPUCTL 0x00000268 /* RWI4R */
#define NV_PRISCV_RISCV_IRQMASK 0x000002b4 /* R-I4R */
#define NV_PRISCV_RISCV_IRQDEST 0x000002b8 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_CMD 0x00000300 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_CMD_OPC 4:0 /* RW-VF */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_STOP 0x00000000 /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RCSR 0x00000010 /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RPC 0x00000012 /* RW--V */
#define NV_PRISCV_RISCV_ICD_CMD_SZ 7:6 /* RW-VF */
#define NV_PRISCV_RISCV_ICD_CMD_IDX 12:8 /* RW-VF */
#define NV_PRISCV_RISCV_ICD_CMD_ERROR 14:14 /* R-IVF */
#define NV_PRISCV_RISCV_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_ICD_CMD_ERROR_FALSE 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_ICD_CMD_BUSY 15:15 /* R-IVF */
#define NV_PRISCV_RISCV_ICD_CMD_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_ICD_CMD_BUSY_TRUE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_ICD_CMD_PARM 31:16 /* RW-VF */
#define NV_PRISCV_RISCV_ICD_RDATA0 0x0000030c /* R--4R */
#define NV_PRISCV_RISCV_ICD_RDATA1 0x00000318 /* R--4R */
#define NV_PRISCV_RISCV_ICD_ADDR0 0x00000304 /* RW-4R */
#define NV_PRISCV_RISCV_ICD_ADDR1 0x00000310 /* RW-4R */
#define NV_PRISCV_RISCV_TRACECTL 0x00000344 /* RW-4R */
#define NV_PRISCV_RISCV_TRACECTL_FULL 30:30 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX 0x00000348 /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_RDIDX_RDIDX 7:0 /* RWIVF */
#define NV_PRISCV_RISCV_TRACE_RDIDX_MAXIDX 23:16 /* R-IVF */
#define NV_PRISCV_RISCV_TRACE_WTIDX 0x0000034c /* RW-4R */
#define NV_PRISCV_RISCV_TRACE_WTIDX_WTIDX 31:24 /* RWIVF */
#define NV_PRISCV_RISCV_TRACEPC_HI 0x00000350 /* RW-4R */
#define NV_PRISCV_RISCV_TRACEPC_LO 0x00000354 /* RW-4R */
#define NV_PRISCV_RISCV_PRIV_ERR_STAT 0x00000360 /* RWI4R */
#define NV_PRISCV_RISCV_PRIV_ERR_INFO 0x00000364 /* R-I4R */
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR 0x00000368 /* R-I4R */
#define NV_PRISCV_RISCV_HUB_ERR_STAT 0x0000036c /* RWI4R */
#endif // __tu102_dev_riscv_pri_h__

37
src/common/modeset/hdmipacket/nvhdmipkt_C671.c
View File

@@ -1136,17 +1136,9 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
NvU32 bppMinX16Itr, bppMaxX16Itr;
NvBool bHasPreCalcFRLData = NV_FALSE;
NvBool forceFRLRateDSC = pClientCtrl->forceFRLRate;
HDMI_FRL_DATA_RATE requestedFRLRate = pClientCtrl->frlRate;
#if defined(NVHDMIPKT_NVKMS)
NvU32 rr = (pVidTransInfo->pTiming->pclk * (NvU64)10000) /
(pVidTransInfo->pTiming->HTotal * (NvU64)pVidTransInfo->pTiming->VTotal);
if (!pVidTransInfo->pTiming->interlaced && (rr >= 480)) {
forceFRLRateDSC = NV_TRUE;
requestedFRLRate = dscMaxFRLRate;
}
NvU32 hVisible, vVisible, rr;
NvBool clampBpp;
#endif
// DSC_All_bpp = 1:
@@ -1256,16 +1248,16 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
frlParams.compressionInfo.hSlices = NV_UNSIGNED_DIV_CEIL(pVidTransInfo->pTiming->HVisible, pClientCtrl->sliceWidth);
}
if (forceFRLRateDSC)
if (pClientCtrl->forceFRLRate)
{
if (requestedFRLRate > dscMaxFRLRate)
if (pClientCtrl->frlRate > dscMaxFRLRate)
{
result = NVHDMIPKT_FAIL;
goto frlQuery_fail;
}
minFRLRateItr = requestedFRLRate;
maxFRLRateItr = requestedFRLRate;
minFRLRateItr = pClientCtrl->frlRate;
maxFRLRateItr = pClientCtrl->frlRate;
}
if (pClientCtrl->forceBppx16)
@@ -1274,6 +1266,23 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis,
bppMaxX16Itr = pClientCtrl->bitsPerPixelX16;
}
#if defined(NVHDMIPKT_NVKMS)
hVisible = pVidTransInfo->pTiming->HVisible;
vVisible = pVidTransInfo->pTiming->VVisible;
rr = (pVidTransInfo->pTiming->pclk * (NvU64)10000) /
(pVidTransInfo->pTiming->HTotal * (NvU64)pVidTransInfo->pTiming->VTotal);
clampBpp = ((rr >= 480) || ((rr >= 165) && (hVisible == 5120) && (vVisible == 2160))) &&
(!pVidTransInfo->pTiming->interlaced) &&
(bppMinX16Itr <= 8 * 16) &&
(bppMaxX16Itr >= 8 * 16);
if (clampBpp) {
bppMaxX16Itr = 8 * 16;
}
#endif
// Determine Primary Compressed Format
// First determine the FRL rate at which video transport is possible even at bppMin
// Then iterate over bppTarget - start at max n decrement until we hit bppMin. The max bpp for which

4
src/common/modeset/timing/nvt_gtf.c
View File

@@ -103,6 +103,7 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
// A proper way to calculate fixed HTotal*VTotal*Rr/10000
pT->pclk = axb_div_c(dwHTCells*dwVTotal, dwRefreshRate, 10000/NVT_GTF_CELL_GRAN);
pT->pclk1khz = pT->pclk * 10;
pT->HSyncPol = NVT_H_SYNC_NEGATIVE;
pT->VSyncPol = NVT_V_SYNC_POSITIVE;
@@ -111,7 +112,7 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
// fill in the extra timing info
pT->etc.flag = 0;
pT->etc.rr = (NvU16)rr;
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk, (NvU32)10000*(NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal);
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk1khz, (NvU32)1000*(NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal);
pT->etc.aspect = 0;
pT->etc.rep = 0x1;
pT->etc.status = NVT_STATUS_GTF;
@@ -128,6 +129,7 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
pT->interlaced = NVT_INTERLACED_NO_EXTRA_VBLANK_ON_FIELD2;
pT->pclk >>= 1;
pT->pclk1khz >>= 1;
pT->VTotal >>= 1;
pT->VVisible = (pT->VVisible + 1) / 2;
}

4
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -813,6 +813,9 @@ typedef struct NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS {
* productId (in)
* Specifies the product ID of panel obtained from the EDID. This
* parameter is expected to be non-zero only in case of internal panel.
* tconId (out)
* RM provides an enumerated TCON specific value to help the client
* identify the panel TCON. Clients can refer to the enum from sdk/nvidia/inc/dds_tcon_db.h
*
* Possible status values returned are:
* NV_OK
@@ -830,6 +833,7 @@ typedef struct NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS {
NvU32 displayId;
NvU16 manfId;
NvU16 productId;
NvU16 tconId;
} NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS;