mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-01-30 21:19:49 +00:00
580.65.06
This commit is contained in:
@@ -1,5 +1,5 @@
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/*******************************************************************************
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Copyright (c) 2015-2024 NVIDIA Corporation
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Copyright (c) 2015-2025 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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@@ -208,7 +208,9 @@ static uvm_hal_class_ops_t host_table[] =
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.write_gpu_put = uvm_hal_maxwell_host_write_gpu_put,
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.tlb_invalidate_all = uvm_hal_maxwell_host_tlb_invalidate_all_a16f,
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.tlb_invalidate_va = uvm_hal_maxwell_host_tlb_invalidate_va,
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.tlb_invalidate_phys = uvm_hal_maxwell_host_tlb_invalidate_phys_unsupported,
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.tlb_invalidate_test = uvm_hal_maxwell_host_tlb_invalidate_test,
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.tlb_flush_prefetch = uvm_hal_maxwell_host_tlb_flush_prefetch_unsupported,
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.replay_faults = uvm_hal_maxwell_replay_faults_unsupported,
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.cancel_faults_global = uvm_hal_maxwell_cancel_faults_global_unsupported,
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.cancel_faults_targeted = uvm_hal_maxwell_cancel_faults_targeted_unsupported,
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@@ -219,6 +221,7 @@ static uvm_hal_class_ops_t host_table[] =
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.access_counter_clear_all = uvm_hal_maxwell_access_counter_clear_all_unsupported,
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.access_counter_clear_targeted = uvm_hal_maxwell_access_counter_clear_targeted_unsupported,
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.access_counter_query_clear_op = uvm_hal_maxwell_access_counter_query_clear_op_unsupported,
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.l2_invalidate_noncoh_sysmem = uvm_hal_host_l2_invalidate_noncoh_sysmem_unsupported,
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.get_time = uvm_hal_maxwell_get_time,
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}
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},
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@@ -309,7 +312,10 @@ static uvm_hal_class_ops_t host_table[] =
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.u.host_ops = {
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.tlb_invalidate_all = uvm_hal_blackwell_host_tlb_invalidate_all,
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.tlb_invalidate_va = uvm_hal_blackwell_host_tlb_invalidate_va,
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.tlb_invalidate_phys = uvm_hal_blackwell_host_tlb_invalidate_phys,
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.tlb_invalidate_test = uvm_hal_blackwell_host_tlb_invalidate_test,
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.tlb_flush_prefetch = uvm_hal_blackwell_host_tlb_flush_prefetch,
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.l2_invalidate_noncoh_sysmem = uvm_hal_blackwell_host_l2_invalidate_noncoh_sysmem,
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.access_counter_query_clear_op = uvm_hal_blackwell_access_counter_query_clear_op_gb100,
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}
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},
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@@ -905,12 +911,6 @@ static void hal_override_properties(uvm_parent_gpu_t *parent_gpu)
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// TODO: Bug 200692962: Add support for access counters in vGPU
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if ((parent_gpu->virt_mode != UVM_VIRT_MODE_NONE) || g_uvm_global.conf_computing_enabled)
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parent_gpu->access_counters_supported = false;
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// TODO: Bug 4637114: [UVM] Remove support for physical access counter
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// notifications. Always set to false, until we remove the PMM reverse
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// mapping code.
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parent_gpu->access_counters_can_use_physical_addresses = false;
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}
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void uvm_hal_init_properties(uvm_parent_gpu_t *parent_gpu)
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@@ -977,9 +977,28 @@ uvm_membar_t uvm_hal_downgrade_membar_type(uvm_gpu_t *gpu, bool is_local_vidmem)
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return UVM_MEMBAR_SYS;
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}
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void uvm_hal_tlb_invalidate_phys(uvm_push_t *push, uvm_dma_map_invalidation_t inval_type)
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{
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uvm_parent_gpu_t *parent = uvm_push_get_gpu(push)->parent;
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switch (inval_type) {
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case UVM_DMA_MAP_INVALIDATION_FLUSH:
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parent->host_hal->tlb_flush_prefetch(push);
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break;
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case UVM_DMA_MAP_INVALIDATION_FULL:
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parent->host_hal->tlb_invalidate_phys(push);
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break;
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default:
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UVM_ASSERT(inval_type == UVM_DMA_MAP_INVALIDATION_NONE);
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break;
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}
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}
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const char *uvm_aperture_string(uvm_aperture_t aperture)
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{
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BUILD_BUG_ON(UVM_APERTURE_MAX != 12);
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BUILD_BUG_ON(UVM_APERTURE_MAX != 13);
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switch (aperture) {
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UVM_ENUM_STRING_CASE(UVM_APERTURE_PEER_0);
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@@ -992,6 +1011,7 @@ const char *uvm_aperture_string(uvm_aperture_t aperture)
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UVM_ENUM_STRING_CASE(UVM_APERTURE_PEER_7);
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UVM_ENUM_STRING_CASE(UVM_APERTURE_PEER_MAX);
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UVM_ENUM_STRING_CASE(UVM_APERTURE_SYS);
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UVM_ENUM_STRING_CASE(UVM_APERTURE_SYS_NON_COHERENT);
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UVM_ENUM_STRING_CASE(UVM_APERTURE_VID);
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UVM_ENUM_STRING_CASE(UVM_APERTURE_DEFAULT);
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UVM_ENUM_STRING_DEFAULT();
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@@ -1121,6 +1141,18 @@ void uvm_hal_print_access_counter_buffer_entry(const uvm_access_counter_buffer_e
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UVM_DBG_PRINT(" tag %x\n", entry->tag);
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}
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const char *uvm_dma_map_invalidation_string(uvm_dma_map_invalidation_t inval_type)
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{
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BUILD_BUG_ON(UVM_DMA_MAP_INVALIDATION_COUNT != 3);
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switch (inval_type) {
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UVM_ENUM_STRING_CASE(UVM_DMA_MAP_INVALIDATION_NONE);
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UVM_ENUM_STRING_CASE(UVM_DMA_MAP_INVALIDATION_FLUSH);
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UVM_ENUM_STRING_CASE(UVM_DMA_MAP_INVALIDATION_FULL);
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UVM_ENUM_STRING_DEFAULT();
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}
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}
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bool uvm_hal_method_is_valid_stub(uvm_push_t *push, NvU32 method_address, NvU32 method_data)
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{
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return true;
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@@ -1129,3 +1161,11 @@ bool uvm_hal_method_is_valid_stub(uvm_push_t *push, NvU32 method_address, NvU32
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void uvm_hal_ce_memcopy_patch_src_stub(uvm_push_t *push, uvm_gpu_address_t *src)
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{
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}
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void uvm_hal_host_l2_invalidate_noncoh_sysmem_unsupported(uvm_push_t *push)
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{
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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UVM_ERR_PRINT("L2 cache invalidation: Called on unsupported GPU %s (arch: 0x%x, impl: 0x%x)\n",
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uvm_gpu_name(gpu), gpu->parent->rm_info.gpuArch, gpu->parent->rm_info.gpuImplementation);
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UVM_ASSERT_MSG(false, "host l2_invalidate_noncoh_sysmem called on unsupported GPU\n");
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}
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