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580.65.06

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This commit is contained in:
Maneet Singh
2025-08-04 11:15:02 -07:00
parent d890313300
commit 307159f262
1315 changed files with 477791 additions and 279973 deletions
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22
src/common/inc/nvBldVer.h
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@@ -36,26 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r576_76
#define NV_BUILD_BRANCH r580_78
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r576_76
#define NV_PUBLIC_BRANCH r580_78
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r575/r576_76-215"
#define NV_BUILD_CHANGELIST_NUM (36268588)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/r580_78-179"
#define NV_BUILD_CHANGELIST_NUM (36308443)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r575/r576_76-215"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36268588)
#define NV_BUILD_NAME "rel/gpu_drv/r580/r580_78-179"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36308443)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r576_76-8"
#define NV_BUILD_CHANGELIST_NUM (36246141)
#define NV_BUILD_BRANCH_VERSION "r580_78-7"
#define NV_BUILD_CHANGELIST_NUM (36308443)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "577.00"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36246141)
#define NV_BUILD_BRANCH_BASE_VERSION R575
#define NV_BUILD_NAME "580.88"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36308443)
#define NV_BUILD_BRANCH_BASE_VERSION R580
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "575.64.05"
#define NV_VERSION_STRING "580.65.06"
#else

3
src/common/inc/nvVer.h
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@@ -7,7 +7,8 @@
#define NV_COPYRIGHT "(C) " NV_COPYRIGHT_YEAR " NVIDIA Corporation. All rights reserved." // Please do not use the non-ascii copyright symbol for (C).
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) || \
defined(NV_DCECORE)
// All Version numbering for Unix builds has moved. (Source should be re-directed to directly include that header.)
#include "nvUnixVersion.h"

44
src/common/inc/swref/common_def_nvlink.h Normal file
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@@ -0,0 +1,44 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef COMMON_DEF_NVLINK_H
#define COMMON_DEF_NVLINK_H
//
// Arch CONNECTION defines, replaces forceconfig. See Bugs 1665737,
// 1665734 and 1734252.
// This per link connection state is passed up from chiplib
// and can be controlled on the command line.
// The max number of connections is speced in __SIZE_1.
//
#define NV_NVLINK_ARCH_CONNECTION 31:0
#define NV_NVLINK_ARCH_CONNECTION__SIZE_1 32
#define NV_NVLINK_ARCH_CONNECTION_DISABLED 0x00000000
#define NV_NVLINK_ARCH_CONNECTION_PEER_MASK 7:0
#define NV_NVLINK_ARCH_CONNECTION_ENABLED 8:8
#define NV_NVLINK_ARCH_CONNECTION_PHYSICAL_LINK 21:16
#define NV_NVLINK_ARCH_CONNECTION_RESERVED 29:20
#define NV_NVLINK_ARCH_CONNECTION_PEERS_COMPUTE_ONLY 30:30
#define NV_NVLINK_ARCH_CONNECTION_CPU 31:31
#endif // COMMON_DEF_NVLINK_H

71
src/common/inc/swref/published/ada/ad102/dev_nv_pcfg_xve_regmap.h Normal file
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@@ -0,0 +1,71 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __dev_nv_pcfg_xve_regmap_h__
#define __dev_nv_pcfg_xve_regmap_h__
#define NV_PCFG_XVE_REGISTER_MAP_START_OFFSET 0x00088000
/*
* <prefix>_MAP has 1 bit set for each dword register.
* <prefix>_COUNT has total number of set bits in <prefix>_MAP.
*/
#define NV_PCFG_XVE_REGISTER_VALID_COUNT 474
#define NV_PCFG_XVE_REGISTER_VALID_MAP { \
/* 0x00088000 */ 0xFFF1FFFF, 0x101FFF9F, \
/* 0x00088100 */ 0x3FFA3C7F, 0x00000000, \
/* 0x00088200 */ 0x03F00000, 0x00000000, \
/* 0x00088300 */ 0x00000000, 0x00000000, \
/* 0x00088400 */ 0x8007FFC0, 0x3F3F5807, \
/* 0x00088500 */ 0x000000BF, 0x00000000, \
/* 0x00088600 */ 0x0140AA1F, 0x00000000, \
/* 0x00088700 */ 0x00013FFF, 0x00000000, \
/* 0x00088800 */ 0xFFEFDFD7, 0x1EDAFFFF, \
/* 0x00088900 */ 0xFFFFFFFF, 0x006FFFFF, \
/* 0x00088A00 */ 0xFF7FFFFF, 0x0007FFFF, \
/* 0x00088B00 */ 0x00000000, 0xFFFFF000, \
/* 0x00088C00 */ 0x0007BFE7, 0xFFC003FC, \
/* 0x00088D00 */ 0xFFFFFFFF, 0x7C1F3FFF, \
/* 0x00088E00 */ 0xFFFFFFFF, 0x00FFFFFF, \
/* 0x00088F00 */ 0x00000000, 0xFF000000 }
#define NV_PCFG_XVE_REGISTER_WR_COUNT 352
#define NV_PCFG_XVE_REGISTER_WR_MAP { \
/* 0x00088000 */ 0x3EF193FA, 0x1007C505, \
/* 0x00088100 */ 0x3FFA0828, 0x00000000, \
/* 0x00088200 */ 0x03200000, 0x00000000, \
/* 0x00088300 */ 0x00000000, 0x00000000, \
/* 0x00088400 */ 0x80007EC0, 0x3F075007, \
/* 0x00088500 */ 0x000000BF, 0x00000000, \
/* 0x00088600 */ 0x0140AA10, 0x00000000, \
/* 0x00088700 */ 0x00013FFF, 0x00000000, \
/* 0x00088800 */ 0x004C5FC3, 0x1C5AFFC0, \
/* 0x00088900 */ 0xFFFC7804, 0x006FFFFF, \
/* 0x00088A00 */ 0xFF7FFDFD, 0x00007FFF, \
/* 0x00088B00 */ 0x00000000, 0xF8A54000, \
/* 0x00088C00 */ 0x00003C01, 0x3FC003FC, \
/* 0x00088D00 */ 0xFFFFFFFC, 0x701B2C3F, \
/* 0x00088E00 */ 0xFFFFFFF8, 0x00FFBFFF, \
/* 0x00088F00 */ 0x00000000, 0xFF000000 }
#endif // {__dev_nv_pcfg_xve_regmap_h__}

38
src/common/inc/swref/published/ampere/ga100/dev_top_addendum.h Normal file
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@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_top_addendum_h__
#define __ga100_dev_top_addendum_h__
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_GRAPHICS NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_GRAPHICS
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_NVDEC NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_NVDEC
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_NVENC NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_NVENC
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_NVJPG NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_NVJPG
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_OFA NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_OFA
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_SEC NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_SEC
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_LCE NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_LCE
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_GSP NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_GSP
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_IOCTRL NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_IOCTRL
#define NV_PTOP_ZB_DEVICE_INFO_DEV_TYPE_ENUM_FLA NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_FLA
#endif // __ga100_dev_top_addendum_h__

3
src/common/inc/swref/published/blackwell/gb100/dev_gsp.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -38,6 +38,7 @@
#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_ASSERTED 0x00000000 /* R-E-V */
#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_DEASSERTED 0x00000002 /* R---V */
#define NV_PGSP_MAILBOX(i) (0x110804+(i)*4) /* RW-4A */
#define NV_PGSP_MAILBOX__SIZE_1 4 /* */
#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMC__SIZE_1 8 /* */
#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */

30
src/common/inc/swref/published/blackwell/gb100/dev_oob_pri.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_oob_pri_h__
#define __gb100_dev_oob_pri_h__
#define NV_POOBHUB_RCV_INDIRECT_CMS2_MEM_RD_ADDR 0x008aa374 /* RW-4R */
#define NV_POOBHUB_RCV_INDIRECT_CMS2_MEM_RD_DATA 0x008aa378 /* R--4R */
#endif // __gb100_dev_oob_pri_h__

59
src/common/inc/swref/published/blackwell/gb100/dev_vm.h
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@@ -40,29 +40,24 @@
#define NV_VIRTUAL_FUNCTION_PHYS_OFFSET_REGION0 0x00BBFFFF:0x00B80000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_PHYS_OFFSET_REGION1 0x00DBFFFF:0x00D80000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE 0x00000F10 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE__VFALIAS NV_XAL_EP_FUNC_L2_SYSMEM_INVALIDATE(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_TOKEN (31-1):0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED 0x00000F14 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED__VFALIAS NV_XAL_EP_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_TOKEN (31-1):0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_STATUS 31:31 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_STATUS_IDLE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_STATUS_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE 0x00000F18 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE__VFALIAS NV_XAL_EP_FUNC_L2_PEERMEM_INVALIDATE(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_TOKEN (31-1):0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED 0x00000F1C /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED__VFALIAS NV_XAL_EP_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_TOKEN (31-1):0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_STATUS 31:31 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_STATUS_IDLE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_STATUS_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR 0x00000F70 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR__VFALIAS NV_XAL_EP_FUNC_BAR2_BLOCK_LOW_ADDR(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MAP 31:10 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING 0:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
@@ -81,7 +76,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP(i) (0x1600+(i)*4) /* R--4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__VFALIAS NV_CTRL_CPU_INTR_TOP(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_VALUE 31:0 /* R--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE__SIZE_1 64 /* */
@@ -89,7 +83,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_NOT_PENDING 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(i) (0x1608+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__VFALIAS NV_CTRL_CPU_INTR_TOP_EN_SET(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE(i) (i) /* */
@@ -99,7 +92,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_DISABLED 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(i) (0x1610+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__VFALIAS NV_CTRL_CPU_INTR_TOP_EN_CLEAR(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE(i) (i) /* */
@@ -109,17 +101,14 @@
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLED 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(i) (0x1000+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 16 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__VFALIAS NV_CTRL_CPU_INTR_LEAF((16*f)+i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(i) (0x1200+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1 16 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__VFALIAS NV_CTRL_CPU_INTR_LEAF_EN_SET((16*f)+i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(i) (0x1400+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 16 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__VFALIAS NV_CTRL_CPU_INTR_LEAF_EN_CLEAR((16*f)+i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_PFB_VECTOR 141 /* */
@@ -138,14 +127,11 @@
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_PRIV_RING_VECTOR 158 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_PTIMER_ALARM_VECTOR 159 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER 0x00001640 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER__VFALIAS NV_CTRL_CPU_INTR_LEAF_TRIGGER(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -WXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH(i) (0x2100+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH__SIZE_1 16 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH__VFALIAS NV_CTRL_MAILBOX_SCRATCH(f*16+i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH_DATA 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL__VFALIAS NV_CTRL_VF_PRIV_DOORBELL(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL_HANDLE 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL_VECTOR 11:0 /* -WXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL_RSVD 30:12 /* -WXVF */
@@ -154,7 +140,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL_CPU_NOTIFICATION_FALSE 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER(i) (0x2300+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER__VFALIAS NV_PTIMER_VF_TIMER(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER_NSEC 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER_USEC 31:10 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER_USEC_INIT 0x0 /* RWI-V */
@@ -162,7 +147,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_REPLAY_FAULT_BUFFER 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(i) (0x00003000+(i)*32) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO__VFALIAS NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_ADDR_MODE 0:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_ADDR_MODE_VIRTUAL 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_ADDR_MODE_PHYSICAL 0x00000001 /* RW--V */
@@ -174,11 +158,9 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_ADDR 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_HI(i) (0x00003004+(i)*32) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_HI__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_HI__VFALIAS NV_PFB_PRI_MMU_FAULT_BUFFER_HI_VIRT(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_HI_ADDR 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET(i) (0x00003008+(i)*32) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET__VFALIAS NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_PTR 19:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_PTR_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED 30:30 /* RWEVF */
@@ -191,7 +173,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_OVERFLOW_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT(i) (0x0000300C+(i)*32) /* R--4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT__VFALIAS NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_PTR 19:0 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_PTR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED 30:30 /* R-EVF */
@@ -202,7 +183,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE(i) (0x00003010+(i)*32) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE__VFALIAS NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */
@@ -215,12 +195,10 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL__VFALIAS NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL_PRF_FILTER 1:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_ALL 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_NONE 0x00000003 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO 0x00003080 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO__VFALIAS NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE 1:0 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE_LOCAL 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE_PEER 0x00000001 /* R---V */
@@ -229,11 +207,9 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO_ADDR 31:12 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO_ADDR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI 0x00003084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI__VFALIAS NV_PFB_PRI_MMU_FAULT_ADDR_HI_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI_ADDR 31:0 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI_ADDR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO 0x00003088 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO__VFALIAS NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_ENGINE_ID 8:0 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_ENGINE_ID_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_APERTURE 11:10 /* R-EVF */
@@ -244,11 +220,9 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_ADDR 31:12 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_ADDR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI 0x0000308C /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI__VFALIAS NV_PFB_PRI_MMU_FAULT_INST_HI_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI_ADDR 31:0 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI_ADDR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO 0x00003090 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO__VFALIAS NV_PFB_PRI_MMU_FAULT_INFO_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_FAULT_TYPE 4:0 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_FAULT_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_REPLAYABLE_FAULT 7:7 /* R-EVF */
@@ -282,7 +256,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_VALID 31:31 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_VALID_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS 0x00003094 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS__VFALIAS NV_PFB_PRI_MMU_FAULT_STATUS_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS 0:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_CLEAR 0x00000001 /* RW--V */
@@ -352,7 +325,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_VALID_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_VALID_SET 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB 0x000030A0 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB__VFALIAS NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE 1:1 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE_INIT 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 /* RW--V */
@@ -361,11 +333,9 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_ADDR_INIT 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_ADDR_ALIGNMENT 0x0000000c /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_UPPER_PDB 0x000030A4 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_UPPER_PDB__VFALIAS NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_UPPER_PDB_ADDR 19:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_UPPER_PDB_ADDR_INIT 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE 0x000030B0 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE__VFALIAS NV_PFB_PRI_MMU_INVALIDATE_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA 0:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA_TRUE 0x00000001 /* RW--V */
@@ -456,7 +426,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PCIE_TRUE 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PCIE_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG 0x00003100 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_CONFIG(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_THRESHOLD 15:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_THRESHOLD_INIT 0x00000080 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MIMC_GRANULARITY 17:16 /* RWIVF */
@@ -481,7 +450,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_COUNT_PCIE_TRUE 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_COUNT_PCIE_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG 0x00003200 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_CONFIG(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_THRESHOLD 15:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_THRESHOLD_INIT 0x00000080 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MIMC_GRANULARITY 17:16 /* RWIVF */
@@ -512,14 +480,12 @@
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE_RESET 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO 0x00003108 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_NOTIFY_BUFFER_LO(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO_EN 0:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO_EN_FALSE 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO_EN_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO_BASE_RESET 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_LO 0x00003208 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_LO__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_NOTIFY_BUFFER_LO(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_LO_EN 0:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_LO_EN_FALSE 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_LO_EN_TRUE 0x00000001 /* RW--V */
@@ -529,11 +495,9 @@
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI_BASE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI_BASE_RESET 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_HI 0x0000310C /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_HI__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_NOTIFY_BUFFER_HI(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_HI_BASE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_HI_BASE_RESET 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_HI 0x0000320C /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_HI__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_NOTIFY_BUFFER_HI(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_HI_BASE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_HI_BASE_RESET 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE 0x00003110 /* R--4P */
@@ -541,12 +505,10 @@
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_HW 12:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_HW_ENTRIES 4096 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_SIZE 0x00003110 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_SIZE__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_SIZE_FIELD 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_SIZE_HW 12:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_SIZE_HW_ENTRIES 4096 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_SIZE 0x00003210 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_SIZE__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_SIZE_FIELD 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_SIZE_HW 12:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_SIZE_HW_ENTRIES 4096 /* R-I-V */
@@ -555,12 +517,10 @@
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET_HW 11:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET_HW_INIT 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_GET 0x00003114 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_GET__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_NOTIFY_BUFFER_GET(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_GET_OFFSET 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_GET_OFFSET_HW 11:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_GET_OFFSET_HW_INIT 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_GET 0x00003214 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_GET__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_NOTIFY_BUFFER_GET(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_GET_OFFSET 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_GET_OFFSET_HW 11:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_GET_OFFSET_HW_INIT 0x00000000 /* RWI-V */
@@ -569,12 +529,10 @@
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET_HW 11:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET_HW_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_PUT 0x00003118 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_PUT__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_NOTIFY_BUFFER_PUT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_PUT_OFFSET 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_PUT_OFFSET_HW 11:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_PUT_OFFSET_HW_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_PUT 0x00003218 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_PUT__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_NOTIFY_BUFFER_PUT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_PUT_OFFSET 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_PUT_OFFSET_HW 11:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_PUT_OFFSET_HW_INIT 0x00000000 /* R-I-V */
@@ -589,7 +547,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK_FALSE 0x0 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK_TRUE 0x1 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO 0x0000311C /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_NOTIFY_BUFFER_INFO(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_FULL 0:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_FULL_FALSE 0x0 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_FULL_TRUE 0x1 /* R---V */
@@ -600,7 +557,6 @@
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_WRITE_NACK_FALSE 0x0 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_WRITE_NACK_TRUE 0x1 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO 0x0000321C /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_NOTIFY_BUFFER_INFO(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_FULL 0:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_FULL_FALSE 0x0 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_FULL_TRUE 0x1 /* R---V */
@@ -612,21 +568,17 @@
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_WRITE_NACK_TRUE 0x1 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(i) (0x00010000+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO__VFALIAS NV_XTL_MSIX_TABLE_ADDR_LO(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO_RSVD 1:0 /* C--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO_RSVD_VALUE 0x00000000 /* C---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO_BITS 31:2 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_HI(i) (0x00010004+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_HI__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_HI__VFALIAS NV_XTL_MSIX_TABLE_ADDR_HI(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_HI_BITS 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_DATA(i) (0x00010008+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_DATA__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_DATA__VFALIAS NV_XTL_MSIX_TABLE_DATA(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_DATA_BITS 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL(i) (0x0001000C+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__VFALIAS NV_XTL_MSIX_TABLE_VECTOR_CONTROL(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT 0:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_UNMASKED 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_MASKED 0x00000001 /* RWI-V */
@@ -634,48 +586,38 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_RSVD_VALUE 0x00000000 /* C---V */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_LO(i) (0x00410000+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_LO__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_LO__VFALIAS NV_XTL_MSIX_TABLE_ADDR_LO(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_LO_RSVD 1:0 /* C--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_LO_RSVD_VALUE 0x00000000 /* C---V */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_LO_BITS 31:2 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_HI(i) (0x00410004+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_HI__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_HI__VFALIAS NV_XTL_MSIX_TABLE_ADDR_HI(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_HI_BITS 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_DATA(i) (0x00410008+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_DATA__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_DATA__VFALIAS NV_XTL_MSIX_TABLE_DATA(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_DATA_BITS 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL(i) (0x0041000C+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL__VFALIAS NV_XTL_MSIX_TABLE_VECTOR_CONTROL(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT 0:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_UNMASKED 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_MASKED 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_RSVD 31:1 /* C--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_RSVD_VALUE 0x00000000 /* C---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_PBA 0x00020000 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_PBA__VFALIAS NV_XTL_MSIX_PBA(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_PBA_BITS 31:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_PBA_BITS_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_PBA 0x00420000 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_PBA__VFALIAS NV_XTL_MSIX_PBA(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_PBA_BITS 31:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_PBA_BITS_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_CFG0 0x00030000 /* C--4R */
#define NV_VIRTUAL_FUNCTION_CFG0__VFALIAS NV_PTOP_USERMODE_INFO /* */
#define NV_VIRTUAL_FUNCTION_CFG0_USERMODE_CLASS_ID 15:0 /* C--UF */
#define NV_VIRTUAL_FUNCTION_CFG0_USERMODE_CLASS_ID_VALUE 50785 /* C---V */
#define NV_VIRTUAL_FUNCTION_CFG0_RSVD 31:16 /* C--UF */
#define NV_VIRTUAL_FUNCTION_CFG0_RSVD_VALUE_ZERO 0x0000 /* C---V */
#define NV_VIRTUAL_FUNCTION_TIME_0 0x30080 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_0__VFALIAS NV_PTIMER_TIME_0 /* */
#define NV_VIRTUAL_FUNCTION_TIME_0_NSEC 31:5 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_TIME_1 0x30084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_1__VFALIAS NV_PTIMER_TIME_1 /* */
#define NV_VIRTUAL_FUNCTION_TIME_1_NSEC 28:0 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL 0x30090 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_DOORBELL__VFALIAS NV_CTRL_VF_DOORBELL(f) /* */
#define NV_VIRTUAL_FUNCTION_DOORBELL_HANDLE 31:0 /* */
#define NV_VIRTUAL_FUNCTION_DOORBELL_VECTOR 11:0 /* -WXUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RSVD 15:12 /* -WXUF */
@@ -689,6 +631,5 @@
#define NV_VIRTUAL_FUNCTION_DOORBELL_GSP_DOORBELL_DISABLE 0x1 /* */
#define NV_VIRTUAL_FUNCTION_DOORBELL_GSP_DOORBELL_ENABLE 0x0 /* */
#define NV_VIRTUAL_FUNCTION_ERR_CONT 0x30094 /* R--4R */
#define NV_VIRTUAL_FUNCTION_ERR_CONT__VFALIAS NV_CTRL_ERR_CONT /* */
#endif // __gb100_dev_vm_h__

2
src/common/inc/swref/published/blackwell/gb100/hwproject.h
View File

@@ -25,5 +25,7 @@
#define __gb100_hwproject_h__
#define NV_LITTER_NUM_SUBCTX 64
#define NV_LOCALIZATION_MODE_BIT_IN_ADDRESS_OFFSET 39
#endif // __gb100_hwproject_h__

29
src/common/inc/swref/published/blackwell/gb10b/dev_falcon_v4.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_falcon_v4_h__
#define __gb10b_dev_falcon_v4_h__
#define NV_PFALCON_FALCON_HWCFG2 0x000000f4 /* R--4R */
#endif // __gb10b_dev_falcon_v4_h__

29
src/common/inc/swref/published/blackwell/gb10b/dev_gsp.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_gsp_h__
#define __gb10b_dev_gsp_h__
#define NV_PGSP 0x113fff:0x110000 /* RW--D */
#endif // __gb10b_dev_gsp_h__

58
src/common/inc/swref/published/blackwell/gb10b/dev_sec_pri.h Normal file
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@@ -0,0 +1,58 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_sec_pri_h__
#define __gb10b_dev_sec_pri_h__
#define NV_PSEC_FALCON_MAILBOX0 0x00840040 /* RW-4R */
#define NV_PSEC_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
#define NV_PSEC_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PSEC_FALCON_MAILBOX1 0x00840044 /* RW-4R */
#define NV_PSEC_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
#define NV_PSEC_QUEUE_HEAD(i) (0x00840c00+(i)*8) /* RW-4A */
#define NV_PSEC_QUEUE_HEAD__SIZE_1 8 /* */
#define NV_PSEC_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
#define NV_PSEC_QUEUE_HEAD_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_PSEC_QUEUE_TAIL(i) (0x00840c04+(i)*8) /* RW-4A */
#define NV_PSEC_QUEUE_TAIL__SIZE_1 8 /* */
#define NV_PSEC_QUEUE_TAIL_ADDRESS 31:0 /* RWIVF */
#define NV_PSEC_QUEUE_TAIL_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_PSEC_EMEMC(i) (0x00840ac0+(i)*8) /* RW-4A */
#define NV_PSEC_EMEMC__SIZE_1 8 /* */
#define NV_PSEC_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PSEC_EMEMC_OFFS_INIT 0x00 /* RWI-V */
#define NV_PSEC_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PSEC_EMEMC_BLK_INIT 0x00 /* RWI-V */
#define NV_PSEC_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PSEC_EMEMC_AINCW_INIT 0x0 /* RWI-V */
#define NV_PSEC_EMEMC_AINCW_TRUE 0x1 /* RW--V */
#define NV_PSEC_EMEMC_AINCW_FALSE 0x0 /* RW--V */
#define NV_PSEC_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PSEC_EMEMC_AINCR_INIT 0x0 /* RWI-V */
#define NV_PSEC_EMEMC_AINCR_TRUE 0x1 /* RW--V */
#define NV_PSEC_EMEMC_AINCR_FALSE 0x0 /* RW--V */
#define NV_PSEC_EMEMD(i) (0x00840ac4+(i)*8) /* RW-4A */
#define NV_PSEC_EMEMD__SIZE_1 8 /* */
#define NV_PSEC_EMEMD_DATA 31:0 /* RWXVF */
#endif // __gb10b_dev_sec_pri_h__

4
src/common/inc/swref/published/blackwell/gb202/dev_xtl_ep_pcfg_gpu.h
View File

@@ -48,6 +48,10 @@
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2 0x00000088 /* RW-4R */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_LTR_ENABLE 10:10 /* RWIVF */
#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_DEFAULT 0x00000000 /* RWI-V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS 0x00000004 /* RW-4R */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE 0:0 /* RWIVF */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE_DISABLE 0x00000000 /* RWI-V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE_ENABLE 0x00000001 /* RW--V */
#endif // __gb202_dev_xtl_ep_pcfg_gpu_h__

2
src/common/inc/swref/published/blackwell/gb202/kind_macros.h
View File

@@ -28,7 +28,7 @@
#define PTEKIND_PITCH(k) ( ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define PTEKIND_COMPRESSIBLE(k) ( ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_DISALLOWS_PLC(k) ( !((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE))
#define PTEKIND_SUPPORTED(k) ( ((k) ==NV_MMU_PTE_KIND_INVALID)|| ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_S8Z24)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define PTEKIND_SUPPORTED(k) ( ((k) ==NV_MMU_PTE_KIND_INVALID)|| ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define KIND_Z(k) ( ((k) >=NV_MMU_CLIENT_KIND_Z16 && (k) <= NV_MMU_CLIENT_KIND_Z24S8))
#define PTEKIND_Z(k) ( ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_Z24S8)|| ((k) >=NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_GENERIC_MEMORY(k) ( ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC))

29
src/common/inc/swref/published/blackwell/gb20b/dev_falcon_v4.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_falcon_v4_h__
#define __gb20b_dev_falcon_v4_h__
#define NV_PFALCON_FALCON_HWCFG2 0x000000f4 /* R--4R */
#endif // __gb20b_dev_falcon_v4_h__

38
src/common/inc/swref/published/blackwell/gb20b/dev_gsp.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_gsp_h__
#define __gb20b_dev_gsp_h__
#define NV_PGSP 0x113fff:0x110000 /* RW--D */
#define NV_PGSP_MAILBOX(i) (0x00110804+(i)*4) /* RW-4A */
#define NV_PGSP_MAILBOX__SIZE_1 4 /* */
#define NV_PGSP_MAILBOX_DATA 31:0 /* RWIVF */
#define NV_PGSP_MAILBOX_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_QUEUE_HEAD(i) (0x00110c00+(i)*8) /* RW-4A */
#define NV_PGSP_QUEUE_HEAD__SIZE_1 8 /* */
#define NV_PGSP_QUEUE_TAIL(i) (0x00110c04+(i)*8) /* RW-4A */
#define NV_PGSP_QUEUE_TAIL__SIZE_1 8 /* */
#endif // __gb20b_dev_gsp_h__

2
src/common/inc/swref/published/blackwell/gb20b/kind_macros.h
View File

@@ -28,7 +28,7 @@
#define PTEKIND_PITCH(k) ( ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define PTEKIND_COMPRESSIBLE(k) ( ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_DISALLOWS_PLC(k) ( !((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE))
#define PTEKIND_SUPPORTED(k) ( ((k) ==NV_MMU_PTE_KIND_INVALID)|| ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_S8Z24)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define PTEKIND_SUPPORTED(k) ( ((k) ==NV_MMU_PTE_KIND_INVALID)|| ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_S8)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define KIND_Z(k) ( ((k) >=NV_MMU_CLIENT_KIND_Z16 && (k) <= NV_MMU_CLIENT_KIND_Z24S8))
#define PTEKIND_Z(k) ( ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_Z24S8)|| ((k) >=NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_GENERIC_MEMORY(k) ( ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC))

268
src/common/inc/swref/published/disp/v03_00/dev_disp.h
View File

@@ -30,149 +30,9 @@
#define NV_PDISP_CHN_NUM_WINIM__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_CURS(i) (73+(i)) /* */
#define NV_PDISP_CHN_NUM_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_CHNCTL_CORE 0x006104E0 /* RW-4R */
#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF 9:9 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN 15:15 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS(i) (0x00610604+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN(i) (0x006104E4+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION 1:1 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_CONNECT 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_DISCONNECT 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT 6:6 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP 7:7 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI 8:8 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF 9:9 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA 10:10 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM(i) (0x00610564+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNSTATUS_CORE 0x00610630 /* R--4R */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE 20:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC_LIMBO 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT1 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT2 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_OPERATION 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT1 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT2 0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_OPERATION 0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_UNCONNECTED 0x00000008 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT1 0x00000009 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT2 0x0000000A /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_IDLE 0x0000000B /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_BUSY 0x0000000C /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN1 0x0000000D /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN2 0x0000000E /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS(i) (0x00610784+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE 18:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_IDLE 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_BUSY 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN(i) (0x00610664+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_WIN__SIZE_1 32 /* */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE 19:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT1 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT2 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_IDLE 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_BUSY 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN1 0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN2 0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_UNCONNECTED 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC 31:31 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_IDLE 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM(i) (0x006106E4+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_WINIM__SIZE_1 32 /* */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE 19:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_UNCONNECTED 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT1 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT2 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_IDLE 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_BUSY 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN1 0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN2 0x00000007 /* R---V */
#define NV_PDISP_FE_DEBUG_CTL(i) (0x00610800+(i)*8) /* RW-4A */
#define NV_PDISP_FE_DEBUG_CTL__SIZE_1 73 /* */
#define NV_PDISP_FE_DEBUG_CTL_MODE 0:0 /* RWIVF */
#define NV_PDISP_FE_DEBUG_CTL_MODE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* R---V */
#define NV_PDISP_FE_PBBASE_WIN__SIZE_1 32 /* */
#define NV_PDISP_FE_PBBASE_WINIM__SIZE_1 32 /* */
#define NV_PDISP_FE_SW 0x00640FFF:0x00640000 /* RW--D */
#define NV_PDISP_SF_USER_0 0x006F03FF:0x006F0000 /* RW--D */
#define NV_UDISP_HASH_BASE 0x00000000 /* */
@@ -211,6 +71,134 @@
#define NV_PDISP_FE_FLIPLOCK 0x0061206C /* RW-4R */
#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME 23:0 /* RWIVF */
#define NV_PDISP_FE_PBBASE_WIN__SIZE_1 32 /* */
#define NV_PDISP_FE_PBBASE_WINIM__SIZE_1 32 /* */
#define NV_PDISP_FE_CHNCTL_CORE 0x006104E0 /* RW-4R */
#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF 9:9 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN 15:15 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS(i) (0x00610604+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN(i) (0x006104E4+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION 1:1 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_CONNECT 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_DISCONNECT 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT 6:6 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP 7:7 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI 8:8 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF 9:9 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA 10:10 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM(i) (0x00610564+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNSTATUS_CORE 0x00610630 /* R--4R */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE 20:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC_LIMBO 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT1 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT2 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_OPERATION 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT1 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT2 0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_OPERATION 0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_UNCONNECTED 0x00000008 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT1 0x00000009 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT2 0x0000000A /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_IDLE 0x0000000B /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_BUSY 0x0000000C /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN1 0x0000000D /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN2 0x0000000E /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS(i) (0x00610784+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE 18:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_IDLE 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_BUSY 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN(i) (0x00610664+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_WIN__SIZE_1 32 /* */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE 19:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT1 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT2 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_IDLE 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_BUSY 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN1 0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN2 0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_UNCONNECTED 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC 31:31 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_IDLE 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM(i) (0x006106E4+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_WINIM__SIZE_1 32 /* */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE 19:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_UNCONNECTED 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT1 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT2 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_IDLE 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_BUSY 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN1 0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN2 0x00000007 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH 0x00611EC0 /* R--4R */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* */

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src/common/inc/swref/published/disp/v04_02/dev_disp.h Normal file
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@@ -0,0 +1,27 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __v04_02_dev_disp_h__
#define __v04_02_dev_disp_h__
#define NV_PDISP 0x006F1FFF:0x00610000 /* RW--D */
#endif // __v04_02_dev_disp_h__

28
src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,15 +26,21 @@
#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K 0x100
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE 6:5
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_NONE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_PROTECTED_PCIE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE 6:5
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_NONE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_PROTECTED_PCIE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_POWER_EFF_MODE_ENABLED 7:7
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_POWER_EFF_MODE_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_POWER_EFF_MODE_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_POWER_EFF_MODE_SUPPORTED 8:8
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_POWER_EFF_MODE_SUPPORTED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_POWER_EFF_MODE_SUPPORTED_FALSE 0x0
#endif // __gh100_dev_gc6_island_addendum_h__

3
src/common/inc/swref/published/hopper/gh100/dev_mmu.h
View File

@@ -175,9 +175,6 @@
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001F /* RW--V */
#define NV_MMU_VER3_PTE_KIND 11:8 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS 51:12 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS_SYS 51:12 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS_PEER 51:12 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS_VID 39:12 /* RWXVF */
#define NV_MMU_VER3_PTE_PEER_ID 63:(64-3) /* RWXVF */
#define NV_MMU_VER3_PTE_PEER_ID_0 0x00000000 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_1 0x00000001 /* RW--V */

12
src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h
View File

@@ -31,12 +31,24 @@
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_TOKEN 30:0
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS 31:31
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS_BUSY 0x1
#define NV_XAL_EP_UFLUSH_FB_FLUSH 0x0010f800 /* R--4R */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_TOKEN 30:0 /* R-IUF */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED 0x0010f804 /* R--4R */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_TOKEN 30:0 /* R-IUF */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_STATUS 31:31 /* R-IUF */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_STATUS_IDLE 0x0 /* R-I-V */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_STATUS_BUSY 0x1 /* R---V */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED 0x0010f80c
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_TOKEN 30:0
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS 31:31
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS_BUSY 0x1
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS 0x0010f808
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_TOKEN 30:0
#define NV_XAL_EP_ZEROS 0x0010f900 /* C--4R */
#define NV_XAL_EP_ZEROS_DATA 31:0 /* C--VF */
#define NV_XAL_EP_ZEROS_DATA_ZEROS 0x00000000 /* C---V */
#define NV_XAL_EP_INTR_0 0x0010f100
#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT 5:5
#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT_PENDING 0x1

10
src/common/inc/swref/published/nv_arch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -59,6 +59,8 @@
#define GPU_ARCHITECTURE_T19X GPU_ARCHITECTURE(_TEGRA, 0x0019)
#define GPU_ARCHITECTURE_T23X GPU_ARCHITECTURE(_TEGRA, 0x0023)
#define GPU_ARCHITECTURE_T26X GPU_ARCHITECTURE(_TEGRA, 0x0026)
#define GPU_ARCHITECTURE_SIMS GPU_ARCHITECTURE(_SIMULATION, 0x01f0) // eg: AMODEL
//
@@ -116,8 +118,6 @@
#define GPU_IMPLEMENTATION_GB203 0x03
#define GPU_IMPLEMENTATION_GB204 0x04
#define GPU_IMPLEMENTATION_GB205 0x05
#define GPU_IMPLEMENTATION_GB206 0x06
@@ -126,6 +126,8 @@
#define GPU_IMPLEMENTATION_GB20B 0x0B
#define GPU_IMPLEMENTATION_GB20C 0x0C
#define GPU_IMPLEMENTATION_T124 0x00
#define GPU_IMPLEMENTATION_T132 0x00
#define GPU_IMPLEMENTATION_T210 0x00
@@ -134,6 +136,8 @@
#define GPU_IMPLEMENTATION_T234 0x04
#define GPU_IMPLEMENTATION_T234D 0x05
#define GPU_IMPLEMENTATION_T264D 0x05
/* SIMS gpus */
#define GPU_IMPLEMENTATION_AMODEL 0x00

18
src/common/inc/swref/published/nv_ref.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -151,6 +151,22 @@
#define NV_PMC_BOOT_42_MINOR_REVISION 15:12 /* R-XVF */
#define NV_PMC_BOOT_42_MAJOR_REVISION 19:16 /* R-XVF */
#define NV_PMC_BOOT_42_IMPLEMENTATION 23:20 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_0 0x00000000 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_1 0x00000001 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_2 0x00000002 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_3 0x00000003 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_4 0x00000004 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_5 0x00000005 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_6 0x00000006 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_7 0x00000007 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_8 0x00000008 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_9 0x00000009 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_A 0x0000000A /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_B 0x0000000B /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_C 0x0000000C /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_D 0x0000000D /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_E 0x0000000E /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_F 0x0000000F /* */
#define NV_PMC_BOOT_42_ARCHITECTURE 29:24 /* */
#define NV_PMC_BOOT_42_CHIP_ID 29:20 /* R-XVF */

47
src/common/inc/swref/published/nvswitch/ls10/dev_nvltlc_ip.h
View File

@@ -810,4 +810,51 @@
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER 31:31 /* RWDVF */
#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER_INIT 0x00000000 /* RWD-V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0 0x0000028c /* RW-4R */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXPOISONDET 23:23 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXPOISONDET_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXPOISONDET_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR 24:24 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR 25:25 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWEVF */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0 0x00000a8c /* RW-4R */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWEVF */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#endif // __ls10_dev_nvltlc_ip_h__

31
src/common/inc/swref/published/t23x/t234/dev_fuse.h Normal file
View File

@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __t234_dev_fuse_h__
#define __t234_dev_fuse_h__
#define NV_FUSE_STATUS_OPT_DISPLAY 0x00820C04 /* R-I4R */
#define NV_FUSE_STATUS_OPT_DISPLAY_DATA 0:0 /* R-IVF */
#define NV_FUSE_STATUS_OPT_DISPLAY_DATA_ENABLE 0x00000000 /* R---V */
#endif // __t234_dev_fuse_h__

50
src/common/inc/swref/published/turing/tu102/dev_ctrl.h
View File

@@ -23,61 +23,13 @@
#ifndef __tu102_dev_ctrl_h__
#define __tu102_dev_ctrl_h__
#define NV_CTRL_CPU_INTR_TOP(i) (0x00B73400+(i)*4) /* R--4A */
#define NV_CTRL_CPU_INTR_TOP__SIZE_1 64 /* */
#define NV_CTRL_CPU_INTR_TOP_VALUE 31:0 /* R--VF */
#define NV_CTRL_CPU_INTR_TOP_EN_SET(i) (0x00B73800+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_TOP_EN_SET__SIZE_1 64 /* */
#define NV_CTRL_CPU_INTR_TOP_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_TOP_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR(i) (0x00B73C00+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR__SIZE_1 64 /* */
#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_LEAF(i) (0x00B74000+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_LEAF__SIZE_1 1024 /* */
#define NV_CTRL_CPU_INTR_LEAF_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_LEAF_ARRAY_SIZE_PER_FN 16 /* */
#define NV_CTRL_CPU_INTR_LEAF_EN_SET(i) (0x00B78000+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_LEAF_EN_SET__SIZE_1 1024 /* */
#define NV_CTRL_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR(i) (0x00B7C000+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 1024 /* */
#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_LEGACY_ENGINE_STALL_INTR_BASE_VECTORID 0xB66880 /* C--4R */
#define NV_CTRL_LEGACY_ENGINE_STALL_INTR_BASE_VECTORID_VECTOR 11:0 /* C--UF */
#define NV_CTRL_LEGACY_ENGINE_STALL_INTR_BASE_VECTORID_VECTOR_INIT 192 /* C---V */
#define NV_CTRL_LEGACY_ENGINE_NONSTALL_INTR_BASE_VECTORID 0xB66884 /* C--4R */
#define NV_CTRL_LEGACY_ENGINE_NONSTALL_INTR_BASE_VECTORID_VECTOR 11:0 /* C--UF */
#define NV_CTRL_LEGACY_ENGINE_NONSTALL_INTR_BASE_VECTORID_VECTOR_INIT 0 /* C---V */
#define NV_CTRL_VIRTUAL_INTR_LEAF(i) (0x00B66800+(i)*4) /* RW-4A */
#define NV_CTRL_VIRTUAL_INTR_LEAF__SIZE_1 2 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_PENDING 31:0 /* RWIVF */
#define NV_CTRL_VIRTUAL_INTR_LEAF_PENDING_INIT 0 /* RWI-V */
#define NV_CTRL_VIRTUAL_INTR_LEAF_PENDING_INTR 1 /* R---V */
#define NV_CTRL_VIRTUAL_INTR_LEAF_PENDING_CLEAR 1 /* -W--V */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET(i) (0x00B66820+(i)*4) /* RW-4A */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET__SIZE_1 2 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VALUE_INIT 0 /* RWI-V */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VECTOR(i) (i) /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VECTOR_ENABLE 1 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VECTOR_ENABLED 1 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VECTOR_DISABLED 0 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR(i) (0x00B66840+(i)*4) /* RW-4A */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR__SIZE_1 2 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR_VALUE_INIT 0 /* RWI-V */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR_VECTOR(i) (i) /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR_VECTOR_DISABLE 1 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR_VECTOR_ENABLED 1 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR_VECTOR_DISABLED 0 /* */
#define NV_CTRL_CPU_INTR_LEAF_TRIGGER(i) (0x00B66C00+(i)*4) /* -W-4A */
#define NV_CTRL_CPU_INTR_LEAF_TRIGGER__SIZE_1 64 /* */
#define NV_CTRL_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -WXVF */
#define NV_CTRL_CPU_DOORBELL_VECTORID 0x00B6687C /* C--4R */
#define NV_CTRL_CPU_DOORBELL_VECTORID_VALUE 11:0 /* C--VF */
#define NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT 129 /* C---V */