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580.65.06

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This commit is contained in:
Maneet Singh
2025-08-04 11:15:02 -07:00
parent d890313300
commit 307159f262
1315 changed files with 477791 additions and 279973 deletions
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28
src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,15 +26,21 @@
#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K 0x100
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE 6:5
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_NONE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_PROTECTED_PCIE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE 6:5
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_NONE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_PROTECTED_PCIE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_POWER_EFF_MODE_ENABLED 7:7
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_POWER_EFF_MODE_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_POWER_EFF_MODE_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_POWER_EFF_MODE_SUPPORTED 8:8
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_POWER_EFF_MODE_SUPPORTED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_POWER_EFF_MODE_SUPPORTED_FALSE 0x0
#endif // __gh100_dev_gc6_island_addendum_h__

3
src/common/inc/swref/published/hopper/gh100/dev_mmu.h
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@@ -175,9 +175,6 @@
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001F /* RW--V */
#define NV_MMU_VER3_PTE_KIND 11:8 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS 51:12 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS_SYS 51:12 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS_PEER 51:12 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS_VID 39:12 /* RWXVF */
#define NV_MMU_VER3_PTE_PEER_ID 63:(64-3) /* RWXVF */
#define NV_MMU_VER3_PTE_PEER_ID_0 0x00000000 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_1 0x00000001 /* RW--V */

12
src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h
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@@ -31,12 +31,24 @@
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_TOKEN 30:0
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS 31:31
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS_BUSY 0x1
#define NV_XAL_EP_UFLUSH_FB_FLUSH 0x0010f800 /* R--4R */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_TOKEN 30:0 /* R-IUF */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED 0x0010f804 /* R--4R */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_TOKEN 30:0 /* R-IUF */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_STATUS 31:31 /* R-IUF */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_STATUS_IDLE 0x0 /* R-I-V */
#define NV_XAL_EP_UFLUSH_FB_FLUSH_COMPLETED_STATUS_BUSY 0x1 /* R---V */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED 0x0010f80c
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_TOKEN 30:0
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS 31:31
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS_BUSY 0x1
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS 0x0010f808
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_TOKEN 30:0
#define NV_XAL_EP_ZEROS 0x0010f900 /* C--4R */
#define NV_XAL_EP_ZEROS_DATA 31:0 /* C--VF */
#define NV_XAL_EP_ZEROS_DATA_ZEROS 0x00000000 /* C---V */
#define NV_XAL_EP_INTR_0 0x0010f100
#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT 5:5
#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT_PENDING 0x1