NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-03-04 04:39:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

580.65.06

Browse Source
This commit is contained in:
Maneet Singh
2025-08-04 11:15:02 -07:00
parent d890313300
commit 307159f262
1315 changed files with 477791 additions and 279973 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
src/common/modeset/timing/nvt_edid.c
View File

@@ -53,7 +53,7 @@ static const NVT_TIMING EDID_EST[] =
{
EST_TIMING( 720, 0, 0, 720,'-', 400, 0,0, 400,'-',70, 0,NVT_STATUS_EDID_EST), // 720x400x70Hz (IBM, VGA)
EST_TIMING( 720, 0, 0, 720,'-', 400, 0,0, 400,'-',88, 0,NVT_STATUS_EDID_EST), // 720x400x88Hz (IBM, XGA2)
{640,0,16,96,800,NVT_H_SYNC_NEGATIVE,480,0,10,2,525,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,2518,25180,{0,60,60000,0,1,{0},{0},{0},{0},NVT_STATUS_EDID_EST,"EDID_Established"}},
{640,0,16,96,800,NVT_H_SYNC_NEGATIVE,480,0,10,2,525,NVT_V_SYNC_NEGATIVE,NVT_PROGRESSIVE,2518,25175,{0,60,60000,0,1,{0},{0},{0},{0},NVT_STATUS_EDID_EST,"EDID_Established"}},
EST_TIMING( 640, 0, 0, 640,'-', 480, 0,0, 480,'-',67, 0,NVT_STATUS_EDID_EST), // 640x480x67Hz (Apple, Mac II)
@@ -154,8 +154,8 @@ NVT_STATUS NvTiming_EnumEST(NvU32 index, NVT_TIMING *pT)
return NVT_STATUS_ERR;
}
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk,
(NvU32)10000*(NvU32)1000,
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk1khz,
(NvU32)1000*(NvU32)1000,
(NvU32)pT->HTotal*(NvU32)pT->VTotal);
return NVT_STATUS_SUCCESS;
@@ -176,8 +176,8 @@ NVT_STATUS NvTiming_EnumESTIII(NvU32 index, NVT_TIMING *pT)
return NVT_STATUS_ERR;
}
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk,
(NvU32)10000*(NvU32)1000,
pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk1khz,
(NvU32)1000*(NvU32)1000,
(NvU32)pT->HTotal*(NvU32)pT->VTotal);
return NVT_STATUS_SUCCESS;
@@ -347,7 +347,7 @@ void parseEdidEstablishedTiming(NVT_EDID_INFO *pInfo)
for (i = 1 << (sizeof(pInfo->established_timings_1_2) * 8 - 1), j = 0; i != 0; i >>= 1, j ++)
{
if ((pInfo->established_timings_1_2 & i) != 0 && EDID_EST[j].pclk != 0)
if ((pInfo->established_timings_1_2 & i) != 0 && EDID_EST[j].pclk1khz != 0)
{
// count the timing
newTiming = EDID_EST[j];
@@ -382,7 +382,7 @@ void parseEdidEstablishedTiming(NVT_EDID_INFO *pInfo)
for (k=7; k<=7; k--)
{
// find if the bit is 1 and we have a valid associated timing
if (pEST->data[j] & (1<<k) && EDID_ESTIII[(j*8)+(7-k)].pclk != 0)
if (pEST->data[j] & (1<<k) && EDID_ESTIII[(j*8)+(7-k)].pclk1khz != 0)
{
newTiming = EDID_ESTIII[(j*8)+(7-k)];
newTiming.etc.status = NVT_STATUS_EDID_ESTn(++count);
@@ -565,7 +565,7 @@ NVT_STATUS parseEdidDetailedTimingDescriptor(NvU8 *p, NVT_TIMING *pT)
// pixel clock
pT->pclk = (NvU32)pDTD->wDTPixelClock;
pT->pclk1khz = (NvU32)((pT->pclk << 3) + (pT->pclk << 1));
pT->pclk1khz = (NvU32)((pDTD->wDTPixelClock << 3) + (pDTD->wDTPixelClock << 1));
// sync polarities
if ((pDTD->bDTFlags & 0x18) == 0x18)
@@ -2048,7 +2048,8 @@ NVT_STATUS NvTiming_GetEDIDBasedASPRTiming( NvU16 width, NvU16 height, NvU16 rr,
if(rr != pT->etc.rr)
{
pT->etc.rrx1k = rr * 1000;
pT->pclk = RRx1kToPclk (pT);
pT->pclk = RRx1kToPclk (pT);
pT->pclk1khz = RRx1kToPclk1khz(pT);
}
pT->etc.status = NVT_STATUS_ASPR;
@@ -2991,7 +2992,7 @@ NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion)
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS NvTiming_CalculateEDIDLimits(NVT_EDID_INFO *pEdidInfo, NVT_EDID_RANGE_LIMIT *pLimit)
{
NvU32 i;
NvU32 i, pclk10khz;
NVMISC_MEMSET(pLimit, 0, sizeof(NVT_EDID_RANGE_LIMIT));
@@ -3022,7 +3023,7 @@ NVT_STATUS NvTiming_CalculateEDIDLimits(NVT_EDID_INFO *pEdidInfo, NVT_EDID_RANGE
pLimit->max_v_rate_hzx1k = pTiming->etc.rrx1k;
}
h_rate_hz = axb_div_c(pTiming->pclk, 10000, (NvU32)pTiming->HTotal);
h_rate_hz = axb_div_c(pTiming->pclk1khz, 1000, (NvU32)pTiming->HTotal);
if (pLimit->min_h_rate_hz > h_rate_hz)
{
@@ -3033,9 +3034,11 @@ NVT_STATUS NvTiming_CalculateEDIDLimits(NVT_EDID_INFO *pEdidInfo, NVT_EDID_RANGE
pLimit->max_h_rate_hz = h_rate_hz;
}
if (pLimit->max_pclk_10khz < pTiming->pclk)
pclk10khz = (pTiming->pclk1khz + 5 ) / 10;
if (pLimit->max_pclk_10khz < pclk10khz)
{
pLimit->max_pclk_10khz = pTiming->pclk;
pLimit->max_pclk_10khz = pclk10khz;
}
}