mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-28 10:53:59 +00:00
580.65.06
This commit is contained in:
Maneet Singh
298
src/nvidia/generated/g_gpu_arch_nvoc.c
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298
src/nvidia/generated/g_gpu_arch_nvoc.c
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@@ -0,0 +1,298 @@
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#define NVOC_GPU_ARCH_H_PRIVATE_ACCESS_ALLOWED
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// Version of generated metadata structures
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#ifdef NVOC_METADATA_VERSION
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#undef NVOC_METADATA_VERSION
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#endif
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#define NVOC_METADATA_VERSION 2
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#include "nvoc/runtime.h"
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#include "nvoc/rtti.h"
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#include "nvtypes.h"
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#include "nvport/nvport.h"
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#include "nvport/inline/util_valist.h"
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#include "utils/nvassert.h"
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#include "g_gpu_arch_nvoc.h"
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#ifdef DEBUG
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char __nvoc_class_id_uniqueness_check__0x4b33af = 1;
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#endif
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extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuArch;
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extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object;
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extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuHalspecOwner;
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// Forward declarations for GpuArch
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void __nvoc_init__Object(Object*);
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void __nvoc_init__GpuHalspecOwner(GpuHalspecOwner*,
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NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev,
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TEGRA_CHIP_TYPE TegraChipHal_tegraType);
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void __nvoc_init__GpuArch(GpuArch*,
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NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev,
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TEGRA_CHIP_TYPE TegraChipHal_tegraType);
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void __nvoc_init_funcTable_GpuArch(GpuArch*);
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NV_STATUS __nvoc_ctor_GpuArch(GpuArch*, NvU32 arg_chipArch, NvU32 arg_chipImpl, NvU32 arg_hidrev, TEGRA_CHIP_TYPE arg_tegraType);
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void __nvoc_init_dataField_GpuArch(GpuArch*);
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void __nvoc_dtor_GpuArch(GpuArch*);
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// Structures used within RTTI (run-time type information)
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extern const struct NVOC_CASTINFO __nvoc_castinfo__GpuArch;
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extern const struct NVOC_EXPORT_INFO __nvoc_export_info__GpuArch;
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// Down-thunk(s) to bridge GpuArch methods from ancestors (if any)
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// Up-thunk(s) to bridge GpuArch methods to ancestors (if any)
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const struct NVOC_CLASS_DEF __nvoc_class_def_GpuArch =
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{
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/*classInfo=*/ {
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/*size=*/ sizeof(GpuArch),
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/*classId=*/ classId(GpuArch),
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/*providerId=*/ &__nvoc_rtti_provider,
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#if NV_PRINTF_STRINGS_ALLOWED
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/*name=*/ "GpuArch",
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#endif
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},
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/*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_GpuArch,
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/*pCastInfo=*/ &__nvoc_castinfo__GpuArch,
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/*pExportInfo=*/ &__nvoc_export_info__GpuArch
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};
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// Metadata with per-class RTTI with ancestor(s)
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static const struct NVOC_METADATA__GpuArch __nvoc_metadata__GpuArch = {
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.rtti.pClassDef = &__nvoc_class_def_GpuArch, // (gpuarch) this
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.rtti.dtor = (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_GpuArch,
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.rtti.offset = 0,
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.metadata__Object.rtti.pClassDef = &__nvoc_class_def_Object, // (obj) super
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.metadata__Object.rtti.dtor = &__nvoc_destructFromBase,
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.metadata__Object.rtti.offset = NV_OFFSETOF(GpuArch, __nvoc_base_Object),
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.metadata__GpuHalspecOwner.rtti.pClassDef = &__nvoc_class_def_GpuHalspecOwner, // (gpuhalspecowner) super
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.metadata__GpuHalspecOwner.rtti.dtor = &__nvoc_destructFromBase,
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.metadata__GpuHalspecOwner.rtti.offset = NV_OFFSETOF(GpuArch, __nvoc_base_GpuHalspecOwner),
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};
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// Dynamic down-casting information
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const struct NVOC_CASTINFO __nvoc_castinfo__GpuArch = {
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.numRelatives = 3,
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.relatives = {
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&__nvoc_metadata__GpuArch.rtti, // [0]: (gpuarch) this
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&__nvoc_metadata__GpuArch.metadata__Object.rtti, // [1]: (obj) super
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&__nvoc_metadata__GpuArch.metadata__GpuHalspecOwner.rtti, // [2]: (gpuhalspecowner) super
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}
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};
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const struct NVOC_EXPORT_INFO __nvoc_export_info__GpuArch =
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{
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/*numEntries=*/ 0,
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/*pExportEntries=*/ 0
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};
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void __nvoc_dtor_Object(Object*);
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void __nvoc_dtor_GpuHalspecOwner(GpuHalspecOwner*);
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void __nvoc_dtor_GpuArch(GpuArch *pThis) {
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__nvoc_dtor_Object(&pThis->__nvoc_base_Object);
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__nvoc_dtor_GpuHalspecOwner(&pThis->__nvoc_base_GpuHalspecOwner);
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PORT_UNREFERENCED_VARIABLE(pThis);
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}
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void __nvoc_init_dataField_GpuArch(GpuArch *pThis) {
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ChipHal *chipHal = &staticCast(pThis, GpuHalspecOwner)->chipHal;
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const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx;
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PORT_UNREFERENCED_VARIABLE(pThis);
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PORT_UNREFERENCED_VARIABLE(chipHal);
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PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
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}
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NV_STATUS __nvoc_ctor_Object(Object* );
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NV_STATUS __nvoc_ctor_GpuHalspecOwner(GpuHalspecOwner* );
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NV_STATUS __nvoc_ctor_GpuArch(GpuArch *pThis, NvU32 arg_chipArch, NvU32 arg_chipImpl, NvU32 arg_hidrev, TEGRA_CHIP_TYPE arg_tegraType) {
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NV_STATUS status = NV_OK;
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status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object);
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if (status != NV_OK) goto __nvoc_ctor_GpuArch_fail_Object;
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status = __nvoc_ctor_GpuHalspecOwner(&pThis->__nvoc_base_GpuHalspecOwner);
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if (status != NV_OK) goto __nvoc_ctor_GpuArch_fail_GpuHalspecOwner;
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__nvoc_init_dataField_GpuArch(pThis);
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status = __nvoc_gpuarchConstruct(pThis, arg_chipArch, arg_chipImpl, arg_hidrev, arg_tegraType);
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if (status != NV_OK) goto __nvoc_ctor_GpuArch_fail__init;
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goto __nvoc_ctor_GpuArch_exit; // Success
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__nvoc_ctor_GpuArch_fail__init:
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__nvoc_dtor_GpuHalspecOwner(&pThis->__nvoc_base_GpuHalspecOwner);
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__nvoc_ctor_GpuArch_fail_GpuHalspecOwner:
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__nvoc_dtor_Object(&pThis->__nvoc_base_Object);
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__nvoc_ctor_GpuArch_fail_Object:
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__nvoc_ctor_GpuArch_exit:
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return status;
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}
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// Vtable initialization
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static void __nvoc_init_funcTable_GpuArch_1(GpuArch *pThis) {
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ChipHal *chipHal = &staticCast(pThis, GpuHalspecOwner)->chipHal;
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const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx;
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PORT_UNREFERENCED_VARIABLE(pThis);
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PORT_UNREFERENCED_VARIABLE(chipHal);
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PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
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// gpuarchGetSystemPhysAddrWidth -- halified (4 hals)
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if (( ((chipHal_HalVarIdx >> 5) == 3UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00005000UL) )) /* ChipHal: T234D | T264D */
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{
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pThis->__gpuarchGetSystemPhysAddrWidth__ = &gpuarchGetSystemPhysAddrWidth_T234D;
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}
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else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
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( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
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{
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pThis->__gpuarchGetSystemPhysAddrWidth__ = &gpuarchGetSystemPhysAddrWidth_GB10B;
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}
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else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
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{
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pThis->__gpuarchGetSystemPhysAddrWidth__ = &gpuarchGetSystemPhysAddrWidth_TU102;
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}
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else
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{
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pThis->__gpuarchGetSystemPhysAddrWidth__ = &gpuarchGetSystemPhysAddrWidth_GH100;
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}
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// gpuarchGetDmaAddrWidth -- halified (2 hals) body
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) )) /* ChipHal: GB10B */
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{
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pThis->__gpuarchGetDmaAddrWidth__ = &gpuarchGetDmaAddrWidth_GB10B;
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}
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// default
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else
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{
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pThis->__gpuarchGetDmaAddrWidth__ = &gpuarchGetDmaAddrWidth_4a4dee;
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}
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// gpuarchIsZeroFb -- halified (2 hals) body
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) ) ||
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( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000c00UL) )) /* ChipHal: GB10B | GB20B | GB20C */
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{
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pThis->__gpuarchIsZeroFb__ = &gpuarchIsZeroFb_cbe027;
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}
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// default
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else
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{
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pThis->__gpuarchIsZeroFb__ = &gpuarchIsZeroFb_491d52;
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}
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// gpuarchSupportsIgpuRg -- halified (2 hals) body
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if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x80000000UL) )) /* ChipHal: GB10B */
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{
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pThis->__gpuarchSupportsIgpuRg__ = &gpuarchSupportsIgpuRg_cbe027;
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}
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// default
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else
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{
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pThis->__gpuarchSupportsIgpuRg__ = &gpuarchSupportsIgpuRg_491d52;
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}
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} // End __nvoc_init_funcTable_GpuArch_1 with approximately 10 basic block(s).
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// Initialize vtable(s) for 4 virtual method(s).
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void __nvoc_init_funcTable_GpuArch(GpuArch *pThis) {
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// Initialize vtable(s) with 4 per-object function pointer(s).
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__nvoc_init_funcTable_GpuArch_1(pThis);
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}
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// Initialize newly constructed object.
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void __nvoc_init__GpuArch(GpuArch *pThis,
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NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev,
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TEGRA_CHIP_TYPE TegraChipHal_tegraType) {
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// Initialize pointers to inherited data.
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pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; // (obj) super
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pThis->__nvoc_pbase_GpuHalspecOwner = &pThis->__nvoc_base_GpuHalspecOwner; // (gpuhalspecowner) super
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pThis->__nvoc_pbase_GpuArch = pThis; // (gpuarch) this
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// Recurse to superclass initialization function(s).
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__nvoc_init__Object(&pThis->__nvoc_base_Object);
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__nvoc_init__GpuHalspecOwner(&pThis->__nvoc_base_GpuHalspecOwner, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, TegraChipHal_tegraType);
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// Pointer(s) to metadata structures(s)
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pThis->__nvoc_base_Object.__nvoc_metadata_ptr = &__nvoc_metadata__GpuArch.metadata__Object; // (obj) super
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pThis->__nvoc_base_GpuHalspecOwner.__nvoc_metadata_ptr = &__nvoc_metadata__GpuArch.metadata__GpuHalspecOwner; // (gpuhalspecowner) super
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pThis->__nvoc_metadata_ptr = &__nvoc_metadata__GpuArch; // (gpuarch) this
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// Initialize per-object vtables.
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__nvoc_init_funcTable_GpuArch(pThis);
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}
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NV_STATUS __nvoc_objCreate_GpuArch(GpuArch **ppThis, Dynamic *pParent, NvU32 createFlags,
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NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev,
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TEGRA_CHIP_TYPE TegraChipHal_tegraType, NvU32 arg_chipArch, NvU32 arg_chipImpl, NvU32 arg_hidrev, TEGRA_CHIP_TYPE arg_tegraType)
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{
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NV_STATUS status;
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Object *pParentObj = NULL;
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GpuArch *pThis;
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// Assign `pThis`, allocating memory unless suppressed by flag.
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status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuArch), (void**)&pThis, (void**)ppThis);
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if (status != NV_OK)
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return status;
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// Zero is the initial value for everything.
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portMemSet(pThis, 0, sizeof(GpuArch));
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pThis->__nvoc_base_Object.createFlags = createFlags;
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// Link the child into the parent if there is one unless flagged not to do so.
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if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY))
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{
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pParentObj = dynamicCast(pParent, Object);
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objAddChild(pParentObj, &pThis->__nvoc_base_Object);
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}
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else
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{
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pThis->__nvoc_base_Object.pParent = NULL;
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}
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__nvoc_init__GpuArch(pThis, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, TegraChipHal_tegraType);
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status = __nvoc_ctor_GpuArch(pThis, arg_chipArch, arg_chipImpl, arg_hidrev, arg_tegraType);
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if (status != NV_OK) goto __nvoc_objCreate_GpuArch_cleanup;
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// Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set.
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*ppThis = pThis;
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return NV_OK;
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__nvoc_objCreate_GpuArch_cleanup:
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// Unlink the child from the parent if it was linked above.
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if (pParentObj != NULL)
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objRemoveChild(pParentObj, &pThis->__nvoc_base_Object);
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// Do not call destructors here since the constructor already called them.
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if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT)
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portMemSet(pThis, 0, sizeof(GpuArch));
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else
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{
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portMemFree(pThis);
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*ppThis = NULL;
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}
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// coverity[leaked_storage:FALSE]
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return status;
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}
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NV_STATUS __nvoc_objCreateDynamic_GpuArch(GpuArch **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) {
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NV_STATUS status;
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NvU32 ChipHal_arch = va_arg(args, NvU32);
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NvU32 ChipHal_impl = va_arg(args, NvU32);
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NvU32 ChipHal_hidrev = va_arg(args, NvU32);
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TEGRA_CHIP_TYPE TegraChipHal_tegraType = va_arg(args, TEGRA_CHIP_TYPE);
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NvU32 arg_chipArch = va_arg(args, NvU32);
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NvU32 arg_chipImpl = va_arg(args, NvU32);
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NvU32 arg_hidrev = va_arg(args, NvU32);
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TEGRA_CHIP_TYPE arg_tegraType = va_arg(args, TEGRA_CHIP_TYPE);
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status = __nvoc_objCreate_GpuArch(ppThis, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, TegraChipHal_tegraType, arg_chipArch, arg_chipImpl, arg_hidrev, arg_tegraType);
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return status;
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}
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