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This commit is contained in:
Maneet Singh
2025-08-04 11:15:02 -07:00
parent d890313300
commit 307159f262
1315 changed files with 477791 additions and 279973 deletions
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1
src/nvidia/inc/kernel/core/bin_data.h
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@@ -106,7 +106,6 @@ typedef enum {
BINDATA_LABEL_LC128_PATCH_LOC_PROD,
BINDATA_LABEL_LC128_PATCH_LOC_DBG,
BINDATA_LABEL_CERTIFICATE_PEM,
BINDATA_LABEL_CERTIFICATE_DER,
} BINDATA_LABEL;
//

49
src/nvidia/inc/kernel/gpu/disp/kern_disp_type.h
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@@ -30,21 +30,6 @@
*
******************************************************************************/
#define NV_PDISP_CHN_NUM_ANY 0x7F
#define DISP_ACCL_NONE (0x00)
#define DISP_ACCL_IGNORE_PI NVBIT(0)
#define DISP_ACCL_SKIP_NOTIF NVBIT(1)
#define DISP_ACCL_SKIP_SEMA NVBIT(2)
#define DISP_ACCL_IGNORE_INTERLOCK NVBIT(3)
#define DISP_ACCL_IGNORE_FLIPLOCK NVBIT(4)
#define DISP_ACCL_TRASH_ONLY NVBIT(5)
#define DISP_ACCL_TRASH_AND_ABORT NVBIT(6)
#define DISP_ACCL_SKIP_SYNCPOINT NVBIT(7)
#define DISP_ACCL_IGNORE_TIMESTAMP NVBIT(8)
#define DISP_ACCL_IGNORE_MGI NVBIT(9)
#define DISP_ACCL_DISABLE_PUTPTR_WRITE NVBIT(16)
#define DISP_ACCL_LOCK_PIO_FIFO NVBIT(16)
#define DISP_ACCL_DISABLE_INTR_DURING_SHTDWN NVBIT(17)
#define DISP_ACCL_ALL ~(DISP_ACCL_NONE)
typedef enum
{
@@ -59,31 +44,6 @@ typedef enum
dispChnClass_Supported
} DISPCHNCLASS;
typedef enum
{
dispChnState_Idle,
dispChnState_Wrtidle,
dispChnState_Empty,
dispChnState_Flushed,
dispChnState_Busy,
dispChnState_Dealloc,
dispChnState_DeallocLimbo,
dispChnState_Limbo1,
dispChnState_Limbo2,
dispChnState_Fcodeinit1,
dispChnState_Fcodeinit2,
dispChnState_Fcode,
dispChnState_Vbiosinit1,
dispChnState_Vbiosinit2,
dispChnState_Vbiosoper,
dispChnState_Unconnected,
dispChnState_Initialize1,
dispChnState_Initialize2,
dispChnState_Shutdown1,
dispChnState_Shutdown2,
dispChnState_Supported
} DISPCHNSTATE;
enum DISPLAY_ICC_BW_CLIENT
{
DISPLAY_ICC_BW_CLIENT_RM,
@@ -105,13 +65,4 @@ typedef struct
NvBool valid;
} VGAADDRDESC;
//
// Map HW channel state to SW channel state
//
typedef struct
{
NvU32 hwChannelState;
DISPCHNSTATE dispChnState;
} CHNSTATEMAP;
#endif // #ifndef KERN_DISP_TYPE_H

4
src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -238,7 +238,7 @@ NV_STATUS gsyncRefSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFT
NV_STATUS gsyncRefMaster_P2060 (OBJGPU *, OBJGSYNC *, REFTYPE, NvU32 *DisplayMask,
NvU32 *Refresh, NvBool retainMaster,
NvBool skipSwapBarrierWar);
NV_STATUS gsyncRefSlaves_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *DisplayMask_s, NvU32 *Refresh);
NV_STATUS gsyncRefSlaves_P2060 (OBJGPU *, OBJGSYNC *, REFTYPE, NvU32 *DisplayMask_s, NvU32 *Refresh);
NV_STATUS gsyncGetCplStatus_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSTATUS, NvU32 *);
NV_STATUS gsyncGetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);

4
src/nvidia/inc/kernel/gpu/external_device/dac_p2061.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,7 +33,7 @@ NV_STATUS gsyncSetHouseSyncMode_P2061(OBJGPU *, DACEXTERNALDEVICE *, NvU8);
NV_STATUS gsyncGetCplStatus_P2061 (OBJGPU *, DACEXTERNALDEVICE *, GSYNCSTATUS, NvU32 *);
NV_STATUS gsyncSetSyncSkew_P2061_V204(OBJGPU *, DACEXTERNALDEVICE *, NvU32);
NV_STATUS gsyncGetSyncSkew_P2061_V204(OBJGPU *, DACEXTERNALDEVICE *, NvU32 *);
NV_STATUS gsyncSetRasterSyncDecodeMode_P2061_V300(OBJGPU *, DACEXTERNALDEVICE *);
NV_STATUS gsyncSetRasterSyncDecodeMode_P2061_V300(OBJGPU *, OBJGPU *, DACEXTERNALDEVICE *);
NV_STATUS gsyncGetVRR_P2061_V300(OBJGPU *, DACEXTERNALDEVICE *, NvU32 *);
NV_STATUS gsyncSetVRR_P2061_V300(OBJGPU *, DACEXTERNALDEVICE *, NvU32);

3
src/nvidia/inc/kernel/gpu/gpu_arch.h Normal file
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@@ -0,0 +1,3 @@
#include "g_gpu_arch_nvoc.h"

8
src/nvidia/inc/kernel/gpu/gpu_child_list.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -228,6 +228,9 @@
#if GPU_CHILD_MODULE(HDACODEC)
GPU_CHILD_SINGLE_INST( OBJHDACODEC, GPU_GET_HDACODEC, 1, NV_FALSE, pHdacodec )
#endif
#if GPU_CHILD_MODULE(GCX)
GPU_CHILD_SINGLE_INST( GCX, GPU_GET_GCX, 1, NV_FALSE, pGcx )
#endif
#if GPU_CHILD_MODULE(LPWR)
GPU_CHILD_SINGLE_INST( Lpwr, GPU_GET_LPWR, 1, NV_FALSE, pLpwr )
#endif
@@ -313,6 +316,9 @@
#if RMCFG_MODULE_KERNEL_GSPLITE && GPU_CHILD_MODULE(KERNEL_GSPLITE)
GPU_CHILD_MULTI_INST( KernelGsplite, GPU_GET_KERNEL_GSPLITE, GPU_MAX_GSPLITES, NV_FALSE, pKernelGsplite )
#endif
#if RMCFG_MODULE_KERNEL_HFRP && GPU_CHILD_MODULE(KERNEL_HFRP)
GPU_CHILD_SINGLE_INST( KernelHFRP, GPU_GET_KERNEL_HFRP, 1, NV_FALSE, pKernelHfrp )
#endif
// Undefine the entry macros to simplify call sites
#undef GPU_CHILD

5
src/nvidia/inc/kernel/gpu/gpu_device_mapping.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -39,6 +39,7 @@ typedef enum
DEVICE_INDEX_FUSE,
DEVICE_INDEX_KFUSE,
DEVICE_INDEX_MIPICAL,
DEVICE_INDEX_HFRP,
DEVICE_INDEX_MAX //Should always be the last entry
} DEVICE_INDEX;
@@ -47,6 +48,8 @@ typedef enum
SOC_DEV_MAPPING_DISP = 0,
SOC_DEV_MAPPING_DPAUX0,
SOC_DEV_MAPPING_DPAUX1,
SOC_DEV_MAPPING_DPAUX2,
SOC_DEV_MAPPING_DPAUX3, // Update NV_MAX_SOC_DPAUX_NUM_DEVICES if adding new DPAUX mappings
SOC_DEV_MAPPING_HDACODEC,
SOC_DEV_MAPPING_MIPICAL,
SOC_DEV_MAPPING_MAX

4
src/nvidia/inc/kernel/gpu/gpu_engine_type.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -71,7 +71,6 @@ typedef enum
RM_ENGINE_TYPE_NVENC0 = (0x00000025),
RM_ENGINE_TYPE_NVENC1 = (0x00000026),
RM_ENGINE_TYPE_NVENC2 = (0x00000027),
// Bug 4175886 - Use this new value for all chips once GB20X is released
RM_ENGINE_TYPE_NVENC3 = (0x00000028),
RM_ENGINE_TYPE_VP = (0x00000029),
RM_ENGINE_TYPE_ME = (0x0000002a),
@@ -130,7 +129,6 @@ typedef enum
#define RM_ENGINE_TYPE_NVJPG RM_ENGINE_TYPE_NVJPEG0
#define RM_ENGINE_TYPE_COPY_SIZE 20
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define RM_ENGINE_TYPE_NVENC_SIZE 4
#define RM_ENGINE_TYPE_NVJPEG_SIZE 8
#define RM_ENGINE_TYPE_NVDEC_SIZE 8

2
src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h
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@@ -42,6 +42,8 @@ NV_STATUS gpuFabricProbeStart(OBJGPU *pGpu,
void gpuFabricProbeStop(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
void gpuFabricProbeStopPhysical(GPU_FABRIC_PROBE_INFO_PHYSICAL *pGpuFabricProbeInfoPhysical,
NvU32 gfId);
NV_STATUS gpuFabricProbeSuspendPhysical(GPU_FABRIC_PROBE_INFO_PHYSICAL *pGpuFabricProbeInfoPhysical, NvU32 *pPrevBwMode);
NV_STATUS gpuFabricProbeResumePhysical(GPU_FABRIC_PROBE_INFO_PHYSICAL *pGpuFabricProbeInfoPhysical, NvU32 newBwMode);
void gpuFabricProbeSuspend(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
void gpuFabricProbeInvalidate(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);

4
src/nvidia/inc/kernel/gpu/gpu_timeout.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -45,7 +45,7 @@ struct OBJGPU;
#define GPU_TIMEOUT_FLAGS_DEFAULT NVBIT(0) //!< default timeout mechanism as set by platform
#define GPU_TIMEOUT_FLAGS_USE_THREAD_STATE NVBIT(1) //!< default timeout time used - use the ThreadState
#define GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE NVBIT(2) //!< even if default time was used - skip the ThreadState
#define GPU_TIMEOUT_FLAGS_OSTIMER NVBIT(3) //!< osGetCurrentTime()
#define GPU_TIMEOUT_FLAGS_OSTIMER NVBIT(3) //!< osGetSystemTime()
#define GPU_TIMEOUT_FLAGS_OSDELAY NVBIT(4) //!< osDelay()
#define GPU_TIMEOUT_FLAGS_TMR NVBIT(5) //!< tmrGetCurrentTime()
#define GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG NVBIT(6) //!< bypass timeout logging in the RM journal

20
src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -69,17 +69,21 @@
#define GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE ((48 << 10) * 2048) // Support 2048 channels
#if RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
#define BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA (12u)
#define BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA (13u)
#define BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA (10u)
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT \
((581u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA)) << 20)
#define GSP_FW_HEAP_SIZE_VGPU_48VMS \
((1370u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA)) << 20)
#else
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (581 << 20)
// for more information on how these values are calculated, refer to init_partition.h where
// the breakdown of formula is included. The asserts describe the values needed.
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (581 << 20)
#define GSP_FW_HEAP_SIZE_VGPU_48VMS (1370u << 20)
#endif // RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
// Min/max bounds for heap size override by regkey
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB (64u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB (256u)
@@ -97,12 +101,16 @@
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB \
(581u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA))
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB \
(1093u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA))
#else
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB (88u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB (280u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB (581u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB (1093u)
#endif // RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB (1040u)
#endif // GSP_FW_HEAP_H

4
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
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@@ -164,6 +164,8 @@ typedef struct GspStaticConfigInfo_t
EcidManufacturingInfo ecidInfo[MAX_GROUP_COUNT];
FW_WPR_LAYOUT_OFFSET fwWprLayoutOffset;
NvBool bSystemRebootRequired;
} GspStaticConfigInfo;
// Pushed from CPU-RM to GSP-RM
@@ -203,6 +205,7 @@ typedef struct GspSystemInfo
BUSINFO chipsetIDInfo;
ACPI_METHOD_DATA acpiMethodData;
NvU32 hypervisorType;
NvU16 virtualConfigBits;
NvBool bIsPassthru;
NvU64 sysTimerOffsetNs;
GSP_VF_INFO gspVFInfo;
@@ -217,6 +220,7 @@ typedef struct GspSystemInfo
NvBool bClockBoostSupported;
NvU64 hostPageSize;
NvBool bIsCmcBasedHws;
NvBool bGspNocatEnabled;
} GspSystemInfo;

73
src/nvidia/inc/kernel/gpu/hfrp/kern_hfrp_commands_responses.h Normal file
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@@ -0,0 +1,73 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _KERN_HFRP_COMMANDS_RESPONSES_H_
#define _KERN_HFRP_COMMANDS_RESPONSES_H_
#include "nvtypes.h"
// default parameter values
#define HFRP_DEFAULT_CLIENT_VERSION 0U
#define HFRP_DEFAULT_SERVER_VERSION 0U
/*!
* CMD_SOC_SET_DEVICE_POWER_STATE
*
* This command sets device power state for Nvidia IPs.
* It is expected that HFRP will follow device power state handling sequence specific to each device.
*
* Command Params:
* deviceId
* Specifies the device ID whose power state needs to be changed.
* 0 - iGPU (This includes iGPU and Display)
* 1 - DLA
* 2 - HDA
* powerState
* 0 - D0 i.e. Power up
* 1 - D3 i.e. Power down
*
*/
#define HFRP_CMD_SOC_SET_DEVICE_POWER_STATE 303U
#pragma pack(1)
typedef struct
{
NvU8 deviceId;
NvU8 powerState;
} CMD_SOC_SET_DEVICE_POWER_STATE_PARAMS;
#pragma pack()
#define NV_CMD_SOC_SET_DEVICE_POWER_STATE_PARAM_DEVICE_ID_IGPU 0U
#define NV_CMD_SOC_SET_DEVICE_POWER_STATE_PARAM_DEVICE_ID_DLA 1U
#define NV_CMD_SOC_SET_DEVICE_POWER_STATE_PARAM_DEVICE_ID_HDA 2U
#define NV_CMD_SOC_SET_DEVICE_POWER_STATE_PARAM_POWER_STATE_D0 0U
#define NV_CMD_SOC_SET_DEVICE_POWER_STATE_PARAM_POWER_STATE_D3 1U
#endif // _KERN_HFRP_COMMANDS_RESPONSES_H_

130
src/nvidia/inc/kernel/gpu/hfrp/kern_hfrp_common.h Normal file
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@@ -0,0 +1,130 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _KERN_HFRP_COMMON_H_
#define _KERN_HFRP_COMMON_H_
#include "nvtypes.h"
typedef enum
{
HFRP_COMMAND_MAILBOX_INDEX_PMU = 0,
HFRP_RESPONSE_MAILBOX_INDEX_PMU = 1,
HFRP_COMMAND_MAILBOX_INDEX_SHIM = 2,
HFRP_RESPONSE_MAILBOX_INDEX_SHIM = 2,
HFRP_COMMAND_MAILBOX_INDEX_DISPLAY = 3,
HFRP_RESPONSE_MAILBOX_INDEX_DISPLAY = 4
} HFRP_MAILBOX_INDEX;
// Size of range of registers for which the aperture is created
#define HFRP_MAILBOX_ACCESS_RANGE 0x200
// Mailbox Layout Address Offsets 1.0 version
// Mailbox Layout Address Offsets 1.0 version
#define HFRP_COMMAND_BUFFER_HEAD_PTR_ADDR_ONE_MAILBOX_INTERFACE 0x110
#define HFRP_COMMAND_BUFFER_TAIL_PTR_ADDR_ONE_MAILBOX_INTERFACE 0x189
#define HFRP_COMMAND_BUFFER_START_ADDR_ONE_MAILBOX_INTERFACE 0x114
#define HFRP_COMMAND_BUFFER_END_ADDR_ONE_MAILBOX_INTERFACE 0x187
#define HFRP_RESPONSE_BUFFER_HEAD_PTR_ADDR_ONE_MAILBOX_INTERFACE 0x188
#define HFRP_RESPONSE_BUFFER_TAIL_PTR_ADDR_ONE_MAILBOX_INTERFACE 0x111
#define HFRP_RESPONSE_BUFFER_START_ADDR_ONE_MAILBOX_INTERFACE 0x18C
#define HFRP_RESPONSE_BUFFER_END_ADDR_ONE_MAILBOX_INTERFACE 0x1FF
#define HFRP_COMMAND_BUFFER_HEAD_PTR_ADDR_TWO_MAILBOX_INTERFACE 0x110
#define HFRP_COMMAND_BUFFER_TAIL_PTR_ADDR_TWO_MAILBOX_INTERFACE (0x111 + HFRP_MAILBOX_ACCESS_RANGE)
#define HFRP_COMMAND_BUFFER_START_ADDR_TWO_MAILBOX_INTERFACE 0x114
#define HFRP_COMMAND_BUFFER_END_ADDR_TWO_MAILBOX_INTERFACE 0x1FF
#define HFRP_RESPONSE_BUFFER_HEAD_PTR_ADDR_TWO_MAILBOX_INTERFACE (0x110 + HFRP_MAILBOX_ACCESS_RANGE)
#define HFRP_RESPONSE_BUFFER_TAIL_PTR_ADDR_TWO_MAILBOX_INTERFACE 0x111
#define HFRP_RESPONSE_BUFFER_START_ADDR_TWO_MAILBOX_INTERFACE (0x114 + HFRP_MAILBOX_ACCESS_RANGE)
#define HFRP_RESPONSE_BUFFER_END_ADDR_TWO_MAILBOX_INTERFACE (0x1FF + HFRP_MAILBOX_ACCESS_RANGE)
#define HFRP_IRQ_IN_SET_ADDR 0x100
#define HFRP_IRQ_OUT_SET_ADDR 0x104
#define HFRP_IRQ_IN_CLR_ADDR 0x108
#define HFRP_IRQ_OUT_CLR_ADDR 0x10C
// Size of message (command or response) header in bytes
#define HFRP_MESSAGE_HEADER_BYTE_SIZE 4U
#define HFRP_MESSAGE_FIELD_SIZE 7U : 0U
#define HFRP_MESSAGE_FIELD_SEQUENCE_ID 17U : 8U
#define HFRP_MESSAGE_FIELD_INDEX_OR_STATUS 27U : 18U
//
// Maximum values of Sequence Id index and Sequence Id Array index (each
// Sequence Id array element has 32 bits that represent 32 Sequence Ids)
//
#define HFRP_NUMBER_OF_SEQUENCEID_INDEX 0x400
#define HFRP_NUMBER_OF_SEQUENCEID_ARRAY_INDEX (HFRP_NUMBER_OF_SEQUENCEID_INDEX / 32U)
#define HFRP_ASYNC_NOTIFICATION_SEQUENCEID_INDEX 0x3FF
// HFRP IRQ Reset and Doorbell bit indices
#define HFRP_IRQ_RESET_BIT_INDEX 0U
#define HFRP_IRQ_DOORBELL_BIT_INDEX 1U
// Mailbox Interface types
#define HFRP_ONE_MAILBOX_INTERFACE 0U
#define HFRP_TWO_MAILBOX_INTERFACE 1U
// Mailbox flags
#define HFRP_COMMAND_MAILBOX_FLAG 0U
#define HFRP_RESPONSE_MAILBOX_FLAG 1U
// macros for supporting DRF operations
#define NV_HFRP_BYTE_FIELD(x) (8U * (x) + 7U) : (8U * (x))
typedef struct
{
NvU32 hfrpCommandBufferHeadPtrAddr;
NvU32 hfrpCommandBufferTailPtrAddr;
NvU32 hfrpCommandBufferStartAddr;
NvU32 hfrpCommandBufferEndAddr;
NvU32 hfrpResponseBufferHeadPtrAddr;
NvU32 hfrpResponseBufferTailPtrAddr;
NvU32 hfrpResponseBufferStartAddr;
NvU32 hfrpResponseBufferEndAddr;
NvU32 hfrpIrqInSetAddr;
NvU32 hfrpIrqOutSetAddr;
NvU32 hfrpIrqInClrAddr;
NvU32 hfrpIrqOutClrAddr;
} HFRP_MAILBOX_IO_INFO;
typedef struct
{
NvU32 sequenceIdState[HFRP_NUMBER_OF_SEQUENCEID_ARRAY_INDEX];
NvU8 *pResponsePayloadArray[HFRP_NUMBER_OF_SEQUENCEID_INDEX];
NvU16 *pResponseStatusArray[HFRP_NUMBER_OF_SEQUENCEID_INDEX];
NvU32 *pResponsePayloadSizeArray[HFRP_NUMBER_OF_SEQUENCEID_INDEX];
NV_STATUS *pStatusArray[HFRP_NUMBER_OF_SEQUENCEID_INDEX];
NvU8 sequenceIdArrayIndex;
} HFRP_SEQUENCEID_INFO;
typedef struct
{
HFRP_MAILBOX_IO_INFO mailboxIoInfo;
HFRP_SEQUENCEID_INFO sequenceIdInfo;
} HFRP_INFO;
#endif // _KERN_HFRP_COMMON_H_

117
src/nvidia/inc/kernel/gpu/hfrp/kernel_hfrp.h Normal file
View File

@@ -0,0 +1,117 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "g_kernel_hfrp_nvoc.h"
#ifndef _KERNELHFRP_H_
#define _KERNELHFRP_H_
#include "nvtypes.h"
#include "nvstatus.h"
#include "nvmisc.h"
#include "utils/nvprintf.h"
#include "os/os.h"
#include "gpu/eng_state.h"
#include "gpu/gpu.h"
#include "gpu/hfrp/kern_hfrp_common.h"
// Total number of HFRP Mailboxes available for the interface
#define HFRP_NUMBER_OF_MAILBOXES 2U
// Maximum Payload size for a message
#define HFRP_MAX_PAYLOAD_SIZE 50U
#define HFRP_COMMAND_MAILBOX_INDEX HFRP_COMMAND_MAILBOX_INDEX_DISPLAY
#define HFRP_RESPONSE_MAILBOX_INDEX HFRP_RESPONSE_MAILBOX_INDEX_DISPLAY
//
// Maximum values of Sequence Id index and Sequence Id Array index (each
// Sequence Id array element has 32 bits that represent 32 Sequence Ids)
//
#define HFRP_NUMBER_OF_SEQUENCEID_INDEX 0x400
#define HFRP_NUMBER_OF_SEQUENCEID_ARRAY_INDEX (HFRP_NUMBER_OF_SEQUENCEID_INDEX / 32U)
#define HFRP_ASYNC_NOTIFICATION_SEQUENCEID_INDEX 0x3FF
NVOC_PREFIX(khfrp) class KernelHFRP: OBJENGSTATE
{
public:
/*! HFRP Create Object */
virtual NV_STATUS khfrpStatePreInitLocked(OBJGPU *pGpu, KernelHFRP *pHfrp);
virtual NV_STATUS khfrpConstructEngine(OBJGPU *pGpu, KernelHFRP *pHfrp, ENGDESCRIPTOR engDesc);
/*! HFRP Destructor */
void khfrpDestruct(KernelHFRP *pHfrp);
void khfrpCommonConstruct(KernelHFRP *pHfrp);
NV_STATUS khfrpIoApertureConstruct(OBJGPU *pGpu, KernelHFRP *pHfrp);
void khfrpIoApertureDestruct(KernelHFRP *pHfrp, NvU32 index);
NvU32 khfrpReadBit(KernelHFRP *pHfrp, NvU32 virtualAddr, NvU32 bitIndex);
void khfrpWriteBit(KernelHFRP *pHfrp, NvU32 virtualAddr, NvU32 bitIndex, NvU32 data);
NV_STATUS khfrpMailboxQueueMessage(KernelHFRP *pHfrp, NvU32 messageHeader, NvU8 *pPayloadArray,
NvU32 payloadSize, NvU32 mailboxFlag);
void khfrpServiceEvent(KernelHFRP *pHfrp);
NvU32 khfrpAllocateSequenceId(KernelHFRP *pHfrp, NvU16 *pResponseStatus, void *pResponsePayload,
NvU32 *pResponsePayloadSize, NV_STATUS *pStatus, NvU32 *pSequenceId);
void khfrpFreeSequenceId(KernelHFRP *pHfrp, NvU32 index);
NvBool khfrpIsSequenceIdFree(KernelHFRP *pHfrp, NvU32 index);
NV_STATUS khfrpPollOnIrqWrapper(KernelHFRP *pHfrp, NvU32 irqRegAddr, NvU32 bitIndex, NvBool bData);
NV_STATUS khfrpPollOnIrqRm(KernelHFRP *pHfrp, NvU32 irqRegAddr, NvU32 bitIndex, NvBool bData);
NV_STATUS khfrpPostCommandBlocking(KernelHFRP *pHfrp, NvU16 commandIndex, void *pCommandPayload, NvU32 commandPayloadSize,
NvU16 *pResponseStatus, void *pResponsePayload, NvU32 *pResponsePayloadSize, NV_STATUS *pStatus);
NV_STATUS khfrpInterfaceReset(KernelHFRP *pHfrp);
NVOC_PROPERTY NvBool PDB_PROP_KHFRP_IS_ENABLED;
NvU32 khfrpPrivBase[5];
NvU32 khfrpIntrCtrlReg[5];
IoAperture *pAperture[HFRP_NUMBER_OF_MAILBOXES];
HFRP_INFO khfrpInfo;
};
#define HFRP_REG_RD32(pKernelHfrp, virtualAddr) \
REG_RD32(pKernelHfrp->pAperture[virtualAddr / HFRP_MAILBOX_ACCESS_RANGE], \
virtualAddr % HFRP_MAILBOX_ACCESS_RANGE)
#define HFRP_REG_WR32(pKernelHfrp, virtualAddr, data32) \
REG_WR32(pKernelHfrp->pAperture[virtualAddr / HFRP_MAILBOX_ACCESS_RANGE], \
virtualAddr % HFRP_MAILBOX_ACCESS_RANGE, data32)
#define HFRP_POLL_ON_IRQ(pKernelHfrp, irqRegAddr, bitIndex, bData) \
khfrpPollOnIrqRm(pKernelHfrp, irqRegAddr, bitIndex, bData)
#endif // _KernelHFRP_H_

7
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -78,7 +78,6 @@
#define MC_ENGINE_IDX_NVENC 38
#define MC_ENGINE_IDX_NVENC1 39
#define MC_ENGINE_IDX_NVENC2 40
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define MC_ENGINE_IDX_NVENC3 41
#define MC_ENGINE_IDX_C2C 42
#define MC_ENGINE_IDX_LTC 43
@@ -153,7 +152,6 @@
#define MC_ENGINE_IDX_PXUC 168
#define MC_ENGINE_IDX_SYSLTC 169
#define MC_ENGINE_IDX_LRCC 170
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define MC_ENGINE_IDX_GSPLITE 171
#define MC_ENGINE_IDX_GSPLITE0 MC_ENGINE_IDX_GSPLITE
#define MC_ENGINE_IDX_GSPLITE1 172
@@ -192,10 +190,7 @@
// Index OFA reference
#define MC_ENGINE_IDX_OFA(x) (MC_ENGINE_IDX_OFA0 + (x))
//
// Bug 4175886 - Remove check once GB20X is released
// Index GSPLITE reference
//
#define MC_ENGINE_IDX_GSPLITEn(x) (MC_ENGINE_IDX_GSPLITE + (x))
MAKE_BITVECTOR(MC_ENGINE_BITVECTOR, MC_ENGINE_IDX_MAX);

15
src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -116,13 +116,13 @@
#define READ_CHANNEL_PAYLOAD_SEMA(channel) channelReadChannelMemdesc(channel, channel->finishPayloadOffset)
#define READ_CHANNEL_PB_SEMA(channel) channelReadChannelMemdesc(channel, channel->semaOffset)
//
// This struct contains parameters needed to send a pushbuffer for a CE
// operation. This interface only supports contiguous operations.
//
typedef struct
// This struct contains parameters needed to send a pushbuffer for a CE
// operation. This interface only supports contiguous operations.
//
typedef struct
{
NvBool bCeMemcopy; // Whether this is a CE memcopy;
NvBool bCeMemcopy; // Whether this is a CE memcopy;
// If set to false, this will be a memset operation
NvU64 dstAddr; // Physical address of the source address
NvU64 srcAddr; // Physical address of the source address; only valid for memcopy
@@ -152,11 +152,12 @@ NV_STATUS channelWaitForFreeEntry(OBJCHANNEL *pChannel, NvU32 *pPutIndex);
NV_STATUS channelFillGpFifo(OBJCHANNEL *pChannel, NvU32 putIndex, NvU32 methodsLength);
NvU32 channelFillCePb(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined,
NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo);
NvU32 channelFillPbFastScrub(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined,
NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo);
NV_STATUS channelFillSec2Pb(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bInsertFinishPayload,
CHANNEL_PB_INFO *pChannelPbInfo, CCSL_CONTEXT *pCcslCtx,
CHANNEL_PB_INFO *pChannelPbInfo, CCSL_CONTEXT *pCcslCtx,
MEMORY_DESCRIPTOR *pScrubMemDesc, MEMORY_DESCRIPTOR *pSemaMemDesc,
NvU64 scrubMthdAuthTagBufGpuVA, NvU32 scrubAuthTagBufIndex,
NvU64 semaMthdAuthTagBufGpuVA, NvU32 semaAuthTagBufIndex, NvU32* methodLength);

3
src/nvidia/inc/kernel/gpu/mem_mgr/heap_base.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -117,7 +117,6 @@ typedef struct HWRESOURCE_INFO
NvU32 hwResId;
NvU32 refCount;
NvBool isVgpuHostAllocated; // used in vGPU guest RM to indicate if this HW resource is allocated by host RM or not. Used in Windows guest.
NvBool isGuestAllocated; // used in vGPU host RM to indicate if this HW resource is allocated from LIST_OBJECT path on behalf of Linux guest.
} HWRESOURCE_INFO;

2
src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h
View File

@@ -129,7 +129,7 @@ NV_STATUS scrubberConstruct(struct OBJGPU *pGpu, struct Heap *pHeap);
*
*/
void scrubberDestruct(struct OBJGPU *pGpu, struct Heap *pHeap, OBJMEMSCRUB *pMemscrub);
void scrubberDestruct(struct OBJGPU *pGpu, struct Heap *pHeap);
/**

1
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h
View File

@@ -60,7 +60,6 @@ extern "C" {
#define PMA_LOCALIZED_MEMORY_ALLOC_STRIDE (32ULL * 1024 * 1024)
#define PMA_LOCALIZED_MEMORY_RESERVE_SIZE (2 * PMA_LOCALIZED_MEMORY_ALLOC_STRIDE)
typedef NvU32 PMA_PAGESTATUS;
#define MAP_IDX_ALLOC_UNPIN 0

147
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -41,7 +41,7 @@
#define PHYS_MEM_ALLOCATOR_H
#include "nvport/nvport.h"
#include "regmap.h"
#include "map_defines.h"
#include "nvmisc.h"
#if defined(SRT_BUILD)
@@ -58,10 +58,6 @@ extern "C" {
typedef struct OBJMEMSCRUB OBJMEMSCRUB;
typedef struct SCRUB_NODE SCRUB_NODE;
#define PMA_REGION_SIZE 32
#define PMA_ADDR2FRAME(addr, base) (((addr) - (base)) >> PMA_PAGE_SHIFT)
#define PMA_FRAME2ADDR(frame, base) ((base) + ((frame) << PMA_PAGE_SHIFT))
//
// These flags are used for initialization in order to set global PMA states,
// in case we need to wait for scrubber to be initialized or wait for a NUMA
@@ -109,19 +105,6 @@ typedef struct SCRUB_NODE SCRUB_NODE;
// These are flags input to the pmaFreePages call
#define PMA_FREE_SKIP_SCRUB NVBIT(0)
// State bits for debugging utilities like nvwatch
#define PMA_SCRUB_INITIALIZE 0
#define PMA_SCRUB_IN_PROGRESS 1
#define PMA_SCRUB_DONE 2
#define PMA_SCRUBBER_VALID 1
#define PMA_SCRUBBER_INVALID 0
#define PMA_NUMA_NO_NODE -1
// Maximum blacklist entries possible
#define PMA_MAX_BLACKLIST_ENTRIES 512
typedef struct
{
NvU32 flags;
@@ -180,97 +163,6 @@ typedef NV_STATUS (*pmaEvictPagesCb_t)(void *ctxPtr, NvU64 pageSize, NvU64 *pPag
typedef NV_STATUS (*pmaEvictRangeCb_t)(void *ctxPtr, NvU64 physBegin, NvU64 physEnd,
MEMORY_PROTECTION prot);
/*!
* @brief Pluggable data structure management. Currently we have regmap.
*/
typedef void *(*pmaMapInit_t)(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected);
typedef void (*pmaMapDestroy_t)(void *pMap);
typedef void (*pmaMapChangeStateAttrib_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef void (*pmaMapChangePageStateAttrib_t)(void *pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef void (*pmaMapChangeBlockStateAttrib_t)(void *pMap, NvU64 frameNum, NvU64 numFrames, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef PMA_PAGESTATUS (*pmaMapRead_t)(void *pMap, NvU64 frameNum, NvBool readAttrib);
typedef NV_STATUS (*pmaMapScanContiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 stride, NvU32 strideStart,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
typedef NV_STATUS (*pmaMapScanDiscontiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 stride, NvU32 strideStart,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
typedef void (*pmaMapGetSize_t)(void *pMap, NvU64 *pBytesTotal);
typedef void (*pmaMapGetLargestFree_t)(void *pMap, NvU64 *pLargestFree);
typedef NV_STATUS (*pmaMapScanContiguousNumaEviction_t)(void *pMap, NvU64 addrBase, NvLength actualSize,
NvU64 pageSize, NvU64 *evictStart, NvU64 *evictEnd);
typedef NvU64 (*pmaMapGetEvictingFrames_t)(void *pMap);
typedef void (*pmaMapSetEvictingFrames_t)(void *pMap, NvU64 frameEvictionsInProcess);
struct _PMA_MAP_INFO
{
NvU32 mode;
pmaMapInit_t pmaMapInit;
pmaMapDestroy_t pmaMapDestroy;
pmaMapChangeStateAttrib_t pmaMapChangeStateAttrib;
pmaMapChangePageStateAttrib_t pmaMapChangePageStateAttrib;
pmaMapChangeBlockStateAttrib_t pmaMapChangeBlockStateAttrib;
pmaMapRead_t pmaMapRead;
pmaMapScanContiguous_t pmaMapScanContiguous;
pmaMapScanDiscontiguous_t pmaMapScanDiscontiguous;
pmaMapGetSize_t pmaMapGetSize;
pmaMapGetLargestFree_t pmaMapGetLargestFree;
pmaMapScanContiguousNumaEviction_t pmaMapScanContiguousNumaEviction;
pmaMapGetEvictingFrames_t pmaMapGetEvictingFrames;
pmaMapSetEvictingFrames_t pmaMapSetEvictingFrames;
};
struct _PMA
{
PORT_SPINLOCK *pPmaLock; // PMA-wide lock
PORT_MUTEX *pEvictionCallbacksLock; // Eviction callback registration lock
// Only used when free scrub-on-free feature is turned on
PORT_RWLOCK *pScrubberValidLock; // A reader-writer lock to protect the scrubber valid bit
PORT_MUTEX *pAllocLock; // Used to protect page stealing in the allocation path
// Region related states
NvU32 regSize; // Actual size of regions array
void * pRegions[PMA_REGION_SIZE]; // All the region maps stored as opaque pointers
NvU32 *pSortedFastFirst; // Pre-sorted array of region IDs
PMA_REGION_DESCRIPTOR *pRegDescriptors [PMA_REGION_SIZE]; // Stores the descriptions of each region
PMA_MAP_INFO *pMapInfo; // The pluggable layer for managing scanning
// Allocation related states
void * evictCtxPtr; // Opaque context pointer for eviction callback
pmaEvictPagesCb_t evictPagesCb; // Discontiguous eviction callback
pmaEvictRangeCb_t evictRangeCb; // Contiguous eviction callback
NvU64 frameAllocDemand; // Frame count of allocations in-process
NvBool bForcePersistence; // Force all allocations to persist across suspend/resume
PMA_STATS pmaStats; // PMA statistics used for client heuristics
// Scrubber related states
NvSPtr initScrubbing; // If the init scrubber has finished in this PMA
NvBool bScrubOnFree; // If "scrub on free" is enabled for this PMA object
NvSPtr scrubberValid; // If scrubber object is valid, using atomic variable to prevent races
OBJMEMSCRUB *pScrubObj; // Object to store the FreeScrub header
// NUMA states
NvBool bNuma; // If we are allocating for a NUMA system
NvBool nodeOnlined; // If node is onlined
NvS32 numaNodeId; // Current Node ID, set at initialization. -1 means invalid
NvU64 coherentCpuFbBase; // Used to calculate FB offset from bus address
NvU64 coherentCpuFbSize; // Used for error checking only
NvU32 numaReclaimSkipThreshold; // percent value below which __GFP_RECLAIM will not be used.
NvBool bNumaAutoOnline; // If NUMA memory is auto-onlined
// Blacklist related states
PMA_BLACKLIST_CHUNK *pBlacklistChunks; // Tracking for blacklist pages
NvU32 blacklistCount; // Number of blacklist pages
NvBool bClientManagedBlacklist; // Blacklisted pages in PMA that will be taken over by Client
// RUSD Callback
pmaUpdateStatsCb_t pStatsUpdateCb; // RUSD update free pages
void *pStatsUpdateCtx; // Context for RUSD update
};
/*!
* @brief This must be called before any other PMA functions. Returns a PMA
* object for later use
@@ -289,7 +181,7 @@ struct _PMA
* code, because it is not very informative.
*
*/
NV_STATUS pmaInitialize(PMA *pPma, NvU32 initFlags);
NV_STATUS pmaInitialize(PMA **ppPma, NvU32 initFlags);
/*!
@@ -398,9 +290,6 @@ NV_STATUS pmaRegisterRegion(PMA *pPma, NvU32 id, NvBool bAsyncEccScrub,
* allocation option. For non-contiguous allocations, it's an error to specify
* an alignment larger than the page size.
*
* For broadcast methods, PMA will guarantee the same physical frames are
* allocated on multiple GPUs, specified by the PMA objects passed in.
*
* Implementors note:
* If region registered with asyncEccScrub and pmaScrubComplete
* has not yet been issued then we cannot return NV_ERR_NO_MEMORY.
@@ -461,11 +350,6 @@ NV_STATUS pmaRegisterRegion(PMA *pPma, NvU32 id, NvBool bAsyncEccScrub,
NV_STATUS pmaAllocatePages(PMA *pPma, NvLength pageCount, NvU64 pageSize,
PMA_ALLOCATION_OPTIONS *pAllocationOptions, NvU64 *pPages);
// allocate on multiple GPU, thus pmaCount
NV_STATUS pmaAllocatePagesBroadcast(PMA **pPma, NvU32 pmaCount, NvLength allocationCount,
NvU64 pageSize, PMA_ALLOCATION_OPTIONS *pAllocationOptions, NvU64 *pPages);
/*!
* @brief Marks previously unpinned pages as pinned.
*
@@ -657,6 +541,16 @@ void pmaGetTotalMemory(PMA *pPma, NvU64 *pBytesTotal);
*/
NV_STATUS pmaGetRegionInfo(PMA *pPma, NvU32 *pRegSize, PMA_REGION_DESCRIPTOR **ppRegionDesc);
/*!
* @brief Get the PMA stats object to give to UVM
*
* @param[in] pPma PMA pointer
*
* @return
* PMA_STATS *
*/
PMA_STATS *pmaGetStats(PMA *pPma);
/*!
* @brief Returns information about the total free FB memory.
*
@@ -766,6 +660,16 @@ void pmaFreeAllocatedBlocksList(PMA *pPma, PRANGELISTTYPE *ppList);
*/
NV_STATUS pmaRegMemScrub(PMA *pPma, OBJMEMSCRUB *pScrubObj);
/*!
* @brief Get memory scrubber that PMA currently has (can be NULL)
*
* @param[in] pPma PMA pointer
*
* @return
* OBJMEMSCRUB * pointer to the memory scrubber PMA currently has
*/
OBJMEMSCRUB *pmaGetMemScrub(PMA *pPma);
/*!
* @brief Unregisters the memory scrubber, when the scrubber is torn
@@ -872,11 +776,6 @@ void pmaGetBlacklistSize(PMA *pPma, NvU32 *pDynamicBlacklistSize, NvU32 *pStatic
*/
void pmaClearScrubbedPages(PMA *pPma, SCRUB_NODE *pPmaScrubList, NvU64 count);
/*!
* @brief Print states of all regions
*/
void pmaPrintMapState(PMA *pPma);
/*!
* @brief Track the given physical address as blacklisted page in PMA. This call will blacklist
* the entire PMA page frame of size 64KB which contains the physical address.

150
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_private.h Normal file
View File

@@ -0,0 +1,150 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef PHYS_MEM_ALLOCATOR_PRIVATE_H
#define PHYS_MEM_ALLOCATOR_PRIVATE_H
#include "nvport/nvport.h"
#include "map_defines.h"
#include "nvmisc.h"
#if defined(SRT_BUILD)
#define RMCFG_MODULE_x 1
#define RMCFG_FEATURE_x 1
#else
#include "rmconfig.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
typedef struct OBJMEMSCRUB OBJMEMSCRUB;
typedef struct SCRUB_NODE SCRUB_NODE;
#define PMA_REGION_SIZE 32
#define PMA_NUMA_NO_NODE -1
// Maximum blacklist entries possible
#define PMA_MAX_BLACKLIST_ENTRIES 512
typedef struct _PMA_MAP_INFO PMA_MAP_INFO;
typedef struct _PMA PMA;
/*!
* @brief Pluggable data structure management. Currently we have regmap.
*/
typedef void *(*pmaMapInit_t)(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected);
typedef void (*pmaMapDestroy_t)(void *pMap);
typedef void (*pmaMapChangeStateAttrib_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef void (*pmaMapChangePageStateAttrib_t)(void *pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef void (*pmaMapChangeBlockStateAttrib_t)(void *pMap, NvU64 frameNum, NvU64 numFrames, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef PMA_PAGESTATUS (*pmaMapRead_t)(void *pMap, NvU64 frameNum, NvBool readAttrib);
typedef NV_STATUS (*pmaMapScanContiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 stride, NvU32 strideStart,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
typedef NV_STATUS (*pmaMapScanDiscontiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 stride, NvU32 strideStart,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
typedef void (*pmaMapGetSize_t)(void *pMap, NvU64 *pBytesTotal);
typedef void (*pmaMapGetLargestFree_t)(void *pMap, NvU64 *pLargestFree, NvU64 *pLargestFreeBase);
typedef NV_STATUS (*pmaMapScanContiguousNumaEviction_t)(void *pMap, NvU64 addrBase, NvLength actualSize,
NvU64 pageSize, NvU64 *evictStart, NvU64 *evictEnd);
typedef NvU64 (*pmaMapGetEvictingFrames_t)(void *pMap);
typedef void (*pmaMapSetEvictingFrames_t)(void *pMap, NvU64 frameEvictionsInProcess);
struct _PMA_MAP_INFO
{
NvU32 mode;
pmaMapInit_t pmaMapInit;
pmaMapDestroy_t pmaMapDestroy;
pmaMapChangeStateAttrib_t pmaMapChangeStateAttrib;
pmaMapChangePageStateAttrib_t pmaMapChangePageStateAttrib;
pmaMapChangeBlockStateAttrib_t pmaMapChangeBlockStateAttrib;
pmaMapRead_t pmaMapRead;
pmaMapScanContiguous_t pmaMapScanContiguous;
pmaMapScanDiscontiguous_t pmaMapScanDiscontiguous;
pmaMapGetSize_t pmaMapGetSize;
pmaMapGetLargestFree_t pmaMapGetLargestFree;
pmaMapScanContiguousNumaEviction_t pmaMapScanContiguousNumaEviction;
pmaMapGetEvictingFrames_t pmaMapGetEvictingFrames;
pmaMapSetEvictingFrames_t pmaMapSetEvictingFrames;
};
struct _PMA
{
PORT_SPINLOCK *pPmaLock; // PMA-wide lock
PORT_MUTEX *pEvictionCallbacksLock; // Eviction callback registration lock
// Only used when free scrub-on-free feature is turned on
PORT_RWLOCK *pScrubberValidLock; // A reader-writer lock to protect the scrubber valid bit
PORT_MUTEX *pAllocLock; // Used to protect page stealing in the allocation path
// Region related states
NvU32 regSize; // Actual size of regions array
void * pRegions[PMA_REGION_SIZE]; // All the region maps stored as opaque pointers
NvU32 *pSortedFastFirst; // Pre-sorted array of region IDs
PMA_REGION_DESCRIPTOR *pRegDescriptors [PMA_REGION_SIZE]; // Stores the descriptions of each region
PMA_MAP_INFO *pMapInfo; // The pluggable layer for managing scanning
// Allocation related states
void * evictCtxPtr; // Opaque context pointer for eviction callback
pmaEvictPagesCb_t evictPagesCb; // Discontiguous eviction callback
pmaEvictRangeCb_t evictRangeCb; // Contiguous eviction callback
NvU64 frameAllocDemand; // Frame count of allocations in-process
NvBool bForcePersistence; // Force all allocations to persist across suspend/resume
PMA_STATS pmaStats; // PMA statistics used for client heuristics
// Scrubber related states
NvSPtr initScrubbing; // If the init scrubber has finished in this PMA
NvBool bScrubOnFree; // If "scrub on free" is enabled for this PMA object
NvSPtr scrubberValid; // If scrubber object is valid, using atomic variable to prevent races
OBJMEMSCRUB *pScrubObj; // Object to store the FreeScrub header
// NUMA states
NvBool bNuma; // If we are allocating for a NUMA system
NvBool nodeOnlined; // If node is onlined
NvS32 numaNodeId; // Current Node ID, set at initialization. -1 means invalid
NvU64 coherentCpuFbBase; // Used to calculate FB offset from bus address
NvU64 coherentCpuFbSize; // Used for error checking only
NvU32 numaReclaimSkipThreshold; // percent value below which __GFP_RECLAIM will not be used.
NvBool bNumaAutoOnline; // If NUMA memory is auto-onlined
// Blacklist related states
PMA_BLACKLIST_CHUNK *pBlacklistChunks; // Tracking for blacklist pages
NvU32 blacklistCount; // Number of blacklist pages
NvBool bClientManagedBlacklist; // Blacklisted pages in PMA that will be taken over by Client
// RUSD Callback
pmaUpdateStatsCb_t pStatsUpdateCb; // RUSD update free pages
void *pStatsUpdateCtx; // Context for RUSD update
};
#ifdef __cplusplus
}
#endif
#endif // PHYS_MEM_ALLOCATOR_PRIVATE_H

19
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,6 +33,17 @@
extern "C" {
#endif
#define PMA_ADDR2FRAME(addr, base) (((addr) - (base)) >> PMA_PAGE_SHIFT)
#define PMA_FRAME2ADDR(frame, base) ((base) + ((frame) << PMA_PAGE_SHIFT))
// State bits
#define PMA_SCRUB_INITIALIZE 0
#define PMA_SCRUB_IN_PROGRESS 1
#define PMA_SCRUB_DONE 2
#define PMA_SCRUBBER_VALID 1
#define PMA_SCRUBBER_INVALID 0
// TODO See if this can be added to NvPort
#define pmaPortAtomicGet(ptr) portAtomicOrSize((ptr), 0)
@@ -183,16 +194,12 @@ void pmaFreeList(PMA *pPma, PRANGELISTTYPE *ppList);
* @param[in] physAddrBase The base address of this address tree
* @param[in] pBlacklistPageBase Structure that contains the blacklisted pages
* @param[in] blacklistCount Number of blacklisted pages
* @param[in] bBlacklistFromInforom Whether the blacklisted pages are coming from
* inforom (i.e., from heap/PMA init) or not
* (i.e., from ECC interrupt handling)
*
* @return NV_OK
* NV_ERR_NO_MEMORY if memory allocation fails
*/
NV_STATUS pmaRegisterBlacklistInfo(PMA *pPma, NvU64 physAddrBase,
PPMA_BLACKLIST_ADDRESS pBlacklistPageBase, NvU32 blacklistCount,
NvBool bBlacklistFromInforom);
PPMA_BLACKLIST_ADDRESS pBlacklistPageBase, NvU32 blacklistCount);
/*!
* @brief Query blacklisting states tracked by PMA

6
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -229,9 +229,9 @@ void pmaRegmapGetSize(void *pMap, NvU64 *pBytesTotal);
*
* @param[in] pMap Pointer to the regmap for the region
* @param[in] pLargestFree Pointer that will return largest free in current region.
*
* @param[in] pLargestFreeOffset Pointer that will return the offset of the largest free chunk.
*/
void pmaRegmapGetLargestFree(void *pMap, NvU64 *pLargestFree);
void pmaRegmapGetLargestFree(void *pMap, NvU64 *pLargestFree, NvU64 *pLargestFreeOffset);
/*!

2
src/nvidia/inc/kernel/gpu/mem_mgr/rm_page_size.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

21
src/nvidia/inc/kernel/gpu/nvlink/common_nvlink.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,9 +27,28 @@
#include "core/core.h"
#include "kernel/gpu/nvlink/kernel_nvlink.h"
#include "kernel/gpu/nvlink/kernel_ioctrl.h"
#include "utils/nvbitvector.h"
#include "ctrl/ctrl2080/ctrl2080nvlink.h" // rmcontrol params
MAKE_BITVECTOR(NV2080_NVLINK_BIT_VECTOR, NV2080_CTRL_NVLINK_MAX_LINKS);
NV_STATUS nvlinkCtrlCmdBusGetNvlinkCaps(OBJGPU *pGpu, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams);
NV_STATUS
convertMaskToBitVector(NvU64 inputLinkMask, NV2080_NVLINK_BIT_VECTOR *pLocalLinkMask);
NV_STATUS
convertBitVectorToLinkMask32(NV2080_NVLINK_BIT_VECTOR *pBitVector, NvU32 *linkMask);
NV_STATUS
convertBitVectorToLinkMasks(NV2080_NVLINK_BIT_VECTOR *pLocalLinkMask,
void *pOutputLinkMask1, NvU32 outputLinkMask1Size,
NV2080_CTRL_NVLINK_LINK_MASK *pOutputLinkMask2);
NV_STATUS
convertLinkMasksToBitVector(const void *pLinkMask1, NvU32 linkMask1Size,
const NV2080_CTRL_NVLINK_LINK_MASK *pLinkMask2,
NV2080_NVLINK_BIT_VECTOR *pOutputBitVector);
#endif // COMMON_NVLINK_H

92
src/nvidia/inc/kernel/gpuvideo/rmifvideng.h Normal file
View File

@@ -0,0 +1,92 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef RMIFVIDENG_H
#define RMIFVIDENG_H
/*!
* @file rmifvideng.h
* @brief RISC-V boot arguments / interface
*/
#include <nvtypes.h>
/*!
* Video engine's frame-buffer interface block has several slots/indices which can
* be bound to support DMA to various surfaces in memory. This is an
* enumeration that gives name to each index based on type of memory-aperture
* the index is used to access.
*
* Traditionally, video falcons have used the 6th index for ucode, and we will
* continue to use that to allow legacy ucode to work seamlessly.
*
* Note: DO NOT CHANGE THE VALUE OF RM_VIDENG_DMAIDX_UCODE. That value is used by
* both the legacy video ucode, which assumes that it will use index 6, and by
* msdecos. Changing it will break legacy video ucode, unless it is updated to
* reflect the new value.
*/
typedef enum _RM_VIDENG_DMAIDX_TYPE
{
RM_VIDENG_DMAIDX_RSVD0 = 0,
RM_VIDENG_DMAIDX_VIRT = 1,
RM_VIDENG_DMAIDX_PHYS_VID = 2,
RM_VIDENG_DMAIDX_PHYS_SYS_COH = 3,
RM_VIDENG_DMAIDX_PHYS_SYS_NCOH = 4,
RM_VIDENG_DMAIDX_RSVD1 = 5,
RM_VIDENG_DMAIDX_UCODE = 6,
RM_VIDENG_DMAIDX_END = 7
} RM_VIDENG_DMAIDX_TYPE;
/*!
* Configuration for riscv msdecos boot params
*/
#define NV_VIDENG_BOOT_PARAMS_VERSION 2
#define NV_VIDENG_BOOT_PARAMS_MEM_ADDR_LO 31:0
#define NV_VIDENG_BOOT_PARAMS_MEM_ADDR_HI 27:0
#define NV_VIDENG_BOOT_PARAMS_MEM_DMA_IDX 31:28
#define NV_VIDENG_TRACESURF_PARAMS_SIZE 27:0
#define NV_VIDENG_TRACESURF_PARAMS_DMA_IDX 31:28
typedef struct
{
/*
* *** WARNING ***
* First 3 fields must be frozen like that always. Should never
* be reordered or changed.
*/
NvU8 version; // version of boot params
NvU8 rsvd; // reserved byte
NvU16 size; // size of boot params
/*
* You can reorder or change below this point but update version.
* Make sure to align it to 16B as ucode expect 16byte alignment to DMA efficiently.
*/
NvU32 videoPgPmuHandshake; // Handshake between PMU and Video Ucode for SW controlled IDLE signal.
NvU64 rsvd2; // reserved field
} NV_VIDENG_BOOT_PARAMS, *PNV_VIDENG_BOOT_PARAMS;
#endif // RMIFVIDENG_H

4
src/nvidia/inc/kernel/mem_mgr/p2p.h
View File

@@ -27,8 +27,8 @@
#include "core/core.h"
NV_STATUS RmP2PGetPages (NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, OBJGPU **, void *, void (*)(void *), void *);
NV_STATUS RmP2PGetPagesWithoutCallbackRegistration (NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, OBJGPU **, void *);
NV_STATUS RmP2PGetPagesPersistent (NvU64, NvU64, void **, NvU64 *, NvU32 *, NvBool, void *, void *, void **);
NV_STATUS RmP2PGetPagesWithoutCallbackRegistration (NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvBool *, OBJGPU **, void *);
NV_STATUS RmP2PGetPagesPersistent (NvU64, NvU64, void **, NvU64 *, NvU32 *, NvBool *, NvBool, void *, void *, void **);
NV_STATUS RmP2PRegisterCallback (NvU64, NvU64, NvU64, void *, void (*)(void *), void *);
NV_STATUS RmP2PPutPages (NvU64, NvU32, NvU64, void *);
NV_STATUS RmP2PGetGpuByAddress (NvU64, NvU64, OBJGPU **);

12
src/nvidia/inc/kernel/rmapi/control.h
View File

@@ -364,18 +364,6 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *pParamCopy, RmCtrlParams *pRmC
// is enabled; see g_bRsAccessEnabled.
//
/*
* On T234, RM is in kernel mode, so when RM is running in kernel mode it
* does not allow usermode clients like MODs to call control calls that are
* marked as KERNEL_PRIVILEGED.
* So defining new macro DISPLAY_PRIVILEGED(i.e PRIVILEGED) for Tegra and mark
* control calls needed by MODs with this so that MODs running as root can call
* these control calls. However keeping same privilege level for DGPUs which
* does not change the current behaviour.
*/
#define DISPLAY_PRIVILEGED KERNEL_PRIVILEGED
#endif // _CONTROL_H_

6
src/nvidia/inc/kernel/rmapi/mapping_list.h
View File

@@ -28,6 +28,7 @@
#include "gpu/mem_mgr/mem_desc.h"
#include "os/os.h"
#include "rmapi/resource.h"
#include "mmu/gmmu_fmt.h" // GMMU_APERTURE
typedef struct VirtualMemory VirtualMemory;
typedef struct Memory Memory;
@@ -57,9 +58,12 @@ struct _def_client_dma_mapping_info
NvU64 FbApertureLen[NV_MAX_SUBDEVICES]; // GPU aperture mapped lengths
MEMORY_DESCRIPTOR *pMemDesc; // Subregion to be mapped
NvU32 Flags;
NvU32 Flags2;
NvBool bP2P;
NvU32 gpuMask;
NvU64 mapPageSize; // Page size at which the memory is mapped.
GMMU_APERTURE aperture;
NvBool bNeedL2InvalidateAtUnmap;
ADDRESS_TRANSLATION addressTranslation;
MEMORY_DESCRIPTOR *pBar1P2PVirtMemDesc; // The peer GPU mapped BAR1 region
MEMORY_DESCRIPTOR *pBar1P2PPhysMemDesc; // The peer GPU vidmem sub region
@@ -163,7 +167,7 @@ CliUpdateDeviceMemoryMapping
RsCpuMapping *CliFindMappingInClient (NvHandle, NvHandle, NvP64);
// DMA Mappings
NV_STATUS intermapCreateDmaMapping (RsClient *, VirtualMemory *, PCLI_DMA_MAPPING_INFO *, NvU32);
NV_STATUS intermapCreateDmaMapping (RsClient *, VirtualMemory *, PCLI_DMA_MAPPING_INFO *, NvU32, NvU32);
NV_STATUS intermapRegisterDmaMapping (RsClient *, VirtualMemory *, PCLI_DMA_MAPPING_INFO, NvU64, NvU32);
NV_STATUS intermapDelDmaMapping (RsClient *, VirtualMemory *, NvU64, NvU32);
void intermapFreeDmaMapping (PCLI_DMA_MAPPING_INFO);

1
src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h
View File

@@ -35,6 +35,7 @@
#define _NV_GPU_OPS_H_
#include "nvgputypes.h"
#include "nv_uvm_types.h"
#include "nv_uvm_user_types.h"
typedef struct gpuSession *gpuSessionHandle;
typedef struct gpuDevice *gpuDeviceHandle;

17
src/nvidia/inc/kernel/rmapi/rmapi.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -39,7 +39,7 @@ typedef struct CALL_CONTEXT CALL_CONTEXT;
typedef struct MEMORY_DESCRIPTOR MEMORY_DESCRIPTOR;
typedef struct RS_RES_FREE_PARAMS_INTERNAL RS_RES_FREE_PARAMS_INTERNAL;
typedef struct RS_LOCK_INFO RS_LOCK_INFO;
typedef struct NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS;
typedef struct NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS;
typedef NvU32 NV_ADDRESS_SPACE;
extern RsServer g_resServ;
@@ -249,20 +249,17 @@ struct _RM_API
NvP64 pLinearAddress, NvU32 flags, NvU32 ProcessId, API_SECURITY_INFO *pSecInfo);
// Map dma memory with default security attributes. Provides RM internal implementation for NvRmMapMemoryDma().
NV_STATUS (*Map)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, NvHandle hMemory,
NvU64 offset, NvU64 length, NvU32 flags, NvU64 *pDmaOffset);
NV_STATUS (*Map)(struct _RM_API *pRmApi, NVOS46_PARAMETERS *pParms);
// Map dma memory. Provides RM internal implementation for NvRmMapMemoryDma().
NV_STATUS (*MapWithSecInfo)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, NvHandle hMemory,
NvU64 offset, NvU64 length, NvU32 flags, NvU64 *pDmaOffset, API_SECURITY_INFO *pSecInfo);
NV_STATUS (*MapWithSecInfo)(struct _RM_API *pRmApi, NVOS46_PARAMETERS *pParms, API_SECURITY_INFO *pSecInfo);
// Unmap dma memory with default security attributes
NV_STATUS (*Unmap)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx,
NvU32 flags, NvU64 dmaOffset, NvU64 size);
NV_STATUS (*Unmap)(struct _RM_API *pRmApi, NVOS47_PARAMETERS *pParms);
// Unmap dma memory
NV_STATUS (*UnmapWithSecInfo)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx,
NvU32 flags, NvU64 dmaOffset, NvU64 size, API_SECURITY_INFO *pSecInfo);
NV_STATUS (*UnmapWithSecInfo)(struct _RM_API *pRmApi, NVOS47_PARAMETERS *pParms, API_SECURITY_INFO *pSecInfo);
API_SECURITY_INFO defaultSecInfo;
NvBool bHasDefaultSecInfo;

14
src/nvidia/inc/kernel/rmapi/rmapi_cache_handlers.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -54,6 +54,18 @@ typedef struct DispSystemGetInternalDisplaysCacheEntry
NV_STATUS _dispSystemGetInternalDisplaysCacheHandler(void *cachedEntry, void* pParams, NvBool bSet);
typedef struct DispDpGetCapsCacheTable
{
// Indexed by sorIndex parameter.
struct
{
NvBool valid;
NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS params;
} cachedEntries[NV_MAX_DEVICES];
} DispDpGetCapsCacheTable;
NV_STATUS _dispDpGetCapsCacheHandler(void *cachedEntry, void *pProvidedParams, NvBool bSet);
typedef struct DispSpecificGetTypeCacheTable
{
struct

2
src/nvidia/inc/kernel/rmapi/rmapi_utils.h
View File

@@ -62,6 +62,6 @@ NvBool rmapiutilIsExternalClassIdInternalOnly(NvU32 externalClassId);
NV_STATUS rmapiutilGetControlInfo(NvU32 cmd, NvU32 *pFlags,
NvU32 *pAccessRight, NvU32 *pParamsSize);
NvBool rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(NvU32 cmd);
NvBool rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(OBJGPU *pGpu, NvU32 cmd);
#endif /* RMAPI_UTILS_H */

16
src/nvidia/inc/kernel/spdm/bin/blackwell/gb100_l2_cert.pem.bin Normal file
View File

@@ -0,0 +1,16 @@
-----BEGIN CERTIFICATE-----
MIICijCCAhCgAwIBAgIQV7ceDOVWAwo2pOUrTKlfHjAKBggqhkjOPQQDAzA1MSIw
IAYDVQQDDBlOVklESUEgRGV2aWNlIElkZW50aXR5IENBMQ8wDQYDVQQKDAZOVklE
SUEwIBcNMjMwMTAxMDAwMDAwWhgPOTk5OTEyMzEyMzU5NTlaMD0xHjAcBgNVBAMM
FU5WSURJQSBHQjEwMCBJZGVudGl0eTEbMBkGA1UECgwSTlZJRElBIENvcnBvcmF0
aW9uMHYwEAYHKoZIzj0CAQYFK4EEACIDYgAE/XKlEaBWlqMDj+rpBFEjY2LYS+Ja
iRyYigtuUNpFRia3nsWoBwewhLA1wrw56KAGDXInX5Yde14hqPXCgjUzNkbN5mrC
mya7oXdUtVYA186E9LlPsm8YEwiPaDd/3Vl8o4HaMIHXMA8GA1UdEwEB/wQFMAMB
Af8wDgYDVR0PAQH/BAQDAgEGMDsGA1UdHwQ0MDIwMKAuoCyGKmh0dHA6Ly9jcmwu
bmRpcy5udmlkaWEuY29tL2NybC9sMS1yb290LmNybDA3BggrBgEFBQcBAQQrMCkw
JwYIKwYBBQUHMAGGG2h0dHA6Ly9vY3NwLm5kaXMubnZpZGlhLmNvbTAdBgNVHQ4E
FgQU7alkfWRaPz2txrnrZMNbkhuk4AIwHwYDVR0jBBgwFoAUV4X/g/JjzGV9aLc6
W/SNSsv7SV8wCgYIKoZIzj0EAwMDaAAwZQIwSDCBZ6OhBe4gV1ueWUwYAeDI/LAj
S8GSEh5PxCwiHMs1EYcOGlCX2e/RlJ8lDFuGAjEAwFOOiBjvktWQP8Fgj7hGefny
JPhnEXLwVYUemI4ejiPsua4GKin56ip9ZoEHdBUQ
-----END CERTIFICATE-----

17
src/nvidia/inc/kernel/spdm/bin/blackwell/gb100_l3_cert.pem.bin Normal file
View File

@@ -0,0 +1,17 @@
-----BEGIN CERTIFICATE-----
MIICrjCCAjOgAwIBAgIQXYBfwgLOvCcgRkD8IC+BhTAKBggqhkjOPQQDAzA9MR4w
HAYDVQQDDBVOVklESUEgR0IxMDAgSWRlbnRpdHkxGzAZBgNVBAoMEk5WSURJQSBD
b3Jwb3JhdGlvbjAgFw0yMzA2MjAwMDAwMDBaGA85OTk5MTIzMTIzNTk1OVowVzEr
MCkGA1UEAwwiTlZJRElBIEdCMTAwIFByb3Zpc2lvbmVyIElDQSAwMDAwMDEbMBkG
A1UECgwSTlZJRElBIENvcnBvcmF0aW9uMQswCQYDVQQGEwJVUzB2MBAGByqGSM49
AgEGBSuBBAAiA2IABBdKHmiD7JKUIKnyKTdLazbcVBj9HMpHaOE9nEcQvoeoZeHn
V1Gc+SwOvxtMl7tckYLx4BQLEs/AXWYx0hAVleVP3krbeIfWtmEwsPa9IQQ4APpH
OYZp9QwBoYHNcci9c6OB2zCB2DAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQE
AwIBBjA8BgNVHR8ENTAzMDGgL6AthitodHRwOi8vY3JsLm5kaXMubnZpZGlhLmNv
bS9jcmwvbDItZ2IxMDAuY3JsMDcGCCsGAQUFBwEBBCswKTAnBggrBgEFBQcwAYYb
aHR0cDovL29jc3AubmRpcy5udmlkaWEuY29tMB0GA1UdDgQWBBQD78BUvvHZTb1l
s+d0V1ySn+B2RTAfBgNVHSMEGDAWgBTtqWR9ZFo/Pa3Guetkw1uSG6TgAjAKBggq
hkjOPQQDAwNpADBmAjEA8M2NglY92IX9SQrtvdfMTxl4A02CqLHZeleuBHgRX7Mn
5C7jfE5c23Ejl0j1JnB1AjEAt+tHqjht6MbZJtLX/09pFnFgcTHG0erYR8v375gq
iC3QSP6Khjum4ukzH0KV6JRm
-----END CERTIFICATE-----

17
src/nvidia/inc/kernel/spdm/bin/blackwell/gb102_l3_cert.pem.bin Normal file
View File

@@ -0,0 +1,17 @@
-----BEGIN CERTIFICATE-----
MIICrjCCAjOgAwIBAgIQTDp9bo1x/07B53iQ9bQY4TAKBggqhkjOPQQDAzA9MR4w
HAYDVQQDDBVOVklESUEgR0IxMDAgSWRlbnRpdHkxGzAZBgNVBAoMEk5WSURJQSBD
b3Jwb3JhdGlvbjAgFw0yMzA2MjAwMDAwMDBaGA85OTk5MTIzMTIzNTk1OVowVzEr
MCkGA1UEAwwiTlZJRElBIEdCMTAyIFByb3Zpc2lvbmVyIElDQSAwMDAwMDEbMBkG
A1UECgwSTlZJRElBIENvcnBvcmF0aW9uMQswCQYDVQQGEwJVUzB2MBAGByqGSM49
AgEGBSuBBAAiA2IABLlIHvkR1rnCQy6LP8vt7ac61aQUucck4u5ewFTN+PQT5BzJ
fUNil1O0Xa+Fj0E0kJWujR+nRmRGSt2dEHzicwwUb5c3rbGv5GuVtVcou7nH4OAg
wlbuqcSd63tE1VsbNqOB2zCB2DAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQE
AwIBBjA8BgNVHR8ENTAzMDGgL6AthitodHRwOi8vY3JsLm5kaXMubnZpZGlhLmNv
bS9jcmwvbDItZ2IxMDAuY3JsMDcGCCsGAQUFBwEBBCswKTAnBggrBgEFBQcwAYYb
aHR0cDovL29jc3AubmRpcy5udmlkaWEuY29tMB0GA1UdDgQWBBTFxiXxIOlpoepP
CUWMAnmFbZp3pzAfBgNVHSMEGDAWgBTtqWR9ZFo/Pa3Guetkw1uSG6TgAjAKBggq
hkjOPQQDAwNpADBmAjEA9N2u/VE9zjbHhp/SAKqV4ADqd2Qlp2QYWVnW4ihwbKXE
duZr6mxVOB+oglhZiwtQAjEA5mBc9V8UgoMbGGY+OUaZouVp3Xx3AzB3oFOXyDx0
57dJoiCAaYnGQwth7I2uMG1N
-----END CERTIFICATE-----

17
src/nvidia/inc/kernel/spdm/bin/blackwell/gb110_l3_cert.pem.bin Normal file
View File

@@ -0,0 +1,17 @@
-----BEGIN CERTIFICATE-----
MIICrTCCAjOgAwIBAgIQdrM3VX0x7FsGvUBMt6frxzAKBggqhkjOPQQDAzA9MR4w
HAYDVQQDDBVOVklESUEgR0IxMDAgSWRlbnRpdHkxGzAZBgNVBAoMEk5WSURJQSBD
b3Jwb3JhdGlvbjAgFw0yMzA2MjAwMDAwMDBaGA85OTk5MTIzMTIzNTk1OVowVzEr
MCkGA1UEAwwiTlZJRElBIEdCMTEwIFByb3Zpc2lvbmVyIElDQSAwMDAwMDEbMBkG
A1UECgwSTlZJRElBIENvcnBvcmF0aW9uMQswCQYDVQQGEwJVUzB2MBAGByqGSM49
AgEGBSuBBAAiA2IABMJGa8BU/6dpV0e/QyJPPCyTj6SoZwfVL0s+f7rlT+fOBdqG
cLPDEgjxz8Jd5cixIbfeOiauaofLzHJ+ahRPYTEIk6wUJZ6bpMJM2xfmQgMakekh
quRS506a2HOWllDO2aOB2zCB2DAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQE
AwIBBjA8BgNVHR8ENTAzMDGgL6AthitodHRwOi8vY3JsLm5kaXMubnZpZGlhLmNv
bS9jcmwvbDItZ2IxMDAuY3JsMDcGCCsGAQUFBwEBBCswKTAnBggrBgEFBQcwAYYb
aHR0cDovL29jc3AubmRpcy5udmlkaWEuY29tMB0GA1UdDgQWBBRzep3uVs+Vnk/s
uHFn2FS9GA2UdDAfBgNVHSMEGDAWgBTtqWR9ZFo/Pa3Guetkw1uSG6TgAjAKBggq
hkjOPQQDAwNoADBlAjEAmkUAQQV+MqzSuzwP/7V2dyXJCEzfOQkBXjYRkME5KRSv
GMKt88z1L2ijOnlSzHmuAjAt3+y8AozrzKckEU6j0OzTF69vs6MTviT2EIN5jOz1
ekya6M2/zNbljakUNa/OUKc=
-----END CERTIFICATE-----

17
src/nvidia/inc/kernel/spdm/bin/blackwell/gb112_l3_cert.pem.bin Normal file
View File

@@ -0,0 +1,17 @@
-----BEGIN CERTIFICATE-----
MIICrjCCAjOgAwIBAgIQco1T7g68D0p3N/zYUSI3gzAKBggqhkjOPQQDAzA9MR4w
HAYDVQQDDBVOVklESUEgR0IxMDAgSWRlbnRpdHkxGzAZBgNVBAoMEk5WSURJQSBD
b3Jwb3JhdGlvbjAgFw0yMzA2MjAwMDAwMDBaGA85OTk5MTIzMTIzNTk1OVowVzEr
MCkGA1UEAwwiTlZJRElBIEdCMTEyIFByb3Zpc2lvbmVyIElDQSAwMDAwMDEbMBkG
A1UECgwSTlZJRElBIENvcnBvcmF0aW9uMQswCQYDVQQGEwJVUzB2MBAGByqGSM49
AgEGBSuBBAAiA2IABAkrJrWMpOnAQxoaw3/BhrchQtqZ1vuWTJQlxSVcgyjf1707
3ojQ8T8XkgXX2PG5thT22S4so47vFnVybVLcpYbaW01FD++PmhAFMS6tPSNantQN
GrAXEbWyFGAMIFeVW6OB2zCB2DAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQE
AwIBBjA8BgNVHR8ENTAzMDGgL6AthitodHRwOi8vY3JsLm5kaXMubnZpZGlhLmNv
bS9jcmwvbDItZ2IxMDAuY3JsMDcGCCsGAQUFBwEBBCswKTAnBggrBgEFBQcwAYYb
aHR0cDovL29jc3AubmRpcy5udmlkaWEuY29tMB0GA1UdDgQWBBRo+nNybqdFGfh5
SM2oiyOeHc3/ezAfBgNVHSMEGDAWgBTtqWR9ZFo/Pa3Guetkw1uSG6TgAjAKBggq
hkjOPQQDAwNpADBmAjEAwXknXQ2wM9gp31Mg06OaL9QBh3bR+Cr365Ei84U40Pqy
yO//dCsRD0FwJpj148oKAjEAxkKgpk4/36tYxChZS1iBanpac8zmirWfb+aoAcQk
Fa5JodtPv2RcTH+Dgjhemv/w
-----END CERTIFICATE-----

17
src/nvidia/inc/kernel/spdm/bin/blackwell/gb202_l3_cert.pem.bin Normal file
View File

@@ -0,0 +1,17 @@
-----BEGIN CERTIFICATE-----
MIICrjCCAjOgAwIBAgIQUSOkhXhBbSP7n+Rubv2umjAKBggqhkjOPQQDAzA9MR4w
HAYDVQQDDBVOVklESUEgR0IyMFggSWRlbnRpdHkxGzAZBgNVBAoMEk5WSURJQSBD
b3Jwb3JhdGlvbjAgFw0yMzA2MjAwMDAwMDBaGA85OTk5MTIzMTIzNTk1OVowVzEr
MCkGA1UEAwwiTlZJRElBIEdCMjAyIFByb3Zpc2lvbmVyIElDQSAwMDAwMDEbMBkG
A1UECgwSTlZJRElBIENvcnBvcmF0aW9uMQswCQYDVQQGEwJVUzB2MBAGByqGSM49
AgEGBSuBBAAiA2IABGmnqQn6K8CeRx7p8Syj/yru6xrXH2Jlr0PRkTiG0s3Ipsi7
REBXf9mncdWeSmwZm1GfEZk4RYW3PlM5ciW8ryzmMp3fpEcCv0jE7/WcOtQNhf4f
LlMep1ZIRbTjRF0tcqOB2zCB2DAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQE
AwIBBjA8BgNVHR8ENTAzMDGgL6AthitodHRwOi8vY3JsLm5kaXMubnZpZGlhLmNv
bS9jcmwvbDItZ2IyMHguY3JsMDcGCCsGAQUFBwEBBCswKTAnBggrBgEFBQcwAYYb
aHR0cDovL29jc3AubmRpcy5udmlkaWEuY29tMB0GA1UdDgQWBBS2bnFvupBaVghC
+gmaxNRajQROBjAfBgNVHSMEGDAWgBT/LcIBT563+wbrUwmzMVv+cfqb2TAKBggq
hkjOPQQDAwNpADBmAjEAxe3sNnG0Pw3TY6UgV0P++s5v4BbvDa5L9I/dw1wOyBrh
EGnwWGqyLIHwExPZ4l1eAjEAlb/4lyDtAiCrCPaIdo9IQ4ftuu38v+kqjL8CM9BY
E3KAWtevkT+K5UgneLnYp/WW
-----END CERTIFICATE-----

17
src/nvidia/inc/kernel/spdm/bin/blackwell/gb203_l3_cert.pem.bin Normal file
View File

@@ -0,0 +1,17 @@
-----BEGIN CERTIFICATE-----
MIICrjCCAjOgAwIBAgIQY4edX5vWiHtepniohPyJHDAKBggqhkjOPQQDAzA9MR4w
HAYDVQQDDBVOVklESUEgR0IyMFggSWRlbnRpdHkxGzAZBgNVBAoMEk5WSURJQSBD
b3Jwb3JhdGlvbjAgFw0yMzA2MjAwMDAwMDBaGA85OTk5MTIzMTIzNTk1OVowVzEr
MCkGA1UEAwwiTlZJRElBIEdCMjAzIFByb3Zpc2lvbmVyIElDQSAwMDAwMDEbMBkG
A1UECgwSTlZJRElBIENvcnBvcmF0aW9uMQswCQYDVQQGEwJVUzB2MBAGByqGSM49
AgEGBSuBBAAiA2IABLfSIJqqBIAqVax5fBbguy2fh1TEaOy3f5vQnTPkLyREI/iZ
9s6tyBWfqM49cwMOFcjf9osRPssGtjVqmoPgbCIqmg53gEX0JBZKNh68ZzFD3U+b
mOxfVtE0TzHKtj2NC6OB2zCB2DAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQE
AwIBBjA8BgNVHR8ENTAzMDGgL6AthitodHRwOi8vY3JsLm5kaXMubnZpZGlhLmNv
bS9jcmwvbDItZ2IyMHguY3JsMDcGCCsGAQUFBwEBBCswKTAnBggrBgEFBQcwAYYb
aHR0cDovL29jc3AubmRpcy5udmlkaWEuY29tMB0GA1UdDgQWBBScZSdMA0GInRZJ
IAefBgqpRQ0owTAfBgNVHSMEGDAWgBT/LcIBT563+wbrUwmzMVv+cfqb2TAKBggq
hkjOPQQDAwNpADBmAjEAyrzLSsZuToNI41pSt8tcCSjQap9qpwJIVENDgpx1dgzd
ck17Hq4Hy4zisHdDr2U9AjEA/FH3fzeciav3fwYhT++wZVY124TPSiayvpZgKZMN
ocnpkdGfd+gccGdAnXiKBMle
-----END CERTIFICATE-----

17
src/nvidia/inc/kernel/spdm/bin/blackwell/gb205_l3_cert.pem.bin Normal file
View File

@@ -0,0 +1,17 @@
-----BEGIN CERTIFICATE-----
MIICrjCCAjOgAwIBAgIQTFIeyXbOey7wxV2IWpNWFDAKBggqhkjOPQQDAzA9MR4w
HAYDVQQDDBVOVklESUEgR0IyMFggSWRlbnRpdHkxGzAZBgNVBAoMEk5WSURJQSBD
b3Jwb3JhdGlvbjAgFw0yMzA2MjAwMDAwMDBaGA85OTk5MTIzMTIzNTk1OVowVzEr
MCkGA1UEAwwiTlZJRElBIEdCMjA1IFByb3Zpc2lvbmVyIElDQSAwMDAwMDEbMBkG
A1UECgwSTlZJRElBIENvcnBvcmF0aW9uMQswCQYDVQQGEwJVUzB2MBAGByqGSM49
AgEGBSuBBAAiA2IABCFvIlzCTz4q5QEbcfODtyuwNTH0GFuJYzSN2rubw1FLCtNa
KUg09W/w0lPww14YXF4nghNqVIGFRYppoF2GzGrh4kQgSgEBd9QljGulkl3suGts
gCWsnduNo0FdMP6GeqOB2zCB2DAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQE
AwIBBjA8BgNVHR8ENTAzMDGgL6AthitodHRwOi8vY3JsLm5kaXMubnZpZGlhLmNv
bS9jcmwvbDItZ2IyMHguY3JsMDcGCCsGAQUFBwEBBCswKTAnBggrBgEFBQcwAYYb
aHR0cDovL29jc3AubmRpcy5udmlkaWEuY29tMB0GA1UdDgQWBBSHPSkKjVT15e6Z
iFglaOVCof/p5TAfBgNVHSMEGDAWgBT/LcIBT563+wbrUwmzMVv+cfqb2TAKBggq
hkjOPQQDAwNpADBmAjEAnDC9SR79IPBa1TA7EQDXE2pvBdTPvJJz/sbYFVSgtgFA
x2fmpnqyStlinm0cHJTMAjEA5qjnaXbodTvnasR1gCVyOO3iMkaYTrJ3eBxstcYt
9ws2ukZk4O8gT54thnfmaG1/
-----END CERTIFICATE-----

17
src/nvidia/inc/kernel/spdm/bin/blackwell/gb206_l3_cert.pem.bin Normal file
View File

@@ -0,0 +1,17 @@
-----BEGIN CERTIFICATE-----
MIICrTCCAjOgAwIBAgIQdy+LB7tht/k8Lzf4oRlrFDAKBggqhkjOPQQDAzA9MR4w
HAYDVQQDDBVOVklESUEgR0IyMFggSWRlbnRpdHkxGzAZBgNVBAoMEk5WSURJQSBD
b3Jwb3JhdGlvbjAgFw0yMzA2MjAwMDAwMDBaGA85OTk5MTIzMTIzNTk1OVowVzEr
MCkGA1UEAwwiTlZJRElBIEdCMjA2IFByb3Zpc2lvbmVyIElDQSAwMDAwMDEbMBkG
A1UECgwSTlZJRElBIENvcnBvcmF0aW9uMQswCQYDVQQGEwJVUzB2MBAGByqGSM49
AgEGBSuBBAAiA2IABDbkgzMef5m1kLzSpMl1Bvslm3d/FvzOoV8VzEm2Asd3QeWL
M3j4wdzY8WWTEbUyxs4BgdMYjHUozfVKwerz4bGSbnK2AyshaUdYZCdjJ3uWsGKL
iHX6FwNAwIH8oPTpg6OB2zCB2DAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQE
AwIBBjA8BgNVHR8ENTAzMDGgL6AthitodHRwOi8vY3JsLm5kaXMubnZpZGlhLmNv
bS9jcmwvbDItZ2IyMHguY3JsMDcGCCsGAQUFBwEBBCswKTAnBggrBgEFBQcwAYYb
aHR0cDovL29jc3AubmRpcy5udmlkaWEuY29tMB0GA1UdDgQWBBSdJzKVm2HveCVT
yNx9i4PAgt4x+DAfBgNVHSMEGDAWgBT/LcIBT563+wbrUwmzMVv+cfqb2TAKBggq
hkjOPQQDAwNoADBlAjEAg7g2d9rbd9Pq6SM2gVB+dyWB//PpVPMG2cNCnMe6BMbT
fOoCYUIflg+U+0EJna86AjBiiHZM0fhEhn6v0v/pd6c2NvH3JHc1Ie5SCDxuPToa
ZF8h26b7xbeR2UYi5iwUVIE=
-----END CERTIFICATE-----

17
src/nvidia/inc/kernel/spdm/bin/blackwell/gb207_l3_cert.pem.bin Normal file
View File

@@ -0,0 +1,17 @@
-----BEGIN CERTIFICATE-----
MIICrDCCAjOgAwIBAgIQS6VT629wJC699wCfI4YdTzAKBggqhkjOPQQDAzA9MR4w
HAYDVQQDDBVOVklESUEgR0IyMFggSWRlbnRpdHkxGzAZBgNVBAoMEk5WSURJQSBD
b3Jwb3JhdGlvbjAgFw0yMzA2MjAwMDAwMDBaGA85OTk5MTIzMTIzNTk1OVowVzEr
MCkGA1UEAwwiTlZJRElBIEdCMjA3IFByb3Zpc2lvbmVyIElDQSAwMDAwMDEbMBkG
A1UECgwSTlZJRElBIENvcnBvcmF0aW9uMQswCQYDVQQGEwJVUzB2MBAGByqGSM49
AgEGBSuBBAAiA2IABC9rBlFPPwahv04Qq/4tE+WSB1/JxGeOGDzo1ZBXkHkWWOkS
BXhZG3WtAqS0l6xuE7OHrwaW2ddRxR5FKktRKZFn31++oIFxvaUh7XfTsvBNfTjI
jN6jdoSVOyrNYRB5Z6OB2zCB2DAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQE
AwIBBjA8BgNVHR8ENTAzMDGgL6AthitodHRwOi8vY3JsLm5kaXMubnZpZGlhLmNv
bS9jcmwvbDItZ2IyMHguY3JsMDcGCCsGAQUFBwEBBCswKTAnBggrBgEFBQcwAYYb
aHR0cDovL29jc3AubmRpcy5udmlkaWEuY29tMB0GA1UdDgQWBBQ/EnLCnrqoIW9S
vAUeom2zXRGwezAfBgNVHSMEGDAWgBT/LcIBT563+wbrUwmzMVv+cfqb2TAKBggq
hkjOPQQDAwNnADBkAjBS+25qnhdpo2Tx/Q40P6qaJ8JNx8GnHMwXYe/LzDewqccS
hTPKLYSHXAsn8gqxNbYCMBsYJ2UJPGbfllp/3WQLI2WEiY6mOr0Jy0Ext3ns65Cl
NrYwOKPxoV0pI/UDQDbyjA==
-----END CERTIFICATE-----

16
src/nvidia/inc/kernel/spdm/bin/blackwell/gb20x_l2_cert.pem.bin Normal file
View File

@@ -0,0 +1,16 @@
-----BEGIN CERTIFICATE-----
MIICiTCCAhCgAwIBAgIQcMEx0xriPsCC3fI6Db5vVTAKBggqhkjOPQQDAzA1MSIw
IAYDVQQDDBlOVklESUEgRGV2aWNlIElkZW50aXR5IENBMQ8wDQYDVQQKDAZOVklE
SUEwIBcNMjMwMTAxMDAwMDAwWhgPOTk5OTEyMzEyMzU5NTlaMD0xHjAcBgNVBAMM
FU5WSURJQSBHQjIwWCBJZGVudGl0eTEbMBkGA1UECgwSTlZJRElBIENvcnBvcmF0
aW9uMHYwEAYHKoZIzj0CAQYFK4EEACIDYgAEcrUoUWco+GWi9SH+WrZlLrY41Tjf
O4A2OTCjXIjNL5CJzu6TSZcqFYJzW3rR0I8zxB/sK9hQ9+ewHb2V17a0V0ny4UTX
W7O8JsJjqwViWYTn77awWCc8tsoQIOq/8iUGo4HaMIHXMA8GA1UdEwEB/wQFMAMB
Af8wDgYDVR0PAQH/BAQDAgEGMDsGA1UdHwQ0MDIwMKAuoCyGKmh0dHA6Ly9jcmwu
bmRpcy5udmlkaWEuY29tL2NybC9sMS1yb290LmNybDA3BggrBgEFBQcBAQQrMCkw
JwYIKwYBBQUHMAGGG2h0dHA6Ly9vY3NwLm5kaXMubnZpZGlhLmNvbTAdBgNVHQ4E
FgQU/y3CAU+et/sG61MJszFb/nH6m9kwHwYDVR0jBBgwFoAUV4X/g/JjzGV9aLc6
W/SNSsv7SV8wCgYIKoZIzj0EAwMDZwAwZAIwPf1trRKbXt1x+YQShRxO/DFNMG5U
zCGfxfVrSMkCSwMGfKydrXfBz6f0ugDmQO0LAjBg2WsesA3sbMAg5dcedyXQVZUH
H5CM/9Z8KO4MJGPtcG9K0/qwf4MBUvUzE5Yp/K8=
-----END CERTIFICATE-----

16
src/nvidia/inc/kernel/spdm/bin/hopper/gh100_l2_cert.pem.bin Normal file
View File

@@ -0,0 +1,16 @@
-----BEGIN CERTIFICATE-----
MIICijCCAhCgAwIBAgIQTCVe3jvQAb8/SjtgX8qJijAKBggqhkjOPQQDAzA1MSIw
IAYDVQQDDBlOVklESUEgRGV2aWNlIElkZW50aXR5IENBMQ8wDQYDVQQKDAZOVklE
SUEwIBcNMjIwMTEyMDAwMDAwWhgPOTk5OTEyMzEyMzU5NTlaMD0xHjAcBgNVBAMM
FU5WSURJQSBHSDEwMCBJZGVudGl0eTEbMBkGA1UECgwSTlZJRElBIENvcnBvcmF0
aW9uMHYwEAYHKoZIzj0CAQYFK4EEACIDYgAE+pg+tDUuILlZILk5wg22YEJ9Oh6c
yPcsv3IvgRWcV4LeZK1pTCoQDIplZ0E4qsLG3G04pxsbMhxbqkiz9pqlTV2rtuVg
SmIqnSYkU1jWXsPS9oVLCGE8VRLl1JvqyOxUo4HaMIHXMA8GA1UdEwEB/wQFMAMB
Af8wDgYDVR0PAQH/BAQDAgEGMDsGA1UdHwQ0MDIwMKAuoCyGKmh0dHA6Ly9jcmwu
bmRpcy5udmlkaWEuY29tL2NybC9sMS1yb290LmNybDA3BggrBgEFBQcBAQQrMCkw
JwYIKwYBBQUHMAGGG2h0dHA6Ly9vY3NwLm5kaXMubnZpZGlhLmNvbTAdBgNVHQ4E
FgQUB0Kg6wOcgGB7oUFhmU2uJffCmx4wHwYDVR0jBBgwFoAUV4X/g/JjzGV9aLc6
W/SNSsv7SV8wCgYIKoZIzj0EAwMDaAAwZQIxAPIQhnveFxYIrPzBqViT2I34SfS4
JGWFnk/1UcdmgJmp+7l6rH/C4qxwntYSgeYrlQIwdjQuofHnhd1RL09OBO34566J
C9bYAosT/86cCojiGjhLnal9hJOH0nS/lrbaoc5a
-----END CERTIFICATE-----

17
src/nvidia/inc/kernel/spdm/bin/hopper/gh100_l3_cert.pem.bin Normal file
View File

@@ -0,0 +1,17 @@
-----BEGIN CERTIFICATE-----
MIICqjCCAi+gAwIBAgIQav5xhPkiMsjfeyQiYXduVjAKBggqhkjOPQQDAzA9MR4w
HAYDVQQDDBVOVklESUEgR0gxMDAgSWRlbnRpdHkxGzAZBgNVBAoMEk5WSURJQSBD
b3Jwb3JhdGlvbjAgFw0yMjAzMDEwMDAwMDBaGA85OTk5MTIzMTIzNTk1OVowUzEn
MCUGA1UEAwweTlZJRElBIEdIMTAwIFByb3Zpc2lvbmVyIElDQSAxMRswGQYDVQQK
DBJOVklESUEgQ29ycG9yYXRpb24xCzAJBgNVBAYTAlVTMHYwEAYHKoZIzj0CAQYF
K4EEACIDYgAEzUdWqjn1OlXhLfFOKAFTghqG+Q3zF4xgSBbZsUEyWYCC3rKjE9Nn
o88ZpBQx85Oo0PkqP2dwoMVNTQMv5cvy9jLaTvSTXZwN2HQHE9u7x7BIYrWi0sG3
5q1IJNSOGO5Lo4HbMIHYMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgEG
MDwGA1UdHwQ1MDMwMaAvoC2GK2h0dHA6Ly9jcmwubmRpcy5udmlkaWEuY29tL2Ny
bC9sMi1naDEwMC5jcmwwNwYIKwYBBQUHAQEEKzApMCcGCCsGAQUFBzABhhtodHRw
Oi8vb2NzcC5uZGlzLm52aWRpYS5jb20wHQYDVR0OBBYEFCloyxYs0HeVcqJ5EAPm
nroMzAqUMB8GA1UdIwQYMBaAFAdCoOsDnIBge6FBYZlNriX3wpseMAoGCCqGSM49
BAMDA2kAMGYCMQDK0BCr49DNJ48Yh5wu388bZifDFxAsiUS4U1fGmpJZFhCbODH6
mRwcMxp6EOayZuYCMQDYKTyNc2FxWFuhHtdCE3ls4S7SInehdErTZNuhFymc4YOM
6VlLWTY/CM+resjjqxQ=
-----END CERTIFICATE-----

13
src/nvidia/inc/kernel/spdm/bin/l1_cert.pem.bin Normal file
View File

@@ -0,0 +1,13 @@
-----BEGIN CERTIFICATE-----
MIICCzCCAZCgAwIBAgIQLTZwscoQBBHB/sDoKgZbVDAKBggqhkjOPQQDAzA1MSIw
IAYDVQQDDBlOVklESUEgRGV2aWNlIElkZW50aXR5IENBMQ8wDQYDVQQKDAZOVklE
SUEwIBcNMjExMTA1MDAwMDAwWhgPOTk5OTEyMzEyMzU5NTlaMDUxIjAgBgNVBAMM
GU5WSURJQSBEZXZpY2UgSWRlbnRpdHkgQ0ExDzANBgNVBAoMBk5WSURJQTB2MBAG
ByqGSM49AgEGBSuBBAAiA2IABA5MFKM7+KViZljbQSlgfky/RRnEQScW9NDZF8SX
gAW96r6u/Ve8ZggtcYpPi2BS4VFu6KfEIrhN6FcHG7WP05W+oM+hxj7nyA1r1jkB
2Ry70YfThX3Ba1zOryOP+MJ9vaNjMGEwDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8B
Af8EBAMCAQYwHQYDVR0OBBYEFFeF/4PyY8xlfWi3Olv0jUrL+0lfMB8GA1UdIwQY
MBaAFFeF/4PyY8xlfWi3Olv0jUrL+0lfMAoGCCqGSM49BAMDA2kAMGYCMQCPeFM3
TASsKQVaT+8S0sO9u97PVGCpE9d/I42IT7k3UUOLSR/qvJynVOD1vQKVXf0CMQC+
EY55WYoDBvs2wPAH1Gw4LbcwUN8QCff8bFmV4ZxjCRr4WXTLFHBKjbfneGSBWwA=
-----END CERTIFICATE-----

1472
src/nvidia/inc/kernel/vgpu/rm_plugin_shared_code.h
View File

File diff suppressed because it is too large Load Diff

54
src/nvidia/inc/kernel/vgpu/rpc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -203,7 +203,7 @@ typedef struct ContextDma ContextDma;
NV_ASSERT(pRpc != NULL); \
if ((status == NV_OK) && (pRpc != NULL)) \
{ \
if (IS_GSP_CLIENT(pGpu)) \
if (IS_FW_CLIENT(pGpu)) \
{ \
NV_RM_RPC_ALLOC_SHARE_DEVICE_FWCLIENT(pGpu, hclient, hdevice, hclientshare, htargetclient, htargetdevice, hclass, \
allocflags, vasize, vamode, bFirstDevice, status); \
@@ -227,7 +227,7 @@ typedef struct ContextDma ContextDma;
NV_ASSERT(pRpc != NULL); \
if ((status == NV_OK) && (pRpc != NULL)) \
{ \
if (IS_GSP_CLIENT(pGpu)) \
if (IS_FW_CLIENT(pGpu)) \
{ \
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \
status = pRmApi->Control(pRmApi, hClient, hObject, cmd, \
@@ -251,7 +251,7 @@ typedef struct ContextDma ContextDma;
NV_ASSERT(pRpc != NULL); \
if ((status == NV_OK) && (pRpc != NULL)) \
{ \
if (IS_GSP_CLIENT(pGpu)) \
if (IS_FW_CLIENT(pGpu)) \
{ \
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \
status = pRmApi->AllocWithHandle(pRmApi, hclient, hparent, hchannel, \
@@ -275,7 +275,7 @@ typedef struct ContextDma ContextDma;
NV_ASSERT(pRpc != NULL); \
if ((status == NV_OK) && (pRpc != NULL)) \
{ \
if (IS_GSP_CLIENT(pGpu)) \
if (IS_FW_CLIENT(pGpu)) \
{ \
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \
status = pRmApi->AllocWithHandle(pRmApi, hclient, hchannel, hobject, \
@@ -299,7 +299,7 @@ typedef struct ContextDma ContextDma;
NV_ASSERT(pRpc != NULL); \
if ((status == NV_OK) && (pRpc != NULL)) \
{ \
if (IS_GSP_CLIENT(pGpu)) \
if (IS_FW_CLIENT(pGpu)) \
{ \
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \
status = pRmApi->Free(pRmApi, hclient, hobject); \
@@ -320,7 +320,7 @@ typedef struct ContextDma ContextDma;
/* used in failure cases, macro doesn't overwrite rmStatus */ \
if (pRpc != NULL) \
{ \
if (IS_GSP_CLIENT(pGpu)) \
if (IS_FW_CLIENT(pGpu)) \
{ \
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \
pRmApi->Free(pRmApi, hclient, hobject); \
@@ -342,7 +342,7 @@ typedef struct ContextDma ContextDma;
NV_ASSERT(pRpc != NULL); \
if ((status == NV_OK) && (pRpc != NULL)) \
{ \
if (IS_GSP_CLIENT(pGpu)) \
if (IS_FW_CLIENT(pGpu)) \
{ \
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \
NV0005_ALLOC_PARAMETERS allocParams = {0}; \
@@ -372,7 +372,7 @@ typedef struct ContextDma ContextDma;
NV_ASSERT(pRpc != NULL); \
if ((status == NV_OK) && (pRpc != NULL)) \
{ \
if (IS_GSP_CLIENT(pGpu)) \
if (IS_FW_CLIENT(pGpu)) \
{ \
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \
NV2080_ALLOC_PARAMETERS alloc_params = {0}; \
@@ -398,7 +398,7 @@ typedef struct ContextDma ContextDma;
NV_ASSERT(pRpc != NULL); \
if ((status == NV_OK) && (pRpc != NULL)) \
{ \
if (IS_GSP_CLIENT(pGpu)) \
if (IS_FW_CLIENT(pGpu)) \
{ \
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \
status = pRmApi->DupObject(pRmApi, hclient, hparent, \
@@ -483,28 +483,6 @@ static inline void NV_RM_RPC_SIM_FREE_INFRA(OBJGPU *pGpu, ...) { return; }
status = NV_ERR_INSUFFICIENT_RESOURCES; \
} while (0)
#define NV_RM_RPC_SET_PAGE_DIRECTORY(pGpu, hClient, hDevice, pParams, status) \
do \
{ \
OBJRPC *pRpc = GPU_GET_RPC(pGpu); \
NV_ASSERT(pRpc != NULL); \
if ((status == NV_OK) && (pRpc != NULL)) \
status = rpcSetPageDirectory_HAL(pGpu, pRpc, hClient, hDevice, pParams); \
else if (pRpc == NULL) \
status = NV_ERR_INSUFFICIENT_RESOURCES; \
} while (0)
#define NV_RM_RPC_UNSET_PAGE_DIRECTORY(pGpu, hClient, hDevice, pParams, status) \
do \
{ \
OBJRPC *pRpc = GPU_GET_RPC(pGpu); \
NV_ASSERT(pRpc != NULL); \
if ((status == NV_OK) && (pRpc != NULL)) \
status = rpcUnsetPageDirectory_HAL(pGpu, pRpc, hClient, hDevice, pParams); \
else if (pRpc == NULL) \
status = NV_ERR_INSUFFICIENT_RESOURCES; \
} while (0)
static inline void NV_RM_RPC_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION(OBJGPU *pGpu, ...) { return; }
#define NV_RM_RPC_INVALIDATE_TLB(pGpu, status, pdbAddress, regVal) \
@@ -522,7 +500,17 @@ static inline void NV_RM_RPC_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION(OB
// DCE_CLIENT_RM specific RPCs
//
#define NV_RM_RPC_DCE_RM_INIT(pGpu, bInit, status) do {} while (0)
#define NV_RM_RPC_DCE_RM_INIT(pGpu, bInit, status) \
do \
{ \
OBJRPC* pRpc = GPU_GET_RPC(pGpu); \
if ((status == NV_OK) && (pRpc != NULL)) \
{ \
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \
status = rpcDceRmInit_dce(pRmApi, bInit); \
} else if (pRpc == NULL) \
status = NV_ERR_INSUFFICIENT_RESOURCES; \
} while (0)
//
// GSP_CLIENT_RM specific RPCs

3
src/nvidia/inc/kernel/vgpu/rpc_global_enums.h
View File

@@ -234,7 +234,8 @@ enum {
X(RM, CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL, 224)
X(RM, CTRL_CMD_GET_HS_CREDITS_MAPPING, 225)
X(RM, CTRL_EXEC_PARTITIONS_EXPORT, 226)
X(RM, NUM_FUNCTIONS, 227)
X(RM, CTRL_CMD_INTERNAL_GPU_CHECK_CTS_ID_VALID, 227)
X(RM, NUM_FUNCTIONS, 228)
#ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H
};
# undef X

4
src/nvidia/inc/kernel/vgpu/rpc_vgpu.h
View File

@@ -85,12 +85,12 @@ static NV_INLINE void NV_RM_RPC_UPDATE_GPU_PDES(OBJGPU *pGpu, ...) { }
status = rpcSetSurfaceProperties_HAL(pGpu, pRpc, hClient, pParams, bSkipCompare); \
} while (0)
#define NV_RM_RPC_CLEANUP_SURFACE(pGpu, pParams, status) \
#define NV_RM_RPC_CLEANUP_SURFACE(pGpu, hClient, pParams, status) \
do \
{ \
OBJRPC *pRpc = GPU_GET_RPC(pGpu); \
if ((status == NV_OK) && (pRpc != NULL)) \
status = rpcCleanupSurface_HAL(pGpu, pRpc, pParams); \
status = rpcCleanupSurface_HAL(pGpu, pRpc, hClient, pParams); \
} while (0)
#define NV_RM_RPC_SWITCH_TO_VGA(pGpu, status) \

51
src/nvidia/inc/kernel/vgpu/sdk-structures.h
View File

@@ -97,6 +97,8 @@ typedef struct vmiopd_SM_info {
#define NV2080_CTRL_CLK_ARCH_MAX_DOMAINS_v1E_0D 32
#define NV2080_CTRL_PERF_CLK_MAX_DOMAINS_v2B_0D 32U
#define NV_RM_RPC_NO_MORE_DATA_TO_READ 0
#define NV_RM_RPC_MORE_RPC_DATA_TO_READ 1
@@ -110,6 +112,8 @@ typedef struct vmiopd_SM_info {
#define NV2080_CTRL_NVLINK_MAX_LINKS_v1A_18 12
#define NV2080_CTRL_NVLINK_MAX_LINKS_v23_04 24
#define NV2080_CTRL_NVLINK_MAX_MASK_SIZE_v2B_11 1
#define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v15_02 8
#define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D 9
@@ -136,11 +140,13 @@ typedef struct vmiopd_SM_info {
#define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1B_05 256
#define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03 240
#define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1B_05 8
#define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03 12
#define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v2B_01 16
#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v1B_05 0x19
#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v25_07 0x1a
#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03 10
#define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03 12
#define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09 32
#define NV2080_INTR_CATEGORY_ENUM_COUNT_v2B_0A 7
#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E 72
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE_v20_04 6
#define NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08 63
@@ -149,7 +155,8 @@ typedef struct vmiopd_SM_info {
#define NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A 2
#define NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE_v26_05 1024
#define NVB0CC_CREDIT_POOL_MAX_COUNT_v29_0A 30
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE_v2B_09 0xFFU
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE_v2B_06 0xFFU
#define NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE_v2B_10 0xFFU
// Host USM type
@@ -178,7 +185,14 @@ typedef struct
NvU32 pidCount;
} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_RPC_EX;
typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG_v03_00[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES];
//NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES for r535/r550/r570 code
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES_v03_00 17U
//NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES for chips_a
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES_v2B_02 18U
typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG_v03_00[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES_v03_00];
typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG_v2B_02[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES_v2B_02];
typedef NvV32 NvRmctrlCmd;
@@ -247,6 +261,7 @@ typedef struct VGPU_BSP_CAPS
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1F_0F 0x36
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A 0x37
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_27_00 0x39
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_2B_00 0x80
#define NV2080_CTRL_PERF_MAX_LIMITS_v1C_0B 0x100
@@ -281,6 +296,20 @@ typedef struct VGPU_BSP_CAPS
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11 0x00000041
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v2A_04 0x00000042
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v2B_03 0x00000043
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v2B_05 0x00000044
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v2B_0C 0x00000045
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v2B_13 0x00000046
// Versioned define for struct vgpuPstateInfo
#define VGPU_PSTATE_MAX_v06_00 5
#define VGPU_VPSTATE_MAX_v06_00 5
#define VGPU_VPSTATE_MAX_v2B_0F 10
#define VGPU_PSTATE_CLK_DOM_MAX_v03_00 10
#define VGPU_PSTATE_CLK_DOM_MAX_v2B_0F 15
#define VGPU_PSTATE_VOLT_DOM_MAX_v03_00 2
#define NV2080_CTRL_BOARDOBJGRP_E255_MAX_OBJECTS_v06_01 (255U)
#define NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX 4
@@ -375,6 +404,7 @@ struct _vgpu_static_info
NV2080_CTRL_BUS_GET_INFO_V2_PARAMS busGetInfoV2;
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS grSmIssueRateModifier;
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS grSmIssueRateModifierV2;
NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS grSmIssueThrottleCtrl;
NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS pcieSupportedGpuAtomics;
NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS ceGetAllCaps;
NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS c2cInfo;
@@ -403,6 +433,7 @@ struct _vgpu_static_info
NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS globalSmOrder;
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS smIssueRateModifier;
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS smIssueRateModifierV2;
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS smIssueThrottleCtrl;
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS floorsweepMaskParams;
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS fecsRecordSize;
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS fecsTraceDefines;
@@ -413,7 +444,7 @@ struct _vgpu_static_info
NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS mcEngineNotificationIntrVectors;
NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS eccStatus;
NvBool guestManagedHwAlloc;
NvU8 jpegCaps[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE];
NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS jpegCaps[NV2080_ENGINE_TYPE_NVJPEG_SIZE];
NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS nvencCaps;
VGPU_BSP_CAPS vgpuBspCaps[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS];
NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS constructedFalconInfo;
@@ -442,6 +473,7 @@ struct _vgpu_static_info
NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS masterGetVfErrCntIntMsk;
GPU_EXEC_SYSPIPE_INFO execSyspipeInfo;
NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS ccuSampleInfo;
NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS intrCategorySubtreeMapParams;
};
typedef struct _vgpu_static_info VGPU_STATIC_INFO, VGPU_STATIC_INFO2;
@@ -465,21 +497,23 @@ ct_assert(NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES == NV2080_CTRL_GRMGR_GR_FS_IN
ct_assert(NV2080_CTRL_GRMGR_MAX_SMC_IDS == NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D);
ct_assert((NV0080_CTRL_GR_INFO_INDEX_MAX + 1) == NV0080_CTRL_GR_INFO_MAX_SIZE_29_00);
ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_ENGINES == NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04);
ct_assert(NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE == NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE_v2B_09);
ct_assert(NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE == NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE_v2B_06);
ct_assert(NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE == NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE_v2B_10);
ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_SM == NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03);
ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_GPC == NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03);
ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_GPC == NV2080_CTRL_INTERNAL_GR_MAX_GPC_v2B_01);
ct_assert(NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT ==
NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v25_07);
ct_assert(NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT == NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03);
ct_assert(NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS == NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F);
ct_assert(NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL == NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL_v16_03);
ct_assert(VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06 < NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL_v16_03);
ct_assert(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE == NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_27_00);
ct_assert(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE == NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_2B_00);
ct_assert(NV2080_CTRL_GPU_MAX_SMC_IDS == 8);
ct_assert(NV2080_GPU_MAX_GID_LENGTH == 0x000000100);
ct_assert(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES == 16);
ct_assert(NV2080_GPU_MAX_NAME_STRING_LENGTH == 0x0000040);
ct_assert(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES == 256);
ct_assert(NV2080_INTR_CATEGORY_ENUM_COUNT == NV2080_INTR_CATEGORY_ENUM_COUNT_v2B_0A);
ct_assert(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX == NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09);
ct_assert(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES == 256);
ct_assert(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES == 32);
@@ -510,9 +544,10 @@ ct_assert(NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E =
ct_assert(RPC_GR_BUFFER_TYPE_GRAPHICS_MAX_v25_0E == RPC_GR_BUFFER_TYPE_GRAPHICS_MAX);
ct_assert(NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT_v1A_07 == NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT);
ct_assert(NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05 == NVC637_CTRL_MAX_EXEC_PARTITIONS);
ct_assert(NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v2A_04 == NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE);
ct_assert(NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v2B_13 == NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE);
ct_assert(NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX_v27_01 == NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX);
ct_assert(NVB0CC_CREDIT_POOL_MAX_COUNT_v29_0A == NVB0CC_CREDIT_POOL_MAX_COUNT);
ct_assert(NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08 == NVB0CC_MAX_CREDIT_INFO_ENTRIES);
ct_assert(NV2080_CTRL_PERF_CLK_MAX_DOMAINS_v2B_0D == NV2080_CTRL_PERF_CLK_MAX_DOMAINS);
#endif /*_RPC_SDK_STRUCTURES_H_*/

11
src/nvidia/inc/kernel/vgpu/vgpu_version.h
View File

@@ -30,8 +30,8 @@
#define RPC_VERSION_FROM_VGX_VERSION(major, minor) (DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \
DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor))
#define VGX_MAJOR_VERSION_NUMBER 0x2A
#define VGX_MINOR_VERSION_NUMBER 0x09
#define VGX_MAJOR_VERSION_NUMBER 0x2B
#define VGX_MINOR_VERSION_NUMBER 0x13
#define VGX_MAJOR_VERSION_NUMBER_VGPU_12_0 0x1A
#define VGX_MINOR_VERSION_NUMBER_VGPU_12_0 0x18
@@ -55,7 +55,8 @@
* 2. This is the first break in migration compatibility after a release.
*/
#define NV_VGPU_GRIDSW_INTERNAL_TO_EXTERNAL_VERSION_MAPPING \
{{0x2A, 0x00}, {0x2A, 0x09}, {0x19, 0x01}}, \
{{0x2B, 0x00}, {0x2B, 0x13}, {0x1A, 0x01}}, \
{{0x2A, 0x00}, {0x2A, 0x08}, {0x19, 0x01}}, \
{{0x29, 0x00}, {0x29, 0x0B}, {0x18, 0x01}}, \
{{0x29, 0x0C}, {0x29, 0x0C}, {0x18, 0x02}}, \
{{0x28, 0x00}, {0x28, 0x09}, {0x17, 0x01}}, \
@@ -109,13 +110,13 @@
/* WARNING: Should be updated with each vGPU release, if there is a break in
* migration compatibility during the development of that release. */
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x19
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x1A
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1
/* WARNING: Should be updated with each vGPU release, if minimum supported
* version change on the host.
*/
#define NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x7
#define NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x12
#define NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1
#endif // __vgpu_vgpu_version_h__

8
src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h
View File

@@ -38,6 +38,7 @@
#define VGPU_SIGNATURE_SIZE NVA081_VGPU_SIGNATURE_SIZE
#define VGPU_MAX_PLUGIN_CHANNELS 5
#define MAX_VGPU_DEVICES_PER_PGPU NVA081_MAX_VGPU_PER_PGPU
#define MAX_VGPU_DEVICES_PER_PGPU_NON_MIG NVA081_MAX_VGPU_PER_PGPU_NON_MIG
#define MAX_VGPU_DEVICES_PER_GI NVA081_MAX_VGPU_PER_GI
#define SET_GUEST_ID_ACTION_SET 0
@@ -46,10 +47,11 @@
// swrl count for MIG when running in non-timesliced mode
#define OBJSCHED_SW_MIG_NO_TIMESLICE_RUNLIST_COUNT 1
// swrl count for MIG when running in timesliced mode
#define OBJSCHED_SW_MIG_TIMESLICE_RUNLIST_COUNT 13
#define OBJSCHED_SW_MIG_TIMESLICE_RUNLIST_COUNT (MAX_VGPU_DEVICES_PER_GI + 1)
// swrl count for non-mig
#define OBJSCHED_SW_RUNLIST_COUNT 33
#define OBJSCHED_SW_RUNLIST_COUNT (MAX_VGPU_DEVICES_PER_PGPU_NON_MIG + 1)
//No. of Reserved CE Channels for KMD/OS in HYPER-V
#define HYPERV_RESERVED_CE_CHANNELS_KMD 32
typedef struct
{

4
src/nvidia/inc/libraries/containers/ringbuf.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -94,7 +94,7 @@ typedef struct RingBufBase
#define ringbufConstructDynamic(pBuf, logSz, pAlloc) \
(pBuf->pAllocator = pAlloc, ringbufConstructDynamic_IMPL(&((pBuf)->base), logSz, sizeof(*((pBuf)->elem)), pAlloc))
((pBuf)->pAllocator = pAlloc, ringbufConstructDynamic_IMPL(&((pBuf)->base), logSz, sizeof(*((pBuf)->elem)), pAlloc))
#define ringbufConstruct(pBuf) \
ringbufConstruct_IMPL(&((pBuf)->base), sizeof((pBuf)->lgSz), (void*)((pBuf)->elem))

2
src/nvidia/inc/libraries/mmu/gmmu_fmt.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

30
src/nvidia/inc/libraries/nvport/memory.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -206,6 +206,32 @@ void portMemFree(void *pData);
*/
void *portMemCopy(void *pDestination, NvLength destSize, const void *pSource, NvLength srcSize);
/**
* @brief Copies data from one address to another.
*
* Copies srcSize bytes from pSource to pDestination, returning pDestination.
* pDestination should be at least destSize bytes, pSource at least srcSize.
* destSize should be equal or greater to srcSize.
*
* This function will also ensure that alignment faults will not be generated
* when the device memory is accessed.
*
* If destSize is 0, it is guaranteed to not access either buffer.
*
* @par Undefined:
* Behavior is undefined if memory regions referred to by pSource and
* pDestination overlap.
*
* @par Checked builds only:
* Will assert/breakpoint if the regions overlap. <br>
* Will assert/breakpoint if destSize < srcSize <br>
* Will assert/breakpoint if either pointer is NULL
*
* @return pDestination on success, NULL if the operation failed.
*
*/
void *portMemCopyAligned(void *pDestination, NvLength destSize, const void *pSource, NvLength srcSize);
/**
* @brief Moves data from one address to another.
*

8
src/nvidia/inc/libraries/nvport/string.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2016-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -158,6 +158,12 @@ char *portStringTok(char *str, const char *delim, char **saveptr);
*/
char *portStringStrStr(char *str, char *substr);
/**
* @brief Returns pointer to the first occurrence of character in the str
*
*/
const char *portStringStrChar(const char *str, int c);
/// @} End core functions
/**

5
src/nvidia/inc/libraries/resserv/rs_resource.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -540,6 +540,8 @@ struct RS_INTER_MAP_PARAMS
NvU64 offset;
NvU64 length;
NvU32 flags;
NvU32 flags2;
NvU32 kindOverride;
NvU64 dmaOffset; ///< [inout] RS-TODO rename this
void *pMemDesc; ///< [out]
@@ -580,6 +582,7 @@ struct RsInterMapping
ListNode mappableNode;
ListNode contextNode;
NvU32 flags; ///< Flags passed when mapping, same flags also passed when unmapping
NvU32 flags2; ///< Additional flags for the mapping
NvU64 dmaOffset;
NvU64 size;
void *pMemDesc;

46
src/nvidia/inc/libraries/utils/nvassert.h
View File

@@ -105,6 +105,14 @@ extern "C" {
#endif
#endif
#if !defined(NV_ASSERT_FAILED_BACKTRACE_ENABLE)
#if defined(NVRM) && NVOS_IS_UNIX && !defined(NVWATCH) && defined(DEBUG)
#define NV_ASSERT_FAILED_BACKTRACE_ENABLE 1
#else
#define NV_ASSERT_FAILED_BACKTRACE_ENABLE 0
#endif
#endif
#if !defined(COVERITY_ASSERT_FAIL)
#if defined(__COVERITY__)
void __coverity_panic__(void);
@@ -129,24 +137,32 @@ void __coverity_panic__(void);
* for both NVLOG and NV_PRINTF.
* The _FUNC macros are used for pre-compiled headers on most platforms.
*/
#if NV_ASSERT_FAILED_USES_STRINGS
#define NV_ASSERT_FAILED_FUNC_COMMA_PARAM(exprStr) , exprStr, __FILE__, __LINE__
#define NV_ASSERT_FAILED_FUNC_PARAM(exprStr) exprStr, __FILE__, __LINE__
#define NV_ASSERT_FAILED_FUNC_COMMA_TYPE ,const char *pszExpr, const char *pszFileName, NvU32 lineNum
#define NV_ASSERT_FAILED_FUNC_TYPE const char *pszExpr, const char *pszFileName, NvU32 lineNum
#else
#define NV_ASSERT_FAILED_FUNC_COMMA_PARAM(exprStr) , __LINE__
#define NV_ASSERT_FAILED_FUNC_PARAM(exprStr) __LINE__
#define NV_ASSERT_FAILED_FUNC_COMMA_TYPE , NvU32 lineNum
#define NV_ASSERT_FAILED_FUNC_TYPE NvU32 lineNum
#endif
#if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS)
void nvAssertInit(void);
void nvAssertDestroy(void);
#if NV_JOURNAL_ASSERT_ENABLE
void nvAssertFailed(void);
void nvAssertOkFailed(NvU32 status);
#else
#define nvAssertFailed(...)
#define nvAssertOkFailed(...)
#endif
void nvAssertFailed(NV_ASSERT_FAILED_FUNC_TYPE);
void nvAssertOkFailed(NvU32 status NV_ASSERT_FAILED_FUNC_COMMA_TYPE);
#define NV_ASSERT_FAILED(exprStr) \
do { \
NV_LOG_SPECIAL(LEVEL_ERROR, RM_GSP_LOG_SPECIAL_ASSERT_FAILED, \
exprStr "\n"); \
nvAssertFailed(); \
nvAssertFailed(0); \
COVERITY_ASSERT_FAIL(); \
PORT_BREAKPOINT(); \
} while(0)
@@ -155,7 +171,7 @@ void nvAssertOkFailed(NvU32 status);
do { \
NV_LOG_SPECIAL(LEVEL_ERROR, RM_GSP_LOG_SPECIAL_ASSERT_OK_FAILED, \
exprStr "\n", status); \
nvAssertOkFailed(status); \
nvAssertOkFailed(status, 0); \
COVERITY_ASSERT_FAIL(); \
PORT_BREAKPOINT(); \
} while(0)
@@ -174,18 +190,6 @@ void nvAssertOkFailed(NvU32 status);
#else // defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS)
#if NV_ASSERT_FAILED_USES_STRINGS
#define NV_ASSERT_FAILED_FUNC_COMMA_PARAM(exprStr) , exprStr, __FILE__, __LINE__
#define NV_ASSERT_FAILED_FUNC_PARAM(exprStr) exprStr, __FILE__, __LINE__
#define NV_ASSERT_FAILED_FUNC_COMMA_TYPE ,const char *pszExpr, const char *pszFileName, NvU32 lineNum
#define NV_ASSERT_FAILED_FUNC_TYPE const char *pszExpr, const char *pszFileName, NvU32 lineNum
#else
#define NV_ASSERT_FAILED_FUNC_COMMA_PARAM(exprStr) , __LINE__
#define NV_ASSERT_FAILED_FUNC_PARAM(exprStr) __LINE__
#define NV_ASSERT_FAILED_FUNC_COMMA_TYPE , NvU32 lineNum
#define NV_ASSERT_FAILED_FUNC_TYPE NvU32 lineNum
#endif
void nvAssertInit(void);
void nvAssertDestroy(void);

18
src/nvidia/inc/libraries/utils/nvbitvector.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -297,8 +297,8 @@ NV_STATUS
bitVectorClr_IMPL
(
NV_BITVECTOR *pBitVector,
NvU16 bitVectorLast,
NvU16 idx
NvU32 bitVectorLast,
NvU32 idx
);
NV_STATUS
@@ -320,8 +320,8 @@ NV_STATUS
bitVectorSet_IMPL
(
NV_BITVECTOR *pBitVector,
NvU16 bitVectorLast,
NvU16 idx
NvU32 bitVectorLast,
NvU32 idx
);
NV_STATUS
@@ -336,8 +336,8 @@ NV_STATUS
bitVectorInv_IMPL
(
NV_BITVECTOR *pBitVector,
NvU16 bitVectorLast,
NvU16 idx
NvU32 bitVectorLast,
NvU32 idx
);
NV_STATUS
@@ -393,8 +393,8 @@ NvBool
bitVectorTest_IMPL
(
const NV_BITVECTOR *pBitVector,
NvU16 bitVectorLast,
NvU16 idx
NvU32 bitVectorLast,
NvU32 idx
);
NV_STATUS

10
src/nvidia/inc/libraries/utils/nvprintf.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -67,13 +67,7 @@ extern "C" {
// Direct dmesg printing through NV_PRINTF_STRING is a no-op on GSP-RM
#define NV_PRINTF_STRING(module, level, format, ...)
#if defined(GSP_PLUGIN_BUILD)
void log_vgpu_log_entry(const NvU64 n_args, const NvU64 * args);
#define LIBOS_LOG_ENTRY log_vgpu_log_entry
#else
void log_rm_log_entry(const NvU64 n_args, const NvU64 * args);
#define LIBOS_LOG_ENTRY log_rm_log_entry
#endif
#define LIBOS_LOG_ENTRY LibosLogEntry
#define NV_PRINTF(level, format, ...) do { \
if (NV_PRINTF_LEVEL_ENABLED(level)) \