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This commit is contained in:
Maneet Singh
2025-08-04 11:15:02 -07:00
parent d890313300
commit 307159f262
1315 changed files with 477791 additions and 279973 deletions
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49
src/nvidia/inc/kernel/gpu/disp/kern_disp_type.h
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@@ -30,21 +30,6 @@
*
******************************************************************************/
#define NV_PDISP_CHN_NUM_ANY 0x7F
#define DISP_ACCL_NONE (0x00)
#define DISP_ACCL_IGNORE_PI NVBIT(0)
#define DISP_ACCL_SKIP_NOTIF NVBIT(1)
#define DISP_ACCL_SKIP_SEMA NVBIT(2)
#define DISP_ACCL_IGNORE_INTERLOCK NVBIT(3)
#define DISP_ACCL_IGNORE_FLIPLOCK NVBIT(4)
#define DISP_ACCL_TRASH_ONLY NVBIT(5)
#define DISP_ACCL_TRASH_AND_ABORT NVBIT(6)
#define DISP_ACCL_SKIP_SYNCPOINT NVBIT(7)
#define DISP_ACCL_IGNORE_TIMESTAMP NVBIT(8)
#define DISP_ACCL_IGNORE_MGI NVBIT(9)
#define DISP_ACCL_DISABLE_PUTPTR_WRITE NVBIT(16)
#define DISP_ACCL_LOCK_PIO_FIFO NVBIT(16)
#define DISP_ACCL_DISABLE_INTR_DURING_SHTDWN NVBIT(17)
#define DISP_ACCL_ALL ~(DISP_ACCL_NONE)
typedef enum
{
@@ -59,31 +44,6 @@ typedef enum
dispChnClass_Supported
} DISPCHNCLASS;
typedef enum
{
dispChnState_Idle,
dispChnState_Wrtidle,
dispChnState_Empty,
dispChnState_Flushed,
dispChnState_Busy,
dispChnState_Dealloc,
dispChnState_DeallocLimbo,
dispChnState_Limbo1,
dispChnState_Limbo2,
dispChnState_Fcodeinit1,
dispChnState_Fcodeinit2,
dispChnState_Fcode,
dispChnState_Vbiosinit1,
dispChnState_Vbiosinit2,
dispChnState_Vbiosoper,
dispChnState_Unconnected,
dispChnState_Initialize1,
dispChnState_Initialize2,
dispChnState_Shutdown1,
dispChnState_Shutdown2,
dispChnState_Supported
} DISPCHNSTATE;
enum DISPLAY_ICC_BW_CLIENT
{
DISPLAY_ICC_BW_CLIENT_RM,
@@ -105,13 +65,4 @@ typedef struct
NvBool valid;
} VGAADDRDESC;
//
// Map HW channel state to SW channel state
//
typedef struct
{
NvU32 hwChannelState;
DISPCHNSTATE dispChnState;
} CHNSTATEMAP;
#endif // #ifndef KERN_DISP_TYPE_H

4
src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -238,7 +238,7 @@ NV_STATUS gsyncRefSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFT
NV_STATUS gsyncRefMaster_P2060 (OBJGPU *, OBJGSYNC *, REFTYPE, NvU32 *DisplayMask,
NvU32 *Refresh, NvBool retainMaster,
NvBool skipSwapBarrierWar);
NV_STATUS gsyncRefSlaves_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *DisplayMask_s, NvU32 *Refresh);
NV_STATUS gsyncRefSlaves_P2060 (OBJGPU *, OBJGSYNC *, REFTYPE, NvU32 *DisplayMask_s, NvU32 *Refresh);
NV_STATUS gsyncGetCplStatus_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSTATUS, NvU32 *);
NV_STATUS gsyncGetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);

4
src/nvidia/inc/kernel/gpu/external_device/dac_p2061.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,7 +33,7 @@ NV_STATUS gsyncSetHouseSyncMode_P2061(OBJGPU *, DACEXTERNALDEVICE *, NvU8);
NV_STATUS gsyncGetCplStatus_P2061 (OBJGPU *, DACEXTERNALDEVICE *, GSYNCSTATUS, NvU32 *);
NV_STATUS gsyncSetSyncSkew_P2061_V204(OBJGPU *, DACEXTERNALDEVICE *, NvU32);
NV_STATUS gsyncGetSyncSkew_P2061_V204(OBJGPU *, DACEXTERNALDEVICE *, NvU32 *);
NV_STATUS gsyncSetRasterSyncDecodeMode_P2061_V300(OBJGPU *, DACEXTERNALDEVICE *);
NV_STATUS gsyncSetRasterSyncDecodeMode_P2061_V300(OBJGPU *, OBJGPU *, DACEXTERNALDEVICE *);
NV_STATUS gsyncGetVRR_P2061_V300(OBJGPU *, DACEXTERNALDEVICE *, NvU32 *);
NV_STATUS gsyncSetVRR_P2061_V300(OBJGPU *, DACEXTERNALDEVICE *, NvU32);

3
src/nvidia/inc/kernel/gpu/gpu_arch.h Normal file
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@@ -0,0 +1,3 @@
#include "g_gpu_arch_nvoc.h"

8
src/nvidia/inc/kernel/gpu/gpu_child_list.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -228,6 +228,9 @@
#if GPU_CHILD_MODULE(HDACODEC)
GPU_CHILD_SINGLE_INST( OBJHDACODEC, GPU_GET_HDACODEC, 1, NV_FALSE, pHdacodec )
#endif
#if GPU_CHILD_MODULE(GCX)
GPU_CHILD_SINGLE_INST( GCX, GPU_GET_GCX, 1, NV_FALSE, pGcx )
#endif
#if GPU_CHILD_MODULE(LPWR)
GPU_CHILD_SINGLE_INST( Lpwr, GPU_GET_LPWR, 1, NV_FALSE, pLpwr )
#endif
@@ -313,6 +316,9 @@
#if RMCFG_MODULE_KERNEL_GSPLITE && GPU_CHILD_MODULE(KERNEL_GSPLITE)
GPU_CHILD_MULTI_INST( KernelGsplite, GPU_GET_KERNEL_GSPLITE, GPU_MAX_GSPLITES, NV_FALSE, pKernelGsplite )
#endif
#if RMCFG_MODULE_KERNEL_HFRP && GPU_CHILD_MODULE(KERNEL_HFRP)
GPU_CHILD_SINGLE_INST( KernelHFRP, GPU_GET_KERNEL_HFRP, 1, NV_FALSE, pKernelHfrp )
#endif
// Undefine the entry macros to simplify call sites
#undef GPU_CHILD

5
src/nvidia/inc/kernel/gpu/gpu_device_mapping.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -39,6 +39,7 @@ typedef enum
DEVICE_INDEX_FUSE,
DEVICE_INDEX_KFUSE,
DEVICE_INDEX_MIPICAL,
DEVICE_INDEX_HFRP,
DEVICE_INDEX_MAX //Should always be the last entry
} DEVICE_INDEX;
@@ -47,6 +48,8 @@ typedef enum
SOC_DEV_MAPPING_DISP = 0,
SOC_DEV_MAPPING_DPAUX0,
SOC_DEV_MAPPING_DPAUX1,
SOC_DEV_MAPPING_DPAUX2,
SOC_DEV_MAPPING_DPAUX3, // Update NV_MAX_SOC_DPAUX_NUM_DEVICES if adding new DPAUX mappings
SOC_DEV_MAPPING_HDACODEC,
SOC_DEV_MAPPING_MIPICAL,
SOC_DEV_MAPPING_MAX

4
src/nvidia/inc/kernel/gpu/gpu_engine_type.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -71,7 +71,6 @@ typedef enum
RM_ENGINE_TYPE_NVENC0 = (0x00000025),
RM_ENGINE_TYPE_NVENC1 = (0x00000026),
RM_ENGINE_TYPE_NVENC2 = (0x00000027),
// Bug 4175886 - Use this new value for all chips once GB20X is released
RM_ENGINE_TYPE_NVENC3 = (0x00000028),
RM_ENGINE_TYPE_VP = (0x00000029),
RM_ENGINE_TYPE_ME = (0x0000002a),
@@ -130,7 +129,6 @@ typedef enum
#define RM_ENGINE_TYPE_NVJPG RM_ENGINE_TYPE_NVJPEG0
#define RM_ENGINE_TYPE_COPY_SIZE 20
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define RM_ENGINE_TYPE_NVENC_SIZE 4
#define RM_ENGINE_TYPE_NVJPEG_SIZE 8
#define RM_ENGINE_TYPE_NVDEC_SIZE 8

2
src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h
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@@ -42,6 +42,8 @@ NV_STATUS gpuFabricProbeStart(OBJGPU *pGpu,
void gpuFabricProbeStop(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
void gpuFabricProbeStopPhysical(GPU_FABRIC_PROBE_INFO_PHYSICAL *pGpuFabricProbeInfoPhysical,
NvU32 gfId);
NV_STATUS gpuFabricProbeSuspendPhysical(GPU_FABRIC_PROBE_INFO_PHYSICAL *pGpuFabricProbeInfoPhysical, NvU32 *pPrevBwMode);
NV_STATUS gpuFabricProbeResumePhysical(GPU_FABRIC_PROBE_INFO_PHYSICAL *pGpuFabricProbeInfoPhysical, NvU32 newBwMode);
void gpuFabricProbeSuspend(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
void gpuFabricProbeInvalidate(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);

4
src/nvidia/inc/kernel/gpu/gpu_timeout.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -45,7 +45,7 @@ struct OBJGPU;
#define GPU_TIMEOUT_FLAGS_DEFAULT NVBIT(0) //!< default timeout mechanism as set by platform
#define GPU_TIMEOUT_FLAGS_USE_THREAD_STATE NVBIT(1) //!< default timeout time used - use the ThreadState
#define GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE NVBIT(2) //!< even if default time was used - skip the ThreadState
#define GPU_TIMEOUT_FLAGS_OSTIMER NVBIT(3) //!< osGetCurrentTime()
#define GPU_TIMEOUT_FLAGS_OSTIMER NVBIT(3) //!< osGetSystemTime()
#define GPU_TIMEOUT_FLAGS_OSDELAY NVBIT(4) //!< osDelay()
#define GPU_TIMEOUT_FLAGS_TMR NVBIT(5) //!< tmrGetCurrentTime()
#define GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG NVBIT(6) //!< bypass timeout logging in the RM journal

20
src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -69,17 +69,21 @@
#define GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE ((48 << 10) * 2048) // Support 2048 channels
#if RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
#define BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA (12u)
#define BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA (13u)
#define BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA (10u)
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT \
((581u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA)) << 20)
#define GSP_FW_HEAP_SIZE_VGPU_48VMS \
((1370u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA)) << 20)
#else
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (581 << 20)
// for more information on how these values are calculated, refer to init_partition.h where
// the breakdown of formula is included. The asserts describe the values needed.
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (581 << 20)
#define GSP_FW_HEAP_SIZE_VGPU_48VMS (1370u << 20)
#endif // RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
// Min/max bounds for heap size override by regkey
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB (64u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB (256u)
@@ -97,12 +101,16 @@
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB \
(581u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA))
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB \
(1093u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA))
#else
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB (88u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB (280u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB (581u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB (1093u)
#endif // RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB (1040u)
#endif // GSP_FW_HEAP_H

4
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
View File

@@ -164,6 +164,8 @@ typedef struct GspStaticConfigInfo_t
EcidManufacturingInfo ecidInfo[MAX_GROUP_COUNT];
FW_WPR_LAYOUT_OFFSET fwWprLayoutOffset;
NvBool bSystemRebootRequired;
} GspStaticConfigInfo;
// Pushed from CPU-RM to GSP-RM
@@ -203,6 +205,7 @@ typedef struct GspSystemInfo
BUSINFO chipsetIDInfo;
ACPI_METHOD_DATA acpiMethodData;
NvU32 hypervisorType;
NvU16 virtualConfigBits;
NvBool bIsPassthru;
NvU64 sysTimerOffsetNs;
GSP_VF_INFO gspVFInfo;
@@ -217,6 +220,7 @@ typedef struct GspSystemInfo
NvBool bClockBoostSupported;
NvU64 hostPageSize;
NvBool bIsCmcBasedHws;
NvBool bGspNocatEnabled;
} GspSystemInfo;

73
src/nvidia/inc/kernel/gpu/hfrp/kern_hfrp_commands_responses.h Normal file
View File

@@ -0,0 +1,73 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _KERN_HFRP_COMMANDS_RESPONSES_H_
#define _KERN_HFRP_COMMANDS_RESPONSES_H_
#include "nvtypes.h"
// default parameter values
#define HFRP_DEFAULT_CLIENT_VERSION 0U
#define HFRP_DEFAULT_SERVER_VERSION 0U
/*!
* CMD_SOC_SET_DEVICE_POWER_STATE
*
* This command sets device power state for Nvidia IPs.
* It is expected that HFRP will follow device power state handling sequence specific to each device.
*
* Command Params:
* deviceId
* Specifies the device ID whose power state needs to be changed.
* 0 - iGPU (This includes iGPU and Display)
* 1 - DLA
* 2 - HDA
* powerState
* 0 - D0 i.e. Power up
* 1 - D3 i.e. Power down
*
*/
#define HFRP_CMD_SOC_SET_DEVICE_POWER_STATE 303U
#pragma pack(1)
typedef struct
{
NvU8 deviceId;
NvU8 powerState;
} CMD_SOC_SET_DEVICE_POWER_STATE_PARAMS;
#pragma pack()
#define NV_CMD_SOC_SET_DEVICE_POWER_STATE_PARAM_DEVICE_ID_IGPU 0U
#define NV_CMD_SOC_SET_DEVICE_POWER_STATE_PARAM_DEVICE_ID_DLA 1U
#define NV_CMD_SOC_SET_DEVICE_POWER_STATE_PARAM_DEVICE_ID_HDA 2U
#define NV_CMD_SOC_SET_DEVICE_POWER_STATE_PARAM_POWER_STATE_D0 0U
#define NV_CMD_SOC_SET_DEVICE_POWER_STATE_PARAM_POWER_STATE_D3 1U
#endif // _KERN_HFRP_COMMANDS_RESPONSES_H_

130
src/nvidia/inc/kernel/gpu/hfrp/kern_hfrp_common.h Normal file
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@@ -0,0 +1,130 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _KERN_HFRP_COMMON_H_
#define _KERN_HFRP_COMMON_H_
#include "nvtypes.h"
typedef enum
{
HFRP_COMMAND_MAILBOX_INDEX_PMU = 0,
HFRP_RESPONSE_MAILBOX_INDEX_PMU = 1,
HFRP_COMMAND_MAILBOX_INDEX_SHIM = 2,
HFRP_RESPONSE_MAILBOX_INDEX_SHIM = 2,
HFRP_COMMAND_MAILBOX_INDEX_DISPLAY = 3,
HFRP_RESPONSE_MAILBOX_INDEX_DISPLAY = 4
} HFRP_MAILBOX_INDEX;
// Size of range of registers for which the aperture is created
#define HFRP_MAILBOX_ACCESS_RANGE 0x200
// Mailbox Layout Address Offsets 1.0 version
// Mailbox Layout Address Offsets 1.0 version
#define HFRP_COMMAND_BUFFER_HEAD_PTR_ADDR_ONE_MAILBOX_INTERFACE 0x110
#define HFRP_COMMAND_BUFFER_TAIL_PTR_ADDR_ONE_MAILBOX_INTERFACE 0x189
#define HFRP_COMMAND_BUFFER_START_ADDR_ONE_MAILBOX_INTERFACE 0x114
#define HFRP_COMMAND_BUFFER_END_ADDR_ONE_MAILBOX_INTERFACE 0x187
#define HFRP_RESPONSE_BUFFER_HEAD_PTR_ADDR_ONE_MAILBOX_INTERFACE 0x188
#define HFRP_RESPONSE_BUFFER_TAIL_PTR_ADDR_ONE_MAILBOX_INTERFACE 0x111
#define HFRP_RESPONSE_BUFFER_START_ADDR_ONE_MAILBOX_INTERFACE 0x18C
#define HFRP_RESPONSE_BUFFER_END_ADDR_ONE_MAILBOX_INTERFACE 0x1FF
#define HFRP_COMMAND_BUFFER_HEAD_PTR_ADDR_TWO_MAILBOX_INTERFACE 0x110
#define HFRP_COMMAND_BUFFER_TAIL_PTR_ADDR_TWO_MAILBOX_INTERFACE (0x111 + HFRP_MAILBOX_ACCESS_RANGE)
#define HFRP_COMMAND_BUFFER_START_ADDR_TWO_MAILBOX_INTERFACE 0x114
#define HFRP_COMMAND_BUFFER_END_ADDR_TWO_MAILBOX_INTERFACE 0x1FF
#define HFRP_RESPONSE_BUFFER_HEAD_PTR_ADDR_TWO_MAILBOX_INTERFACE (0x110 + HFRP_MAILBOX_ACCESS_RANGE)
#define HFRP_RESPONSE_BUFFER_TAIL_PTR_ADDR_TWO_MAILBOX_INTERFACE 0x111
#define HFRP_RESPONSE_BUFFER_START_ADDR_TWO_MAILBOX_INTERFACE (0x114 + HFRP_MAILBOX_ACCESS_RANGE)
#define HFRP_RESPONSE_BUFFER_END_ADDR_TWO_MAILBOX_INTERFACE (0x1FF + HFRP_MAILBOX_ACCESS_RANGE)
#define HFRP_IRQ_IN_SET_ADDR 0x100
#define HFRP_IRQ_OUT_SET_ADDR 0x104
#define HFRP_IRQ_IN_CLR_ADDR 0x108
#define HFRP_IRQ_OUT_CLR_ADDR 0x10C
// Size of message (command or response) header in bytes
#define HFRP_MESSAGE_HEADER_BYTE_SIZE 4U
#define HFRP_MESSAGE_FIELD_SIZE 7U : 0U
#define HFRP_MESSAGE_FIELD_SEQUENCE_ID 17U : 8U
#define HFRP_MESSAGE_FIELD_INDEX_OR_STATUS 27U : 18U
//
// Maximum values of Sequence Id index and Sequence Id Array index (each
// Sequence Id array element has 32 bits that represent 32 Sequence Ids)
//
#define HFRP_NUMBER_OF_SEQUENCEID_INDEX 0x400
#define HFRP_NUMBER_OF_SEQUENCEID_ARRAY_INDEX (HFRP_NUMBER_OF_SEQUENCEID_INDEX / 32U)
#define HFRP_ASYNC_NOTIFICATION_SEQUENCEID_INDEX 0x3FF
// HFRP IRQ Reset and Doorbell bit indices
#define HFRP_IRQ_RESET_BIT_INDEX 0U
#define HFRP_IRQ_DOORBELL_BIT_INDEX 1U
// Mailbox Interface types
#define HFRP_ONE_MAILBOX_INTERFACE 0U
#define HFRP_TWO_MAILBOX_INTERFACE 1U
// Mailbox flags
#define HFRP_COMMAND_MAILBOX_FLAG 0U
#define HFRP_RESPONSE_MAILBOX_FLAG 1U
// macros for supporting DRF operations
#define NV_HFRP_BYTE_FIELD(x) (8U * (x) + 7U) : (8U * (x))
typedef struct
{
NvU32 hfrpCommandBufferHeadPtrAddr;
NvU32 hfrpCommandBufferTailPtrAddr;
NvU32 hfrpCommandBufferStartAddr;
NvU32 hfrpCommandBufferEndAddr;
NvU32 hfrpResponseBufferHeadPtrAddr;
NvU32 hfrpResponseBufferTailPtrAddr;
NvU32 hfrpResponseBufferStartAddr;
NvU32 hfrpResponseBufferEndAddr;
NvU32 hfrpIrqInSetAddr;
NvU32 hfrpIrqOutSetAddr;
NvU32 hfrpIrqInClrAddr;
NvU32 hfrpIrqOutClrAddr;
} HFRP_MAILBOX_IO_INFO;
typedef struct
{
NvU32 sequenceIdState[HFRP_NUMBER_OF_SEQUENCEID_ARRAY_INDEX];
NvU8 *pResponsePayloadArray[HFRP_NUMBER_OF_SEQUENCEID_INDEX];
NvU16 *pResponseStatusArray[HFRP_NUMBER_OF_SEQUENCEID_INDEX];
NvU32 *pResponsePayloadSizeArray[HFRP_NUMBER_OF_SEQUENCEID_INDEX];
NV_STATUS *pStatusArray[HFRP_NUMBER_OF_SEQUENCEID_INDEX];
NvU8 sequenceIdArrayIndex;
} HFRP_SEQUENCEID_INFO;
typedef struct
{
HFRP_MAILBOX_IO_INFO mailboxIoInfo;
HFRP_SEQUENCEID_INFO sequenceIdInfo;
} HFRP_INFO;
#endif // _KERN_HFRP_COMMON_H_

117
src/nvidia/inc/kernel/gpu/hfrp/kernel_hfrp.h Normal file
View File

@@ -0,0 +1,117 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "g_kernel_hfrp_nvoc.h"
#ifndef _KERNELHFRP_H_
#define _KERNELHFRP_H_
#include "nvtypes.h"
#include "nvstatus.h"
#include "nvmisc.h"
#include "utils/nvprintf.h"
#include "os/os.h"
#include "gpu/eng_state.h"
#include "gpu/gpu.h"
#include "gpu/hfrp/kern_hfrp_common.h"
// Total number of HFRP Mailboxes available for the interface
#define HFRP_NUMBER_OF_MAILBOXES 2U
// Maximum Payload size for a message
#define HFRP_MAX_PAYLOAD_SIZE 50U
#define HFRP_COMMAND_MAILBOX_INDEX HFRP_COMMAND_MAILBOX_INDEX_DISPLAY
#define HFRP_RESPONSE_MAILBOX_INDEX HFRP_RESPONSE_MAILBOX_INDEX_DISPLAY
//
// Maximum values of Sequence Id index and Sequence Id Array index (each
// Sequence Id array element has 32 bits that represent 32 Sequence Ids)
//
#define HFRP_NUMBER_OF_SEQUENCEID_INDEX 0x400
#define HFRP_NUMBER_OF_SEQUENCEID_ARRAY_INDEX (HFRP_NUMBER_OF_SEQUENCEID_INDEX / 32U)
#define HFRP_ASYNC_NOTIFICATION_SEQUENCEID_INDEX 0x3FF
NVOC_PREFIX(khfrp) class KernelHFRP: OBJENGSTATE
{
public:
/*! HFRP Create Object */
virtual NV_STATUS khfrpStatePreInitLocked(OBJGPU *pGpu, KernelHFRP *pHfrp);
virtual NV_STATUS khfrpConstructEngine(OBJGPU *pGpu, KernelHFRP *pHfrp, ENGDESCRIPTOR engDesc);
/*! HFRP Destructor */
void khfrpDestruct(KernelHFRP *pHfrp);
void khfrpCommonConstruct(KernelHFRP *pHfrp);
NV_STATUS khfrpIoApertureConstruct(OBJGPU *pGpu, KernelHFRP *pHfrp);
void khfrpIoApertureDestruct(KernelHFRP *pHfrp, NvU32 index);
NvU32 khfrpReadBit(KernelHFRP *pHfrp, NvU32 virtualAddr, NvU32 bitIndex);
void khfrpWriteBit(KernelHFRP *pHfrp, NvU32 virtualAddr, NvU32 bitIndex, NvU32 data);
NV_STATUS khfrpMailboxQueueMessage(KernelHFRP *pHfrp, NvU32 messageHeader, NvU8 *pPayloadArray,
NvU32 payloadSize, NvU32 mailboxFlag);
void khfrpServiceEvent(KernelHFRP *pHfrp);
NvU32 khfrpAllocateSequenceId(KernelHFRP *pHfrp, NvU16 *pResponseStatus, void *pResponsePayload,
NvU32 *pResponsePayloadSize, NV_STATUS *pStatus, NvU32 *pSequenceId);
void khfrpFreeSequenceId(KernelHFRP *pHfrp, NvU32 index);
NvBool khfrpIsSequenceIdFree(KernelHFRP *pHfrp, NvU32 index);
NV_STATUS khfrpPollOnIrqWrapper(KernelHFRP *pHfrp, NvU32 irqRegAddr, NvU32 bitIndex, NvBool bData);
NV_STATUS khfrpPollOnIrqRm(KernelHFRP *pHfrp, NvU32 irqRegAddr, NvU32 bitIndex, NvBool bData);
NV_STATUS khfrpPostCommandBlocking(KernelHFRP *pHfrp, NvU16 commandIndex, void *pCommandPayload, NvU32 commandPayloadSize,
NvU16 *pResponseStatus, void *pResponsePayload, NvU32 *pResponsePayloadSize, NV_STATUS *pStatus);
NV_STATUS khfrpInterfaceReset(KernelHFRP *pHfrp);
NVOC_PROPERTY NvBool PDB_PROP_KHFRP_IS_ENABLED;
NvU32 khfrpPrivBase[5];
NvU32 khfrpIntrCtrlReg[5];
IoAperture *pAperture[HFRP_NUMBER_OF_MAILBOXES];
HFRP_INFO khfrpInfo;
};
#define HFRP_REG_RD32(pKernelHfrp, virtualAddr) \
REG_RD32(pKernelHfrp->pAperture[virtualAddr / HFRP_MAILBOX_ACCESS_RANGE], \
virtualAddr % HFRP_MAILBOX_ACCESS_RANGE)
#define HFRP_REG_WR32(pKernelHfrp, virtualAddr, data32) \
REG_WR32(pKernelHfrp->pAperture[virtualAddr / HFRP_MAILBOX_ACCESS_RANGE], \
virtualAddr % HFRP_MAILBOX_ACCESS_RANGE, data32)
#define HFRP_POLL_ON_IRQ(pKernelHfrp, irqRegAddr, bitIndex, bData) \
khfrpPollOnIrqRm(pKernelHfrp, irqRegAddr, bitIndex, bData)
#endif // _KernelHFRP_H_

7
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -78,7 +78,6 @@
#define MC_ENGINE_IDX_NVENC 38
#define MC_ENGINE_IDX_NVENC1 39
#define MC_ENGINE_IDX_NVENC2 40
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define MC_ENGINE_IDX_NVENC3 41
#define MC_ENGINE_IDX_C2C 42
#define MC_ENGINE_IDX_LTC 43
@@ -153,7 +152,6 @@
#define MC_ENGINE_IDX_PXUC 168
#define MC_ENGINE_IDX_SYSLTC 169
#define MC_ENGINE_IDX_LRCC 170
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define MC_ENGINE_IDX_GSPLITE 171
#define MC_ENGINE_IDX_GSPLITE0 MC_ENGINE_IDX_GSPLITE
#define MC_ENGINE_IDX_GSPLITE1 172
@@ -192,10 +190,7 @@
// Index OFA reference
#define MC_ENGINE_IDX_OFA(x) (MC_ENGINE_IDX_OFA0 + (x))
//
// Bug 4175886 - Remove check once GB20X is released
// Index GSPLITE reference
//
#define MC_ENGINE_IDX_GSPLITEn(x) (MC_ENGINE_IDX_GSPLITE + (x))
MAKE_BITVECTOR(MC_ENGINE_BITVECTOR, MC_ENGINE_IDX_MAX);

15
src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -116,13 +116,13 @@
#define READ_CHANNEL_PAYLOAD_SEMA(channel) channelReadChannelMemdesc(channel, channel->finishPayloadOffset)
#define READ_CHANNEL_PB_SEMA(channel) channelReadChannelMemdesc(channel, channel->semaOffset)
//
// This struct contains parameters needed to send a pushbuffer for a CE
// operation. This interface only supports contiguous operations.
//
typedef struct
// This struct contains parameters needed to send a pushbuffer for a CE
// operation. This interface only supports contiguous operations.
//
typedef struct
{
NvBool bCeMemcopy; // Whether this is a CE memcopy;
NvBool bCeMemcopy; // Whether this is a CE memcopy;
// If set to false, this will be a memset operation
NvU64 dstAddr; // Physical address of the source address
NvU64 srcAddr; // Physical address of the source address; only valid for memcopy
@@ -152,11 +152,12 @@ NV_STATUS channelWaitForFreeEntry(OBJCHANNEL *pChannel, NvU32 *pPutIndex);
NV_STATUS channelFillGpFifo(OBJCHANNEL *pChannel, NvU32 putIndex, NvU32 methodsLength);
NvU32 channelFillCePb(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined,
NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo);
NvU32 channelFillPbFastScrub(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined,
NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo);
NV_STATUS channelFillSec2Pb(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bInsertFinishPayload,
CHANNEL_PB_INFO *pChannelPbInfo, CCSL_CONTEXT *pCcslCtx,
CHANNEL_PB_INFO *pChannelPbInfo, CCSL_CONTEXT *pCcslCtx,
MEMORY_DESCRIPTOR *pScrubMemDesc, MEMORY_DESCRIPTOR *pSemaMemDesc,
NvU64 scrubMthdAuthTagBufGpuVA, NvU32 scrubAuthTagBufIndex,
NvU64 semaMthdAuthTagBufGpuVA, NvU32 semaAuthTagBufIndex, NvU32* methodLength);

3
src/nvidia/inc/kernel/gpu/mem_mgr/heap_base.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -117,7 +117,6 @@ typedef struct HWRESOURCE_INFO
NvU32 hwResId;
NvU32 refCount;
NvBool isVgpuHostAllocated; // used in vGPU guest RM to indicate if this HW resource is allocated by host RM or not. Used in Windows guest.
NvBool isGuestAllocated; // used in vGPU host RM to indicate if this HW resource is allocated from LIST_OBJECT path on behalf of Linux guest.
} HWRESOURCE_INFO;

2
src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h
View File

@@ -129,7 +129,7 @@ NV_STATUS scrubberConstruct(struct OBJGPU *pGpu, struct Heap *pHeap);
*
*/
void scrubberDestruct(struct OBJGPU *pGpu, struct Heap *pHeap, OBJMEMSCRUB *pMemscrub);
void scrubberDestruct(struct OBJGPU *pGpu, struct Heap *pHeap);
/**

1
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h
View File

@@ -60,7 +60,6 @@ extern "C" {
#define PMA_LOCALIZED_MEMORY_ALLOC_STRIDE (32ULL * 1024 * 1024)
#define PMA_LOCALIZED_MEMORY_RESERVE_SIZE (2 * PMA_LOCALIZED_MEMORY_ALLOC_STRIDE)
typedef NvU32 PMA_PAGESTATUS;
#define MAP_IDX_ALLOC_UNPIN 0

147
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -41,7 +41,7 @@
#define PHYS_MEM_ALLOCATOR_H
#include "nvport/nvport.h"
#include "regmap.h"
#include "map_defines.h"
#include "nvmisc.h"
#if defined(SRT_BUILD)
@@ -58,10 +58,6 @@ extern "C" {
typedef struct OBJMEMSCRUB OBJMEMSCRUB;
typedef struct SCRUB_NODE SCRUB_NODE;
#define PMA_REGION_SIZE 32
#define PMA_ADDR2FRAME(addr, base) (((addr) - (base)) >> PMA_PAGE_SHIFT)
#define PMA_FRAME2ADDR(frame, base) ((base) + ((frame) << PMA_PAGE_SHIFT))
//
// These flags are used for initialization in order to set global PMA states,
// in case we need to wait for scrubber to be initialized or wait for a NUMA
@@ -109,19 +105,6 @@ typedef struct SCRUB_NODE SCRUB_NODE;
// These are flags input to the pmaFreePages call
#define PMA_FREE_SKIP_SCRUB NVBIT(0)
// State bits for debugging utilities like nvwatch
#define PMA_SCRUB_INITIALIZE 0
#define PMA_SCRUB_IN_PROGRESS 1
#define PMA_SCRUB_DONE 2
#define PMA_SCRUBBER_VALID 1
#define PMA_SCRUBBER_INVALID 0
#define PMA_NUMA_NO_NODE -1
// Maximum blacklist entries possible
#define PMA_MAX_BLACKLIST_ENTRIES 512
typedef struct
{
NvU32 flags;
@@ -180,97 +163,6 @@ typedef NV_STATUS (*pmaEvictPagesCb_t)(void *ctxPtr, NvU64 pageSize, NvU64 *pPag
typedef NV_STATUS (*pmaEvictRangeCb_t)(void *ctxPtr, NvU64 physBegin, NvU64 physEnd,
MEMORY_PROTECTION prot);
/*!
* @brief Pluggable data structure management. Currently we have regmap.
*/
typedef void *(*pmaMapInit_t)(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected);
typedef void (*pmaMapDestroy_t)(void *pMap);
typedef void (*pmaMapChangeStateAttrib_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef void (*pmaMapChangePageStateAttrib_t)(void *pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef void (*pmaMapChangeBlockStateAttrib_t)(void *pMap, NvU64 frameNum, NvU64 numFrames, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef PMA_PAGESTATUS (*pmaMapRead_t)(void *pMap, NvU64 frameNum, NvBool readAttrib);
typedef NV_STATUS (*pmaMapScanContiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 stride, NvU32 strideStart,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
typedef NV_STATUS (*pmaMapScanDiscontiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 stride, NvU32 strideStart,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
typedef void (*pmaMapGetSize_t)(void *pMap, NvU64 *pBytesTotal);
typedef void (*pmaMapGetLargestFree_t)(void *pMap, NvU64 *pLargestFree);
typedef NV_STATUS (*pmaMapScanContiguousNumaEviction_t)(void *pMap, NvU64 addrBase, NvLength actualSize,
NvU64 pageSize, NvU64 *evictStart, NvU64 *evictEnd);
typedef NvU64 (*pmaMapGetEvictingFrames_t)(void *pMap);
typedef void (*pmaMapSetEvictingFrames_t)(void *pMap, NvU64 frameEvictionsInProcess);
struct _PMA_MAP_INFO
{
NvU32 mode;
pmaMapInit_t pmaMapInit;
pmaMapDestroy_t pmaMapDestroy;
pmaMapChangeStateAttrib_t pmaMapChangeStateAttrib;
pmaMapChangePageStateAttrib_t pmaMapChangePageStateAttrib;
pmaMapChangeBlockStateAttrib_t pmaMapChangeBlockStateAttrib;
pmaMapRead_t pmaMapRead;
pmaMapScanContiguous_t pmaMapScanContiguous;
pmaMapScanDiscontiguous_t pmaMapScanDiscontiguous;
pmaMapGetSize_t pmaMapGetSize;
pmaMapGetLargestFree_t pmaMapGetLargestFree;
pmaMapScanContiguousNumaEviction_t pmaMapScanContiguousNumaEviction;
pmaMapGetEvictingFrames_t pmaMapGetEvictingFrames;
pmaMapSetEvictingFrames_t pmaMapSetEvictingFrames;
};
struct _PMA
{
PORT_SPINLOCK *pPmaLock; // PMA-wide lock
PORT_MUTEX *pEvictionCallbacksLock; // Eviction callback registration lock
// Only used when free scrub-on-free feature is turned on
PORT_RWLOCK *pScrubberValidLock; // A reader-writer lock to protect the scrubber valid bit
PORT_MUTEX *pAllocLock; // Used to protect page stealing in the allocation path
// Region related states
NvU32 regSize; // Actual size of regions array
void * pRegions[PMA_REGION_SIZE]; // All the region maps stored as opaque pointers
NvU32 *pSortedFastFirst; // Pre-sorted array of region IDs
PMA_REGION_DESCRIPTOR *pRegDescriptors [PMA_REGION_SIZE]; // Stores the descriptions of each region
PMA_MAP_INFO *pMapInfo; // The pluggable layer for managing scanning
// Allocation related states
void * evictCtxPtr; // Opaque context pointer for eviction callback
pmaEvictPagesCb_t evictPagesCb; // Discontiguous eviction callback
pmaEvictRangeCb_t evictRangeCb; // Contiguous eviction callback
NvU64 frameAllocDemand; // Frame count of allocations in-process
NvBool bForcePersistence; // Force all allocations to persist across suspend/resume
PMA_STATS pmaStats; // PMA statistics used for client heuristics
// Scrubber related states
NvSPtr initScrubbing; // If the init scrubber has finished in this PMA
NvBool bScrubOnFree; // If "scrub on free" is enabled for this PMA object
NvSPtr scrubberValid; // If scrubber object is valid, using atomic variable to prevent races
OBJMEMSCRUB *pScrubObj; // Object to store the FreeScrub header
// NUMA states
NvBool bNuma; // If we are allocating for a NUMA system
NvBool nodeOnlined; // If node is onlined
NvS32 numaNodeId; // Current Node ID, set at initialization. -1 means invalid
NvU64 coherentCpuFbBase; // Used to calculate FB offset from bus address
NvU64 coherentCpuFbSize; // Used for error checking only
NvU32 numaReclaimSkipThreshold; // percent value below which __GFP_RECLAIM will not be used.
NvBool bNumaAutoOnline; // If NUMA memory is auto-onlined
// Blacklist related states
PMA_BLACKLIST_CHUNK *pBlacklistChunks; // Tracking for blacklist pages
NvU32 blacklistCount; // Number of blacklist pages
NvBool bClientManagedBlacklist; // Blacklisted pages in PMA that will be taken over by Client
// RUSD Callback
pmaUpdateStatsCb_t pStatsUpdateCb; // RUSD update free pages
void *pStatsUpdateCtx; // Context for RUSD update
};
/*!
* @brief This must be called before any other PMA functions. Returns a PMA
* object for later use
@@ -289,7 +181,7 @@ struct _PMA
* code, because it is not very informative.
*
*/
NV_STATUS pmaInitialize(PMA *pPma, NvU32 initFlags);
NV_STATUS pmaInitialize(PMA **ppPma, NvU32 initFlags);
/*!
@@ -398,9 +290,6 @@ NV_STATUS pmaRegisterRegion(PMA *pPma, NvU32 id, NvBool bAsyncEccScrub,
* allocation option. For non-contiguous allocations, it's an error to specify
* an alignment larger than the page size.
*
* For broadcast methods, PMA will guarantee the same physical frames are
* allocated on multiple GPUs, specified by the PMA objects passed in.
*
* Implementors note:
* If region registered with asyncEccScrub and pmaScrubComplete
* has not yet been issued then we cannot return NV_ERR_NO_MEMORY.
@@ -461,11 +350,6 @@ NV_STATUS pmaRegisterRegion(PMA *pPma, NvU32 id, NvBool bAsyncEccScrub,
NV_STATUS pmaAllocatePages(PMA *pPma, NvLength pageCount, NvU64 pageSize,
PMA_ALLOCATION_OPTIONS *pAllocationOptions, NvU64 *pPages);
// allocate on multiple GPU, thus pmaCount
NV_STATUS pmaAllocatePagesBroadcast(PMA **pPma, NvU32 pmaCount, NvLength allocationCount,
NvU64 pageSize, PMA_ALLOCATION_OPTIONS *pAllocationOptions, NvU64 *pPages);
/*!
* @brief Marks previously unpinned pages as pinned.
*
@@ -657,6 +541,16 @@ void pmaGetTotalMemory(PMA *pPma, NvU64 *pBytesTotal);
*/
NV_STATUS pmaGetRegionInfo(PMA *pPma, NvU32 *pRegSize, PMA_REGION_DESCRIPTOR **ppRegionDesc);
/*!
* @brief Get the PMA stats object to give to UVM
*
* @param[in] pPma PMA pointer
*
* @return
* PMA_STATS *
*/
PMA_STATS *pmaGetStats(PMA *pPma);
/*!
* @brief Returns information about the total free FB memory.
*
@@ -766,6 +660,16 @@ void pmaFreeAllocatedBlocksList(PMA *pPma, PRANGELISTTYPE *ppList);
*/
NV_STATUS pmaRegMemScrub(PMA *pPma, OBJMEMSCRUB *pScrubObj);
/*!
* @brief Get memory scrubber that PMA currently has (can be NULL)
*
* @param[in] pPma PMA pointer
*
* @return
* OBJMEMSCRUB * pointer to the memory scrubber PMA currently has
*/
OBJMEMSCRUB *pmaGetMemScrub(PMA *pPma);
/*!
* @brief Unregisters the memory scrubber, when the scrubber is torn
@@ -872,11 +776,6 @@ void pmaGetBlacklistSize(PMA *pPma, NvU32 *pDynamicBlacklistSize, NvU32 *pStatic
*/
void pmaClearScrubbedPages(PMA *pPma, SCRUB_NODE *pPmaScrubList, NvU64 count);
/*!
* @brief Print states of all regions
*/
void pmaPrintMapState(PMA *pPma);
/*!
* @brief Track the given physical address as blacklisted page in PMA. This call will blacklist
* the entire PMA page frame of size 64KB which contains the physical address.

150
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_private.h Normal file
View File

@@ -0,0 +1,150 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef PHYS_MEM_ALLOCATOR_PRIVATE_H
#define PHYS_MEM_ALLOCATOR_PRIVATE_H
#include "nvport/nvport.h"
#include "map_defines.h"
#include "nvmisc.h"
#if defined(SRT_BUILD)
#define RMCFG_MODULE_x 1
#define RMCFG_FEATURE_x 1
#else
#include "rmconfig.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
typedef struct OBJMEMSCRUB OBJMEMSCRUB;
typedef struct SCRUB_NODE SCRUB_NODE;
#define PMA_REGION_SIZE 32
#define PMA_NUMA_NO_NODE -1
// Maximum blacklist entries possible
#define PMA_MAX_BLACKLIST_ENTRIES 512
typedef struct _PMA_MAP_INFO PMA_MAP_INFO;
typedef struct _PMA PMA;
/*!
* @brief Pluggable data structure management. Currently we have regmap.
*/
typedef void *(*pmaMapInit_t)(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected);
typedef void (*pmaMapDestroy_t)(void *pMap);
typedef void (*pmaMapChangeStateAttrib_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef void (*pmaMapChangePageStateAttrib_t)(void *pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef void (*pmaMapChangeBlockStateAttrib_t)(void *pMap, NvU64 frameNum, NvU64 numFrames, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask);
typedef PMA_PAGESTATUS (*pmaMapRead_t)(void *pMap, NvU64 frameNum, NvBool readAttrib);
typedef NV_STATUS (*pmaMapScanContiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 stride, NvU32 strideStart,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
typedef NV_STATUS (*pmaMapScanDiscontiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 stride, NvU32 strideStart,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
typedef void (*pmaMapGetSize_t)(void *pMap, NvU64 *pBytesTotal);
typedef void (*pmaMapGetLargestFree_t)(void *pMap, NvU64 *pLargestFree, NvU64 *pLargestFreeBase);
typedef NV_STATUS (*pmaMapScanContiguousNumaEviction_t)(void *pMap, NvU64 addrBase, NvLength actualSize,
NvU64 pageSize, NvU64 *evictStart, NvU64 *evictEnd);
typedef NvU64 (*pmaMapGetEvictingFrames_t)(void *pMap);
typedef void (*pmaMapSetEvictingFrames_t)(void *pMap, NvU64 frameEvictionsInProcess);
struct _PMA_MAP_INFO
{
NvU32 mode;
pmaMapInit_t pmaMapInit;
pmaMapDestroy_t pmaMapDestroy;
pmaMapChangeStateAttrib_t pmaMapChangeStateAttrib;
pmaMapChangePageStateAttrib_t pmaMapChangePageStateAttrib;
pmaMapChangeBlockStateAttrib_t pmaMapChangeBlockStateAttrib;
pmaMapRead_t pmaMapRead;
pmaMapScanContiguous_t pmaMapScanContiguous;
pmaMapScanDiscontiguous_t pmaMapScanDiscontiguous;
pmaMapGetSize_t pmaMapGetSize;
pmaMapGetLargestFree_t pmaMapGetLargestFree;
pmaMapScanContiguousNumaEviction_t pmaMapScanContiguousNumaEviction;
pmaMapGetEvictingFrames_t pmaMapGetEvictingFrames;
pmaMapSetEvictingFrames_t pmaMapSetEvictingFrames;
};
struct _PMA
{
PORT_SPINLOCK *pPmaLock; // PMA-wide lock
PORT_MUTEX *pEvictionCallbacksLock; // Eviction callback registration lock
// Only used when free scrub-on-free feature is turned on
PORT_RWLOCK *pScrubberValidLock; // A reader-writer lock to protect the scrubber valid bit
PORT_MUTEX *pAllocLock; // Used to protect page stealing in the allocation path
// Region related states
NvU32 regSize; // Actual size of regions array
void * pRegions[PMA_REGION_SIZE]; // All the region maps stored as opaque pointers
NvU32 *pSortedFastFirst; // Pre-sorted array of region IDs
PMA_REGION_DESCRIPTOR *pRegDescriptors [PMA_REGION_SIZE]; // Stores the descriptions of each region
PMA_MAP_INFO *pMapInfo; // The pluggable layer for managing scanning
// Allocation related states
void * evictCtxPtr; // Opaque context pointer for eviction callback
pmaEvictPagesCb_t evictPagesCb; // Discontiguous eviction callback
pmaEvictRangeCb_t evictRangeCb; // Contiguous eviction callback
NvU64 frameAllocDemand; // Frame count of allocations in-process
NvBool bForcePersistence; // Force all allocations to persist across suspend/resume
PMA_STATS pmaStats; // PMA statistics used for client heuristics
// Scrubber related states
NvSPtr initScrubbing; // If the init scrubber has finished in this PMA
NvBool bScrubOnFree; // If "scrub on free" is enabled for this PMA object
NvSPtr scrubberValid; // If scrubber object is valid, using atomic variable to prevent races
OBJMEMSCRUB *pScrubObj; // Object to store the FreeScrub header
// NUMA states
NvBool bNuma; // If we are allocating for a NUMA system
NvBool nodeOnlined; // If node is onlined
NvS32 numaNodeId; // Current Node ID, set at initialization. -1 means invalid
NvU64 coherentCpuFbBase; // Used to calculate FB offset from bus address
NvU64 coherentCpuFbSize; // Used for error checking only
NvU32 numaReclaimSkipThreshold; // percent value below which __GFP_RECLAIM will not be used.
NvBool bNumaAutoOnline; // If NUMA memory is auto-onlined
// Blacklist related states
PMA_BLACKLIST_CHUNK *pBlacklistChunks; // Tracking for blacklist pages
NvU32 blacklistCount; // Number of blacklist pages
NvBool bClientManagedBlacklist; // Blacklisted pages in PMA that will be taken over by Client
// RUSD Callback
pmaUpdateStatsCb_t pStatsUpdateCb; // RUSD update free pages
void *pStatsUpdateCtx; // Context for RUSD update
};
#ifdef __cplusplus
}
#endif
#endif // PHYS_MEM_ALLOCATOR_PRIVATE_H

19
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,6 +33,17 @@
extern "C" {
#endif
#define PMA_ADDR2FRAME(addr, base) (((addr) - (base)) >> PMA_PAGE_SHIFT)
#define PMA_FRAME2ADDR(frame, base) ((base) + ((frame) << PMA_PAGE_SHIFT))
// State bits
#define PMA_SCRUB_INITIALIZE 0
#define PMA_SCRUB_IN_PROGRESS 1
#define PMA_SCRUB_DONE 2
#define PMA_SCRUBBER_VALID 1
#define PMA_SCRUBBER_INVALID 0
// TODO See if this can be added to NvPort
#define pmaPortAtomicGet(ptr) portAtomicOrSize((ptr), 0)
@@ -183,16 +194,12 @@ void pmaFreeList(PMA *pPma, PRANGELISTTYPE *ppList);
* @param[in] physAddrBase The base address of this address tree
* @param[in] pBlacklistPageBase Structure that contains the blacklisted pages
* @param[in] blacklistCount Number of blacklisted pages
* @param[in] bBlacklistFromInforom Whether the blacklisted pages are coming from
* inforom (i.e., from heap/PMA init) or not
* (i.e., from ECC interrupt handling)
*
* @return NV_OK
* NV_ERR_NO_MEMORY if memory allocation fails
*/
NV_STATUS pmaRegisterBlacklistInfo(PMA *pPma, NvU64 physAddrBase,
PPMA_BLACKLIST_ADDRESS pBlacklistPageBase, NvU32 blacklistCount,
NvBool bBlacklistFromInforom);
PPMA_BLACKLIST_ADDRESS pBlacklistPageBase, NvU32 blacklistCount);
/*!
* @brief Query blacklisting states tracked by PMA

6
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -229,9 +229,9 @@ void pmaRegmapGetSize(void *pMap, NvU64 *pBytesTotal);
*
* @param[in] pMap Pointer to the regmap for the region
* @param[in] pLargestFree Pointer that will return largest free in current region.
*
* @param[in] pLargestFreeOffset Pointer that will return the offset of the largest free chunk.
*/
void pmaRegmapGetLargestFree(void *pMap, NvU64 *pLargestFree);
void pmaRegmapGetLargestFree(void *pMap, NvU64 *pLargestFree, NvU64 *pLargestFreeOffset);
/*!

2
src/nvidia/inc/kernel/gpu/mem_mgr/rm_page_size.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

21
src/nvidia/inc/kernel/gpu/nvlink/common_nvlink.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,9 +27,28 @@
#include "core/core.h"
#include "kernel/gpu/nvlink/kernel_nvlink.h"
#include "kernel/gpu/nvlink/kernel_ioctrl.h"
#include "utils/nvbitvector.h"
#include "ctrl/ctrl2080/ctrl2080nvlink.h" // rmcontrol params
MAKE_BITVECTOR(NV2080_NVLINK_BIT_VECTOR, NV2080_CTRL_NVLINK_MAX_LINKS);
NV_STATUS nvlinkCtrlCmdBusGetNvlinkCaps(OBJGPU *pGpu, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams);
NV_STATUS
convertMaskToBitVector(NvU64 inputLinkMask, NV2080_NVLINK_BIT_VECTOR *pLocalLinkMask);
NV_STATUS
convertBitVectorToLinkMask32(NV2080_NVLINK_BIT_VECTOR *pBitVector, NvU32 *linkMask);
NV_STATUS
convertBitVectorToLinkMasks(NV2080_NVLINK_BIT_VECTOR *pLocalLinkMask,
void *pOutputLinkMask1, NvU32 outputLinkMask1Size,
NV2080_CTRL_NVLINK_LINK_MASK *pOutputLinkMask2);
NV_STATUS
convertLinkMasksToBitVector(const void *pLinkMask1, NvU32 linkMask1Size,
const NV2080_CTRL_NVLINK_LINK_MASK *pLinkMask2,
NV2080_NVLINK_BIT_VECTOR *pOutputBitVector);
#endif // COMMON_NVLINK_H