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555.42.02

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(cherry picked from commit 5a1c474040)
This commit is contained in:
Bernhard Stoeckner
2024-05-21 15:11:46 +02:00
committed by Gaurav Juvekar
parent caa2dd11a0
commit 3084c04453
1004 changed files with 172522 additions and 150960 deletions
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28
src/common/inc/displayport/displayport.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -459,12 +459,35 @@ typedef struct VesaPsrSinkCaps
typedef struct PanelReplayCaps
{
NvBool panelReplaySupported;
// Indicates if Panel replay is supported or not
NvBool bPanelReplaySupported;
} panelReplayCaps;
typedef struct PanelReplayConfig
{
// This field is used to configure Panel replay on sink device
NvBool enablePanelReplay;
// This field is used to configure CRC with Panel replay on sink device
NvBool bEnableCrcWithPr;
// Configures sink to Generate an IRQ_HPD when DPCD 02020h[3] = 1.
NvBool bHpdOnAdaptiveSyncSdpMissing;
//
// Used to configure sink to Generate an IRQ_HPD after finding a VSC SDP
// for PR uncorrectable error.
//
NvBool bHpdOnSdpUncorrectableError;
// Configures sink to Generate an IRQ_HPD for RFB storage error.
NvBool bHpdOnRfbStorageErrors;
//
// Configures sink to generate an IRQ_HPD after finding an active video image
// CRC mismatch.
//
NvBool bHpdOnRfbActiveFrameCrcError;
} panelReplayConfig;
// PR state
@@ -500,6 +523,7 @@ typedef struct
// Maximum link rate of Main Link lanes = Value x 270M.
// To get it to KHz unit, we need to multiply 270K.
#define DP_LINK_BW_FREQUENCY_MULTIPLIER_KHZ (270*1000)
#define DP_LINK_BW_FREQUENCY_MULTIPLIER_270MHZ_TO_KHZ DP_LINK_BW_FREQUENCY_MULTIPLIER_KHZ
// Multiplier constant to get link rate table's in KHZ
#define DP_LINK_RATE_TABLE_MULTIPLIER_KHZ 200

27
src/common/inc/displayport/dpcd.h
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@@ -443,13 +443,17 @@ number of Downstream ports will be limited to 32.
#define NV_DPCD_TRAINING_LANEX_SET_PREEMPHASIS_MAX_REACHED 5:5 /* RWXUF */
#define NV_DPCD_TRAINING_LANEX_SET_PREEMPHASIS_MAX_REACHED_TRUE (0x00000001) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL (0x00000107) /* RWXUR */
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP 4:4 /* RWXUF */
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LESS_THAN_0_5 (0x00000001) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED 7:7 /* RWXUF */
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_FALSE (0x00000000) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_TRUE (0x00000001) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL (0x00000107) /* RWXUR */
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP 4:4 /* RWXUF */
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LESS_THAN_0_5 (0x00000001) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE 6:6 /* RWXUF */
#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE_NO (0x00000000) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE_YES (0x00000001) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED 7:7 /* RWXUF */
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_FALSE (0x00000000) /* RWXUV */
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_TRUE (0x00000001) /* RWXUV */
#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET (0x00000108) /* RWXUR */
#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B_10B 0:0 /* RWXUF */
@@ -1074,6 +1078,9 @@ number of Downstream ports will be limited to 32.
#define NV_DPCD_EDP_GENERAL_CAP2_PANEL_LUMINANCE_CONTROL_CAP 4:4 /* R-XUF */
#define NV_DPCD_EDP_GENERAL_CAP2_PANEL_LUMINANCE_CONTROL_CAP_NO (0x00000000) /* R-XUV */
#define NV_DPCD_EDP_GENERAL_CAP2_PANEL_LUMINANCE_CONTROL_CAP_YES (0x00000001) /* R-XUV */
#define NV_DPCD_EDP_GENERAL_CAP2_VARIABLE_BKLGHT_CONTROL_CAP 5:5 /* R-XUF */
#define NV_DPCD_EDP_GENERAL_CAP2_VARIABLE_BKLGHT_CONTROL_CAP_NO (0x00000000) /* R-XUV */
#define NV_DPCD_EDP_GENERAL_CAP2_VARIABLE_BKLGHT_CONTROL_CAP_YES (0x00000001) /* R-XUV */
#define NV_DPCD_EDP_GENERAL_CAP3 (0x00000704) /* R-XUV */
#define NV_DPCD_EDP_GENERAL_CAP3_X_REGION_CAP 3:0 /* R-XUF */
#define NV_DPCD_EDP_GENERAL_CAP3_X_REGION_CAP_NOT_SUPPORTED (0x00000000) /* R-XUV */
@@ -1099,6 +1106,9 @@ number of Downstream ports will be limited to 32.
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_AUTONOMOUS_1 (0x00000001) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_DISABLE (0x00000002) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_ENABLE (0x00000003) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_VARIABLE_BKLGHT_CTRL 6:6 /* RWXUF */
#define NV_DPCD_EDP_DISPLAY_CTL_VARIABLE_BKLGHT_CTRL_ENABLED (0x00000001) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_VARIABLE_BKLGHT_CTRL_DISABLED (0x00000000) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_VBLANK_BKLGHT_UPDATE_EN 7:7 /* RWXUF */
#define NV_DPCD_EDP_DISPLAY_CTL_VBLANK_BKLGHT_UPDATE_EN_ENABLED (0x00000001) /* RWXUV */
#define NV_DPCD_EDP_DISPLAY_CTL_VBLANK_BKLGHT_UPDATE_EN_DISABLED (0x00000000) /* RWXUV */
@@ -1151,6 +1161,9 @@ number of Downstream ports will be limited to 32.
#define NV_DPCD_EDP_BKLGHT_CTL_STATUS_FAULT_CONDITION_INIT (0x00000000) /* R-XUV */
#define NV_DPCD_EDP_BKLGHT_CTL_STATUS_FAULT_CONDITION_FAULT (0x00000001) /* R-XUV */
#define NV_DPCD_EDP_BKLGHT_CTL_STATUS_FAULT_CONDITION_NORMAL (0x00000000) /* R-XUV */
#define NV_DPCD_EDP_BKLGHT_CTL_STATUS_VARIABLE_BKLGHT_STATUS 1:1 /* R-XUF */
#define NV_DPCD_EDP_BKLGHT_CTL_STATUS_VARIABLE_BKLGHT_STATUS_DISABLED (0x00000000) /* R-XUV */
#define NV_DPCD_EDP_BKLGHT_CTL_STATUS_VARIABLE_BKLGHT_STATUS_ENABLED (0x00000001) /* R-XUV */
#define NV_DPCD_EDP_BKLGHT_FREQ_SET (0x00000728) /* RWXUR */
#define NV_DPCD_EDP_BKLGHT_FREQ_SET_VAL 7:0 /* RWXUF */
#define NV_DPCD_EDP_BKLGHT_FREQ_SET_VAL_INIT (0x00000000) /* RWXUV */

187
src/common/inc/displayport/dpcd20.h
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@@ -44,57 +44,148 @@
#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_UNCOMPRESSED_TO_FROM_COMPRESSED_YES (0x00000001)
// PANEL REPLAY RELATED DPCD
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY (0x000000B0)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED 0:0
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE 1:1
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY (0x000000B0) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION (0x000001B0)
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE 0:0
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION (0x000001B0) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE 0:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_CRC 1:1 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_CRC_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_CRC_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_ADAPTIVE_SYNC_SDP_MISSING 2:2 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_ADAPTIVE_SYNC_SDP_MISSING_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_ADAPTIVE_SYNC_SDP_MISSING_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_SDP_UNCORRECTABLE_ERROR 3:3 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_SDP_UNCORRECTABLE_ERROR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_SDP_UNCORRECTABLE_ERROR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_STORAGE_ERRORS 4:4 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_STORAGE_ERRORS_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_STORAGE_ERRORS_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_ACTIVE_FRAME_CRC_ERROR 5:5 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_ACTIVE_FRAME_CRC_ERROR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_ACTIVE_FRAME_CRC_ERROR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS (0x00002020)
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ACTIVE_FRAME_CRC_ERROR 0:0
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ACTIVE_FRAME_CRC_ERROR_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ACTIVE_FRAME_CRC_ERROR_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_RFB_STORAGE_ERROR 1:1
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_RFB_STORAGE_ERROR_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_RFB_STORAGE_ERROR_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_VSC_SDP_UNCORRECTABLE_ERROR 2:2
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_VSC_SDP_UNCORRECTABLE_ERROR_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_VSC_SDP_UNCORRECTABLE_ERROR_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ADAPTIVE_SYNC_SDP_MISSING 3:3
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ADAPTIVE_SYNC_SDP_MISSING_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ADAPTIVE_SYNC_SDP_MISSING_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS (0x00002022)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS 2:0
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_0 (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_1 (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_2 (0x00000002)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_ERROR (0x00000007)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED 4:3
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_LOCKED (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_COASTING (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_GOVERNING (0x00000002)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_RELOCKING (0x00000003)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_VALID 5:5
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_VALID_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_VALID_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS (0x00002020) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ACTIVE_FRAME_CRC_ERROR 0:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ACTIVE_FRAME_CRC_ERROR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ACTIVE_FRAME_CRC_ERROR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_RFB_STORAGE_ERROR 1:1 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_RFB_STORAGE_ERROR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_RFB_STORAGE_ERROR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_VSC_SDP_UNCORRECTABLE_ERROR 2:2 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_VSC_SDP_UNCORRECTABLE_ERROR_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_VSC_SDP_UNCORRECTABLE_ERROR_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ADAPTIVE_SYNC_SDP_MISSING 3:3 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ADAPTIVE_SYNC_SDP_MISSING_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ADAPTIVE_SYNC_SDP_MISSING_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS (0x00002022) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS 2:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_0 (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_1 (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_2 (0x00000002) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_ERROR (0x00000007) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED 4:3 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_LOCKED (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_COASTING (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_GOVERNING (0x00000002) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_RELOCKING (0x00000003) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_VALID 5:5 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_VALID_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_VALID_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO (0x00002024) /* R-XUR */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_STATE 0:0 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_STATE_INACTIVE (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_STATE_ACTIVE (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_CRC_VALID 2:2 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_CRC_VALID_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_CRC_VALID_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID 3:3 /* R-XUF */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID_YES (0x00000001) /* R-XUV */
//
// Adding DPCD registers for DP Tunneling feature.
//
#define NV_DPCD20_DP_TUNNEL_CAPABILITIES (0x000E000D) /* R-XUR */
#define NV_DPCD20_DP_TUNNEL_CAPABILITIES_DPTUNNELING_SUPPORT 0:0 /* R-XUF */
#define NV_DPCD20_DP_TUNNEL_CAPABILITIES_DPTUNNELING_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNEL_CAPABILITIES_DPTUNNELING_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNEL_CAPABILITIES_PANEL_REPLAY_TUNNELING_OPTIMIZATION_SUPPORT 6:6 /* R-XUF */
#define NV_DPCD20_DP_TUNNEL_CAPABILITIES_PANEL_REPLAY_TUNNELING_OPTIMIZATION_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNEL_CAPABILITIES_PANEL_REPLAY_TUNNELING_OPTIMIZATION_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNEL_CAPABILITIES_DPIN_BW_ALLOCATION_MODE_SUPPORT 7:7 /* R-XUF */
#define NV_DPCD20_DP_TUNNEL_CAPABILITIES_DPIN_BW_ALLOCATION_MODE_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNEL_CAPABILITIES_DPIN_BW_ALLOCATION_MODE_SUPPORT_YES (0x00000001) /* R-XUV */
// DPCD Registers for DPRX Event Status Indicator Field
#define NV_DPCD20_LINK_SERVICE_IRQ_VECTOR_ESI0 (0x00002005) /* R-XUR */
#define NV_DPCD20_LINK_SERVICE_IRQ_VECTOR_ESI0_DP_TUNNELING_IRQ 5:5 /* R-XUF */
#define NV_DPCD20_LINK_SERVICE_IRQ_VECTOR_ESI0_DP_TUNNELING_IRQ_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LINK_SERVICE_IRQ_VECTOR_ESI0_DP_TUNNELING_IRQ_YES (0x00000001) /* R-XUV */
// DPCD Registers for DP IN BW Allocation
#define NV_DPCD20_USB4_DRIVER_BW_CAPABILITY (0x000E0020) /* R-XUR */
#define NV_DPCD20_USB4_DRIVER_BW_ALLOCATION 7:7 /* R-XUF */
#define NV_DPCD20_USB4_DRIVER_BW_ALLOCATION_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_USB4_DRIVER_BW_ALLOCATION_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNEL_BW_GRANULARITY (0x000E0022) /* R-XUR */
#define NV_DPCD20_DP_TUNNEL_BW_GRANULARITY_VAL 1:0 /* R-XUF */
#define NV_DPCD20_DP_TUNNEL_BW_GRANULARITY_VAL_0_25_GBPS (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNEL_BW_GRANULARITY_VAL_0_50_GBPS (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNEL_BW_GRANULARITY_VAL_1_00_GBPS (0x00000002) /* R-XUV */
#define NV_DPCD20_DP_TUNNEL_ESTIMATED_BW (0x000E0023) /* R-XUR */
#define NV_DPCD20_DP_TUNNEL_ALLOCATED_BW (0x000E0024) /* R-XUR */
#define NV_DPCD20_DP_TUNNEL_REQUESTED_BW (0x000E0031) /* R-XUR */
#define NV_DPCD20_DP_TUNNELING_STATUS (0x000E0025) /* R-XUR */
#define NV_DPCD20_DP_TUNNELING_BW_REQUEST_FAILED 0:0 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_BW_REQUEST_FAILED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_BW_REQUEST_FAILED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_BW_REQUEST_SUCCEEDED 1:1 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_BW_REQUEST_SUCCEEDED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_BW_REQUEST_SUCCEEDED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_ESTIMATED_BW_CHANGED 2:2 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_ESTIMATED_BW_CHANGED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_ESTIMATED_BW_CHANGED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_BW_ALLOCATION_CAPABILITY_CHANGED 3:3 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_BW_ALLOCATION_CAPABILITY_CHANGED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_BW_ALLOCATION_CAPABILITY_CHANGED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_EXIT_DISCOVERY_MODE 4:4 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_EXIT_DISCOVERY_MODE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_EXIT_DISCOVERY_MODE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_8B10B_MAX_LINK_RATE (0x000E0028) /* R-XUR */
#define NV_DPCD20_DP_TUNNELING_8B10B_MAX_LINK_RATE_VAL 7:0 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_8B10B_MAX_LINK_RATE_VAL_1_62_GBPS (0x00000006) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_8B10B_MAX_LINK_RATE_VAL_2_70_GBPS (0x0000000A) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_8B10B_MAX_LINK_RATE_VAL_5_40_GBPS (0x00000014) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_8B10B_MAX_LINK_RATE_VAL_8_10_GBPS (0x0000001E) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_MAX_LANE_COUNT (0x000E0029) /* R-XUR */
#define NV_DPCD20_DP_TUNNELING_MAX_LANE_COUNT_LANE 7:0 /* R-XUF */
#define NV_DPCD20_DP_TUNNELING_MAX_LANE_COUNT_LANE_ONE (0x00000001) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_MAX_LANE_COUNT_LANE_TWO (0x00000002) /* R-XUV */
#define NV_DPCD20_DP_TUNNELING_MAX_LANE_COUNT_LANE_FOUR (0x00000004) /* R-XUV */
#define NV_DPCD20_DPTX_BW_ALLOCATION_MODE_CONTROL (0x000E0030) /* R-XUR */
#define NV_DPCD20_DPTX_UNMASK_BW_ALLOCATION_IRQ 6:6 /* R-XUF */
#define NV_DPCD20_DPTX_UNMASK_BW_ALLOCATION_IRQ_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DPTX_UNMASK_BW_ALLOCATION_IRQ_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DPTX_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE 7:7 /* R-XUF */
#define NV_DPCD20_DPTX_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DPTX_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO (0x00002024)
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_STATE 0:0
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_STATE_INACTIVE (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_STATE_ACTIVE (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_CRC_VALID 2:2
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_CRC_VALID_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_CRC_VALID_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID 3:3
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID_YES (0x00000001)
#endif // #ifndef _DISPLAYPORT20_H_

24
src/common/inc/nvBldVer.h
View File

@@ -36,26 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r550_00
#define NV_BUILD_BRANCH r555_79
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r550_00
#define NV_PUBLIC_BRANCH r555_79
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r550_00-326"
#define NV_BUILD_CHANGELIST_NUM (34471492)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r555/r555_79-111"
#define NV_BUILD_CHANGELIST_NUM (34260717)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r550/r550_00-326"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34471492)
#define NV_BUILD_NAME "rel/gpu_drv/r555/r555_79-111"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34260717)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r550_00-324"
#define NV_BUILD_CHANGELIST_NUM (34468048)
#define NV_BUILD_TYPE "Nightly"
#define NV_BUILD_NAME "r550_00-240627"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34454921)
#define NV_BUILD_BRANCH_BASE_VERSION R550
#define NV_BUILD_BRANCH_VERSION "r555_79-1"
#define NV_BUILD_CHANGELIST_NUM (34253977)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "555.81"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34253977)
#define NV_BUILD_BRANCH_BASE_VERSION R555
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "550.100"
#define NV_VERSION_STRING "555.42.02"
#else

12
src/common/inc/nvctassert.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1997-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1997-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -139,14 +139,14 @@
// Adding this macro to fix MISRA 2012 rule 20.12
#define NV_CTASSERT_STRINGIFY_MACRO(b) #b
#if !defined(NVOC) && ((defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) || CLANG_C_STATIC_ASSERT)
// ISO C11 defines the _Static_assert keyword
# define ct_assert(b) _Static_assert((b), "Compile time assertion failed: " NV_CTASSERT_STRINGIFY_MACRO(b))
# define ct_assert_i(b,line) _Static_assert((b), "Compile time assertion failed: " NV_CTASSERT_STRINGIFY_MACRO(b)NV_CTASSERT_STRINGIFY_MACRO(line))
#elif (defined(__cplusplus) && __cplusplus >= 201103L) || (defined(_MSVC_LANG) && _MSVC_LANG >= 201103L)
#if (defined(__cplusplus) && __cplusplus >= 201103L) || (defined(_MSVC_LANG) && _MSVC_LANG >= 201103L)
// ISO C++11 defines the static_assert keyword
# define ct_assert(b) static_assert((b), "Compile time assertion failed: " NV_CTASSERT_STRINGIFY_MACRO(b))
# define ct_assert_i(b,line) static_assert((b), "Compile time assertion failed: " NV_CTASSERT_STRINGIFY_MACRO(b)NV_CTASSERT_STRINGIFY_MACRO(line))
#elif !defined(NVOC) && ((defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) || CLANG_C_STATIC_ASSERT)
// ISO C11 defines the _Static_assert keyword
# define ct_assert(b) _Static_assert((b), "Compile time assertion failed: " NV_CTASSERT_STRINGIFY_MACRO(b))
# define ct_assert_i(b,line) _Static_assert((b), "Compile time assertion failed: " NV_CTASSERT_STRINGIFY_MACRO(b)NV_CTASSERT_STRINGIFY_MACRO(line))
#else
// For compilers which don't support ISO C11 or C++11, we fall back to an
// array (type) declaration

20
src/common/inc/nvlog_defs.h
View File

@@ -438,6 +438,26 @@ typedef enum _NVLOG_ARGTYPE
NVLOG_ARGTYPE__COUNT
} NVLOG_ARGTYPE;
// Default flags for NvLog registry, used for single-buffer option or the read fails
#ifndef NVLOG_DEFAULT_FLAGS
#define NVLOG_DEFAULT_FLAGS \
( \
DRF_NUM(_REG_STR_RM, _NVLOG, _BUFFER_FLAGS, \
( \
DRF_DEF(LOG, _BUFFER_FLAGS, _DISABLED, _NO) | \
DRF_DEF(LOG, _BUFFER_FLAGS, _TYPE, _RING) | \
DRF_DEF(LOG, _BUFFER_FLAGS, _EXPANDABLE, _NO) | \
DRF_DEF(LOG, _BUFFER_FLAGS, _NONPAGED, _YES) | \
DRF_DEF(LOG, _BUFFER_FLAGS, _LOCKING, _STATE) | \
DRF_DEF(LOG, _BUFFER_FLAGS, _OCA, _YES) \
)) | \
DRF_DEF(_REG_STR_RM, _NVLOG, _BUFFER_SIZE, _DEFAULT) | \
DRF_NUM(_REG_STR_RM, _NVLOG, _RUNTIME_LEVEL, 0) | \
DRF_DEF(_REG_STR_RM, _NVLOG, _TIMESTAMP, _32) | \
DRF_DEF(_REG_STR_RM, _NVLOG, _INITED, _YES) \
)
#endif // NVLOG_DEFAULT_FLAGS
/**
* @brief General info about the NvLog Print system
*/

33
src/common/inc/pex.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -36,5 +36,36 @@
#define PEX_FUNC_GETLTRLATENCY 0x00000006 // Get PCI Express Latency Tolerance Reporting Info
#define PEX_FUNC_NAMEPCIDEVICE 0x00000007 // Get name of PCI or PCIE device
#define PEX_FUNC_SETLTRLATENCY 0x00000008 // Set PCI Express Latency Tolerance Reporting Values
#define PEX_FUNC_AUXPOWERLIMIT 0x0000000A // Set Aux power limit
#define PEX_FUNC_PEXRST_DELAY 0x0000000B // Set Pex reset delay
/*
* 0h: Denied.
* Indicates that the platform cannot support the power requested.
* 1h: Granted.
* Indicates that the device is permitted to draw the requested auxiliary power.
* 2h: Granted.
* Indicates that the platform will not remove main power from the slot
* while the system is in S0.
*/
#define NV_AUX_POWER_REQUEST_STATUS 1:0
#define NV_AUX_POWER_REQUEST_STATUS_DENIED 0x00
#define NV_AUX_POWER_REQUEST_STATUS_GRANTED_WITHOUT_12V_POWER 0x01
#define NV_AUX_POWER_REQUEST_STATUS_GRANTED_WITH_12V_POWER 0x02
/*
* Retry, with interval.
* Bit 4, is a status bit. If set, it indicates that the platform cannot support
* the power requested at this time, but it may be able to do so in the future.
* Bits 3:0 contains the waiting time, in seconds, after which request can be made again.
*/
#define NV_AUX_POWER_REQUEST_STATUS_RETRY_LATER 4:0
#define NV_AUX_POWER_REQUEST_STATUS_RETRY_LATER_STATUS 4:4
#define NV_AUX_POWER_REQUEST_STATUS_RETRY_LATER_STATUS_FALSE 0x0
#define NV_AUX_POWER_REQUEST_STATUS_RETRY_LATER_STATUS_TRUE 0x1
#define NV_AUX_POWER_REQUEST_STATUS_RETRY_LATER_INTERVAL 3:0
#define NV_AUX_POWER_REQUEST_STATUS_RETRY_LATER_INTERVAL_MIN 0x1
#define NV_AUX_POWER_REQUEST_STATUS_RETRY_LATER_INTERVAL_MAX 0xF
#endif // PEX_H

5
src/common/inc/swref/published/ampere/ga100/dev_nv_xve.h
View File

@@ -26,6 +26,11 @@
#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */
#define NV_XVE_LINK_CONTROL_STATUS 0x00000088 /* RW-4R */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED 19:16 /* R--VF */
#define NV_XVE_DBG0 0x0000084C /* RW-4R */
#define NV_XVE_DBG0_OUTSTANDING_DOWNSTREAM_READ_CNTR_RESET 9:9 /* RWCVF */
#define NV_XVE_DBG0_OUTSTANDING_DOWNSTREAM_READ_CNTR_RESET_TRIGGER 0x00000001 /* -W--T */
#define NV_XVE_DBG0_OUTSTANDING_DOWNSTREAM_READ_CNTR_RESET_DONE 0x00000000 /* R-C-V */
#define NV_XVE_DBG0_OUTSTANDING_DOWNSTREAM_READ_CNTR_RESET_PENDING 0x00000001 /* R---V */
#define NV_XVE_DBG_CYA_0 0x00000898 /* RW-4R */
#define NV_XVE_DBG_CYA_0_BAR0_ADDR_WIDTH 19:19 /* RWCVF */
#define NV_XVE_DBG_CYA_0_BAR0_ADDR_WIDTH_32BIT 0x00000000 /* RWC-V */

62
src/common/inc/swref/published/ampere/ga100/dev_runlist.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,64 +24,4 @@
#ifndef __ga100_dev_runlist_h__
#define __ga100_dev_runlist_h__
#define NV_CHRAM_CHANNEL(i) (0x000+(i)*4) /* RW-4A */
#define NV_CHRAM_CHANNEL__SIZE_1 2048 /* */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL 0:0 /* -WIVF */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_SET_BITS 0x00000000 /* -WI-V */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_CLEAR_BITS 0x00000001 /* -W--V */
#define NV_CHRAM_CHANNEL_ENABLE 1:1 /* RWIVF */
#define NV_CHRAM_CHANNEL_ENABLE_NOT_IN_USE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ENABLE_IN_USE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_NEXT 2:2 /* RWIVF */
#define NV_CHRAM_CHANNEL_NEXT_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_NEXT_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_BUSY 3:3 /* R-IVF */
#define NV_CHRAM_CHANNEL_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED 4:4 /* RWIVF */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_ENG_FAULTED 5:5 /* RWIVF */
#define NV_CHRAM_CHANNEL_ENG_FAULTED_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ENG_FAULTED_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_ON_PBDMA 6:6 /* R-IVF */
#define NV_CHRAM_CHANNEL_ON_PBDMA_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ON_PBDMA_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ON_ENG 7:7 /* R-IVF */
#define NV_CHRAM_CHANNEL_ON_ENG_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ON_ENG_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_PENDING 8:8 /* RWIVF */
#define NV_CHRAM_CHANNEL_PENDING_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_PENDING_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_CTX_RELOAD 9:9 /* RWIVF */
#define NV_CHRAM_CHANNEL_CTX_RELOAD_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_CTX_RELOAD_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY 10:10 /* R-IVF */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ENG_BUSY 11:11 /* R-IVF */
#define NV_CHRAM_CHANNEL_ENG_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ENG_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL 12:12 /* RWIVF */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_UPDATE 31:0 /* */
#define NV_CHRAM_CHANNEL_UPDATE_ENABLE_CHANNEL 0x00000002 /* */
#define NV_CHRAM_CHANNEL_UPDATE_DISABLE_CHANNEL 0x00000003 /* */
#define NV_CHRAM_CHANNEL_UPDATE_FORCE_CTX_RELOAD 0x00000200 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_PBDMA_FAULTED 0x00000011 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_ENG_FAULTED 0x00000021 /* */
#define NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL 0xFFFFFFFF /* */
#define NV_RUNLIST_PREEMPT 0x098 /* RW-4R */
#define NV_RUNLIST_PREEMPT_ID 11:0 /* */
#define NV_RUNLIST_PREEMPT_ID_HW 10:0 /* RWIUF */
#define NV_RUNLIST_PREEMPT_ID_HW_NULL 0x00000000 /* RWI-V */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING 20:20 /* R-IVF */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING 21:21 /* R-IVF */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PREEMPT_TYPE 25:24 /* RWIVF */
#define NV_RUNLIST_PREEMPT_TYPE_RUNLIST 0x00000000 /* RWI-V */
#define NV_RUNLIST_PREEMPT_TYPE_TSG 0x00000001 /* RW--V */
#endif // __ga100_dev_runlist_h__

19
src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,15 +26,12 @@
#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K 0x100
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE 6:5
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_NONE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_PROTECTED_PCIE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0
#endif // __gh100_dev_gc6_island_addendum_h__

26
src/common/inc/swref/published/maxwell/gm107/dev_boot.h
View File

@@ -43,4 +43,30 @@
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_MSPPP 1:1 /* */
#define NV_PMC_ENABLE_MSPPP_ENABLE 0x00000001 /* */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE0 6:6 /* */
#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_CE1 7:7 /* */
#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PWR 13:13 /* RWIVF */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_MSVLD 15:15 /* */
#define NV_PMC_ENABLE_MSVLD_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_MSVLD_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_MSPDEC 17:17 /* */
#define NV_PMC_ENABLE_MSPDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_MSPDEC_ENABLED 0x00000001 /* */
#endif // __gm107_dev_boot_h__

28
src/common/inc/swref/published/maxwell/gm107/dev_nv_xp.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_nv_xp_h__
#define __gm107_dev_nv_xp_h__
#define NV_XP_PL_CYA_1(i) (0x0008C300+(i)*4) /* RW-4A */
#define NV_XP_PL_CYA_1_BLOCK_HOST2XP_HOLD_LTSSM 4:4 /* RWIVF */
#endif // __gm107_dev_nv_xp_h__

2
src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h
View File

@@ -163,4 +163,6 @@
#define NV_XVE_CYA_2 0x00000704 /* RW-4R */
#define NV_XVE_DEVICE_CONTROL_STATUS_2 0x000000A0 /* RWI4R */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1 0x00000260 /* RW-4R */
#define NV_XVE_SW_RESET 0x00000718 /* RW-4R */
#define NV_XVE_SW_RESET_RESET 0:0 /* RWCVF */
#endif // __gm107_dev_nv_xve_h__

28
src/common/inc/swref/published/maxwell/gm107/dev_nv_xve_addendum.h Normal file
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@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_nv_xve_addendum_h__
#define __gm107_dev_nv_xve_addendum_h__
#define NV_XVE_SW_RESET_RESET_ENABLE 0x00000001
#define NV_XVE_SW_RESET_RESET_DISABLE 0x00000000
#endif // __gm107_dev_nv_xve_addendum_h__

28
src/common/inc/swref/published/maxwell/gm200/dev_nv_xp.h Normal file
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@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_nv_xp_h__
#define __gm200_dev_nv_xp_h__
#define NV_XP_PL_CYA_1(i) (0x0008C300+(i)*4) /* RW-4A */
#define NV_XP_PL_CYA_1_BLOCK_HOST2XP_HOLD_LTSSM 4:4 /* RWIVF */
#endif // __gm200_dev_nv_xp_h__

36
src/common/inc/swref/published/maxwell/gm200/dev_nv_xve.h Normal file
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@@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_nv_xve_h__
#define __gm200_dev_nv_xve_h__
#define NV_XVE_SW_RESET 0x00000718 /* RW-4R */
#define NV_XVE_SW_RESET_RESET 0:0 /* RWCVF */
#define NV_XVE_SW_RESET_GPU_ON_SW_RESET_ENABLE 0x00000001 /* RW--V */
#define NV_XVE_SW_RESET_GPU_ON_SW_RESET_DISABLE 0x00000000 /* RW--V */
#define NV_XVE_SW_RESET_GPU_ON_SW_RESET 1:1 /* RWCVF */
#define NV_XVE_SW_RESET_COUNTER_EN 2:2 /* RWCVF */
#define NV_XVE_SW_RESET_COUNTER_VAL 14:4 /* RWCVF */
#define NV_XVE_SW_RESET_CLOCK_ON_SW_RESET 15:15 /* RWCVF */
#define NV_XVE_SW_RESET_CLOCK_COUNTER_EN 16:16 /* RWCVF */
#define NV_XVE_SW_RESET_CLOCK_COUNTER_VAL 27:17 /* RWCVF */
#endif // __gm200_dev_nv_xve_h__

28
src/common/inc/swref/published/maxwell/gm200/dev_nv_xve_addendum.h Normal file
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@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_nv_xve_addendum_h__
#define __gm200_dev_nv_xve_addendum_h__
#define NV_XVE_SW_RESET_RESET_ENABLE 0x00000001
#define NV_XVE_SW_RESET_RESET_DISABLE 0x00000000
#endif // __gm200_dev_nv_xve_addendum_h__

3
src/common/inc/swref/published/nv_ref.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -153,6 +153,7 @@
#define NV_PMC_BOOT_42_ARCHITECTURE_GA100 0x00000017 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GH100 0x00000018 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_AD100 0x00000019 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_AMODEL 0x0000001F /* */
#define NV_PMC_BOOT_42_CHIP_ID_GA100 0x00000170 /* */

5
src/common/inc/swref/published/nvswitch/ls10/dev_nport_ip.h
View File

@@ -467,4 +467,9 @@
#define NV_NPORT_SCRATCH_WARM 0x00000fc0 /* RW-4R */
#define NV_NPORT_SCRATCH_WARM_DATA 31:0 /* RWEVF */
#define NV_NPORT_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
#define NV_NPORT_STATUS 0x00000474 /* R--4R */
#define NV_NPORT_STATUS_INGRESS_IDLE 0:0 /* R-XVF */
#define NV_NPORT_STATUS_INGRESS_IDLE_IDLE 0x00000001 /* R---V */
#define NV_NPORT_STATUS_ROUTE_IDLE 1:1 /* R-XVF */
#define NV_NPORT_STATUS_ROUTE_IDLE_IDLE 0x00000001 /* R---V */
#endif // __ls10_dev_nport_ip_h__

5
src/common/inc/swref/published/nvswitch/ls10/dev_nvlsaw_ip.h
View File

@@ -96,5 +96,8 @@
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1__SIZE_1 4 /* */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_3(i) (0x00000c50+(i)*0x4) /* RW-4A */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_3(i) (0x00000c50+(i)*0x4) /* RW-4A */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_3__SIZE_1 4 /* */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_3_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_3_VALUE_INIT 0x00000000 /* RWE-V */
#endif // __ls10_dev_nvlsaw_ip_h__

29
src/common/inc/swref/published/pascal/gp102/dev_nv_xp.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gp102_dev_nv_xp_h__
#define __gp102_dev_nv_xp_h__
#define NV_XP_PL_CYA_1(i) (0x0008C300+(i)*4) /* RW-4A */
#define NV_XP_PL_CYA_1_BLOCK_HOST2XP_HOLD_LTSSM 4:4 /* RWIVF */
#define NV_XP_PL_CYA_1_BLOCK_HOST2XP_HOLD_LTSSM_ENABLE 0x00000001 /* RW--V */
#endif // __gp102_dev_nv_xp_h__

37
src/common/inc/swref/published/pascal/gp102/dev_nv_xve.h Normal file
View File

@@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gp102_dev_nv_xve_h__
#define __gp102_dev_nv_xve_h__
#define NV_XVE_SW_RESET 0x00000718 /* RW-4R */
#define NV_XVE_SW_RESET_RESET 0:0 /* RWCVF */
#define NV_XVE_SW_RESET_GPU_ON_SW_RESET_INIT 0x00000001 /* RWC-V */
#define NV_XVE_SW_RESET_GPU_ON_SW_RESET_ENABLE 0x00000001 /* RW--V */
#define NV_XVE_SW_RESET_GPU_ON_SW_RESET_DISABLE 0x00000000 /* RW--V */
#define NV_XVE_SW_RESET_GPU_ON_SW_RESET 1:1 /* RWCVF */
#define NV_XVE_SW_RESET_COUNTER_EN 2:2 /* RWCVF */
#define NV_XVE_SW_RESET_COUNTER_VAL 14:4 /* RWCVF */
#define NV_XVE_SW_RESET_CLOCK_ON_SW_RESET 15:15 /* RWCVF */
#define NV_XVE_SW_RESET_CLOCK_COUNTER_EN 16:16 /* RWCVF */
#define NV_XVE_SW_RESET_CLOCK_COUNTER_VAL 27:17 /* RWCVF */
#endif // __gp102_dev_nv_xve_h__

28
src/common/inc/swref/published/pascal/gp102/dev_nv_xve_addendum.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gp102_dev_nv_xve_addendum_h__
#define __gp102_dev_nv_xve_addendum_h__
#define NV_XVE_SW_RESET_RESET_ENABLE 0x00000001
#define NV_XVE_SW_RESET_RESET_DISABLE 0x00000000
#endif // __gp102_dev_nv_xve_addendum_h__