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555.42.02

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(cherry picked from commit 5a1c474040)
This commit is contained in:
Bernhard Stoeckner
2024-05-21 15:11:46 +02:00
committed by Gaurav Juvekar
parent caa2dd11a0
commit 3084c04453
1004 changed files with 172522 additions and 150960 deletions
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17
src/common/sdk/nvidia/inc/cc_drv.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -57,14 +57,13 @@ typedef enum ROTATE_IV_TYPE {
// Status value written into NvNotification.Info16
typedef enum KEY_ROTATION_STATUS {
KEY_ROTATION_STATUS_IDLE = 0, // Key rotation complete/not in progress
KEY_ROTATION_STATUS_PENDING = 1, // RM is waiting for clients to report their channels are idle for key rotation
KEY_ROTATION_STATUS_IN_PROGRESS = 2, // Key rotation is in progress
KEY_ROTATION_STATUS_FAILED_TIMEOUT = 3, // Key rotation timeout failure, RM will RC non-idle channels
KEY_ROTATION_STATUS_FAILED_THRESHOLD = 4, // Key rotation failed because upper threshold was crossed, RM will RC non-idle channels
KEY_ROTATION_STATUS_FAILED_ROTATION = 5, // Internal RM failure while rotating keys for a certain channel, RM will RC the channel
KEY_ROTATION_STATUS_PENDING_TIMER_SUSPENDED = 6, // Key rotation timer suspended waiting for kernel key rotation to complete
KEY_ROTATION_STATUS_MAX_COUNT = 7,
KEY_ROTATION_STATUS_IDLE = 0, // Key rotation complete/not in progress
KEY_ROTATION_STATUS_PENDING = 1, // RM is waiting for clients to report their channels are idle for key rotation
KEY_ROTATION_STATUS_IN_PROGRESS = 2, // Key rotation is in progress
KEY_ROTATION_STATUS_FAILED_TIMEOUT = 3, // Key rotation timeout failure, RM will RC non-idle channels
KEY_ROTATION_STATUS_FAILED_THRESHOLD = 4, // Key rotation failed because upper threshold was crossed, RM will RC non-idle channels
KEY_ROTATION_STATUS_FAILED_ROTATION = 5, // Internal RM failure while rotating keys for a certain channel, RM will RC the channel.
KEY_ROTATION_STATUS_MAX_COUNT = 6,
} KEY_ROTATION_STATUS;
typedef struct CC_AES_CRYPTOBUNDLE {

13
src/common/sdk/nvidia/inc/class/cl0050.h
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@@ -30,8 +30,6 @@
// Source file: class/cl0050.finn
//
#include "nvcfg_sdk.h"
#define NV_CE_UTILS (0x50U) /* finn: Evaluated from "NV0050_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV0050_ALLOCATION_PARAMETERS_MESSAGE_ID (0x0050U)
@@ -58,13 +56,12 @@ typedef struct NV0050_ALLOCATION_PARAMETERS {
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FIFO_LITE_TRUE (0x00000001)
// Whether the CeUtils will use BAR1 or BAR2 for data copy
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE 3:3
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_NO_BAR1_USE_TRUE (0x00000001)
// Force a specific CE engine to be used be setting forceCeId
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID 4:4
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_TRUE (0x00000001)
// Use a CC secure channel
#define NV0050_CEUTILS_FLAGS_CC_SECURE 5:5
#define NV0050_CEUTILS_FLAGS_CC_SECURE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_CC_SECURE_TRUE (0x00000001)

66
src/common/sdk/nvidia/inc/class/cl00de.h
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@@ -98,9 +98,21 @@ typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFOS {
RUSD_CLK_PUBLIC_DOMAIN_INFO info[RUSD_CLK_PUBLIC_DOMAIN_MAX_TYPE];
} RUSD_CLK_PUBLIC_DOMAIN_INFOS;
typedef struct RUSD_ENG_UTILIZATION {
NvU32 clkPercentBusy;
NvU32 samplingPeriodUs;
} RUSD_ENG_UTILIZATION;
#define RUSD_ENG_UTILIZATION_VID_ENG_NVENC 0
#define RUSD_ENG_UTILIZATION_VID_ENG_NVDEC 1
#define RUSD_ENG_UTILIZATION_VID_ENG_NVJPG 2
#define RUSD_ENG_UTILIZATION_VID_ENG_NVOFA 3
#define RUSD_ENG_UTILIZATION_COUNT 4
typedef struct RUSD_PERF_DEVICE_UTILIZATION_INFO {
NvU8 gpuPercentBusy;
NvU8 memoryPercentBusy;
NvU32 gpuPercentBusy;
NvU32 memoryPercentBusy;
RUSD_ENG_UTILIZATION engUtil[RUSD_ENG_UTILIZATION_COUNT];
} RUSD_PERF_DEVICE_UTILIZATION_INFO;
typedef struct RUSD_PERF_DEVICE_UTILIZATION {
@@ -115,7 +127,7 @@ typedef struct RUSD_PERF_CURRENT_PSTATE {
typedef struct RUSD_CLK_THROTTLE_REASON {
volatile NvU64 lastModifiedTimestamp;
NvU32 reasonMask;
NvU32 reasonMask; // Bitmask of RUSD_CLK_THROTTLE_REASON
} RUSD_CLK_THROTTLE_REASON;
typedef struct RUSD_MEM_ERROR_COUNTS {
@@ -140,12 +152,12 @@ typedef struct RUSD_POWER_LIMIT_INFO {
NvU32 enforcedmW;
} RUSD_POWER_LIMIT_INFO;
typedef struct RUSD_ENFORCED_POWER_LIMITS {
typedef struct RUSD_POWER_LIMITS {
volatile NvU64 lastModifiedTimestamp;
RUSD_POWER_LIMIT_INFO info;
} RUSD_POWER_LIMITS;
typedef struct RUSD_TEMPERATURE_INFO{
typedef struct RUSD_TEMPERATURE_INFO {
NvTemp gpuTemperature;
NvTemp hbmTemperature;
} RUSD_TEMPERATURE_INFO;
@@ -194,6 +206,11 @@ typedef struct RUSD_INST_POWER_USAGE {
RUSD_INST_POWER_INFO info;
} RUSD_INST_POWER_USAGE;
typedef struct RUSD_SHADOW_ERR_CONT {
volatile NvU64 lastModifiedTimestamp;
NvU32 shadowErrContVal;
} RUSD_SHADOW_ERR_CONT;
typedef struct NV00DE_SHARED_DATA {
volatile NvU64 seq;
@@ -202,19 +219,56 @@ typedef struct NV00DE_SHARED_DATA {
NvU64 totalPmaMemory;
NvU64 freePmaMemory;
// gpuUpdateUserSharedData is sensitive to these two sections being contiguous
//
// GSP polling data section
// All data structs are a volatile NvU64 timestamp followed by data contents.
// Access by reading timestamp, then copying the struct contents, then reading the timestamp again.
// If time0 matches time1, data has not changed during the read, and contents are valid.
// If timestamp is RUSD_TIMESTAMP_WRITE_IN_PROGRESS, data was edited during the read, retry.
// If timestamp is RUSD_TIMESTAMP_INVALID, data is not available or not supported on this platform.
//
// POLL_CLOCK
NV_DECLARE_ALIGNED(RUSD_CLK_PUBLIC_DOMAIN_INFOS clkPublicDomainInfos, 8);
// POLL_PERF
NV_DECLARE_ALIGNED(RUSD_CLK_THROTTLE_REASON clkThrottleReason, 8);
// POLL_PERF
NV_DECLARE_ALIGNED(RUSD_PERF_DEVICE_UTILIZATION perfDevUtil, 8);
// POLL_MEMORY
NV_DECLARE_ALIGNED(RUSD_MEM_ECC memEcc, 8);
// POLL_PERF
NV_DECLARE_ALIGNED(RUSD_PERF_CURRENT_PSTATE perfCurrentPstate, 8);
NV_DECLARE_ALIGNED(RUSD_POWER_LIMITS powerLimitGpu, 8); // Module Limit is not supported on Ampere/Hopper
// POLL_POWER
// Module Limit is not supported on Ampere/Hopper
NV_DECLARE_ALIGNED(RUSD_POWER_LIMITS powerLimitGpu, 8);
// POLL_THERMAL
NV_DECLARE_ALIGNED(RUSD_TEMPERATURE temperature, 8);
// POLL_MEMORY
NV_DECLARE_ALIGNED(RUSD_MEM_ROW_REMAP memRowRemap, 8);
// POLL_POWER
NV_DECLARE_ALIGNED(RUSD_AVG_POWER_USAGE avgPowerUsage, 8);
// POLL_POWER
NV_DECLARE_ALIGNED(RUSD_INST_POWER_USAGE instPowerUsage, 8);
// Non-polled GSP data section
NV_DECLARE_ALIGNED(RUSD_SHADOW_ERR_CONT shadowErrCont, 8);
} NV00DE_SHARED_DATA;
//
// Polling mask bits, pass into ALLOC_PARAMETERS or NV00DE_CTRL_REQEUSET_DATA_POLL
// to request above polled data to be provided
//
#define NV00DE_RUSD_POLL_CLOCK 0x1
#define NV00DE_RUSD_POLL_PERF 0x2
#define NV00DE_RUSD_POLL_MEMORY 0x4

8
src/common/sdk/nvidia/inc/class/cl00fe.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -43,5 +43,11 @@
typedef struct NV_MEMORY_MAPPER_ALLOCATION_PARAMS {
NvHandle hSemaphoreSurface;
NvU32 maxQueueSize;
NvHandle hNotificationMemory;
NV_DECLARE_ALIGNED(NvU64 notificationOffset, 8);
} NV_MEMORY_MAPPER_ALLOCATION_PARAMS;
typedef struct NV_MEMORY_MAPPER_NOTIFICATION {
NvU32 status; // NV_STATUS error code
} NV_MEMORY_MAPPER_NOTIFICATION;

51
src/common/sdk/nvidia/inc/class/cl0100.h Normal file
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@@ -0,0 +1,51 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0100.finn
//
/*
* The lock stress object (LOCK_STRESS_OBJECT) is a test-only object that exports
* multiple RM controls which exercise acquiring different combinations of RM locks in
* order to stress and properly test RM locking specifically. These API's only exercise
* legal combinations of RM locks that are in use elsewhere in RM but they are intended
* to be exhaustive in covering all possible combinations of RM locks. The API's
* themselves, don't do much outside of incrementing/decrementing global integers that
* can be validated later on within a test executable to ensure that all accesses to
* these global integers were synchronous.
*
* The lock stress object is not allocatable without the "RmEnableLockStress" registry
* key being turned on, which is off by default. The creation/destruction of the object
* does not accomplish anything useful but simply serves as a way to check for the
* registry key's enablement before allowing executing any of the test API's this object
* provides.
*/
#define LOCK_STRESS_OBJECT 0x0100U

2
src/common/sdk/nvidia/inc/class/cl2080_notification.h
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@@ -202,7 +202,7 @@ extern "C" {
#define NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED (161)
#define NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST (162)
#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163)
#define NV2080_NOTIFIERS_POSSIBLE_ERROR (164)
#define NV2080_NOTIFIERS_UNUSED_1 (164) // Unused
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165)
#define NV2080_NOTIFIERS_RESERVED166 (166)
#define NV2080_NOTIFIERS_RESERVED167 (167)

42
src/common/sdk/nvidia/inc/class/cl90cdtrace.h Normal file
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@@ -0,0 +1,42 @@
/*
* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl90cdtrace_h_
#define _cl90cdtrace_h_
#include <nvtypes.h>
/* This file defines parameters for RATS/RM tracing */
typedef struct NV_RATS_GSP_TRACE_RECORD_V1
{
NvU16 seqNo;
NvU16 gspSeqNo;
NvU32 info;
NvU64 recordType;
NvU64 timeStamp;
NvU64 threadId;
} NV_RATS_GSP_TRACE_RECORD_V1;
typedef NV_RATS_GSP_TRACE_RECORD_V1 NV_RATS_GSP_TRACE_RECORD;
#endif

20
src/common/sdk/nvidia/inc/class/clc8b5.h
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@@ -52,10 +52,6 @@
#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001)
#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13
#define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001)
#define NVC8B5_LAUNCH_DMA_COPY_TYPE 21:20
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT (0x00000000)
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_DEFAULT (0x00000000)
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_SECURE (0x00000001)
#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23
#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001)
#define NVC8B5_LAUNCH_DMA_DISABLE_PLC 26:26
@@ -65,22 +61,6 @@
#define NVC8B5_OFFSET_OUT_LOWER (0x0000040C)
#define NVC8B5_OFFSET_OUT_LOWER_VALUE 31:0
#define NVC8B5_LINE_LENGTH_IN (0x00000418)
#define NVC8B5_SET_SECURE_COPY_MODE (0x00000500)
#define NVC8B5_SET_SECURE_COPY_MODE_MODE 0:0
#define NVC8B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT (0x00000000)
#define NVC8B5_SET_SECURE_COPY_MODE_MODE_DECRYPT (0x00000001)
#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER (0x00000514)
#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER 24:0
#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER (0x00000518)
#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER_LOWER 31:0
#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER (0x00000530)
#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER_UPPER 24:0
#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER (0x00000534)
#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER_LOWER 31:0
#define NVC8B5_SET_ENCRYPT_IV_ADDR_UPPER (0x00000538)
#define NVC8B5_SET_ENCRYPT_IV_ADDR_UPPER_UPPER 24:0
#define NVC8B5_SET_ENCRYPT_IV_ADDR_LOWER (0x0000053C)
#define NVC8B5_SET_ENCRYPT_IV_ADDR_LOWER_LOWER 31:0
#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS (0x000006FC)
#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE 0:0
#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE (0x00000000)

8
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -44,8 +44,6 @@
*
* NV0000_CTRL_GET_FEATURES_SLI
* When this bit is set, SLI is supported.
* NV0000_CTRL_GET_FEATURES_UEFI
* When this bit is set, it is a UEFI system.
* NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT
* When this bit is set, EFI has initialized core channel
*
@@ -68,10 +66,6 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS {
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI 1:1
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U)

147
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -106,7 +106,9 @@
* NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID
* This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode).
* NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE
* This indicates whether this DFP supports Dynamic MUX
* This indicates whether this DFP supports DDS (NV dynamic display mux).
* NV0073_CTRL_DFP_FLAGS_MDM
* This indicates whether this DFP supports MDM (Microsoft dynamic display mux).
* UHBRSupportedByDfp
* Bitmask to specify the UHBR link rates supported by this dfp.
*
@@ -194,6 +196,9 @@ typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS {
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_MDM 31:31
#define NV0073_CTRL_DFP_FLAGS_MDM_DISABLED (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_MDM_ENABLED (0x00000001U)
@@ -1287,6 +1292,140 @@ typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS {
/*
* NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA
*
* This structure describes diagnostic information about display power
* gating entry sequence
*
* totalRmEntryLatencyUs
* Duration in microseconds that RM took to service 'Enter
* Display Power Gating' command. This includes time for all
* steps that RM performs as part of display power gating entry
* sequence including the below parameters.
* hwOkToGateLatencyUs
* Duration in microseconds that HW took to assert ok_to_gate.
* Only valid when displayId is not equal to 0xFFFFFFFF
* jadeApiLatencyUs
* Duration in microseconds that Jade took to service 'Enter
* Display Power Gating' command
*
*/
typedef struct NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA {
NvU32 totalRmEntryLatencyUs;
NvU32 hwOkToGateLatencyUs;
NvU32 jadeEntryApiLatencyUs;
} NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA;
/*
* NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING
*
* This command can be used to enter display power gating with an option to
* save-restore settings for the specified displayId.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the display for which the state
* needs to be saved-restored during exit of Display Power Gating.
* The display ID must be a dfp display as determined with the
* NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. If more than one
* displayId bit is set or the displayId is not a dfp, this call will
* return NV_ERR_INVALID_ARGUMENT. For the case where no save-restore
* is needed, displayId should be set to 0xFFFFFFFF.
* flags
* This parameter specifies special request from client for RM(for future use)
* diagnosticData
* This parameter provides diagnostic information about display power
* gating entry sequence
*
* Possible status values returned are:
* NV_OK - If Display Power Gating Entry was successful
* NV_ERR_GENERIC - If Display Power Gating Entry failed
* NV_ERR_INVALID_ARGUMENT - If incorrect parameters are sent
*/
#define NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING (0x731174U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING_PARAMS_MESSAGE_ID (0x74U)
typedef struct NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 flag;
NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA diagnosticData;
} NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING_PARAMS;
#define NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_FLAGS_RESERVED 31:0
#define NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_FLAGS_RESERVED_INIT (0x00000000U)
/*
* NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA
*
* This structure describes diagnostic information about display power
* gating exit sequence
*
* totalRmExitLatencyUs
* Duration in microseconds that RM took to service 'Exit
* Display Power Gating' command. This includes time for all
* steps that RM performs as part of display power gating exit
* sequence including the below parameters.
* riscvBootupLatencyUs
* Duration in microseconds that LTM RISCV took to bootup.
* jadeExitApiLatencyUs
* Duration in microseconds that Jade took to service 'Exit
* Display Power Gating' command
*
*/
typedef struct NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA {
NvU32 totalRmExitLatencyUs;
NvU32 riscvBootupLatencyUs;
NvU32 jadeExitApiLatencyUs;
} NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA;
/*
* NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING
*
* This command can be used to exit display power gating. If preceding
* NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING command requested for
* save-restore of settings for a particular displayId then this command
* will restore settings for that displayId.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* flags
* This parameter specifies special request from client for RM(for future use)
* diagnosticData
* This parameter provides diagnostic information about display power
* gating exit sequence
*
* Possible status values returned are:
* NV_OK - When Display Power Gating Exit was successful
* NV_ERR_GENERIC - When Display Power Gating Exit failed
* NV_ERR_INVALID_ARGUMENT - When incorrect parameters are sent
*/
#define NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING (0x731175U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING_PARAMS_MESSAGE_ID (0x75U)
typedef struct NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING_PARAMS {
NvU32 subDeviceInstance;
NvU32 flag;
NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA diagnosticData;
} NV0073_CTRL_CMD_DFP_EXIT_DISPLAY_POWER_GATING_PARAMS;
#define NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_FLAGS_RESERVED 31:0
#define NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_FLAGS_RESERVED_INIT (0x00000000U)
/*
* NV0073_CTRL_CMD_DFP_EDP_DRIVER_UNLOAD
*
@@ -1307,9 +1446,9 @@ typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_DFP_EDP_DRIVER_UNLOAD (0x731174U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DFP_EDP_DRIVER_UNLOAD (0x731176U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS_MESSAGE_ID (0x74U)
#define NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS_MESSAGE_ID (0x76U)
typedef struct NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS {
NvU32 subDeviceInstance;

90
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1562,15 +1562,6 @@ typedef struct NV0073_CTRL_DP_GET_EDP_DATA_PARAMS {
* Specifies TU size value
* watermark
* Specifies stream watermark.
* linkClkFreqHz -- moving to MvidWarParams. Use that instead.
* Specifies the link freq in Hz. Note that this is the byte clock.
* eg: = (5.4 Ghz / 10)
* actualPclkHz; -- moving to MvidWarParams. Use that instead.
* Specifies the actual pclk freq in Hz.
* mvidWarEnabled
* Specifies whether MVID WAR is enabled.
* MvidWarParams
* Is valid if mvidWarEnabled is true.
* bEnableTwoHeadOneOr
* Whether two head one OR is enabled. If this is set then RM will
* replicate SF settings of Master head on Slave head. Head index
@@ -1614,19 +1605,7 @@ typedef struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS {
NvBool bEnhancedFraming;
NvU32 tuSize;
NvU32 waterMark;
NvU32 actualPclkHz; // deprecated -Use MvidWarParams
NvU32 linkClkFreqHz; // deprecated -Use MvidWarParams
NvBool bEnableAudioOverRightPanel;
struct {
NvU32 activeCnt;
NvU32 activeFrac;
NvU32 activePolarity;
NvBool mvidWarEnabled;
struct {
NvU32 actualPclkHz;
NvU32 linkClkFreqHz;
} MvidWarParams;
} Legacy;
} SST;
} NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS;
@@ -1817,6 +1796,10 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
* Returns NV_TRUE if LTTPR Link Training feature is set
* bOverrideLinkBw
* Returns NV_TRUE if DFP limits defined in DCB have to be honored, else NV_FALSE
* bUseRgFlushSequence
* Returns NV_TRUE if GPU uses the new RG flush design
* bSupportDPDownSpread
* Returns NV_TRUE if GPU support downspread.
*
* DSC caps
*
@@ -1845,6 +1828,8 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
NvBool bFECSupported;
NvBool bIsTrainPhyRepeater;
NvBool bOverrideLinkBw;
NvBool bUseRgFlushSequence;
NvBool bSupportDPDownSpread;
NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC;
} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS;
@@ -2837,4 +2822,65 @@ typedef struct NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS {
} NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS;
/*
* NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL
*
* This command is used to query VBL capability and status as well as
* control enable/disable of VBL feature of eDP LCD panels.
*
* subDeviceInstance [in]
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId [in]
* This parameter specifies the ID of the DP display which owns
* the Main Link to be adjusted. The display ID must a DP display
* as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
* If more than one displayId bit is set or the displayId is not a DP,
* this call will return NV_ERR_INVALID_ARGUMENT.
* cmd [in]
* This parameter is an input to this command. The cmd parameter tells
* whether we have to get the value of a specific field or set the
* value in case of a writeable field.
* control [in]
* This parameter is input by the user. It is used by the user to decide the control
* value to be written to the VBL control field. The command to write is
* the NV0073_CTRL_CMD_DP_AUXCH_VBL_CTL_SET command.
* bVblControlCapable [out]
* This parameter reflects the VBL control capability of the Sink which can be
* fetched by using the NV0073_CTRL_CMD_DP_AUXCH_VBL_CTL_CAPABLE_QUERY command.
* bVblStatus [out]
* This parameter reflects the Sink VBL status which can be
* fetched by using the NV0073_CTRL_CMD_DP_AUXCH_VBL_STATUS_QUERY command.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL (0x731386U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL_PARAMS_MESSAGE_ID" */
/* valid commands */
#define NV0073_CTRL_CMD_DP_AUXCH_QUERY_VBL_CTL_CAPABLE 0x00000000
#define NV0073_CTRL_CMD_DP_AUXCH_QUERY_VBL_STATUS 0x00000001
#define NV0073_CTRL_CMD_DP_AUXCH_SET_VBL_CTL 0x00000002
/* valid state values */
#define NV0073_CTRL_CMD_DP_AUXCH_SET_VBL_CTL_DISABLE 0x00000000
#define NV0073_CTRL_CMD_DP_AUXCH_SET_VBL_CTL_ENABLE 0x00000001
#define NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL_PARAMS_MESSAGE_ID (0x86U)
typedef struct NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU8 cmd;
NvU8 control;
NvBool bVblControlCapable;
NvBool bVblStatus;
} NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL_PARAMS;
/* _ctrl0073dp_h_ */

20
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -56,10 +56,22 @@ typedef NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_
typedef NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL (0x730405U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_ENABLE (0x730405U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_ENABLE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS_MESSAGE_ID (0x5U)
#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_ENABLE_PARAMS_MESSAGE_ID (0x5U)
typedef NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS;
typedef NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_ENABLE_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_DISABLE (0x730406U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_DISABLE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_DISABLE_PARAMS_MESSAGE_ID (0x6U)
typedef NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_DISABLE_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR (0x730407U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID (0x7U)
typedef NV0073_CTRL_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS;
/* ctrl0073internal_h */

256
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -30,6 +30,7 @@
// Source file: ctrl/ctrl0073/ctrl0073system.finn
//
#include "nvlimits.h"
#include "ctrl/ctrl0073/ctrl0073base.h"
/* NV04_DISPLAY_COMMON system-level control commands and parameters */
@@ -89,9 +90,9 @@
* Possible status values returned are:
* NV_OK
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_CAPS_V2 (0x730138U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_CAPS_V2 (0x730101U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x38U)
#define NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x01U)
typedef struct NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS {
NvU8 capsTbl[NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE];
@@ -130,7 +131,7 @@ typedef struct NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS {
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS (0x730102U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID (0x2U)
#define NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID (0x02U)
typedef struct NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS {
NvU32 subDeviceInstance;
@@ -184,12 +185,12 @@ typedef struct NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE (0x730108U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE (0x730104U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE_RIGHT_EYE 0x00000000U
#define NV0073_CTRL_CMD_SYSTEM_GET_SCANLINE_LEFT_EYE 0x00000001U
#define NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_MESSAGE_ID (0x8U)
#define NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS_MESSAGE_ID (0x04U)
typedef struct NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS {
NvU32 subDeviceInstance;
@@ -224,9 +225,9 @@ typedef struct NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_COUNTER (0x730109U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_COUNTER (0x730105U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS_MESSAGE_ID (0x9U)
#define NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS_MESSAGE_ID (0x05U)
typedef struct NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS {
NvU32 subDeviceInstance;
@@ -261,9 +262,9 @@ typedef struct NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_ENABLE (0x73010aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_VBLANK_ENABLE (0x730106U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS_MESSAGE_ID (0xAU)
#define NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS_MESSAGE_ID (0x06U)
typedef struct NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS {
NvU32 subDeviceInstance;
@@ -303,9 +304,9 @@ typedef struct NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED (0x730120U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED (0x730107U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID (0x20U)
#define NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID (0x07U)
typedef struct NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS {
NvU32 subDeviceInstance;
@@ -385,9 +386,9 @@ typedef struct NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NVOS_STATUS_ERROR_RETRY
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE (0x730122U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE (0x730108U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID (0x22U)
#define NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID (0x08U)
typedef struct NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS {
NvU32 subDeviceInstance;
@@ -455,9 +456,9 @@ typedef struct NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS {
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_CONFIG (0x730123U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_CONFIG (0x730109U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS_MESSAGE_ID (0x23U)
#define NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS_MESSAGE_ID (0x09U)
typedef struct NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS {
NvU32 subDeviceInstance;
@@ -509,9 +510,9 @@ typedef struct NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS {
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_STATE (0x730124U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_STATE (0x73010aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS_MESSAGE_ID (0x24U)
#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS_MESSAGE_ID (0x0AU)
typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS {
NvU32 subDeviceInstance;
@@ -576,9 +577,9 @@ typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP (0x730125U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP (0x73010bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS_MESSAGE_ID (0x25U)
#define NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS_MESSAGE_ID (0x0BU)
typedef struct NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS {
NvU32 subDeviceInstance;
@@ -639,9 +640,9 @@ typedef struct NV0073_CTRL_SYSTEM_GET_HEAD_ROUTING_MAP_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE (0x730126U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE (0x73010cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID (0x26U)
#define NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID (0x0CU)
typedef struct NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS {
NvU32 subDeviceInstance;
@@ -763,10 +764,10 @@ typedef struct NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS {
* Only returned if subdeviceInstance was not valid.
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP (0x73015aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP (0x730115U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID (0x5AU)
#define NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID (0x15U)
typedef struct NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS {
NvU32 subDeviceInstance;
@@ -799,9 +800,9 @@ typedef struct NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_INTERNAL_DISPLAYS (0x73015bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_INTERNAL_DISPLAYS (0x730116U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS_MESSAGE_ID (0x5BU)
#define NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS_MESSAGE_ID (0x16U)
typedef struct NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS {
NvU32 subDeviceInstance;
@@ -837,13 +838,13 @@ typedef struct NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS {
*
*/
#define NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID (0x5CU)
#define NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID (0x17U)
typedef struct NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS {
NvU32 subDeviceInstance;
} NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS;
#define NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED (0x73015cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED (0x730117U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID" */
/*
@@ -945,12 +946,12 @@ typedef struct NV0073_CTRL_SYSTEM_CONNECTOR_INFO {
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECTOR_TABLE (0x730165U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECTOR_TABLE (0x73011dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS_MESSAGE_ID" */
/* maximum number of connector table entries */
#define NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_MAX_ENTRIES (16U)
#define NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS_MESSAGE_ID (0x65U)
#define NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS_MESSAGE_ID (0x1DU)
typedef struct NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS {
NvU32 subDeviceInstance;
@@ -995,9 +996,9 @@ typedef struct NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS {
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS (0x730166U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS (0x73011eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS_MESSAGE_ID (0x66U)
#define NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS_MESSAGE_ID (0x1EU)
typedef struct NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS {
NvU32 subDeviceInstance;
@@ -1174,9 +1175,9 @@ typedef struct NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS {
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x730168U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x730120U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x68U)
#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS {
NvU32 method;
@@ -1285,9 +1286,9 @@ typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS {
* When set to NV_FALSE, signifies that the vrr monitor is to be removed.
*
*/
#define NV0073_CTRL_CMD_SYSTEM_VRR_DISPLAY_INFO (0x730185U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_VRR_DISPLAY_INFO (0x73012cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID (0x85U)
#define NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID (0x2CU)
typedef struct NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS {
NvU32 subDeviceInstance;
@@ -1340,9 +1341,9 @@ typedef struct NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS {
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE (0x73017bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE (0x73012dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID (0x7BU)
#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID (0x2DU)
typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS {
NvU32 subDeviceInstance;
@@ -1381,9 +1382,9 @@ typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS {
* NV_ERR_INVALID_STATE
*/
#define NV0073_CTRL_CMD_SYSTEM_CLEAR_ELV_BLOCK (0x73017dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_CLEAR_ELV_BLOCK (0x73012eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS_MESSAGE_ID (0x7DU)
#define NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS_MESSAGE_ID (0x2EU)
typedef struct NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS {
NvU32 subDeviceInstance;
@@ -1433,9 +1434,9 @@ typedef struct NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS {
* NV_ERR_INVALID_STATE
*/
#define NV0073_CTRL_CMD_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR (0x73017eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR (0x73012fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS_MESSAGE_ID (0x7EU)
#define NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS_MESSAGE_ID (0x2FU)
typedef struct NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS {
NvU32 subDeviceInstance;
@@ -1485,9 +1486,9 @@ typedef struct NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS {
* minVblankExtension
* When VRR is enabled, this is the minimum amount of lines that should be present in the Vblank. The purpose is to cap the maximum refresh (currently only for HDMI 2.1 VRR compliance)
*/
#define NV0073_CTRL_CMD_SYSTEM_CONFIG_VRR_PSTATE_SWITCH (0x730184U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_CONFIG_VRR_PSTATE_SWITCH (0x730134U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS_MESSAGE_ID (0x84U)
#define NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS_MESSAGE_ID (0x34U)
typedef struct NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS {
NvU32 subDeviceInstance;
@@ -1500,6 +1501,38 @@ typedef struct NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS {
NvU32 minVblankExtension;
} NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR
*
* This command engages the WAR when VR devices are connected,
* where the Pstate switching can cause delay in Vblank callbacks
* reported to KMD, by servicing disp interrupts inline and reporting the
* callbacks to KMD. Without the WAR, there can be stutters during pstate switch.
* Bug#1778552
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
* bEngageWAR
* Indicates if inline disp interrupt serving WAR has to be engaged or
* disengaged.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR (0x730187U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID (0x87U)
typedef struct NV0073_CTRL_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS {
NvU32 subDeviceInstance;
NvBool bEngageWAR;
} NV0073_CTRL_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS;
/*
@@ -1522,9 +1555,9 @@ typedef struct NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS {
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX (0x730190U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX (0x73013dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS_MESSAGE_ID (0x90U)
#define NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS_MESSAGE_ID (0x3DU)
typedef struct NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS {
NvU32 subDeviceInstance;
@@ -1568,9 +1601,9 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS {
* NV_ERR_GENERIC
*/
#define NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH (0x730196U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH (0x730143U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID (0x96U)
#define NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID (0x43U)
typedef struct NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS {
NvU32 subDeviceInstance;
@@ -1619,9 +1652,9 @@ typedef struct NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS {
* the parameters.
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG (0x730197U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG (0x730144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID (0x97U)
#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID (0x44U)
typedef NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS;
@@ -1634,9 +1667,9 @@ typedef NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS NV0073_CTRL_SYSTEM_GET_HO
* the parameters.
*/
#define NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG (0x730198U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG (0x730145U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID (0x98U)
#define NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID (0x45U)
typedef NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS;
@@ -1665,9 +1698,9 @@ typedef NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS NV0073_CTRL_SYSTEM_SET_HO
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS (0x73019bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS (0x73014aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS_MESSAGE_ID (0x9BU)
#define NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS_MESSAGE_ID (0x4AU)
typedef struct NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS {
NvU32 subDeviceInstance;
@@ -1694,9 +1727,9 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT (0x73019cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT (0x73014bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS_MESSAGE_ID (0x9CU)
#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS_MESSAGE_ID (0x4BU)
typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS {
NvU32 subDeviceInstance;
@@ -1726,9 +1759,9 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT (0x73019dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT (0x73014cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID (0x9DU)
#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID (0x4CU)
typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS {
NvU32 subDeviceInstance;
@@ -1777,9 +1810,9 @@ typedef struct NV0073_CTRL_RM_VRR_SHARED_DATA {
NV_DECLARE_ALIGNED(NvU64 dataTimeStamp, 8);
} NV0073_CTRL_RM_VRR_SHARED_DATA;
#define NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE (0x73019eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE (0x73014dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID (0x9EU)
#define NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID (0x4DU)
typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS {
NvU32 subDeviceInstance;
@@ -1797,20 +1830,22 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS {
* The VBlank Semaphore Control API ("VBlank Sem Control") allows clients to
* register for a semaphore release to be performed on the specified memory.
*
* One or more clients may register a memory allocation + offset by specifying
* _PARAMS::bEnabled = NV_TRUE and describing a video memory object with
* _PARAMS::hMemory and an offset within that memory object
* (_PARAMS::memoryOffset). Until the hMemory + memoryOffset combination is
* disabled by a subsequent call with bEnabled = NV_FALSE, during each vblank on
* the specified head, RM will interpret the specified memory location as an
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA data structure.
* One or more clients may register a memory allocation + offset by describing a
* video memory object with _PARAMS::hMemory and an offset within that memory
* object (_PARAMS::memoryOffset). Until the hMemory + memoryOffset combination
* is disabled, during each vblank on the specified heads, RM will interpret the
* specified memory location as an
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA data structure. Each enabled
* head will inspect the corresponding
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD at
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA::head[head].
*
* _PARAMS::memoryOffset must be a multiple of 8, so that GPU semaphore releases
* and GSP can write to 8-byte fields within
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA with natural alignment.
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD with natural alignment.
*
* During vblank, the _CONTROL_DATA::control field will be read, and the
* following pseudocode will be performed:
* During vblank, the _CONTROL_DATA_ONE_HEAD::requestCounter field will be read,
* and the following pseudocode will be performed:
*
* swapInterval = DRF_VAL(data->flags)
* useMinimumGpuTime = DRV_VAL(data->flags)
@@ -1832,16 +1867,16 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS {
* previousVblankCount = currentVblankCount
*
* I.e., if the client-described conditions are met, the RM will write
* _CONTROL_DATA::semaphore to the client-requested 'requestCounter' along with
* several informational fields (vblankCount, releaseGpuTime).
* _CONTROL_DATA_ONE_HEAD::semaphore to the client-requested 'requestCounter'
* along with several informational fields (vblankCount, releaseGpuTime).
*
* The intent is for clients to use semaphore releases to write:
*
* _CONTROL_DATA::minimumGpuTime (if desired)
* _CONTROL_DATA::swapInterval
* _CONTROL_DATA::requestCounter
* _CONTROL_DATA_ONE_HEAD::minimumGpuTime (if desired)
* _CONTROL_DATA_ONE_HEAD::swapInterval
* _CONTROL_DATA_ONE_HEAD::requestCounter
*
* and then perform a semaphore acquire on _CONTROL_DATA::semaphore >=
* and then perform a semaphore acquire on _CONTROL_DATA_ONE_HEAD::semaphore >=
* requestCounter (using the ACQ_GEQ semaphore operation). This will block any
* following methods in the client's channel (e.g., a blit) until the requested
* conditions are met. Note the ::requestCounter should be written last,
@@ -1849,10 +1884,10 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS {
* vblank callback, to inspect the other fields.
*
* Additionally, clients should use the CPU (not semaphore releases in their
* channel) to write the field _CONTROL_DATA::requestCounterAccel at the same
* time that they enqueue the semaphore release to write to
* _CONTROL_DATA::requestCounter. ::requestCounterAccel will be used by resman
* to "accelerate" the vblank sem control by copying the value from
* channel) to write the field _CONTROL_DATA_ONE_HEAD::requestCounterAccel at
* the same time that they enqueue the semaphore release to write to
* _CONTROL_DATA_ONE_HEAD::requestCounter. ::requestCounterAccel will be used
* by resman to "accelerate" the vblank sem control by copying the value from
* ::requestCounterAccel to ::semaphore. This will be done when the vblank sem
* control is disabled, and when a client calls
* NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS. It is important for resman
@@ -1866,13 +1901,35 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS {
*
* The same hMemory (with difference memoryOffsets) may be used by multiple
* VBlank Sem Controls.
*
* Lastly, the bUseHeadIndexMap field in the enable params is used to tell
* resman to honor the headIndexMap[] table in the enable params. Normally, the
* N-th bit in the enable params headMask corresponds to element N in the
* _CONTROL_DATA::head[] array. But, headIndexMap[] allows the N-th bit in
* headMask to be remapped to a different index in the head[] array. E.g.,
*
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA *pData = ...;
*
* FOR_EACH_INDEX_IN_MASK(32, head, pParams->headMask)
* {
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD *pDataOneHead;
* NvU32 headIndex = pParams->bUseHeadIndexMap ?
* pParams->headIndexMap[head] : head;
* pDataOneHead = &pData->head[headIndex];
* ...
* }
* FOR_EACH_INDEX_IN_MASK_END;
*
* This remapping is important for nvkms' use of the RMAPI. To support
* 2head1or, nvkms may remap head indices between the headMask passed to RM and
* the array indices in _CONTROL_DATA::head[] as used by OpenGL.
*/
/* Fields within NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA::flags */
/* Fields within NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD::flags */
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_SWAP_INTERVAL 15:0
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_USE_MINIMUM_GPU_TIME 16:16
typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA {
typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD {
NvU32 requestCounterAccel;
NvU32 requestCounter;
NvU32 flags;
@@ -1881,19 +1938,34 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA {
NvU32 semaphore;
NV_DECLARE_ALIGNED(NvU64 vblankCount, 8);
NV_DECLARE_ALIGNED(NvU64 releaseGpuTime, 8);
} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD;
typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA {
NV_DECLARE_ALIGNED(NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD head[NV_MAX_HEADS], 8);
} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA;
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL (0x73019fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE (0x73014eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS_MESSAGE_ID (0x9FU)
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS_MESSAGE_ID (0x4EU)
typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS {
typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS {
NvU32 subDeviceInstance;
NvBool bEnable;
NvU32 head;
NvU32 headMask;
NvU8 headIndexMap[NV_MAX_HEADS];
NvHandle hMemory;
NV_DECLARE_ALIGNED(NvU64 memoryOffset, 8);
} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS;
NvBool bUseHeadIndexMap;
} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS;
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE (0x73014fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS_MESSAGE_ID (0x4FU)
typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS {
NvU32 subDeviceInstance;
NvHandle hMemory;
NV_DECLARE_ALIGNED(NvU64 memoryOffset, 8);
} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS;
/*
* Accelerate all VBlank Sem Controls on the specified heads.
@@ -1902,9 +1974,9 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS {
* their pending ::semaphore fields to the value in their ::requestCounterAccel
* field.
*/
#define NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS (0x7301a2U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS (0x730150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS_MESSAGE_ID (0xA2U)
#define NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS_MESSAGE_ID (0x50U)
typedef struct NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS {
NvU32 subDeviceInstance;
@@ -1929,9 +2001,9 @@ typedef struct NV0073_CTRL_SHARED_MEMDESC_INFO {
NvU32 cpuCacheAttrib;
} NV0073_CTRL_SHARED_MEMDESC_INFO;
#define NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA (0x7301a3U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA (0x730151U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS_MESSAGE_ID (0xA3U)
#define NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS_MESSAGE_ID (0x51U)
typedef struct NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS {
NV_DECLARE_ALIGNED(NV0073_CTRL_SHARED_MEMDESC_INFO memDescInfo, 8);

7
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -309,7 +309,8 @@ typedef struct NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS {
#define NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS {
NvU32 virtualizationMode;
NvU32 virtualizationMode;
NvBool isGridBuild;
} NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS;
@@ -502,7 +503,7 @@ typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
// Update this macro if new HW exceeds GPU Classlist MAX_SIZE
#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 174
#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 100
#define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */

2
src/common/sdk/nvidia/inc/ctrl/ctrl00de.h
View File

@@ -40,6 +40,8 @@
* NV00DE_CTRL_CMD_REQUEST_DATA_POLL
*
* @brief Request some polled data elements to be updated
* Equivalent to requesting polling using NV00DE_ALLOC_PARAMETERS->polledDataMask
* See cl00de.h for mask bits
*
* @param[in] polledDataMask Bitmask of data to be updated
*

17
src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -89,3 +89,18 @@ typedef struct NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS {
NvU32 operationsProcessedCount;
} NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS;
/*
* NV00FE_CTRL_CMD_RESIZE_QUEUE
*
* Resize the MemoryMapper command queue
* All pending commands remain in queue
*
*/
#define NV00FE_CTRL_CMD_RESIZE_QUEUE (0xfe0102U) /* finn: Evaluated from "(FINN_NV_MEMORY_MAPPER_INTERFACE_ID << 8) | NV00FE_CTRL_RESIZE_QUEUE_PARAMS_MESSAGE_ID" */
#define NV00FE_CTRL_RESIZE_QUEUE_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV00FE_CTRL_RESIZE_QUEUE_PARAMS {
NvU32 maxQueueSize;
} NV00FE_CTRL_RESIZE_QUEUE_PARAMS;

237
src/common/sdk/nvidia/inc/ctrl/ctrl0100.h Normal file
View File

@@ -0,0 +1,237 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0100.finn
//
#include "ctrl/ctrlxxxx.h"
#define NV0100_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0100, NV0100_CTRL_##cat, idx)
/* Client command categories (6bits) */
#define NV0100_CTRL_RESERVED (0x00U)
#define NV0100_CTRL_LOCK_STRESS (0x01U)
/*
* NV0100_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0100_CTRL_CMD_NULL (0x1000000U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NV0100_CTRL_CMD_RESET_LOCK_STRESS_STATE
*
* This command resets RM's lock stress counters to 0, allowing for a new lock stress
* run to start.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0100_CTRL_CMD_RESET_LOCK_STRESS_STATE (0x1000101U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | 0x1" */
/*
* Bit fields to indicate to the caller whether an action was performed on a counter
* Setting any of these fields to 1 means to increment/decrement the respective counter.
* Setting any of these fields to 0 means to ignore the respective counter.
*/
#define NV0100_CTRL_GLOBAL_RMAPI_LOCK_STRESS_COUNTER_ACTION 0:0
#define NV0100_CTRL_GPU_LOCK_STRESS_COUNTER_ACTION 1:1
#define NV0100_CTRL_CLIENT_LOCK_STRESS_COUNTER_ACTION 2:2
#define NV0100_CTRL_INTERNAL_CLIENT_LOCK_STRESS_COUNTER_ACTION 3:3
#define NV0100_CTRL_ALL_LOCK_STRESS_COUNTER_ACTION 3:0
/*
* Bit fields to indicate to the caller what type of action was performed on a counter
* Setting any of these fields to 1 means to increment the respective counter.
* Setting any of these fields to 0 means to decrement the respective counter.
*/
#define NV0100_CTRL_GLOBAL_RMAPI_LOCK_STRESS_COUNTER_INCREMENT 4:4
#define NV0100_CTRL_GPU_LOCK_STRESS_COUNTER_INCREMENT 5:5
#define NV0100_CTRL_CLIENT_LOCK_STRESS_COUNTER_INCREMENT 6:6
#define NV0100_CTRL_INTERNAL_CLIENT_LOCK_STRESS_COUNTER_INCREMENT 7:7
#define NV0100_CTRL_ALL_LOCK_STRESS_COUNTER_INCREMENT 7:4
typedef struct NV0100_CTRL_LOCK_STRESS_OUTPUT {
NvU8 action;
} NV0100_CTRL_LOCK_STRESS_OUTPUT;
/*
* NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_ALL_RM_LOCKS
*
* This command does a random increment/decrement on global counters in RM and reports
* the operation performed back to the caller. This is done with all RM locks held.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_ALL_RM_LOCKS (0x1000102U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_ALL_RM_LOCKS_PARAMS_MESSAGE_ID" */
#define NV0100_CTRL_PERFORM_LOCK_STRESS_ALL_RM_LOCKS_PARAMS_MESSAGE_ID (0x2U)
typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_ALL_RM_LOCKS_PARAMS;
/*
* NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_NO_GPUS_LOCK
*
* This command does a random increment/decrement on global counters in RM and reports
* the operation performed back to the caller. This is done with all RM locks held except
* for the GPU locks.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_NO_GPUS_LOCK (0x1000103U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_PARAMS_MESSAGE_ID" */
#define NV0100_CTRL_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_PARAMS_MESSAGE_ID (0x3U)
typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_PARAMS;
/*
* NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_API_LOCK_READ_MODE
*
* This command does a random increment/decrement on global counters in RM and reports
* the operation performed back to the caller. This is done with the API lock held in
* read mode and GPU locks held.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_API_LOCK_READ_MODE (0x1000104U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID" */
#define NV0100_CTRL_PERFORM_LOCK_STRESS_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID (0x4U)
typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_API_LOCK_READ_MODE_PARAMS;
/*
* NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_API_LOCK_READ_MODE
*
* This command does a random increment/decrement on global counters in RM and reports
* the operation performed back to the caller. This is done with the API lock held in
* read mode.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_API_LOCK_READ_MODE (0x1000105U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID" */
#define NV0100_CTRL_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID (0x5U)
typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_NO_GPUS_LOCK_API_LOCK_READ_MODE_PARAMS;
/*
* NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_ALL_RM_LOCKS
*
* This command does a random increment/decrement on global counters in RM and reports
* the operation performed back to the caller. This is done with all RM locks held in the
* internal RM API path.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_ALL_RM_LOCKS (0x1000106U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_ALL_RM_LOCKS_PARAMS_MESSAGE_ID" */
#define NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_ALL_RM_LOCKS_PARAMS_MESSAGE_ID (0x6U)
typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_ALL_RM_LOCKS_PARAMS;
/*
* NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK
*
* This command does a random increment/decrement on global counters in RM and reports
* the operation performed back to the caller. This is done with all RM locks held except
* for the GPU locks in the internal RM API path.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK (0x1000107U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_PARAMS_MESSAGE_ID" */
#define NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_PARAMS_MESSAGE_ID (0x7U)
typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_PARAMS;
/*
* NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_API_LOCK_READ_MODE
*
* This command does a random increment/decrement on global counters in RM and reports
* the operation performed back to the caller. This is done with the API lock taken in
* read mode and GPU locks held in the internal RM API path.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_API_LOCK_READ_MODE (0x1000108U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID" */
#define NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID (0x8U)
typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_API_LOCK_READ_MODE_PARAMS;
/*
* NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_API_LOCK_READ_MODE
*
* This command does a random increment/decrement on global counters in RM and reports
* the operation performed back to the caller. This is done with the API lock held in read
* mode in the internal RM API path.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0100_CTRL_CMD_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_API_LOCK_READ_MODE (0x1000109U) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID" */
#define NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_API_LOCK_READ_MODE_PARAMS_MESSAGE_ID (0x9U)
typedef NV0100_CTRL_LOCK_STRESS_OUTPUT NV0100_CTRL_PERFORM_LOCK_STRESS_INTERNAL_NO_GPUS_LOCK_API_LOCK_READ_MODE_PARAMS;
/*
* NV0100_CTRL_CMD_GET_LOCK_STRESS_COUNTERS
*
* This command gets the value of the global lock stress counters in RM at the end of
* the lock stress test.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0100_CTRL_CMD_GET_LOCK_STRESS_COUNTERS (0x100010aU) /* finn: Evaluated from "(FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID << 8) | NV0100_CTRL_GET_LOCK_STRESS_COUNTERS_PARAMS_MESSAGE_ID" */
#define NV0100_CTRL_GET_LOCK_STRESS_COUNTERS_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV0100_CTRL_GET_LOCK_STRESS_COUNTERS_PARAMS {
NvS32 globalLockStressCounter;
NvS32 gpuLockStressCounter;
NvS32 clientLockStressCounter;
NvS32 internalClientLockStressCounter;
} NV0100_CTRL_GET_LOCK_STRESS_COUNTERS_PARAMS;

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

111
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -705,75 +705,13 @@ typedef struct NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS {
NvU32 busSpeed;
} NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS;
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS (0x00000001)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS (0x00000002)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS (0x00000003)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS (0x00000004)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS (0x00000005)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS (0x00000006)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS (0x00000001)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS (0x00000002)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS (0x00000003)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS (0x00000004)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS (0x00000005)
#define NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS (0x00000006)
/*
* NV2080_CTRL_CMD_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED
*
* This command Initiates a change in PCIE Bus Speed for a HWBC device's upstream
* link.
*
* busSpeed
* This field specifies the target speed to which to train.
* Legal values for this parameter are:
* NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS
* NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS
* primaryBus
* This field is the PCI Express Primary Bus number that uniquely identifies
* a HWBC device's upstream port, i.e. the BR04 Upstream Port.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED (0x20801806) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS {
NvU32 busSpeed;
NvU8 primaryBus;
} NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS;
#define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_2500MBPS (0x00000001)
#define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_5000MBPS (0x00000002)
/*
* NV2080_CTRL_CMD_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED
*
* This command gets the current PCIE Bus Speed for a HWBC device's upstream
* link.
*
* primaryBus
* This field is the PCI Express Primary Bus number that uniquely identifies
* a HWBC device's upstream port, i.e. the BR04 Upstream Port.
* busSpeed
* This field specifies a pointer in the caller's address space
* to the NvU32 variable into which the bus speed is to be returned.
* On success, this parameter will contain one of the following values:
* NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS
* NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED (0x20801807) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS {
NvU32 busSpeed;
NvU8 primaryBus;
} NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS;
#define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_2500MBPS (0x00000001)
#define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_5000MBPS (0x00000002)
/*
* NV2080_CTRL_CMD_BUS_MAP_BAR2
@@ -791,7 +729,7 @@ typedef struct NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS {
* NV_ERR_NOT_SUPPORTED
*
*/
#define NV2080_CTRL_CMD_BUS_MAP_BAR2 (0x20801809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_BUS_MAP_BAR2 (0x20801809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID (0x9U)
@@ -853,31 +791,6 @@ typedef struct NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS {
NvU32 size;
} NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_HWBC_GET_UPSTREAM_BAR0
*
* This command gets the BAR0 for a HWBC device's upstream port.
*
* primaryBus
* This field is the PCI Express Primary Bus number that uniquely identifies
* a HWBC device's upstream port, i.e. the BR04 Upstream Port.
* physBAR0
* This field returns the BAR0 physical address of the HWBC device's
* upstream port.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_BUS_HWBC_GET_UPSTREAM_BAR0 (0x2080180e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS {
NV_DECLARE_ALIGNED(NvU64 physBAR0, 8);
NvU8 primaryBus;
} NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE
* This command would reports the current Audio device power state or Sets new power state.
@@ -1417,15 +1330,9 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
*
* remoteType[OUT]
* NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU
* in either self-hosted mode or externally-hostedmode.
*/
/*
* in either self-hosted mode or
* externally-hostedmode.
*/
#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID (0x2BU)

159
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -2151,7 +2151,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS {
/*!
* [IN]: swizzId
* [in]: swizzId
* PartitionID associated with a created smc partition. Currently used only for a
* device monitoring client to get the physical values of the FB. The client needs to pass
* 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId.
@@ -2160,7 +2160,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS {
*/
NvU32 swizzId;
/*!
* [OUT]: physical/local fbp mask.
* [out]: physical/local fbp mask.
*/
NV_DECLARE_ALIGNED(NvU64 fbpEnMask, 8);
} NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS;
@@ -2170,11 +2170,11 @@ typedef struct NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS {
/*!
* [IN]: physical/local FB partition index.
* [in]: physical/local FB partition index.
*/
NvU32 fbpIndex;
/*!
* [OUT]: physical/local ltc mask.
* [out]: physical/local ltc mask.
*/
NvU32 ltcEnMask;
} NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS;
@@ -2184,11 +2184,11 @@ typedef struct NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS {
/*!
* [IN]: physical/local FB partition index.
* [in]: physical/local FB partition index.
*/
NvU32 fbpIndex;
/*!
* [OUT]: physical/local lts mask.
* [out]: physical/local lts mask.
* Note that lts bits are flattened out for all ltc with in a fbp.
*/
NvU32 ltsEnMask;
@@ -2199,11 +2199,11 @@ typedef struct NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS {
/*!
* [IN]: physical/local FB partition index.
* [in]: physical/local FB partition index.
*/
NvU32 fbpIndex;
/*!
* [OUT]: physical/local FBPA mask.
* [out]: physical/local FBPA mask.
*/
NvU32 fbpaEnMask;
} NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS;
@@ -2213,11 +2213,11 @@ typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS {
/*!
* [IN]: physical/local FB partition index.
* [in]: physical/local FB partition index.
*/
NvU32 fbpIndex;
/*!
* [OUT]: physical/local FBPA-SubPartition mask.
* [out]: physical/local FBPA-SubPartition mask.
*/
NvU32 fbpaSubpEnMask;
} NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS;
@@ -2227,11 +2227,11 @@ typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS {
/*!
* [IN]: physical/local FB partition index.
* [in]: physical/local FB partition index.
*/
NvU32 fbpIndex;
/*!
* [OUT]: Logical/local FBP index
* [out]: Logical/local FBP index
*/
NvU32 fbpLogicalIndex;
} NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS;
@@ -2241,11 +2241,11 @@ typedef struct NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS {
/*!
* [IN]: physical/local FB partition index.
* [in]: physical/local FB partition index.
*/
NvU32 fbpIndex;
/*!
* [OUT]: physical/local ROP mask.
* [out]: physical/local ROP mask.
*/
NvU32 ropEnMask;
} NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS;
@@ -2255,16 +2255,16 @@ typedef struct NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS {
/*!
* [IN]: Physical FB partition index.
* [in]: Physical FB partition index.
*/
NvU32 fbpIndex;
/*!
* [IN]: swizzId
* [in]: swizzId
* PartitionID associated with a created smc partition.
*/
NvU32 swizzId;
/*!
* [OUT]: physical ltc mask.
* [out]: physical ltc mask.
*/
NvU32 ltcEnMask;
} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS;
@@ -2274,16 +2274,16 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS {
/*!
* [IN]: Physical FB partition index.
* [in]: Physical FB partition index.
*/
NvU32 fbpIndex;
/*!
* [IN]: swizzId
* [in]: swizzId
* PartitionID associated with a created smc partition.
*/
NvU32 swizzId;
/*!
* [OUT]: physical lts mask.
* [out]: physical lts mask.
*/
NvU32 ltsEnMask;
} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS;
@@ -2293,16 +2293,16 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS {
/*!
* [IN]: Physical FB partition index.
* [in]: Physical FB partition index.
*/
NvU32 fbpIndex;
/*!
* [IN]: swizzId
* [in]: swizzId
* PartitionID associated with a created smc partition.
*/
NvU32 swizzId;
/*!
* [OUT]: physical fbpa mask.
* [out]: physical fbpa mask.
*/
NvU32 fbpaEnMask;
} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS;
@@ -2312,16 +2312,16 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS {
/*!
* [IN]: Physical FB partition index.
* [in]: Physical FB partition index.
*/
NvU32 fbpIndex;
/*!
* [IN]: swizzId
* [in]: swizzId
* PartitionID associated with a created smc partition.
*/
NvU32 swizzId;
/*!
* [OUT]: physical rop mask.
* [out]: physical rop mask.
*/
NvU32 ropEnMask;
} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS;
@@ -2331,11 +2331,11 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS {
/*!
* [IN]: Physical FB partition index.
* [in]: Physical FB partition index.
*/
NvU32 fbpIndex;
/*!
* [IN]: swizzId
* [in]: swizzId
* PartitionID associated with a created smc partition. Currently used only for a
* device monitoring client to get the physical values of the FB. The client needs to pass
* 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId.
@@ -2344,7 +2344,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS {
*/
NvU32 swizzId;
/*!
* [OUT]: physical FBPA_SubPartition mask associated with requested partition.
* [out]: physical FBPA_SubPartition mask associated with requested partition.
*/
NV_DECLARE_ALIGNED(NvU64 fbpaSubpEnMask, 8);
} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS;
@@ -2354,11 +2354,11 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS {
*/
typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS {
/*!
* [IN]: physical/local sys Id.
* [in]: physical/local sys Id.
*/
NvU32 sysIdx;
/*!
* [OUT]: physical/local sysltc mask.
* [out]: physical/local sysltc mask.
*/
NvU32 sysl2LtcEnMask;
} NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS;
@@ -2368,31 +2368,66 @@ typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS {
*/
typedef struct NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS {
/*!
* [IN]: physical/local FB partition index.
* [in]: physical/local FB partition index.
*/
NvU32 fbpIndex;
/*!
* [OUT]: physical/local PAC mask.
* [out]: physical/local PAC mask.
*/
NvU32 pacEnMask;
} NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS;
/*!
* Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK.
*/
typedef struct NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS {
/*!
* [in]: physical/local FB partition index.
*/
NvU32 fbpIndex;
/*!
* [out]: logical/local ltc mask.
*/
NV_DECLARE_ALIGNED(NvU64 logicalLtcEnMask, 8);
} NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS;
/*!
* Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK.
*/
typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS {
/*!
* [in]: Physical FB partition index.
*/
NvU32 fbpIndex;
/*!
* [in]: swizzId
* PartitionID associated with a created smc partition.
*/
NvU32 swizzId;
/*!
* [out]: logical ltc mask.
*/
NV_DECLARE_ALIGNED(NvU64 logicalLtcEnMask, 8);
} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS;
// Possible values for queryType
#define NV2080_CTRL_FB_FS_INFO_INVALID_QUERY 0x0U
#define NV2080_CTRL_FB_FS_INFO_FBP_MASK 0x1U
#define NV2080_CTRL_FB_FS_INFO_LTC_MASK 0x2U
#define NV2080_CTRL_FB_FS_INFO_LTS_MASK 0x3U
#define NV2080_CTRL_FB_FS_INFO_FBPA_MASK 0x4U
#define NV2080_CTRL_FB_FS_INFO_ROP_MASK 0x5U
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK 0x6U
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK 0x7U
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK 0x8U
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK 0x9U
#define NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK 0xAU
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK 0xBU
#define NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP 0xCU
#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK 0xDU
#define NV2080_CTRL_FB_FS_INFO_PAC_MASK 0xEU
#define NV2080_CTRL_FB_FS_INFO_INVALID_QUERY 0x0U
#define NV2080_CTRL_FB_FS_INFO_FBP_MASK 0x1U
#define NV2080_CTRL_FB_FS_INFO_LTC_MASK 0x2U
#define NV2080_CTRL_FB_FS_INFO_LTS_MASK 0x3U
#define NV2080_CTRL_FB_FS_INFO_FBPA_MASK 0x4U
#define NV2080_CTRL_FB_FS_INFO_ROP_MASK 0x5U
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK 0x6U
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK 0x7U
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK 0x8U
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK 0x9U
#define NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK 0xAU
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK 0xBU
#define NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP 0xCU
#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK 0xDU
#define NV2080_CTRL_FB_FS_INFO_PAC_MASK 0xEU
#define NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK 0xFU
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK 0x10U
typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
NvU16 queryType;
@@ -2414,6 +2449,8 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS fbpLogicalMap;
NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS sysl2Ltc;
NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS pac;
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS logicalLtc, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS dmLogicalLtc, 8);
} queryParams;
} NV2080_CTRL_FB_FS_INFO_QUERY;
@@ -2761,6 +2798,30 @@ typedef struct NV2080_CTRL_CMD_FB_STATS_ENTRY {
NV_DECLARE_ALIGNED(NvU64 freeSize, 8);
} NV2080_CTRL_CMD_FB_STATS_ENTRY;
/*
* NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE
*
* This control command is used by clients to commit TLB invalidates
*
* gfid[OUT]
* - Specifices GPU function ID.
*
* invalidateAll[OUT]
* - Specifies whether to invalidate all using boolean
*
* @returns Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*
*/
#define NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE (0x20801353U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID (0x53U)
typedef struct NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS {
NvU32 gfid;
NvBool invalidateAll;
} NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS;
typedef struct NV2080_CTRL_CMD_FB_STATS_OWNER_INFO {
//! Total allocated size for this owner
NV_DECLARE_ALIGNED(NvU64 allocSize, 8);

28
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
View File

@@ -905,34 +905,6 @@ typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS {
NvBool bEnableAfterKeyRotation;
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2
*
* This command does the same thing as @ref NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION.
* The difference is that it doesn't take a list of clients and instead all channels belong
* to the client on which this control call is made.
*
* numChannels
* The number of valid entries in hChannelList array.
* hChannelList
* An array of NvHandle listing the channel handles
* to be stopped.
* bEnableAfterKeyRotation
* This determines if channel is enabled by RM after it completes key rotation.
* Possible status values returned are:
* NV_OK
* NVOS_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 (0x2080111b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID (0x1BU)
typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS {
NvU32 numChannels;
NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
NvBool bEnableAfterKeyRotation;
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS;
/*

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

23
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -60,8 +60,12 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
/* valid gpu info index values */
#define NV2080_CTRL_GPU_INFO_INDEX_INDEX 23:0
#define NV2080_CTRL_GPU_INFO_INDEX_ECID_LO32 (0x00000001U)
#define NV2080_CTRL_GPU_INFO_INDEX_ECID_HI32 (0x00000002U)
#define NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT (0x00000004U)
@@ -69,6 +73,7 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 (0x00000013U)
#define NV2080_CTRL_GPU_INFO_INDEX_ECID_EXTENDED (0x0000001bU)
#define NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS (0x0000001fU)
@@ -100,8 +105,6 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY (0x0000003aU)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY (0x0000003bU)
#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU)
#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU)
@@ -112,6 +115,9 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U)
#define NV2080_CTRL_GPU_INFO_INDEX_RESERVED 31:31
/* valid minor revision extended values */
#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U)
#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P (0x00000001U)
@@ -201,6 +207,7 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED (0x00000001U)
/* valid local EGM supported values */
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES (0x00000001U)
@@ -210,8 +217,6 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES (0x00000001U)
/* valid CMP (Crypto Mining Processor) SKU values */
#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES (0x00000001U)
@@ -1121,7 +1126,7 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS {
#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000019U)
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x0000001EU)
@@ -3805,8 +3810,6 @@ typedef struct NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS {
NV_DECLARE_ALIGNED(NvU64 egmGpaFabricBaseAddr, 8);
} NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES
*
@@ -3931,6 +3934,9 @@ typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS {
* [out] busPeerId
* Bus peer ID. For an invalid or a non-existent peer this field
* has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
* [out] busEgmPeerId
* Bus EGM peer ID. For an invalid or a non-existent peer this field
* has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
*/
#define NV2080_GET_P2P_CAPS_UUID_LEN 16U
@@ -3942,6 +3948,7 @@ typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO {
NvU32 p2pOptimalWriteCEs;
NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE];
NvU32 busPeerId;
NvU32 busEgmPeerId;
} NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO;
/*!

210
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -74,7 +74,6 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS {
NvU32 windowPresentMask;
NvBool bFbRemapperEnabled;
NvU32 numHeads;
NvBool bPrimaryVga;
NvU32 i2cPort;
NvU32 internalDispActiveMask;
NvU32 embeddedDisplayPortMask;
@@ -212,23 +211,6 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS {
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS
*
* Set flags for use by the video event buffer
*
* flags
* VIDEO_TRACE_FLAG__*
*
*/
#define NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS {
NvU32 flags;
} NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER
* @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS
@@ -265,36 +247,30 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS {
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS;
/*!
* Retrieve BSP Static data.
* BSP Static data.
*/
#define NV2080_CTRL_CMD_INTERNAL_BSP_GET_CAPS (0x20800a24) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_MAX_BSPS 8
#define NV2080_CTRL_CMD_INTERNAL_MAX_BSPS 8
typedef struct NV2080_CTRL_INTERNAL_BSP_CAPS {
NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE];
} NV2080_CTRL_INTERNAL_BSP_CAPS;
#define NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID (0x24U)
typedef struct NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS {
NV2080_CTRL_INTERNAL_BSP_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS];
NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS];
} NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS;
/*!
* Retrieve MSENC Static data.
* MSENC Static data.
*/
#define NV2080_CTRL_CMD_INTERNAL_MSENC_GET_CAPS (0x20800a25) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 8
#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 8
typedef struct NV2080_CTRL_INTERNAL_MSENC_CAPS {
NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE];
} NV2080_CTRL_INTERNAL_MSENC_CAPS;
#define NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID (0x25U)
typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS {
NV2080_CTRL_INTERNAL_MSENC_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS];
NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS];
@@ -411,30 +387,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMDESC_INFO {
NvU32 cpuCacheAttrib;
} NV2080_CTRL_INTERNAL_MEMDESC_INFO;
/*
* NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY
*
* Set memory for use by the video event buffer
*
* memDescInfo
* Information to set up memory descriptor on GSP
*
* engDesc
* Video engdesc to find correct engine
*
* bEngineFound
* Bool for whether or not the engine is actually assigned to a video object
*/
#define NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY (0x20800a29) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS_MESSAGE_ID (0x29U)
typedef struct NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO memDescInfo, 8);
NvU32 engDesc;
NvBool bEngineFound;
} NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS;
/*!
* @ref NV0080_CTRL_CMD_GR_GET_INFO
* @ref NV0080_CTRL_CMD_GR_GET_INFO_V2
@@ -2372,8 +2324,6 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS {
NvU32 egmPeerId;
} NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR
*
@@ -2468,6 +2418,21 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS {
NvBool bRawMode;
} NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO
*
* This command gets the CCU samples Info from physical-RM.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO (0x20800ab2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xB2" */
typedef struct NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS {
NvU32 ccuSampleSize;
} NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_CCU_MAP
*
@@ -2482,11 +2447,19 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS {
#define NV2080_CTRL_CMD_INTERNAL_CCU_MAP (0x20800ab3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX 1
typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO {
NV_DECLARE_ALIGNED(NvU64 phyAddr, 8);
NvU32 shrBufSize;
NvU32 cntBlkSize;
} NV2080_CTRL_INTERNAL_CCU_MAP_INFO;
#define NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID (0xB3U)
typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 phyAddr[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_CCU_MAP_INFO mapInfo[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8);
} NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP
*
@@ -2524,6 +2497,9 @@ typedef struct NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS {
* [in] busPeerId
* Bus peer ID. For an invalid or a non-existent peer this field
* has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
* [in] busEgmPeerId
* Bus EGM peer ID. For an invalid or a non-existent peer this field
* has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
*/
typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO {
NvU32 gpuId;
@@ -2533,6 +2509,7 @@ typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO {
NvU32 p2pOptimalWriteCEs;
NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE];
NvU32 busPeerId;
NvU32 busEgmPeerId;
} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO;
/*!
@@ -2955,16 +2932,10 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS {
*
* Initialize FBSR on GSP to prepare for suspend-resume
*
* [in] fbsrType
* Fbsr object type
* [in] numRegions
* Number of regions that GSP should allocate records for
* [in] hClient
* Handle to client of SYSMEM memlist object
* [in] hSysMem
* Handle to SYSMEM memlist object
* [in] gspFbAllocsSysOffset
* Offset in SYSMEM for GSP's FB Allocations
* [in] bEnteringGcoffState
* Value of PDB_PROP_GPU_GCOFF_STATE_ENTERING
*
@@ -2979,44 +2950,29 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS {
#define NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID (0xC2U)
typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
NvU32 fbsrType;
NvU32 numRegions;
NvHandle hClient;
NvHandle hSysMem;
NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8);
NvBool bEnteringGcoffState;
} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO
* NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING
*
* Send info of FB region that will be saved/restored by GSP on suspend-resume
* Disable all the active channels during suspend
* Resume FIFO scheduling from GSP after resume on Kernel-RM
*
* [in] fbsrType
* Fbsr object type
* [in] hClient
* Handle to client of FBMEM memlist object
* [in] hVidMem
* Handle to FBMEM memlist object
* [in] vidOffset
* Offset in FBMEM region to save/restore
* [in] sysOffset
* Offset in SYSMEM region to save to/restore from
* [in] size
* Size of region being saved/restored
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID (0xC3U)
#define NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS {
NvU32 fbsrType;
NvHandle hClient;
NvHandle hVidMem;
NV_DECLARE_ALIGNED(NvU64 vidOffset, 8);
NV_DECLARE_ALIGNED(NvU64 sysOffset, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
} NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID (0xC3U)
typedef struct NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS {
NvBool bDisableActiveChannels;
} NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB
@@ -3213,22 +3169,6 @@ typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNA
typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE
*
* Query Coherent FB Aperture Size.
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU)
typedef struct NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS {
// Get Coherent Fb Aperture Size
NV_DECLARE_ALIGNED(NvU64 coherentFbApertureSize, 8);
} NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS;
/*!
* Macros for NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE flag
*/
@@ -3634,15 +3574,11 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
*
* bwMode[IN]
* - Nvlink Bandwidth mode
*
* bLocalEgmEnabled[IN]
* - EGM Enablement Status that needs to be set in GSP-RM
*/
#define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U)
typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS {
NvU8 bwMode;
NvBool bLocalEgmEnabled;
NvU8 bwMode;
} NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS;
/*!
@@ -3741,8 +3677,7 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS {
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE 3U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL 0U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER 1U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER 2U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 3U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 2U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT 6U
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK {
@@ -3777,7 +3712,7 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS {
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEY
*
* This command handles key rotation for a given H2D key (and corresponding D2H key)
* by deriving new key on GSP and updating the key on relevant SEC2 or LCE.
@@ -3869,6 +3804,22 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS
/*!
* NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID
*
* This command is an internal command sent from Kernel RM to Physical RM
* to update the logical Uproc Id for the configuration.
*
* logicalUprocId [OUT]
*/
#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID (0x20800aef) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID (0xEFU)
typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS {
NvU8 logicalUprocId;
} NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP
*
@@ -4138,4 +4089,39 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS {
typedef NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS;
/*!
* NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER
*
* @brief Notify the offloaded RM that CPU-RM enters the power management cycle.
*
* bInPMTransition : [IN]
* newPMLevel : [IN]
* New PM Level : NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_[0-7]
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
*/
#define NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID (0xE9U)
typedef struct NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS {
NvBool bInPMTransition;
NvU32 newPMLevel;
} NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS;
#define NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER (0x20800ae9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP
*
* @brief To get the free heap size of GSP-RM
*
* freeHeapSize : [OUT]
*
* @return NV_OK
*/
#define NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID (0xEBU)
typedef struct NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS {
NV_DECLARE_ALIGNED(NvU64 freeHeapSize, 8);
} NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP (0x20800aeb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID" */
/* ctrl2080internal_h */

155
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -136,6 +136,7 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002U)
@@ -259,6 +260,12 @@ typedef struct NV2080_CTRL_NVLINK_DEVICE_INFO {
* This field specifies the link number on the remote end of the link
* remoteDeviceInfo
* This field stores the device information for the remote end of the link
* nvlinkMinL1Threshold
* This field stores the Min L1 Thresohld of the link
* nvlinkMaxL1Threshold
* This field stores the Max L1 Threshold of the link
* nvlinkL1ThresholdUnits
* This field stores the L1 Threshold Units of the link
*
*/
typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
@@ -310,6 +317,11 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
// Ampere+ only
NvU32 laneRxdetStatusMask;
// L1 Threshold Info
NvU32 nvlinkMinL1Threshold;
NvU32 nvlinkMaxL1Threshold;
NvU32 nvlinkL1ThresholdUnits;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO remoteDeviceInfo, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO localDeviceInfo, 8);
} NV2080_CTRL_NVLINK_LINK_STATUS_INFO;
@@ -361,6 +373,8 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 (0x00000005U)
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FFU)
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 (0x00000001U)
@@ -369,6 +383,8 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0 (0x00000005U)
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FFU)
#define NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 (0x00000001U)
@@ -387,12 +403,18 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
#define NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID (0x000000FFU)
#define NV2080_CTRL_NVLINK_MAX_LINKS 32
// L1 Threshold Units
typedef enum NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT {
NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US = 0,
NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US = 1,
} NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT;
#define NV2080_CTRL_NVLINK_MAX_LINKS 32
// NVLink REFCLK types
#define NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID (0x00U)
#define NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS (0x01U)
#define NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX (0x02U)
#define NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID (0x00U)
#define NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS (0x01U)
#define NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX (0x02U)
#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID (0x2U)
@@ -811,6 +833,96 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS;
#define NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX0 0U
#define NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX1 1U
#define NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX0 2U
#define NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX1 3U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_SIZE 4U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L0 4U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L1 5U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L2 6U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L3 7U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_SIZE 8U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L0 8U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L1 9U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L2 10U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L3 11U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L4 12U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L5 13U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L6 14U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L7 15U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_RECOVERY 16U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_REPLAY 17U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_REPLAY 18U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_MASKED 19U
#define NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_FLIT 20U
#define NV2080_CTRL_NVLINK_COUNTER_LP_DL 21U
#define NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER NV2080_CTRL_NVLINK_COUNTER_LP_DL
#define NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS 2U
#define NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ 28
#define NV2080_CTRL_NVLINK_COUNTER_V2_GROUP(i) ((i) / 64)
#define NV2080_CTRL_NVLINK_COUNTER_V2_COUNTER_MASK(i) ((NvU64)1 << ((i) % 64))
/*
* NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2
* This command gets the counts for different counter types.
*
* [in] linkMask
* Mask of links to be queried
*
* [in] counterMask
* Mask of counter types to be queried
* One of NV2080_CTRL_NVLINK_COUNTERS_TYPE_* macros
*
* [out] counter
* This array contains the error counts for each error type as requested from
* the counterMask. The array indexes correspond to the mask bits one-to-one.
*/
typedef struct NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES {
NvBool overFlow;
NV_DECLARE_ALIGNED(NvU64 value, 8);
} NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES;
#define NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID (0x50U)
typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES counter[NV2080_CTRL_NVLINK_MAX_LINKS][NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ], 8);
} NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2 (0x20803050U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID)" */
/*
* NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2
* This command clears/resets the counters for the specified types.
*
* [in] linkMask
* This parameter specifies for which links we want to clear the
* counters.
*
* [in] counterMask
* This parameter specifies the input mask for desired counters to be
* cleared. Note that all counters cannot be cleared.
*/
#define NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID (0x51U)
typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8);
} NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2 (0x20803051U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID)" */
/*
* NV2080_CTRL_CMD_NVLINK_INJECT_ERROR
@@ -2225,6 +2337,9 @@ typedef struct NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS {
#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA (0x00000001)
#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR (0x00000002)
#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW (0x00000003)
#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_REMOTE (0x00000004)
#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_LOCAL (0x00000005)
#define NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_EXT_LOCAL (0x00000006)
/*
* NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE
@@ -2395,11 +2510,14 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS {
*
* [Out] postRxDetLinkMask
* Mask of links discovered
* [Out] laneRxdetStatusMask
* RXDET per-lane status mask
*/
#define NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID (0x2aU)
typedef struct NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS {
NvU32 postRxDetLinkMask;
NvU32 laneRxdetStatusMask[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET (0x2080302aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID" */
@@ -2609,6 +2727,12 @@ typedef struct NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS {
* Current Nvlink refclk source
* [Out] nvlinkReqLinkClockMhz
* Requested link clock value
* [Out] nvlinkMinL1Threshold
* Requested link Min L1 Threshold
* [Out] nvlinkMaxL1Threshold
* Requested link Max L1 Threshold
* [Out] nvlinkL1ThresholdUnits
* Requested link L1 Threshold Units
*/
typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES {
NvBool bLinkConnectedToSystem;
@@ -2625,6 +2749,9 @@ typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES {
NvU32 nvlinkLinkDataRateKiBps;
NvU8 nvlinkRefClkType;
NvU32 nvlinkReqLinkClockMhz;
NvU32 nvlinkMinL1Threshold;
NvU32 nvlinkMaxL1Threshold;
NvU32 nvlinkL1ThresholdUnits;
} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES;
/*
@@ -2642,7 +2769,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES {
typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS {
NvU32 linkMask;
NvU32 nvlinkRefClkSpeedKHz;
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS;
@@ -2694,15 +2821,12 @@ typedef struct NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS {
*
* Sync the NVLink lane shutdown properties with GSP-RM
*
* [In] bLaneShutdownEnabled
* Whether nvlink shutdown is enabled for the chip
* [In] bLaneShutdownOnUnload
* Whether nvlink shutdown should be triggered on driver unload
*/
#define NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID (0x35U)
typedef struct NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS {
NvBool bLaneShutdownEnabled;
NvBool bLaneShutdownOnUnload;
} NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS;
@@ -2888,19 +3012,26 @@ typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS {
#define NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE (0x2080303d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT (0xFFFFFFFF)
/*
* NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD
*
* This command is used to set the L1 threshold value
* This command is used to set the L1 threshold value.
* A value of NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT
* will reset the L1 Threshold to the default values.
*
* [in] l1Threshold
* Used to set the L1 threshold value
*
* [in] l1ExitThreshold
* Used to set the L1 Exit threshold value
*/
#define NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID (0x3eU)
typedef struct NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS {
NvU32 l1Threshold;
NvU32 l1ExitThreshold;
} NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD (0x2080303eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID" */
@@ -2913,11 +3044,14 @@ typedef struct NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS {
* [out] l1Threshold
* Used to get the L1 threshold value
*
* [out] l1ExitThreshold
* Used to get the L1 Exit Thrshold value
*/
#define NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID (0x3fU)
typedef struct NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS {
NvU32 l1Threshold;
NvU32 l1ExitThreshold;
} NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD (0x2080303fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID" */
@@ -3113,5 +3247,6 @@ typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY (0x20803048U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x48" */
/* _ctrl2080nvlink_h_ */

42
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,8 +34,6 @@
/*************************** SPDM COMMANDS ************************************/
#include "cc_drv.h"
/*!
* @brief SPDM Command Types
*
@@ -45,7 +43,6 @@
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5)
#define RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST (0x6)
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
@@ -117,25 +114,6 @@ typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL {
typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL *PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL;
/*!
* HCC FIPS Self-test.
*/
#define CE_FIPS_SELF_TEST_DATA_SIZE 16
#define CE_FIPS_SELF_TEST_AUTH_TAG_SIZE 16
#define CE_FIPS_SELF_TEST_IV_SIZE 12
typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST {
NvU8 cmdType;
NvU8 isEnc;
CC_KMB kmb;
NvU8 text[CE_FIPS_SELF_TEST_DATA_SIZE];
NvU8 authTag[CE_FIPS_SELF_TEST_AUTH_TAG_SIZE];
} RM_GSP_SPDM_CMD_FIPS_SELFTEST;
typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST *PRM_GSP_SPDM_CMD_FIPS_SELFTEST;
/*!
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
* getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in
@@ -154,9 +132,6 @@ typedef union RM_GSP_SPDM_CMD {
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd;
RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL ccHeartbeatCtrl;
RM_GSP_SPDM_CMD_FIPS_SELFTEST ccFipsTest;
} RM_GSP_SPDM_CMD;
typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
@@ -174,7 +149,6 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL (0x5)
#define RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST (0x6)
@@ -194,20 +168,20 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
* SPDM message structure.
*/
typedef struct RM_GSP_SPDM_MSG {
NvU8 msgType;
NvU8 msgType;
// status returned from GSP message infrastructure.
NvU32 status;
NvU32 status;
NvU32 rsvd1;
NvU32 rsvd1;
NvU32 rsvd2;
NvU32 rsvd2;
NvU32 rsvd3;
NvU32 rsvd3;
NvU32 rsvd4;
NvU32 rsvd4;
NvU32 rsvd5;
NvBool rsvd5;
} RM_GSP_SPDM_MSG;
typedef struct RM_GSP_SPDM_MSG *PRM_GSP_SPDM_MSG;

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

3
src/common/sdk/nvidia/inc/ctrl/ctrl208f.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -47,5 +47,6 @@
#include "ctrl208f/ctrl208fpmgr.h"
#include "ctrl208f/ctrl208fdma.h"
#include "ctrl208f/ctrl208fmmu.h"
#include "ctrl208f/ctrl208fucodecoverage.h"

7
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -53,9 +53,8 @@
#define NV208F_CTRL_PMGR (0x13)
#define NV208F_CTRL_DMA (0x14)
// const NV208F_CTRL_TMR = (0x15); // not supported
#define NV208F_CTRL_RMFS (0x16)
#define NV208F_CTRL_GSPMSGTIMING (0x17)
#define NV208F_CTRL_BUS (0x18)
#define NV208F_CTRL_GSPMSGTIMING (0x16)
#define NV208F_CTRL_BUS (0x17)
/*
* NV208F_CTRL_CMD_NULL

50
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -460,20 +460,11 @@ typedef struct NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS {
NV_DECLARE_ALIGNED(NvU64 address, 8);
} NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS;
typedef struct NV208F_CTRL_FB_REMAPPING_RBC_ADDRESS_INFO {
NvU32 bank;
NvU32 stackId;
NvU32 row;
NvU32 partition;
NvU32 sublocation;
} NV208F_CTRL_FB_REMAPPING_RBC_ADDRESS_INFO;
#define NV208F_CTRL_FB_REMAP_ROW_ADDRESS_TYPE_PHYSICAL 0x0
#define NV208F_CTRL_FB_REMAP_ROW_ADDRESS_TYPE_RBC 0x1
/*
* NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO
*
* physicalAddress
* Physical address to be remapped
* source
* The reason for retirement. Valid values for this parameter are
* from NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_*
@@ -489,23 +480,11 @@ typedef struct NV208F_CTRL_FB_REMAPPING_RBC_ADDRESS_INFO {
* Attempting to remap a reserved row
* NV208F_CTRL_FB_REMAP_ROW_STATUS_INTERNAL_ERROR
* Some other RM failure
* addressType
* Type of address passed. Valid values are:
* NV208F_CTRL_FB_REMAP_ROW_ADDRESS_TYPE_PHYSICAL
* The specified address is physical address.
* NV208F_CTRL_FB_REMAP_ROW_ADDRESS_TYPE_RBC
* The specified address is DRAM Row Bank Column address.
* address
* Union of physicalAddress and rbcAddress. Set the appropriate one based on the address type.
*/
typedef struct NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO {
NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8);
NvU8 source;
NvU32 status;
NvU8 addressType;
union {
NV_DECLARE_ALIGNED(NvU64 physicalAddress, 8);
NV208F_CTRL_FB_REMAPPING_RBC_ADDRESS_INFO rbcAddress;
} address;
} NV208F_CTRL_FB_REMAPPING_ADDRESS_INFO;
/* valid values for status */
@@ -612,25 +591,4 @@ typedef struct NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS {
NvBool bForcePurge;
} NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS;
/*
* NV208F_CTRL_CMD_FB_GET_FLOORSWEPT_FBPA_MASK
*
* This command calculates the floorswept fbpa mask by taking 1/2 HBM
* floorsweeping into account
*
* fbpaMask
* This value of the mask.
*
* Possbile status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV208F_CTRL_CMD_FB_GET_FLOORSWEPT_FBPA_MASK (0x208f0516) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS_MESSAGE_ID (0x16U)
typedef struct NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS {
NvU32 fbpaMask;
} NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS;
/* _ctrl208ffb_h_ */

137
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fucodecoverage.h Normal file
View File

@@ -0,0 +1,137 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl208f/ctrl208fucodecoverage.finn
//
#include "ctrl/ctrl208f/ctrl208fbase.h"
/* Numerical ID for each ucode */
#define NV208F_UCODE_COVERAGE_SEC2 1
#define NV208F_UCODE_COVERAGE_PMU 2
#define NV208F_UCODE_COVERAGE_GSP_TASK_RM 3
#define NV208F_UCODE_COVERAGE_GSP_TASK_VGPU 4
/*
* NV208F_CTRL_UCODE_COVERAGE_STATE_PARAMS
*
* Parameters struct shared by the control calls
* NV208F_CTRL_CMD_UCODE_COVERAGE_GET_STATE and
* NV208F_CTRL_CMD_UCODE_COVERAGE_SET_STATE.
*/
typedef struct NV208F_CTRL_UCODE_COVERAGE_STATE_PARAMS {
NvU32 ucode;
NvU32 gfid;
NvBool bEnabled;
NvBool bClear;
} NV208F_CTRL_UCODE_COVERAGE_STATE_PARAMS;
/*
* NV208F_CTRL_CMD_UCODE_COVERAGE_GET_STATE
*
* Retrieves the status of the target ucode's coverage
*
* ucode numeric id of the desired ucode to target
* gfid specifies which partition to send the command to
* (applies to ucode=NV208F_UCODE_COVERAGE_GSP_TASK_VGPU only)
* bEnabled whether the ucode's SanitizerCoverage run-time data gathering
* is enabled (NV_TRUE) or not (NV_FALSE)
*
* Possible status values returned are
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV208F_CTRL_CMD_UCODE_COVERAGE_GET_STATE (0x208f1901) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_UCODE_COVERAGE_INTERFACE_ID << 8) | NV208F_CTRL_UCODE_COVERAGE_GET_STATE_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_UCODE_COVERAGE_GET_STATE_PARAMS_MESSAGE_ID (0x1U)
typedef NV208F_CTRL_UCODE_COVERAGE_STATE_PARAMS NV208F_CTRL_UCODE_COVERAGE_GET_STATE_PARAMS;
/*
* NV208F_CTRL_CMD_UCODE_COVERAGE_SET_STATE
*
* Enables/disables and optionally clears coverage data of the target ucode
*
* ucode numeric id of the desired ucode to target
* gfid specifies which partition to send the command to
* (applies to ucode=NV208F_UCODE_COVERAGE_GSP_TASK_VGPU only)
* bEnabled whether to enable (NV_TRUE) or disable (NV_FALSE) coverage for the given ucode
* bClear whether to clear coverage prior to enabling enabling coverage collection
*
* Possible status values returned are
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV208F_CTRL_CMD_UCODE_COVERAGE_SET_STATE (0x208f1902) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_UCODE_COVERAGE_INTERFACE_ID << 8) | NV208F_CTRL_UCODE_COVERAGE_SET_STATE_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_UCODE_COVERAGE_SET_STATE_PARAMS_MESSAGE_ID (0x2U)
typedef NV208F_CTRL_UCODE_COVERAGE_STATE_PARAMS NV208F_CTRL_UCODE_COVERAGE_SET_STATE_PARAMS;
/*
* NV208F_UCODE_COVERAGE_RPC_MAX_BYTES_*
*
* Maximum number of bytes that can be retrieved by one RPC call
* (potentially differs per-ucode). These are used to size the buffer in the
* respective ucode RPC parameters.
*/
#define NV208F_UCODE_COVERAGE_RPC_MAX_BYTES_PMU 128
#define NV208F_UCODE_COVERAGE_RPC_MAX_BYTES_GSPRM 65536
/*
* NV208F_CTRL_CMD_UCODE_COVERAGE_GET_DATA
*
* Retrieves coverage data of the target ucode
*
* data buffer to retrieve data into
* ucode numeric id of the desired ucode to retrieve data from
* gfid specifies which partition to send the command to
* (applies to ucode=NV208F_UCODE_FUZZER_GSP_TASK_VGPU only)
* offset offset of internal buffer to copy from
*
* Possible status values returned are
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV208F_CTRL_CMD_UCODE_COVERAGE_GET_DATA (0x208f1903) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_UCODE_COVERAGE_INTERFACE_ID << 8) | NV208F_CTRL_UCODE_COVERAGE_GET_DATA_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_UCODE_COVERAGE_GET_DATA_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV208F_CTRL_UCODE_COVERAGE_GET_DATA_PARAMS {
NvU8 data[NV208F_UCODE_COVERAGE_RPC_MAX_BYTES_GSPRM];
NvU32 ucode;
NvU32 gfid;
NvU32 offset;
} NV208F_CTRL_UCODE_COVERAGE_GET_DATA_PARAMS;
/* _ctrl208fucodecoverage_h_ */

1
src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h
View File

@@ -39,7 +39,6 @@
#define NV5070_CTRL_RESERVED (0x00)
#define NV5070_CTRL_CHNCTL (0x01)
#define NV5070_CTRL_RG (0x02)
#define NV5070_CTRL_SEQ (0x03)
#define NV5070_CTRL_OR (0x04)
#define NV5070_CTRL_INST (0x05)
#define NV5070_CTRL_VERIF (0x06)

6
src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h
View File

@@ -33,8 +33,6 @@
#include "ctrl5070common.h"
#include "ctrl/ctrl5070/ctrl5070base.h"
/*
* NV5070_CTRL_CMD_SET_DAC_PWR
*
@@ -151,8 +149,6 @@ typedef struct NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS {
NvU32 flags;
} NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS;
/*
* NV5070_CTRL_CMD_GET_SOR_PWM
*
@@ -193,7 +189,7 @@ typedef struct NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV5070_CTRL_CMD_GET_SOR_PWM (0x50700420) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_CMD_GET_SOR_PWM (0x50700420) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS_MESSAGE_ID (0x20U)

521
src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h
View File

@@ -1,521 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl5070/ctrl5070seq.finn
//
#include "ctrl/ctrl5070/ctrl5070base.h"
/*
* NV5070_CTRL_CMD_GET_SOR_SEQ_CTL
*
* This command returns SOR sequencer's power up and down PCs and sequencer
* program to be used for power up and dowm.
*
* orNumber
* The OR number for which the seq ctrls are to be modified.
*
* puPcAlt
* Alternate power up PC.
*
* pdPc
* Power down PC.
*
* pdPcAlt
* Alternate power down PC.
*
* normalStart
* Whether normal mode is using normal or alt PC
*
* safeStart
* Whether safe mode is using normal or alt PC
*
* normalState
* Whether normal state is PD or PU.
*
* safeState
* Whether safe state is PD or PU.
*
* flags
* There is only one flag defined currently
* 1. GET_SEQ_PROG: Whether or not current seq program must be
* return back. Caller should set this to _YES to read the
* current seq program.
*
* seqProgram
* The sequencer program consisting of power up and down sequences.
* For NV50, this consists of 16 DWORDS. The program is
* relevant only when GET_SEQ_PROG flags is set to _YES.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL (0x50700301U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PU_PC_ALT_VALUE 3:0
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PD_PC_VALUE 3:0
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PD_PC_ALT_VALUE 3:0
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_START_VAL 0:0
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U)
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_START_VAL_ALT (0x00000001U)
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_START_VAL 0:0
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_START_VAL_NORMAL (0x00000000U)
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_START_VAL_ALT (0x00000001U)
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_STATE_VAL 0:0
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PD (0x00000000U)
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PU (0x00000001U)
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_STATE_VAL 0:0
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_STATE_VAL_PD (0x00000000U)
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SAFE_STATE_VAL_PU (0x00000001U)
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_FLAGS_GET_SEQ_PROG 0:0
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_NO (0x00000000U)
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_YES (0x00000001U)
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SEQ_PROG_SIZE 16U
#define NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS {
NV5070_CTRL_CMD_BASE_PARAMS base;
NvU32 orNumber;
NvU32 puPcAlt;
NvU32 pdPc;
NvU32 pdPcAlt;
NvU32 normalStart;
NvU32 safeStart;
NvU32 normalState;
NvU32 safeState;
NvU32 flags;
NvU32 seqProgram[NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_SEQ_PROG_SIZE];
} NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS;
/*
* NV5070_CTRL_CMD_SET_SOR_SEQ_CTL
*
* This command does the following in that order
* (a) Loads a specified sequencer program for power up and down.
* (b) Updates SOR sequencer's power up and down PCs, tells seq to SKIP
* current wait for vsync and waits until sequencer actually SKIPs or halts
* (see more below under SKIP_WAIT_FOR_VSYNC flag) and
* (c) Update power settings (safe/normal start and state).
*
* orNumber
* The OR number for which the seq ctrls are to be modified.
*
* puPcAlt
* Alternate power up PC.
*
* pdPc
* Power down PC.
*
* pdPcAlt
* Alternate power down PC.
*
* normalStart
* Whether normal mode should use normal or alt PC.
*
* safeStart
* Whether safe mode should use normal or alt PC.
*
* normalState
* Whether normal state should be PD or PU.
*
* safeState
* Whether safe state should be PD or PU.
*
* flags
* The following flags have been defined
* 1. SKIP_WAIT_FOR_VSYNC: Should seq be forced to skip waiting
* for vsync if it's currently waiting on such an instruction.
* If the current instruction doesn't have a wait for vsync,
* SKIP will be applied to the next one and so on until
* either sequencer halts or an instruction with a wait for
* vsync is found. The call will block until seq halts or
* SKIPs a wait for vsync.
* 2. SEQ_PROG_PRESENT: Whether or not a new seq program has
* been specified.
*
* seqProgram
* The sequencer program consisting of power up and down sequences.
* For NV50, this consists of 16 DWORDS. The program is
* relevant only when SEQ_PROG_PRESENT flags is set to _YES.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL (0x50700302U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_VALUE 3:0
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_VALUE 3:0
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_VALUE 3:0
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_VAL 0:0
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_VAL_ALT (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_START_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_VAL 0:0
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_VAL_NORMAL (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_VAL_ALT (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_START_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_VAL 0:0
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PD (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_VAL_PU (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_VAL 0:0
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_VAL_PD (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_VAL_PU (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SAFE_STATE_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC 0:0
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT 1:1
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SEQ_PROG_SIZE 16U
#define NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS {
NV5070_CTRL_CMD_BASE_PARAMS base;
NvU32 orNumber;
NvU32 puPcAlt;
NvU32 pdPc;
NvU32 pdPcAlt;
NvU32 normalStart;
NvU32 safeStart;
NvU32 normalState;
NvU32 safeState;
NvU32 flags;
NvU32 seqProgram[NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_SEQ_PROG_SIZE];
} NV5070_CTRL_CMD_SET_SOR_SEQ_CTL_PARAMS;
/*
* NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL
*
* This command returns PIOR sequencer's power up and down PCs and sequencer
* program to be used for power up and dowm.
*
* orNumber
* The OR number for which the seq ctrls are to be modified.
*
* puPcAlt
* Alternate power up PC.
*
* pdPc
* Power down PC.
*
* pdPcAlt
* Alternate power down PC.
*
* normalStart
* Whether normal mode is using normal or alt PC
*
* safeStart
* Whether safe mode is using normal or alt PC
*
* normalState
* Whether normal state is PD or PU.
*
* safeState
* Whether safe state is PD or PU.
*
* flags
* There is only one flag defined currently
* 1. GET_SEQ_PROG: Whether or not current seq program must be
* return back. Caller should set this to _YES to read the
* current seq program.
*
* seqProgram
* The sequencer program consisting of power up and down sequences.
* For NV50, this consists of 16 DWORDS. The program is
* relevant only when GET_SEQ_PROG flags is set to _YES.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL (0x50700303U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PU_PC_ALT_VALUE 3:0
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PD_PC_VALUE 3:0
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PD_PC_ALT_VALUE 3:0
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_START_VAL 0:0
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U)
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_START_VAL_ALT (0x00000001U)
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_START_VAL 0:0
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_START_VAL_NORMAL (0x00000000U)
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_START_VAL_ALT (0x00000001U)
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_STATE_VAL 0:0
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PD (0x00000000U)
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PU (0x00000001U)
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_STATE_VAL 0:0
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PD (0x00000000U)
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PU (0x00000001U)
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_FLAGS_GET_SEQ_PROG 0:0
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_NO (0x00000000U)
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_FLAGS_GET_SEQ_PROG_YES (0x00000001U)
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SEQ_PROG_SIZE 8U
#define NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS {
NV5070_CTRL_CMD_BASE_PARAMS base;
NvU32 orNumber;
NvU32 puPcAlt;
NvU32 pdPc;
NvU32 pdPcAlt;
NvU32 normalStart;
NvU32 safeStart;
NvU32 normalState;
NvU32 safeState;
NvU32 flags;
NvU32 seqProgram[NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_SEQ_PROG_SIZE];
} NV5070_CTRL_CMD_GET_PIOR_SEQ_CTL_PARAMS;
/*
* NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL
*
* This command does the following in that order
* (a) Loads a specified sequencer program for power up and down.
* (b) Updates PIOR sequencer's power up and down PCs, tells seq to SKIP
* current wait for vsync and waits until sequencer actually SKIPs or halts
* (see more below under SKIP_WAIT_FOR_VSYNC flag) and
* (c) Update power settings (safe/normal start and state).
*
* orNumber
* The OR number for which the seq ctrls are to be modified.
*
* puPcAlt
* Alternate power up PC.
*
* pdPc
* Power down PC.
*
* pdPcAlt
* Alternate power down PC.
*
* normalStart
* Whether normal mode should use normal or alt PC
*
* safeStart
* Whether safe mode should use normal or alt PC
*
* normalState
* Whether normal state should be PD or PU.
*
* safeState
* Whether safe state should be PD or PU.
*
* flags
* The following flags have been defined
* 1. SKIP_WAIT_FOR_VSYNC: Should seq be forced to skip waiting
* for vsync if it's currently waiting on such an instruction.
* If the current instruction doesn't have a wait for vsync,
* SKIP will be applied to the next one and so on until
* either sequencer halts or an instruction with a wait for
* vsync is found. The call will block until seq halts or
* SKIPs a wait for vsync.
* 2. SEQ_PROG_PRESENT: Whether or not a new seq program has
* been specified.
*
* seqProgram
* The sequencer program consisting of power up and down sequences.
* For NV50, this consists of 8 DWORDS. The program is
* relevant only when SEQ_PROG_PRESENT flags is set to _YES.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL (0x50700304U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_VALUE 3:0
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PU_PC_ALT_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_VALUE 3:0
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_VALUE 3:0
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PD_PC_ALT_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_VAL 0:0
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_VAL_NORMAL (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_VAL_ALT (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_START_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_VAL 0:0
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_VAL_NORMAL (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_VAL_ALT (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_START_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_VAL 0:0
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PD (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_VAL_PU (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_NORMAL_STATE_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_VAL 0:0
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PD (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_VAL_PU (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_SPECIFIED 31:31
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_SPECIFIED_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SAFE_STATE_SPECIFIED_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC 0:0
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SKIP_WAIT_FOR_VSYNC_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT 1:1
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_NO (0x00000000U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_FLAGS_SEQ_PROG_PRESENT_YES (0x00000001U)
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SEQ_PROG_SIZE 8U
#define NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS {
NV5070_CTRL_CMD_BASE_PARAMS base;
NvU32 orNumber;
NvU32 puPcAlt;
NvU32 pdPc;
NvU32 pdPcAlt;
NvU32 normalStart;
NvU32 safeStart;
NvU32 normalState;
NvU32 safeState;
NvU32 flags;
NvU32 seqProgram[NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_SEQ_PROG_SIZE];
} NV5070_CTRL_CMD_SET_PIOR_SEQ_CTL_PARAMS;
/*
* NV5070_CTRL_CMD_CTRL_SEQ_PROG_SPEED
*
* This call allows a fast sequencer program to be selected. It's intended for
* situations where panel sequencing is not required and the usual sequencing
* delays cost too much time.
*
* displayId
* The corresponding display ID. (Note that this call is currently only
* supported for LVDS on an internal encoder, i.e. a SOR.)
* cmd
* The command to perform. Valid values are:
* NV5070_CTRL_SEQ_PROG_SPEED_CMD_GET
* Get the current state.
* NV5070_CTRL_SEQ_PROG_SPEED_CMD_SET
* Set the current state.
* state
* The state of panel sequencing for this displayId. This is an input
* when cmd = SET and an output when cmd = GET.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_NOT_SUPPORTED
*
*/
#define NV5070_CTRL_CMD_CTRL_SEQ_PROG_SPEED (0x50700305U) /* finn: Evaluated from "(FINN_NV50_DISPLAY_SEQ_INTERFACE_ID << 8) | NV5070_CTRL_SEQ_PROG_SPEED_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_SEQ_PROG_SPEED_CMD_GET (0x00000000U)
#define NV5070_CTRL_SEQ_PROG_SPEED_CMD_SET (0x00000001U)
#define NV5070_CTRL_SEQ_PROG_SPEED_STATE_NORMAL (0x00000000U)
#define NV5070_CTRL_SEQ_PROG_SPEED_STATE_FAST (0x00000001U)
#define NV5070_CTRL_SEQ_PROG_SPEED_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV5070_CTRL_SEQ_PROG_SPEED_PARAMS {
NV5070_CTRL_CMD_BASE_PARAMS base;
NvU32 displayId;
NvU32 cmd;
NvU32 state;
} NV5070_CTRL_SEQ_PROG_SPEED_PARAMS;
/* _ctrl5070seq_h_ */

8
src/common/sdk/nvidia/inc/ctrl/ctrl5080.h
View File

@@ -188,6 +188,14 @@ typedef struct NV5080_CTRL_DEFERRED_API_V2_PARAMS {
} api_bundle;
} NV5080_CTRL_DEFERRED_API_V2_PARAMS;
/* This is just used to forward NV5080_CTRL_CMD_DEFERRED_API_V2 from kernel RM
* to physical RM. The parameters are unchanged. */
#define NV5080_CTRL_CMD_DEFERRED_API_INTERNAL (0x50800104) /* finn: Evaluated from "(FINN_NV50_DEFERRED_API_CLASS_DEFERRED_INTERFACE_ID << 8) | NV5080_CTRL_DEFERRED_API_INTERNAL_PARAMS_MESSAGE_ID" */
#define NV5080_CTRL_DEFERRED_API_INTERNAL_PARAMS_MESSAGE_ID (0x4U)
typedef NV5080_CTRL_DEFERRED_API_V2_PARAMS NV5080_CTRL_DEFERRED_API_INTERNAL_PARAMS;
/*
* NV5080_CTRL_CMD_REMOVE_API
*

42
src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2013-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,50 +23,12 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl90e7.finn
//
#include "nvfixedtypes.h"
#include "ctrl/ctrlxxxx.h"
/* GF100_SUBDEVICE_INFOROM control commands and parameters */
#define NV90E7_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90E7, NV90E7_CTRL_##cat, idx)
/* Command categories (6 bits) */
#define NV90E7_CTRL_RESERVED (0x00)
#define NV90E7_CTRL_BBX (0x01)
/*
* NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME
*
* This command is used to query the last BBX flush timestamp and duration. If BBX has not yet
* been flushed, the status returned is NV_ERR_NOT_READY.
*
* timestamp
* This parameter specifies the start timestamp of the last BBX flush.
*
* durationUs
* This parameter specifies the duration (us) of the last BBX flush.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_READY
* NV_ERR_NOT_SUPPORTED
*/
#define NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME (0x90e70113) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID << 8) | NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID" */
#define NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS {
NV_DECLARE_ALIGNED(NvU64 timestamp, 8);
NvU32 durationUs;
} NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS;
#include "ctrl90e7/ctrl90e7bbx.h"

56
src/common/sdk/nvidia/inc/ctrl/ctrl90e7/ctrl90e7base.h Normal file
View File

@@ -0,0 +1,56 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl90e7/ctrl90e7base.finn
//
#include "ctrl/ctrlxxxx.h"
/* GF100_SUBDEVICE_INFOROM control commands and parameters */
#define NV90E7_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90E7, NV90E7_CTRL_##cat, idx)
/* Command categories (6 bits) */
#define NV90E7_CTRL_RESERVED (0x00)
#define NV90E7_CTRL_BBX_LEGACY_PRIVILEGED (0xc1) /* finn: Evaluated from "(NV90E7_CTRL_BBX | NVxxxx_CTRL_LEGACY_PRIVILEGED)" */
#define NV90E7_CTRL_BBX (0x01)
#define NV90E7_CTRL_RPR (0x02)
/*
* NV90E7_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV90E7_CTRL_CMD_NULL (0x90e70000) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_RESERVED_INTERFACE_ID << 8) | 0x0" */

65
src/common/sdk/nvidia/inc/ctrl/ctrl90e7/ctrl90e7bbx.h Normal file
View File

@@ -0,0 +1,65 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl90e7/ctrl90e7bbx.finn
//
#include "nvfixedtypes.h"
#include "ctrl/ctrl90e7/ctrl90e7base.h"
/*
* NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME
*
* This command is used to query the last BBX flush timestamp and duration. If BBX has not yet
* been flushed, the status returned is NV_ERR_NOT_READY.
*
* timestamp
* This parameter specifies the start timestamp of the last BBX flush.
*
* durationUs
* This parameter specifies the duration (us) of the last BBX flush.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_READY
* NV_ERR_NOT_SUPPORTED
*/
#define NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME (0x90e70113) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID << 8) | NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID" */
#define NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS {
NV_DECLARE_ALIGNED(NvU64 timestamp, 8);
NvU32 durationUs;
} NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS;

65
src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h
View File

@@ -1,17 +1,17 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2007-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -32,29 +32,6 @@
#include "ctrl/ctrla06f/ctrla06fbase.h"
/*
* NVA06F_CTRL_GET_CLASS_ENGINEID
*
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVA06F_CTRL_GET_CLASS_ENGINEID (0xa06f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
#define NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS;
/*
* NVA06F_CTRL_RESET_CHANNEL
*
* Please see description of NV906F_CTRL_RESET_CHANNEL for more information.
*/
#define NVA06F_CTRL_CMD_RESET_CHANNEL (0xa06f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS;
/*
* NVA06F_CTRL_CMD_GPFIFO_SCHEDULE
*
@@ -111,20 +88,6 @@ typedef struct NVA06F_CTRL_BIND_PARAMS {
NvU32 engineType;
} NVA06F_CTRL_BIND_PARAMS;
/*
* NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO
*
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa06f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
#define NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
/*
* NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER
*
@@ -132,7 +95,7 @@ typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA06F_CTRL_GET_MMU_FAULT_INFO_PAR
* bNotifyEachChannelInTSG
* When true, the error notifier will be set on every channel in
* the TSG that contains the channel.
*
*
* Possible status values returned are:
* NV_OK
*/
@@ -248,7 +211,7 @@ typedef struct NVA06F_CTRL_RESTART_RUNLIST_PARAMS {
* Also set an error notifier to notify user space that channel is stopped.
*
* bImmediate
* Input parameter. If NV_FALSE, we will wait for default RM timeout
* Input parameter. If NV_FALSE, we will wait for default RM timeout
* for channel to idle. If NV_TRUE, we don't wait for channel to idle.
* If channel is not idle, we forcefully preempt it off the runlist.
* If the preempt times out, we will RC the channel.
@@ -266,4 +229,20 @@ typedef struct NVA06F_CTRL_STOP_CHANNEL_PARAMS {
NvBool bImmediate;
} NVA06F_CTRL_STOP_CHANNEL_PARAMS;
/*
* NVA06F_CTRL_CMD_GET_CONTEXT_ID
*
* This command returns the context ID of a given channel.
*
* Possible status values returned are:
* NV_OK
*/
#define NVA06F_CTRL_CMD_GET_CONTEXT_ID (0xa06f0113) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_CONTEXT_ID_PARAMS_MESSAGE_ID" */
#define NVA06F_CTRL_GET_CONTEXT_ID_PARAMS_MESSAGE_ID (0x13U)
typedef struct NVA06F_CTRL_GET_CONTEXT_ID_PARAMS {
NvU32 contextId;
} NVA06F_CTRL_GET_CONTEXT_ID_PARAMS;
/* _ctrla06fgpfifo_h_ */

23
src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h
View File

@@ -1,17 +1,17 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -46,21 +46,6 @@
typedef NVA06F_CTRL_STOP_CHANNEL_PARAMS NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS;
/*
* NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL
*
* This command is an internal command sent from Kernel RM to Physical RM
* to perform the channel reset operations in hardware
*
* Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information.
*
*/
#define NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL (0xa06f0302) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVA06F_CTRL_INTERNAL_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVA06F_CTRL_INTERNAL_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA06F_CTRL_INTERNAL_RESET_CHANNEL_PARAMS;
/*
* NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE
*

22
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
View File

@@ -952,26 +952,4 @@ typedef struct NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS {
NvBool isBar064bit;
} NVA081_CTRL_VGPU_GET_BAR_INFO_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH
*
* This command is to get the migration bandwidth of the physical GPU.
*
* migrationBandwidth [OUT]
* This param specifies the migration bandwidth of GPU
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_REQUEST
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*/
#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH (0xa0810122) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS_MESSAGE_ID (0x22U)
typedef struct NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS {
NvU32 migrationBandwidth;
} NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS;
/* _ctrlA081vgpuconfig_h_ */

91
src/common/sdk/nvidia/inc/ctrl/ctrla16f.h
View File

@@ -1,17 +1,17 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -57,92 +57,11 @@
/*
* NVA16F_CTRL_GET_CLASS_ENGINEID
*
* Please see description of NVA06F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVA16F_CTRL_GET_CLASS_ENGINEID (0xa16f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
#define NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
typedef NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS;
/*
* NVA16F_CTRL_RESET_CHANNEL
*
* Please see description of NVA06F_CTRL_RESET_CHANNEL for more information.
*
*/
#define NVA16F_CTRL_CMD_RESET_CHANNEL (0xa16f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS;
/*
* NVA16F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE (0xa16f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS;
/*
* NVA16F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVA16F_CTRL_CMD_BIND (0xa16f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_BIND_PARAMS_MESSAGE_ID" */
#define NVA16F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U)
typedef NVA06F_CTRL_BIND_PARAMS NVA16F_CTRL_BIND_PARAMS;
/*
* NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa16f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U)
typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
/*
* NVA16F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVA16F_CTRL_CMD_EVENT_SET_TRIGGER (0xa16f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x6" */
/*
* NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO
*
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa16f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
#define NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
#define NVA16F_CTRL_CMD_EVENT_SET_TRIGGER (0xa16f0106) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x6" */
/* _ctrla16f.h_ */

91
src/common/sdk/nvidia/inc/ctrl/ctrla26f.h
View File

@@ -1,17 +1,17 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -57,92 +57,11 @@
/*
* NVA26F_CTRL_GET_CLASS_ENGINEID
*
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVA26F_CTRL_GET_CLASS_ENGINEID (0xa26f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
#define NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS;
/*
* NVA26F_CTRL_RESET_CHANNEL
*
* Please see description of NVA06F_CTRL_CMD_RESET_CHANNEL for more information.
*
*/
#define NVA26F_CTRL_CMD_RESET_CHANNEL (0xa26f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS;
/*
* NVA26F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE (0xa26f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS;
/*
* NVA26F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVA26F_CTRL_CMD_BIND (0xa26f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_BIND_PARAMS_MESSAGE_ID" */
#define NVA26F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U)
typedef NVA06F_CTRL_BIND_PARAMS NVA26F_CTRL_BIND_PARAMS;
/*
* NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa26f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U)
typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
/*
* NVA26F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVA26F_CTRL_CMD_EVENT_SET_TRIGGER (0xa26f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x6" */
/*
* NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO
*
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa26f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
#define NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
#define NVA26F_CTRL_CMD_EVENT_SET_TRIGGER (0xa26f0106) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x6" */
/* _ctrla26f.h_ */

107
src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h
View File

@@ -1,17 +1,17 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -59,94 +59,6 @@
/*
* NVB06F_CTRL_GET_CLASS_ENGINEID
*
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVB06F_CTRL_GET_CLASS_ENGINEID (0xb06f0101) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS;
/*
* NVB06F_CTRL_RESET_CHANNEL
*
* Please see description of NVA06F_CTRL_RESET_CHANNEL for more information.
*
*/
#define NVB06F_CTRL_CMD_RESET_CHANNEL (0xb06f0102) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS;
/*
* NVB06F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE (0xb06f0103) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS;
/*
* NVB06F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVB06F_CTRL_CMD_BIND (0xb06f0104) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_BIND_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U)
typedef NVA06F_CTRL_BIND_PARAMS NVB06F_CTRL_BIND_PARAMS;
/*
* NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xb06f0205) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U)
typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
/*
* NVB06F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVB06F_CTRL_CMD_EVENT_SET_TRIGGER (0xb06f0206) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
/*
* NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO
*
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xb06f0107) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
#define NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
/*
* NVB06F_CTRL_CMD_GET_ENGINE_CTX_SIZE
*
@@ -321,7 +233,7 @@ typedef struct NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS {
*
* ACQUIRE_FAIL
* A value of NV_TRUE indicates that the engine scheduler failed to
* acquire a semaphore for this channel.
* acquire a semaphore for this channel.
*
* Possible status values returned are:
* NV_OK
@@ -382,7 +294,7 @@ typedef NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_GET_CHANNEL_HW_STATE_PAR
*
* ACQUIRE_FAIL
* A value of NV_TRUE indicates that the engine scheduler failed to
* acquire a semaphore for this channel.
* acquire a semaphore for this channel.
*
* Possible status values returned are:
* NV_OK
@@ -456,4 +368,11 @@ typedef struct NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS {
/*
* NVB06F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVB06F_CTRL_CMD_EVENT_SET_TRIGGER (0xb06f0206) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
/* _ctrlb06f.h_ */

92
src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h
View File

@@ -1,17 +1,17 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -57,92 +57,10 @@
/*
* NVC06F_CTRL_GET_CLASS_ENGINEID
*
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVC06F_CTRL_GET_CLASS_ENGINEID (0xc06f0101) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
#define NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS;
/*
* NVC06F_CTRL_RESET_CHANNEL
*
* Please see description of NVA06F_CTRL_RESET_CHANNEL for more information.
*
*/
#define NVC06F_CTRL_CMD_RESET_CHANNEL (0xc06f0102) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS;
/*
* NVC06F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE (0xc06f0103) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS;
/*
* NVC06F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVC06F_CTRL_CMD_BIND (0xc06f0104) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_BIND_PARAMS_MESSAGE_ID" */
#define NVC06F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U)
typedef NVA06F_CTRL_BIND_PARAMS NVC06F_CTRL_BIND_PARAMS;
/*
* NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc06f0205) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U)
typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
/*
* NVC06F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVC06F_CTRL_CMD_EVENT_SET_TRIGGER (0xc06f0206) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
#define NVC06F_CTRL_CMD_EVENT_SET_TRIGGER (0xc06f0106) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
/*
* NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO
*
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc06f0107) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
#define NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
/* _ctrlc06f.h_ */

81
src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h
View File

@@ -1,17 +1,17 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -58,56 +58,6 @@
/*
* NVC36F_CTRL_GET_CLASS_ENGINEID
*
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVC36F_CTRL_GET_CLASS_ENGINEID (0xc36f0101) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */
#define NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS;
/*
* NVC36F_CTRL_RESET_CHANNEL
*
* Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information.
*
*/
#define NVC36F_CTRL_CMD_RESET_CHANNEL (0xc36f0102) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */
#define NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U)
typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS;
/*
* NVC36F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE (0xc36f0103) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
#define NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS;
/*
* NVC36F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVC36F_CTRL_CMD_BIND (0xc36f0104) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_BIND_PARAMS_MESSAGE_ID" */
#define NVC36F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U)
typedef NVA06F_CTRL_BIND_PARAMS NVC36F_CTRL_BIND_PARAMS;
/*
* NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
@@ -115,36 +65,15 @@ typedef NVA06F_CTRL_BIND_PARAMS NVC36F_CTRL_BIND_PARAMS;
*/
#define NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc36f0205) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */
typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC36F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NVC36F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVC36F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
#define NVC36F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
/*
* NVC36F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVC36F_CTRL_CMD_EVENT_SET_TRIGGER (0xc36f0206) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
#define NVC36F_CTRL_CMD_EVENT_SET_TRIGGER (0xc36f0206) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
/*
* NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO
*
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc36f0107) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */
#define NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
/*
* NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN
*

1
src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h
View File

@@ -39,7 +39,6 @@
#define NVC370_CTRL_RESERVED (0x00)
#define NVC370_CTRL_CHNCTL (0x01)
#define NVC370_CTRL_RG (0x02)
#define NVC370_CTRL_SEQ (0x03)
#define NVC370_CTRL_OR (0x04)
#define NVC370_CTRL_INST (0x05)
#define NVC370_CTRL_VERIF (0x06)

112
src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h
View File

@@ -1,17 +1,17 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -23,8 +23,6 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlc46f.finn
@@ -58,105 +56,3 @@
*/
#define NVC46F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL)
/*
* NVC46F_CTRL_GET_CLASS_ENGINEID
*
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVC46F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC46F_CTRL_GET_CLASS_ENGINEID_PARAMS;
/*
* NVC46F_CTRL_RESET_CHANNEL
*
* Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information.
*
*/
#define NVC46F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL)
typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC46F_CTRL_CMD_RESET_CHANNEL_PARAMS;
/*
* NVC46F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVC46F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC46F_CTRL_GPFIFO_SCHEDULE_PARAMS;
/*
* NVC46F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVC46F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND)
typedef NVA06F_CTRL_BIND_PARAMS NVC46F_CTRL_BIND_PARAMS;
/*
* NVC46F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVC46F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION)
typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC46F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NVC46F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVC46F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
#define NVC46F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
/*
* NVC46F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVC46F_CTRL_CMD_EVENT_SET_TRIGGER (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER)
/*
* NVC46F_CTRL_CMD_GET_MMU_FAULT_INFO
*
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVC46F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC46F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
/*
* NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN
*
* This command returns an opaque work submit token to the caller which
* can be used to write to doorbell register to finish submitting work.
*
* workSubmitToken The 32-bit work submit token
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN)
typedef struct NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS {
NvU32 workSubmitToken;
} NVC46F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS;
/* _ctrlc46f.h_ */

108
src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h
View File

@@ -1,17 +1,17 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -62,106 +62,6 @@
*/
#define NVC56F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL)
/*
* NVC56F_CTRL_GET_CLASS_ENGINEID
*
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVC56F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC56F_CTRL_GET_CLASS_ENGINEID_PARAMS;
/*
* NVC56F_CTRL_RESET_CHANNEL
*
* Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information.
*
*/
#define NVC56F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL)
typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC56F_CTRL_CMD_RESET_CHANNEL_PARAMS;
/*
* NVC56F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVC56F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC56F_CTRL_GPFIFO_SCHEDULE_PARAMS;
/*
* NVC56F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVC56F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND)
typedef NVA06F_CTRL_BIND_PARAMS NVC56F_CTRL_BIND_PARAMS;
/*
* NVC56F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVC56F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION)
typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC56F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NVC56F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVC56F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
#define NVC56F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
/*
* NVC56F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVC56F_CTRL_CMD_EVENT_SET_TRIGGER (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER)
/*
* NVC56F_CTRL_CMD_GET_MMU_FAULT_INFO
*
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVC56F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC56F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
/*
* NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN
*
* This command returns an opaque work submit token to the caller which
* can be used to write to doorbell register to finish submitting work.
*
* workSubmitToken The 32-bit work submit token
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN)
typedef struct NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS {
NvU32 workSubmitToken;
} NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS;
/*
* NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR
*
@@ -245,7 +145,7 @@ typedef struct NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS {
*/
#define SECURITY_POLICY_ATTACKER_ADVANTAGE_DEFAULT (60)
#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MIN (50)
#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MAX (65)
#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MAX (75)
#define NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY (0xc56f010d) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */

106
src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,8 +23,6 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlc86f.finn
@@ -61,105 +59,3 @@
*/
#define NVC86F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL)
/*
* NVC86F_CTRL_GET_CLASS_ENGINEID
*
* Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information.
*
*/
#define NVC86F_CTRL_GET_CLASS_ENGINEID (NVC36F_CTRL_GET_CLASS_ENGINEID)
typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC86F_CTRL_GET_CLASS_ENGINEID_PARAMS;
/*
* NVC86F_CTRL_RESET_CHANNEL
*
* Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information.
*
*/
#define NVC86F_CTRL_CMD_RESET_CHANNEL (NVC36F_CTRL_CMD_RESET_CHANNEL)
typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC86F_CTRL_CMD_RESET_CHANNEL_PARAMS;
/*
* NVC86F_CTRL_CMD_GPFIFO_SCHEDULE
*
* Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information.
*
*/
#define NVC86F_CTRL_CMD_GPFIFO_SCHEDULE (NVC36F_CTRL_CMD_GPFIFO_SCHEDULE)
typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC86F_CTRL_GPFIFO_SCHEDULE_PARAMS;
/*
* NVC86F_CTRL_CMD_BIND
*
* Please see description of NVA06F_CTRL_CMD_BIND for more information.
*/
#define NVC86F_CTRL_CMD_BIND (NVC36F_CTRL_CMD_BIND)
typedef NVA06F_CTRL_BIND_PARAMS NVC86F_CTRL_BIND_PARAMS;
/*
* NVC86F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVC86F_CTRL_CMD_EVENT_SET_NOTIFICATION (NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION)
typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC86F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
#define NVC86F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
/*
* NVC86F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVC86F_CTRL_CMD_EVENT_SET_TRIGGER (NVC36F_CTRL_CMD_EVENT_SET_TRIGGER)
/*
* NVC86F_CTRL_CMD_GET_MMU_FAULT_INFO
*
* Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information.
*
*/
#define NVC86F_CTRL_CMD_GET_MMU_FAULT_INFO (NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO)
typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC86F_CTRL_GET_MMU_FAULT_INFO_PARAMS;
/*
* NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN
*
* This command returns an opaque work submit token to the caller which
* can be used to write to doorbell register to finish submitting work.
*
* workSubmitToken The 32-bit work submit token
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN)
typedef struct NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS {
NvU32 workSubmitToken;
} NVC86F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS;
/* _ctrlC86F.h_ */

33
src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -387,36 +387,5 @@ typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS {
NvU32 maxCeChannels;
} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS;
/*
* NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE
* This control call returns if key rotation is enabled.
*
* hSubDevice: [IN]
* subdevice handle for the GPU queried
* keyRotationState: [OUT]
* NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_* value
*
* Possible return values:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_CLIENT
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE (0xcb33010c) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xC" */
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED 0 // key rotation is disabled
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED 1 // key rotation enabled for kernel keys
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED 2 // key rotation enabled for user keys
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED 3 // key rotation enabled for both keys
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS {
NvHandle hSubDevice;
NvU32 keyRotationState;
} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS;
/* _ctrlcb33_h_ */

32
src/common/sdk/nvidia/inc/g_finn_rm_api.h
View File

@@ -40,7 +40,7 @@
* FINN compiler version
*/
#define FINN_VERSION_MAJOR 1
#define FINN_VERSION_MINOR 21
#define FINN_VERSION_MINOR 22
#define FINN_VERSION_PATCH 0
typedef struct FINN_RM_API
@@ -318,6 +318,10 @@ typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED;
typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC;
#define FINN_NV_MEMORY_MAPPER_INTERFACE_ID (0xfe01U)
typedef FINN_RM_API FINN_NV_MEMORY_MAPPER;
#define FINN_LOCK_STRESS_OBJECT_RESERVED_INTERFACE_ID (0x10000U)
typedef FINN_RM_API FINN_LOCK_STRESS_OBJECT_RESERVED;
#define FINN_LOCK_STRESS_OBJECT_LOCK_STRESS_INTERFACE_ID (0x10001U)
typedef FINN_RM_API FINN_LOCK_STRESS_OBJECT_LOCK_STRESS;
#define FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID (0x208000U)
typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RESERVED;
@@ -442,6 +446,8 @@ typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GR;
#define FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID (0x208f0bU)
typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_MMU;
#define FINN_NV20_SUBDEVICE_DIAG_UCODE_COVERAGE_INTERFACE_ID (0x208f19U)
typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_UCODE_COVERAGE;
#define FINN_NV30_GSYNC_RESERVED_INTERFACE_ID (0x30f100U)
typedef FINN_RM_API FINN_NV30_GSYNC_RESERVED;
#define FINN_NV30_GSYNC_GSYNC_INTERFACE_ID (0x30f101U)
@@ -468,8 +474,6 @@ typedef FINN_RM_API FINN_NV50_DISPLAY_EVENT;
typedef FINN_RM_API FINN_NV50_DISPLAY_OR;
#define FINN_NV50_DISPLAY_RG_INTERFACE_ID (0x507002U)
typedef FINN_RM_API FINN_NV50_DISPLAY_RG;
#define FINN_NV50_DISPLAY_SEQ_INTERFACE_ID (0x507003U)
typedef FINN_RM_API FINN_NV50_DISPLAY_SEQ;
#define FINN_NV50_DISPLAY_SYSTEM_INTERFACE_ID (0x507007U)
typedef FINN_RM_API FINN_NV50_DISPLAY_SYSTEM;
@@ -600,15 +604,11 @@ typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_RESERVED;
typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_FB;
#define FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID (0xa16f00U)
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED;
#define FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID (0xa16f01U)
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO;
#define FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID (0xa16f02U)
#define FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID (0xa16f01U)
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT;
#define FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID (0xa26f00U)
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED;
#define FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID (0xa26f01U)
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO;
#define FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID (0xa26f02U)
#define FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID (0xa26f01U)
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT;
#define FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID (0xb06900U)
typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_RESERVED;
@@ -639,9 +639,7 @@ typedef FINN_RM_API FINN_MAXWELL_PROFILER_DEVICE_RESERVED;
typedef FINN_RM_API FINN_MAXWELL_SEC2_SEC2;
#define FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc06f00U)
typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc06f01U)
typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO;
#define FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc06f02U)
#define FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc06f01U)
typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT;
#define FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc0e000U)
typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED;
@@ -694,16 +692,10 @@ typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_RESERVED;
typedef FINN_RM_API FINN_GV100_SUBDEVICE_FB_FB;
#define FINN_TURING_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc46f00U)
typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_TURING_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc46f01U)
typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_GPFIFO;
#define FINN_TURING_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc46f02U)
typedef FINN_RM_API FINN_TURING_CHANNEL_GPFIFO_A_EVENT;
#define FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc56f00U)
typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc56f01U)
typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO;
#define FINN_AMPERE_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc56f02U)
typedef FINN_RM_API FINN_AMPERE_CHANNEL_GPFIFO_A_EVENT;
#define FINN_AMPERE_SMC_PARTITION_REF_RESERVED_INTERFACE_ID (0xc63700U)
typedef FINN_RM_API FINN_AMPERE_SMC_PARTITION_REF_RESERVED;
#define FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID (0xc63701U)
@@ -718,10 +710,6 @@ typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED;
typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER;
#define FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc86f00U)
typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc86f01U)
typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO;
#define FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc86f02U)
typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT;
#define FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED_INTERFACE_ID (0xcb3300U)
typedef FINN_RM_API FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED;

17
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 1993-2023, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 1993-2024, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -67,9 +67,9 @@
#define PMU_BREAKPOINT (61)
#define PMU_HALT_ERROR (62)
#define INFOROM_PAGE_RETIREMENT_EVENT (63)
#define INFOROM_DRAM_RETIREMENT_EVENT INFOROM_PAGE_RETIREMENT_EVENT
#define INFOROM_PAGE_RETIREMENT_FAILURE (64)
#define INFOROM_DRAM_RETIREMENT_EVENT (63)
#define INFOROM_DRAM_RETIREMENT_FAILURE (64)
#define INFOROM_DRAM_RETIREMENT_FAILURE INFOROM_PAGE_RETIREMENT_FAILURE
#define ROBUST_CHANNEL_NVENC1_ERROR (65)
#define ROBUST_CHANNEL_NVDEC0_ERROR (68)
#define ROBUST_CHANNEL_GR_CLASS_ERROR (69)
@@ -124,8 +124,15 @@
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)
#define ROBUST_CHANNEL_FAST_PATH_ERROR (141)
#define GPU_INIT_ERROR (143)
#define ROBUST_CHANNEL_KEY_ROTATION_ERROR (144)
#define ROBUST_CHANNEL_LAST_ERROR (ROBUST_CHANNEL_KEY_ROTATION_ERROR)
#define RESERVED0_ERROR (144)
#define RESERVED1_ERROR (145)
#define RESERVED2_ERROR (146)
#define RESERVED3_ERROR (147)
#define RESERVED4_ERROR (148)
#define RESERVED5_ERROR (149)
#define RESERVED6_ERROR (150)
#define ROBUST_CHANNEL_KEY_ROTATION_ERROR (151)
#define ROBUST_CHANNEL_LAST_ERROR (151)
// Indexed CE reference

7
src/common/sdk/nvidia/inc/nvimpshared.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -66,10 +66,6 @@ typedef struct DRAM_CLK_INSTANCE {
// This table is used to collect information from other modules that is needed
// for RM IMP calculations. (Used on Tegra only.)
//
#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_UNKNOWN 0U
#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_LPDDR4 1U
#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_LPDDR5 2U
typedef struct TEGRA_IMP_IMPORT_DATA {
//
// max_iso_bw_kbps stores the maximum possible ISO bandwidth available to
@@ -79,7 +75,6 @@ typedef struct TEGRA_IMP_IMPORT_DATA {
//
NvU32 max_iso_bw_kbps;
NvU32 dram_type;
// On Orin, each dram channel is 16 bits wide.
NvU32 num_dram_channels;

31
src/common/sdk/nvidia/inc/nvmisc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -494,6 +494,23 @@ do \
//
#define NV_TWO_N_MINUS_ONE(n) (((1ULL<<(n/2))<<((n+1)/2))-1)
//
// Create a 64b bitmask with n bits set
// This is the same as ((1ULL<<n) - 1), but it doesn't overflow for n=64
//
// ...
// n=-1, 0x0000000000000000
// n=0, 0x0000000000000000
// n=1, 0x0000000000000001
// ...
// n=63, 0x7FFFFFFFFFFFFFFF
// n=64, 0xFFFFFFFFFFFFFFFF
// n=65, 0xFFFFFFFFFFFFFFFF
// n=66, 0xFFFFFFFFFFFFFFFF
// ...
//
#define NV_BITMASK64(n) ((n<1) ? 0ULL : (NV_U64_MAX>>((n>64) ? 0 : (64-n))))
#define DRF_READ_1WORD_BS(d,r,f,v) \
((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS(NV##d##r##f,(v)): \
((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS(NV##d##r##f,(v)): \
@@ -574,6 +591,13 @@ nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
n32 = BIT_IDX_32(LOWESTBIT(n32));\
}
// Destructive operation on n64
#define LOWESTBITIDX_64(n64) \
{ \
n64 = BIT_IDX_64(LOWESTBIT(n64));\
}
// Destructive operation on n32
#define HIGHESTBITIDX_32(n32) \
{ \
@@ -918,6 +942,11 @@ static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address)
// Use (lo) if (b) is less than 64, and (hi) if >= 64.
//
#define NV_BIT_SET_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) |= NVBIT64(b); else (hi) |= NVBIT64( b & 0x3F ); }
//
// Clear the bit at pos (b) for U64 which is < 128.
// Use (lo) if (b) is less than 64, and (hi) if >= 64.
//
#define NV_BIT_CLEAR_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) &= ~NVBIT64(b); else (hi) &= ~NVBIT64( b & 0x3F ); }
// Get the number of elements the specified fixed-size array
#define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0])))

11
src/common/sdk/nvidia/inc/nvos.h
View File

@@ -257,6 +257,14 @@ typedef struct
#define NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED (0x00000001)
#define NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED (0x00000002)
//
// When allocating memory, register the memory descriptor to GSP-RM
// so that GSP-RM is aware of and can access it
//
#define NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM 27:27
#define NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_FALSE (0x00000000)
#define NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_TRUE (0x00000001)
//
// If _NO_MAP is requested, the RM in supported platforms will not map the
// allocated system or IO memory into user space. The client can later map
@@ -2053,6 +2061,7 @@ typedef struct
#define NVOS46_FLAGS_PAGE_SIZE_BIG (0x00000002)
#define NVOS46_FLAGS_PAGE_SIZE_BOTH (0x00000003)
#define NVOS46_FLAGS_PAGE_SIZE_HUGE (0x00000004)
#define NVOS46_FLAGS_PAGE_SIZE_512M (0x00000005)
// Some systems allow the device to use the system L3 cache when accessing the
// system memory. For example, the iGPU on T19X can allocate from the system L3
@@ -2292,6 +2301,8 @@ typedef struct
NvU8 forceMonitorState;
NvU8 bForcePerfBiosLevel;
NvU8 bIsD3HotTransition; // [OUT] To tell client if it's a D3Hot transition
NvU8 bForcePowerStateFail;
NvU32 errorStatus; // [OUT] To tell client if there is bubble up errors
NvU32 fastBootPowerState;
} NVPOWERSTATE_PARAMETERS, *PNVPOWERSTATE_PARAMETERS;

3
src/common/sdk/nvidia/inc/nvstatuscodes.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -152,6 +152,7 @@ NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manag
NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value")
NV_STATUS_CODE(NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE, 0x0000007C, "PMU RPC error due to no queue slot available for this event")
NV_STATUS_CODE(NV_ERR_KEY_ROTATION_IN_PROGRESS, 0x0000007D, "Operation not allowed as key rotation is in progress")
NV_STATUS_CODE(NV_ERR_TEST_ONLY_CODE_NOT_ENABLED, 0x0000007E, "Test-only code path not enabled")
// Warnings:
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")

6
src/common/sdk/nvidia/inc/nvtypes.h
View File

@@ -148,6 +148,12 @@ typedef signed short NvS16; /* -32768 to 32767 */
(((NvU32)(c) & 0xff) << 8) | \
(((NvU32)(d) & 0xff))))
// Macro to build an NvU64 from two DWORDS, listed from msb to lsb
#define NvU64_BUILD(a, b) \
((NvU64)( \
(((NvU64)(a) & ~0U) << 32) | \
(((NvU64)(b) & ~0U))))
#if NVTYPES_USE_STDINT
typedef uint32_t NvV32; /* "void": enumerated or multiple fields */
typedef uint32_t NvU32; /* 0 to 4294967295 */