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555.42.02

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(cherry picked from commit 5a1c474040)
This commit is contained in:
Bernhard Stoeckner
2024-05-21 15:11:46 +02:00
committed by Gaurav Juvekar
parent caa2dd11a0
commit 3084c04453
1004 changed files with 172522 additions and 150960 deletions
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17
src/nvidia/inc/kernel/gpu/conf_compute/ccsl_context.h
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@@ -27,18 +27,9 @@
#include "nvtypes.h"
#include "cc_drv.h"
struct decryptBundle_t
{
NvU8 keyIn[CC_AES_256_GCM_KEY_SIZE_BYTES];
NvU8 ivMaskIn[CC_AES_256_GCM_IV_SIZE_BYTES];
};
typedef struct decryptBundle_t *pDecryptBundle;
struct ccslContext_t
{
NvHandle hClient;
NvHandle hSubdevice;
NvHandle hChannel;
enum {CSL_MSG_CTR_32, CSL_MSG_CTR_64} msgCounterSize;
@@ -60,19 +51,11 @@ struct ccslContext_t
NvU64 keyHandleIn;
NvU64 keyHandleOut;
NvU64 keyHandleOutFallback;
NvU32 globalKeyIdIn;
NvU32 globalKeyIdOut;
void *openrmCtx;
MEMORY_DESCRIPTOR *pMemDesc;
volatile CC_CRYPTOBUNDLE_STATS *pEncStatsBuffer;
void * pConfCompute;
pDecryptBundle pDecryptBundles;
NvU32 currDecryptBundle;
};
typedef struct ccslContext_t *pCcslContext;

2
src/nvidia/inc/kernel/gpu/gpu_child_list.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

6
src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h
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@@ -35,10 +35,13 @@
#define GPU_FABRIC_PROBE_DEFAULT_PROBE_SLOWDOWN_THRESHOLD 10
typedef struct GPU_FABRIC_PROBE_INFO_KERNEL GPU_FABRIC_PROBE_INFO_KERNEL;
typedef struct GPU_FABRIC_PROBE_INFO_PHYSICAL GPU_FABRIC_PROBE_INFO_PHYSICAL;
NV_STATUS gpuFabricProbeStart(OBJGPU *pGpu,
GPU_FABRIC_PROBE_INFO_KERNEL **ppGpuFabricProbeInfoKernel);
void gpuFabricProbeStop(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
void gpuFabricProbeStopPhysical(GPU_FABRIC_PROBE_INFO_PHYSICAL *pGpuFabricProbeInfoPhysical,
NvU32 gfId);
void gpuFabricProbeSuspend(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
NV_STATUS gpuFabricProbeResume(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
@@ -52,7 +55,6 @@ NV_STATUS gpuFabricProbeGetGpaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64
NV_STATUS gpuFabricProbeGetGpaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pGpaAddressRange);
NV_STATUS gpuFabricProbeGetFlaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddress);
NV_STATUS gpuFabricProbeGetFlaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddressRange);
NV_STATUS gpuFabricProbeGetEgmGpaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pEgmGpaAddress);
NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *numProbes);
NV_STATUS gpuFabricProbeGetFabricCliqueId(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pFabricCliqueId);
NV_STATUS gpuFabricProbeGetFabricHealthStatus(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pFabricHealthStatusMask);
@@ -72,6 +74,6 @@ NV_STATUS gpuFabricProbeReceivePhysicalCallback(NvU32 gpuInstance, NvU64 *pNotif
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams);
NV_STATUS gpuFabricProbeReceiveUpdatePhysicalCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask,
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams);
NV_STATUS gpuFabricProbeGetGfid(OBJGPU *pGpu, NvU32 *pGfid);
#endif // GPU_FABRIC_PROBE_H

2
src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

2
src/nvidia/inc/kernel/gpu/gpu_timeout.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

8
src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,17 +26,11 @@
#include "core/core.h"
typedef struct {
RmPhysAddr cmdQueuePhysAddr;
} GSP_RMFS_INIT_ARGUMENTS;
typedef struct {
RmPhysAddr sharedMemPhysAddr;
NvU32 pageTableEntryCount;
NvLength cmdQueueOffset;
NvLength statQueueOffset;
NvLength locklessCmdQueueOffset;
NvLength locklessStatQueueOffset;
} MESSAGE_QUEUE_INIT_ARGUMENTS;
typedef struct {

37
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -67,6 +67,13 @@ typedef struct GspSMInfo_t
NvU32 rtCoreCount;
} GspSMInfo;
typedef struct
{
NvU32 ecidLow;
NvU32 ecidHigh;
NvU32 ecidExtended;
} EcidManufacturingInfo;
// Fetched from GSP-RM into CPU-RM
typedef struct GspStaticConfigInfo_t
{
@@ -88,10 +95,10 @@ typedef struct GspStaticConfigInfo_t
NvBool poisonFuseEnabled;
NvU64 fb_length;
NvU32 fbio_mask;
NvU64 fbio_mask;
NvU32 fb_bus_width;
NvU32 fb_ram_type;
NvU32 fbp_mask;
NvU64 fbp_mask;
NvU32 l2_cache_size;
NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL];
@@ -110,9 +117,24 @@ typedef struct GspStaticConfigInfo_t
NvBool bIsTesla;
NvBool bIsMobile;
NvBool bIsGc6Rtd3Allowed;
NvBool bIsGc8Rtd3Allowed;
NvBool bIsGcOffRtd3Allowed;
NvBool bIsGcoffLegacyAllowed;
/* "Total Board Power" refers to power requirement of GPU,
* while in GC6 state. Majority of this power will be used
* to keep V-RAM active to preserve its content.
 * Some energy maybe consumed by Always-on components on GPU chip.
* This power will be provided by 3.3v voltage rail.
*/
NvU16 RTD3GC6TotalBoardPower;
/* PERST# (i.e. PCI Express Reset) is a sideband signal
* generated by the PCIe Host to indicate the PCIe devices,
* that the power-rails and the reference-clock are stable.
* The endpoint device typically uses this signal as a global reset.
*/
NvU16 RTD3GC6PerstDelay;
NvU64 bar1PdeBase;
NvU64 bar2PdeBase;
@@ -143,6 +165,8 @@ typedef struct GspStaticConfigInfo_t
NvBool bAtsSupported;
NvBool bIsGpuUefi;
EcidManufacturingInfo ecidInfo;
} GspStaticConfigInfo;
// Pushed from CPU-RM to GSP-RM
@@ -151,6 +175,7 @@ typedef struct GspSystemInfo
NvU64 gpuPhysAddr;
NvU64 gpuPhysFbAddr;
NvU64 gpuPhysInstAddr;
NvU64 gpuPhysIoAddr;
NvU64 nvDomainBusDeviceFunc;
NvU64 simAccessBufPhysAddr;
NvU64 notifyOpSharedSurfacePhysAddr;
@@ -159,6 +184,9 @@ typedef struct GspSystemInfo
NvU64 maxUserVa;
NvU32 pciConfigMirrorBase;
NvU32 pciConfigMirrorSize;
NvU32 PCIDeviceID;
NvU32 PCISubDeviceID;
NvU32 PCIRevisionID;
NvU8 oorArch;
NvU64 clPdbProperties;
NvU32 Chipset;
@@ -179,9 +207,10 @@ typedef struct GspSystemInfo
NvBool bIsPassthru;
NvU64 sysTimerOffsetNs;
GSP_VF_INFO gspVFInfo;
NvBool bIsPrimary;
NvBool isGridBuild;
NvU32 gridBuildCsp;
NvBool bTdrEventSupported;
NvBool bPreserveVideoMemoryAllocations;
} GspSystemInfo;

5
src/nvidia/inc/kernel/gpu/gsp/gsp_trace_rats_macro.h
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@@ -35,7 +35,10 @@
#define GSP_TRACING_RATS_ENABLED 0
#define GSP_TRACE_RATS_ADD_RECORD(recordIdentifier, pGpu, info) (void) 0
#define KERNEL_GSP_TRACING_RATS_ENABLED 0
#include "kernel/gpu/gsp/kernel_gsp_trace_rats.h"
#include "class/cl90cdtrace.h"
#define KERNEL_GSP_TRACING_RATS_ENABLED 1
#ifndef GET_RATS_TIMESTAMP_NS
#define GET_RATS_TIMESTAMP_NS() NV_ASSERT(0)

59
src/nvidia/inc/kernel/gpu/gsp/kernel_gsp_trace_rats.h Normal file
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@@ -0,0 +1,59 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef KERNEL_RATS_GSP_TRACE_H
#define KERNEL_RATS_GSP_TRACE_H
#include "core/core.h"
#include "containers/multimap.h"
#include "class/cl90cdtrace.h"
#include "rmapi/event_buffer.h"
typedef struct
{
EventBuffer *pEventBuffer;
NvHandle hClient;
NvHandle hNotifier;
NvHandle hEventBuffer;
NvU64 pUserInfo;
} NV_EVENT_BUFFER_BIND_POINT_GSP_TRACE;
MAKE_MULTIMAP(GspTraceEventBufferBindMultiMap, NV_EVENT_BUFFER_BIND_POINT_GSP_TRACE);
void gspTraceNotifyAllConsumers(OBJGPU *pGpu, void *pArgs);
void gspTraceEventBufferLogRecord(OBJGPU *pGpu, NV_RATS_GSP_TRACE_RECORD *intrTraceRecord);
NV_STATUS gspTraceAddBindpoint(OBJGPU *pGpu,
RsClient *pClient,
RsResourceRef *pEventBufferRef,
NvHandle hNotifier,
NvU64 tracepointMask,
NvU32 gspLoggingBufferSize,
NvU32 gspLoggingBufferWatermark);
void gspTraceRemoveBindpoint(OBJGPU *pGpu, NvU64 uid, NV_EVENT_BUFFER_BIND_POINT_GSP_TRACE* pBind);
void gspTraceRemoveAllBindpoints(EventBuffer *pEventBuffer);
#endif

3
src/nvidia/inc/kernel/gpu/gsp/message_queue.h
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@@ -29,8 +29,7 @@
// Used for indexing into the MESSAGE_QUEUE_COLLECTION array.
#define RPC_TASK_RM_QUEUE_IDX 0
#define RPC_TASK_ISR_QUEUE_IDX 1
#define RPC_QUEUE_COUNT 2
#define RPC_QUEUE_COUNT 1
typedef struct _message_queue_info MESSAGE_QUEUE_INFO;
typedef struct MESSAGE_QUEUE_COLLECTION MESSAGE_QUEUE_COLLECTION;

8
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
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@@ -152,8 +152,12 @@
#define MC_ENGINE_IDX_PXUC 168
#define MC_ENGINE_IDX_SYSLTC 169
#define MC_ENGINE_IDX_LRCC 170
#define MC_ENGINE_IDX_RESERVED171 171
#define MC_ENGINE_IDX_RESERVED172 172
#define MC_ENGINE_IDX_RESERVED173 173
#define MC_ENGINE_IDX_RESERVED174 174
// This must be kept as the max bit if we need to add more engines
#define MC_ENGINE_IDX_MAX 171
#define MC_ENGINE_IDX_MAX 175
// Index GR reference
#define MC_ENGINE_IDX_GRn(x) (MC_ENGINE_IDX_GR0 + (x))
@@ -178,7 +182,7 @@
((MC_ENGINE_IDX_CE(0) <= (x)) && ((x) <= MC_ENGINE_IDX_CE_MAX))
// Index OFA reference
#define MC_ENGINE_IDX_OFA(x) (MC_ENGINE_IDX_OFA0 + (x))
#define MC_ENGINE_IDX_OFA(x) (MC_ENGINE_IDX_OFA0 + (x))
MAKE_BITVECTOR(MC_ENGINE_BITVECTOR, MC_ENGINE_IDX_MAX);
typedef MC_ENGINE_BITVECTOR *PMC_ENGINE_BITVECTOR;

28
src/nvidia/inc/kernel/gpu/kern_gpu_power.h
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@@ -42,35 +42,15 @@ typedef enum
typedef struct
{
NvU32 refCount;
NvU16 GC6PerstDelay; // waiting time for Upstream Port of GPU,
// before asserting perst# signal,
// during RTD3/GC6 Entry.
NvU16 GC6TotalBoardPower; // Power required by GPU to sustain RTD3/GC6.
GPU_GC6_STATE currentState;
NvU32 executedStepMask; // step mask executed during entry sequence
NvU32 stepMask[NV2080_CTRL_GC6_FLAVOR_ID_MAX]; // step mask cache
} _GPU_GC6_STATE;
// GPU event mask operation
#define GC6_REFCOUNT_MASK_SET(pGpu, refCountBit) \
do \
{ \
if (pGpu != NULL) \
{ \
((pGpu->gc6State.refCountMask) |= (NVBIT(refCountBit))); \
} \
} while(0)
#define GC6_REFCOUNT_MASK_CLEAR(pGpu, refCountBit) \
do \
{ \
if (pGpu != NULL) \
{ \
((pGpu->gc6State.refCountMask) &= ~(NVBIT(refCountBit))); \
} \
} while(0)
#define GC6_REFCOUNT_MASK_GET_FROM_EVENT(event) ((event / 2))
// GC6 related defines
#define GC6_FB_CLAMP_TIMEOUT_MS 10
// Macros for GPU_GC6_STATE
#define IS_GPU_GC6_STATE_POWERED_ON(obj) (obj->gc6State.currentState == GPU_GC6_STATE_POWERED_ON)
#define IS_GPU_GC6_STATE_EXITED(obj) (obj->gc6State.currentState == GPU_GC6_STATE_EXITED)

4
src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils_sizes.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,7 +33,7 @@
#define CE_MAX_BYTES_PER_LINE 0xffffffffULL
#define CE_METHOD_SIZE_PER_BLOCK 0x64
#define FAST_SCRUBBER_METHOD_SIZE_PER_BLOCK 0x94
#define FAST_SCRUBBER_METHOD_SIZE_PER_BLOCK 0x78
// number of bytes per sec2 method-stream (including host methods)
#define SEC2_METHOD_SIZE_PER_BLOCK 0x94

6
src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h
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@@ -130,12 +130,6 @@ typedef struct
NV_ADDRESS_SPACE srcAddressSpace;
NvU32 dstCpuCacheAttrib;
NvU32 srcCpuCacheAttrib;
NvBool bSecureCopy; // The copy encrypts/decrypts protected memory
NvBool bEncrypt; // encrypt/decrypt
NvU64 authTagAddr;
NvU64 encryptIvAddr;
} CHANNEL_PB_INFO;
NV_STATUS channelSetupIDs(OBJCHANNEL *pChannel, OBJGPU *pGpu, NvBool bUseVasForCeCopy, NvBool bMIGInUse);

10
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h
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@@ -35,11 +35,17 @@
#endif
#if defined(SRT_BUILD)
#define RMCFG_MODULE_x 1
#define RMCFG_FEATURE_x 1
#else
#include "rmconfig.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
// Default page size 64KB
#define PMA_GRANULARITY 0x10000
#define PMA_PAGE_SHIFT 16
@@ -71,6 +77,7 @@ typedef NvU32 PMA_PAGESTATUS;
#define ATTRIB_PERSISTENT NVBIT(MAP_IDX_PERSISTENT)
#define ATTRIB_NUMA_REUSE NVBIT(MAP_IDX_NUMA_REUSE)
#define ATTRIB_BLACKLIST NVBIT(MAP_IDX_BLACKLIST)
#define ATTRIB_MASK (ATTRIB_EVICTING | ATTRIB_SCRUBBING \
| ATTRIB_PERSISTENT | ATTRIB_NUMA_REUSE \
| ATTRIB_BLACKLIST)
@@ -79,6 +86,7 @@ typedef NvU32 PMA_PAGESTATUS;
#define PMA_STATE_BITS_PER_PAGE 2 // Alloc & pinned state
#define PMA_ATTRIB_BITS_PER_PAGE 5 // Persistence, Scrubbing, Evicting, Reuse & Blacklisting attributes
#define PMA_BITS_PER_PAGE (PMA_STATE_BITS_PER_PAGE + PMA_ATTRIB_BITS_PER_PAGE)
//

1
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h
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@@ -46,6 +46,7 @@
#if defined(SRT_BUILD)
#define RMCFG_MODULE_x 1
#define RMCFG_FEATURE_x 1
#else
#include "rmconfig.h"
#endif

3
src/nvidia/inc/kernel/gpu/spdm/libspdm_includes.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,7 +34,6 @@
#include "internal/libspdm_common_lib.h"
#include "internal/libspdm_secured_message_lib.h"
#include "library/spdm_requester_lib.h"
#include "nvspdm_cryptlib_extensions.h"
/* ------------------------ Macros and Defines ----------------------------- */
//

4
src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h
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@@ -33,3 +33,7 @@
RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL))
NV_STATUS subdeviceCtrlCmdCcuSetStreamState(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS *pParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO,
RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL))
NV_STATUS subdeviceCtrlCmdCcuGetSampleInfo(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS *pParams);

2
src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_rc.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a