mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-01-27 03:29:47 +00:00
535.86.05
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@@ -26,6 +26,7 @@
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#include "uvm_conf_computing.h"
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#include "uvm_kvmalloc.h"
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#include "uvm_gpu.h"
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#include "uvm_hal.h"
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#include "uvm_mem.h"
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#include "uvm_processors.h"
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#include "uvm_tracker.h"
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@@ -60,8 +61,7 @@ NV_STATUS uvm_conf_computing_init_parent_gpu(const uvm_parent_gpu_t *parent)
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uvm_assert_mutex_locked(&g_uvm_global.global_lock);
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// TODO: Bug 2844714.
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// Since we have no routine to traverse parent gpus,
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// TODO: Bug 2844714: since we have no routine to traverse parent GPUs,
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// find first child GPU and get its parent.
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first = uvm_global_processor_mask_find_first_gpu(&g_uvm_global.retained_gpus);
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if (!first)
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@@ -448,3 +448,51 @@ NV_STATUS uvm_conf_computing_cpu_decrypt(uvm_channel_t *channel,
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return status;
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}
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NV_STATUS uvm_conf_computing_fault_decrypt(uvm_parent_gpu_t *parent_gpu,
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void *dst_plain,
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const void *src_cipher,
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const void *auth_tag_buffer,
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NvU8 valid)
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{
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NV_STATUS status;
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// There is no dedicated lock for the CSL context associated with replayable
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// faults. The mutual exclusion required by the RM CSL API is enforced by
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// relying on the GPU replayable service lock (ISR lock), since fault
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// decryption is invoked as part of fault servicing.
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UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.replayable_faults.service_lock));
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UVM_ASSERT(!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu));
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status = nvUvmInterfaceCslDecrypt(&parent_gpu->fault_buffer_info.rm_info.replayable.cslCtx,
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parent_gpu->fault_buffer_hal->entry_size(parent_gpu),
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(const NvU8 *) src_cipher,
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NULL,
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(NvU8 *) dst_plain,
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&valid,
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sizeof(valid),
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(const NvU8 *) auth_tag_buffer);
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if (status != NV_OK)
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UVM_ERR_PRINT("nvUvmInterfaceCslDecrypt() failed: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name);
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return status;
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}
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void uvm_conf_computing_fault_increment_decrypt_iv(uvm_parent_gpu_t *parent_gpu, NvU64 increment)
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{
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NV_STATUS status;
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// See comment in uvm_conf_computing_fault_decrypt
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UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.replayable_faults.service_lock));
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UVM_ASSERT(!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu));
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status = nvUvmInterfaceCslIncrementIv(&parent_gpu->fault_buffer_info.rm_info.replayable.cslCtx,
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UVM_CSL_OPERATION_DECRYPT,
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increment,
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NULL);
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UVM_ASSERT(status == NV_OK);
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}
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