mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-01-31 13:39:47 +00:00
535.86.05
This commit is contained in:
@@ -7756,31 +7756,35 @@ nvswitch_service_nvldl_fatal_link_ls10
|
||||
bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1);
|
||||
if (nvswitch_test_flags(pending, bit))
|
||||
{
|
||||
dlDeferredIntrLinkMask |= bit;
|
||||
nvswitch_clear_flags(&unhandled, bit);
|
||||
{
|
||||
dlDeferredIntrLinkMask |= bit;
|
||||
|
||||
//
|
||||
// Since reset and drain will reset the link, including clearing
|
||||
// pending interrupts, skip the clear write below. There are cases
|
||||
// where link clocks will not be on after reset and drain so there
|
||||
// maybe PRI errors on writing to the register
|
||||
//
|
||||
bRequireResetAndDrain = NV_TRUE;
|
||||
//
|
||||
// Since reset and drain will reset the link, including clearing
|
||||
// pending interrupts, skip the clear write below. There are cases
|
||||
// where link clocks will not be on after reset and drain so there
|
||||
// maybe PRI errors on writing to the register
|
||||
//
|
||||
bRequireResetAndDrain = NV_TRUE;
|
||||
}
|
||||
nvswitch_clear_flags(&unhandled, bit);
|
||||
}
|
||||
|
||||
bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1);
|
||||
if (nvswitch_test_flags(pending, bit))
|
||||
{
|
||||
dlDeferredIntrLinkMask |= bit;
|
||||
nvswitch_clear_flags(&unhandled, bit);
|
||||
{
|
||||
dlDeferredIntrLinkMask |= bit;
|
||||
|
||||
//
|
||||
// Since reset and drain will reset the link, including clearing
|
||||
// pending interrupts, skip the clear write below. There are cases
|
||||
// where link clocks will not be on after reset and drain so there
|
||||
// maybe PRI errors on writing to the register
|
||||
//
|
||||
bRequireResetAndDrain = NV_TRUE;
|
||||
//
|
||||
// Since reset and drain will reset the link, including clearing
|
||||
// pending interrupts, skip the clear write below. There are cases
|
||||
// where link clocks will not be on after reset and drain so there
|
||||
// maybe PRI errors on writing to the register
|
||||
//
|
||||
bRequireResetAndDrain = NV_TRUE;
|
||||
}
|
||||
nvswitch_clear_flags(&unhandled, bit);
|
||||
}
|
||||
|
||||
if (bRequireResetAndDrain)
|
||||
|
||||
@@ -223,10 +223,12 @@ _nvswitch_is_soe_attached_ls10
|
||||
)
|
||||
{
|
||||
NvU32 val;
|
||||
NvBool bSoeAttached;
|
||||
|
||||
val = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _SOE_ATTACH_DETACH);
|
||||
bSoeAttached = FLD_TEST_DRF(_NVLSAW, _SOE_ATTACH_DETACH, _STATUS, _ATTACHED, val);
|
||||
|
||||
return FLD_TEST_DRF(_NVLSAW, _SOE_ATTACH_DETACH, _STATUS, _ATTACHED, val);
|
||||
return bSoeAttached;
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -1338,4 +1340,3 @@ soeSetupHal_LS10
|
||||
pHal->waitForInitAck = _soeWaitForInitAck_LS10;
|
||||
pHal->i2cAccess = _soeI2CAccess_LS10;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user