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535.86.05

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This commit is contained in:
Bernhard Stoeckner
2023-07-18 15:54:53 +02:00
parent 22a077c4fe
commit 337e28efda
264 changed files with 67251 additions and 107479 deletions
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10
src/common/sdk/nvidia/inc/alloc/alloc_channel.h
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@@ -41,7 +41,6 @@ typedef struct NV_MEMORY_DESC_PARAMS {
NvU32 cacheAttrib;
} NV_MEMORY_DESC_PARAMS;
/*
* NV_CHANNEL_ALLOC_PARAMS.flags values.
*
@@ -289,6 +288,8 @@ typedef struct NV_MEMORY_DESC_PARAMS {
#define CC_CHAN_ALLOC_IV_SIZE_DWORD 3U
#define CC_CHAN_ALLOC_NONCE_SIZE_DWORD 8U
#define NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID (0x906fU)
@@ -330,6 +331,13 @@ typedef struct NV_CHANNEL_ALLOC_PARAMS {
NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved
NvU32 ProcessID; // reserved
NvU32 SubProcessID; // reserved
// IV used for CPU-side encryption / GPU-side decryption.
NvU32 encryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved
// IV used for CPU-side decryption / GPU-side encryption.
NvU32 decryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved
// Nonce used CPU-side signing / GPU-side signature verification.
NvU32 hmacNonce[CC_CHAN_ALLOC_NONCE_SIZE_DWORD]; // reserved
} NV_CHANNEL_ALLOC_PARAMS;
typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS;

20
src/common/sdk/nvidia/inc/cc_drv.h
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@@ -36,20 +36,16 @@
#include "nvcfg_sdk.h"
// CLASS NV_CONF_COMPUTE
#define CC_AES_256_GCM_IV_SIZE_BYTES (0xcU) /* finn: Evaluated from "(96 / 8)" */
#define CC_AES_256_GCM_IV_SIZE_DWORD (0x3U) /* finn: Evaluated from "(CC_AES_256_GCM_IV_SIZE_BYTES / 4)" */
#define CC_AES_256_GCM_KEY_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */
#define CC_AES_256_GCM_KEY_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_AES_256_GCM_KEY_SIZE_BYTES / 4)" */
#define CC_AES_256_GCM_IV_SIZE_BYTES (0xcU) /* finn: Evaluated from "(96 / 8)" */
#define CC_AES_256_GCM_IV_SIZE_DWORD (0x3U) /* finn: Evaluated from "(CC_AES_256_GCM_IV_SIZE_BYTES / 4)" */
#define CC_AES_256_GCM_KEY_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */
#define CC_AES_256_GCM_KEY_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_AES_256_GCM_KEY_SIZE_BYTES / 4)" */
#define CC_HMAC_NONCE_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */
#define CC_HMAC_NONCE_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_HMAC_NONCE_SIZE_BYTES / 4)" */
#define CC_HMAC_KEY_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */
#define CC_HMAC_KEY_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_HMAC_KEY_SIZE_BYTES / 4)" */
#define CC_HMAC_NONCE_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */
#define CC_HMAC_NONCE_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_HMAC_NONCE_SIZE_BYTES / 4)" */
#define CC_HMAC_KEY_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */
#define CC_HMAC_KEY_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_HMAC_KEY_SIZE_BYTES / 4)" */
#define APM_AES_128_CTR_IV_SIZE_BYTES (0xcU) /* finn: Evaluated from "(96 / 8)" */
#define APM_AES_128_CTR_IV_SIZE_DWORD (0x3U) /* finn: Evaluated from "(APM_AES_128_CTR_IV_SIZE_BYTES / 4)" */
#define APM_AES_128_CTR_KEY_SIZE_BYTES (0x10U) /* finn: Evaluated from "(128 / 8)" */
#define APM_AES_128_CTR_KEY_SIZE_DWORD (0x4U) /* finn: Evaluated from "(APM_AES_128_CTR_KEY_SIZE_BYTES / 4)" */
// Type is shared between CC control calls and RMKeyStore
typedef enum ROTATE_IV_TYPE {

3
src/common/sdk/nvidia/inc/class/cl2080_notification.h
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@@ -203,7 +203,8 @@ extern "C" {
#define NV2080_NOTIFIERS_NVPCF_EVENTS (177)
#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (178)
#define NV2080_NOTIFIERS_VRR_SET_TIMEOUT (179)
#define NV2080_NOTIFIERS_MAXCOUNT (180)
#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (180)
#define NV2080_NOTIFIERS_MAXCOUNT (181)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))

7
src/common/sdk/nvidia/inc/class/clcba2.h
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@@ -112,6 +112,9 @@ typedef volatile struct _clcba2_tag0 {
#define NVCBA2_EXECUTE_TIMESTAMP 5:5
#define NVCBA2_EXECUTE_TIMESTAMP_DISABLE (0x00000000)
#define NVCBA2_EXECUTE_TIMESTAMP_ENABLE (0x00000001)
#define NVCBA2_EXECUTE_PHYSICAL_SCRUBBER 6:6
#define NVCBA2_EXECUTE_PHYSICAL_SCRUBBER_DISABLE (0x00000000)
#define NVCBA2_EXECUTE_PHYSICAL_SCRUBBER_ENABLE (0x00000001)
// Class definitions
#define NVCBA2_DECRYPT_COPY_SIZE_MAX_BYTES (2*1024*1024)
@@ -133,6 +136,10 @@ typedef volatile struct _clcba2_tag0 {
#define NVCBA2_ERROR_OS_APPLICATION (0x0000000D)
#define NVCBA2_ERROR_INVALID_CTXSW_REQUEST (0x0000000E)
#define NVCBA2_ERROR_BUFFER_OVERFLOW (0x0000000F)
#define NVCBA2_ERROR_SCRUBBER_FAILURE (0x00000019)
#define NVCBA2_ERROR_SCRUBBER_INVALD_ADDRESS (0x0000001a)
#define NVCBA2_ERROR_SCRUBBER_INSUFFICIENT_PERMISSIONS (0x0000001b)
#define NVCBA2_ERROR_SCRUBBER_MUTEX_ACQUIRE_FAILURE (0x0000001c)
#ifdef __cplusplus
}; /* extern "C" */

77
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
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@@ -3433,7 +3433,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
* NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS
*
* This command is an internal command sent from Kernel RM to Physical RM
* to disable the GPU system memory access after quiescing the GPU or
* to disable the GPU system memory access after quiescing the GPU or
* re-enable sysmem access.
*
* bDisable [IN]
@@ -3642,6 +3642,72 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS {
NvBool bIsPcieTrusted;
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL
*
* This command is used to trigger the initialization / suspension of encrypted RPCs for Confidential Compute.
* bEncryptionControl : [IN]
* NV_TRUE indicates initialization.
* NV_FALSE indicates suspension.
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL (0x208001b2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS_MESSAGE_ID (0xB2U)
typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS {
NvBool bEncryptionControl;
} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS
*
* This command is an internal command sent from Kernel RM to Physical RM
* to derive SWL keys and IV masks for a given engine
*
* engineId: [IN]
* NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived
* ivMaskSet: [OUT]
* Set of IV masks for given engine
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS (0x20800ae1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE 3U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL 0U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER 1U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 2U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT 6U
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK {
NvU32 ivMask[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE];
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK;
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID (0xE1U)
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS {
NvU32 engineId;
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT];
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS
*
* This command is an internal command sent from Kernel RM to Physical RM
* to derive LCE keys and IV masks for a given engine
*
* engineId: [IN]
* NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived
* ivMaskSet: [OUT]
* Set of IV masks for given engine
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS (0x20800ae2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID (0xE2U)
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS {
NvU32 engineId;
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT];
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS;
/*
@@ -3675,7 +3741,7 @@ typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO {
NV_DECLARE_ALIGNED(NvU64 size, 8);
/*!
* Offset in bytes into the surface where read/write must happen
* Offset in bytes into the surface where read/write must happen
*/
NV_DECLARE_ALIGNED(NvU64 offset, 8);
@@ -3690,6 +3756,8 @@ typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO {
NvU32 cpuCacheAttrib;
} NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO;
#define CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES (0x10U) /* finn: Evaluated from "(128 / 8)" */
#define NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID (0xFAU)
typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS {
@@ -3699,6 +3767,11 @@ typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS {
*/
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO src, 8);
/*!
* Authentication tag if data is encrypted
*/
NvU8 authTag[CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES];
/*!
* Destination surface info
*/

29
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h
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@@ -58,14 +58,9 @@
typedef struct RM_GSP_SPDM_CC_INIT_CTX {
NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc
NvU8 dmaIdx; // To indicate DMA engine which DMA idx is needed
NvU64_ALIGN32 dmaAddr; // The address RM allocate in SYS memory or FB memory.
NvU32 addrSpace; // The memory type allocated by RM (SYS or FB ...)
NvU32 regionId; // If memory is in WPR, this is a WPR id.
NvU32 rmBufferSizeInByte; // The memort size allocated by RM(exclude NV_SPDM_DESC_HEADER)
} RM_GSP_SPDM_CC_INIT_CTX;
@@ -119,10 +114,6 @@ typedef struct RM_GSP_SPDM_CC_CTRL_CTX {
NvU32 endpointId; // To indicate SPDM endpoint Id
NvU32 ctrlCode; // control code
NvU32 ctrlParam; // Associated with ctrlCode
} RM_GSP_SPDM_CC_CTRL_CTX;
typedef struct RM_GSP_SPDM_CC_CTRL_CTX *PRM_GSP_SPDM_CC_CTRL_CTX;
@@ -214,24 +205,26 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
* SPDM message structure.
*/
typedef struct RM_GSP_SPDM_MSG {
NvU8 msgType;
NvU8 msgType;
NvU32 version;
NvU32 version;
NvU32 guestId;
NvU32 guestId;
NvU32 endpointId;
NvU32 endpointId;
// status returned from GSP message infrastructure.
NvU32 status;
NvU32 status;
NvU32 rsvd1;
NvU32 rsvd1;
NvU32 rsvd2;
NvU32 rsvd2;
NvU32 rsvd3;
NvU32 rsvd3;
NvU32 rsvd4;
NvU32 rsvd4;
NvBool rsvd5;
} RM_GSP_SPDM_MSG;
typedef struct RM_GSP_SPDM_MSG *PRM_GSP_SPDM_MSG;

26
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
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@@ -721,4 +721,30 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS {
NvU32 fractionalMultiVgpu;
} NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_VALIDATE_SWIZZID
*
* This command is used to vallidate input swizzid from RM
*
* vgpuTypeId [IN]
* This param specifies the Type ID for VGPU profile
*
* swizzId [IN]
* This param specifies the GPU Instance ID or Swizz ID
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_REQUEST
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*/
#define NVA081_CTRL_CMD_VGPU_CONFIG_VALIDATE_SWIZZID (0xa081011a) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS_MESSAGE_ID (0x1aU)
typedef struct NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS {
NvU32 vgpuTypeId;
NvU32 swizzId;
} NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS;
/* _ctrlA081vgpuconfig_h_ */