mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-02 14:37:43 +00:00
535.86.05
This commit is contained in:
Bernhard Stoeckner
@@ -3433,7 +3433,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
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* NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS
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*
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* This command is an internal command sent from Kernel RM to Physical RM
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* to disable the GPU system memory access after quiescing the GPU or
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* to disable the GPU system memory access after quiescing the GPU or
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* re-enable sysmem access.
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*
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* bDisable [IN]
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@@ -3642,6 +3642,72 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS {
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NvBool bIsPcieTrusted;
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} NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS;
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/*!
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* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL
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*
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* This command is used to trigger the initialization / suspension of encrypted RPCs for Confidential Compute.
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* bEncryptionControl : [IN]
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* NV_TRUE indicates initialization.
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* NV_FALSE indicates suspension.
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*/
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#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL (0x208001b2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS_MESSAGE_ID (0xB2U)
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typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS {
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NvBool bEncryptionControl;
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} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS;
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/*!
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* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS
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*
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* This command is an internal command sent from Kernel RM to Physical RM
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* to derive SWL keys and IV masks for a given engine
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*
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* engineId: [IN]
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* NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived
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* ivMaskSet: [OUT]
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* Set of IV masks for given engine
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*/
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#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS (0x20800ae1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE 3U
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#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL 0U
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#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER 1U
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#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 2U
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#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT 6U
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typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK {
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NvU32 ivMask[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE];
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} NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK;
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#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID (0xE1U)
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typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS {
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NvU32 engineId;
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NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT];
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} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS;
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/*!
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* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS
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*
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* This command is an internal command sent from Kernel RM to Physical RM
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* to derive LCE keys and IV masks for a given engine
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*
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* engineId: [IN]
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* NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived
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* ivMaskSet: [OUT]
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* Set of IV masks for given engine
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*/
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#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS (0x20800ae2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID (0xE2U)
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typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS {
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NvU32 engineId;
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NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT];
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} NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS;
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/*
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@@ -3675,7 +3741,7 @@ typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO {
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NV_DECLARE_ALIGNED(NvU64 size, 8);
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/*!
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* Offset in bytes into the surface where read/write must happen
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* Offset in bytes into the surface where read/write must happen
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*/
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NV_DECLARE_ALIGNED(NvU64 offset, 8);
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@@ -3690,6 +3756,8 @@ typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO {
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NvU32 cpuCacheAttrib;
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} NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO;
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#define CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES (0x10U) /* finn: Evaluated from "(128 / 8)" */
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#define NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID (0xFAU)
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typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS {
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@@ -3699,6 +3767,11 @@ typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS {
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*/
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NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO src, 8);
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/*!
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* Authentication tag if data is encrypted
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*/
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NvU8 authTag[CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES];
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/*!
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* Destination surface info
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*/
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@@ -58,14 +58,9 @@
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typedef struct RM_GSP_SPDM_CC_INIT_CTX {
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NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc
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NvU8 dmaIdx; // To indicate DMA engine which DMA idx is needed
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NvU64_ALIGN32 dmaAddr; // The address RM allocate in SYS memory or FB memory.
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NvU32 addrSpace; // The memory type allocated by RM (SYS or FB ...)
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NvU32 regionId; // If memory is in WPR, this is a WPR id.
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NvU32 rmBufferSizeInByte; // The memort size allocated by RM(exclude NV_SPDM_DESC_HEADER)
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} RM_GSP_SPDM_CC_INIT_CTX;
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@@ -119,10 +114,6 @@ typedef struct RM_GSP_SPDM_CC_CTRL_CTX {
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NvU32 endpointId; // To indicate SPDM endpoint Id
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NvU32 ctrlCode; // control code
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NvU32 ctrlParam; // Associated with ctrlCode
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} RM_GSP_SPDM_CC_CTRL_CTX;
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typedef struct RM_GSP_SPDM_CC_CTRL_CTX *PRM_GSP_SPDM_CC_CTRL_CTX;
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@@ -214,24 +205,26 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
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* SPDM message structure.
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*/
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typedef struct RM_GSP_SPDM_MSG {
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NvU8 msgType;
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NvU8 msgType;
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NvU32 version;
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NvU32 version;
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NvU32 guestId;
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NvU32 guestId;
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NvU32 endpointId;
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NvU32 endpointId;
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// status returned from GSP message infrastructure.
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NvU32 status;
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NvU32 status;
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NvU32 rsvd1;
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NvU32 rsvd1;
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NvU32 rsvd2;
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NvU32 rsvd2;
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NvU32 rsvd3;
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NvU32 rsvd3;
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NvU32 rsvd4;
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NvU32 rsvd4;
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NvBool rsvd5;
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} RM_GSP_SPDM_MSG;
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typedef struct RM_GSP_SPDM_MSG *PRM_GSP_SPDM_MSG;
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@@ -721,4 +721,30 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS {
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NvU32 fractionalMultiVgpu;
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} NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS;
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/*
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* NVA081_CTRL_CMD_VGPU_CONFIG_VALIDATE_SWIZZID
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*
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* This command is used to vallidate input swizzid from RM
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*
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* vgpuTypeId [IN]
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* This param specifies the Type ID for VGPU profile
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*
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* swizzId [IN]
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* This param specifies the GPU Instance ID or Swizz ID
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_INVALID_REQUEST
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* NV_ERR_INVALID_STATE
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NVA081_CTRL_CMD_VGPU_CONFIG_VALIDATE_SWIZZID (0xa081011a) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS_MESSAGE_ID" */
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#define NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS_MESSAGE_ID (0x1aU)
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typedef struct NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS {
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NvU32 vgpuTypeId;
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NvU32 swizzId;
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} NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS;
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/* _ctrlA081vgpuconfig_h_ */
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