535.86.05

src/nvidia/inc/kernel/core/printf.h

@@ -172,7 +172,7 @@ void osFlushLog(void);
 
 #include "utils/nvprintf.h"
 
-#define MAX_ERROR_STRING 256
+#define MAX_ERROR_STRING 512
 #ifndef NVPORT_CHECK_PRINTF_ARGUMENTS
 #define NVPORT_CHECK_PRINTF_ARGUMENTS(x,c)
 #endif

src/nvidia/inc/kernel/gpu/conf_compute/ccsl_context.h

@@ -0,0 +1,61 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef CCSL_CONTEXT_H
+#define CCSL_CONTEXT_H
+
+#include "nvtypes.h"
+#include "cc_drv.h"
+
+struct ccslContext_t
+{
+    NvHandle hClient;
+    NvHandle hChannel;
+
+    enum {CSL_MSG_CTR_32, CSL_MSG_CTR_64} msgCounterSize;
+
+    NvU8 keyIn[CC_AES_256_GCM_KEY_SIZE_BYTES];
+    union
+    {
+        struct
+        {
+            NvU8 ivIn[CC_AES_256_GCM_IV_SIZE_BYTES];
+            NvU8 ivMaskIn[CC_AES_256_GCM_IV_SIZE_BYTES];
+        };
+        NvU8 nonce[CC_HMAC_NONCE_SIZE_BYTES];
+    };
+
+    NvU8 keyOut[CC_AES_256_GCM_KEY_SIZE_BYTES];
+    NvU8 ivOut[CC_AES_256_GCM_IV_SIZE_BYTES];
+    NvU8 ivMaskOut[CC_AES_256_GCM_IV_SIZE_BYTES];
+
+    NvU64 keyHandleIn;
+    NvU64 keyHandleOut;
+
+    void *openrmCtx;
+};
+
+typedef struct ccslContext_t *pCcslContext;
+typedef struct ccslContext_t CCSL_CONTEXT;
+
+#endif // CCSL_CONTEXT_H

src/nvidia/inc/kernel/gpu/gsp/message_queue.h

@@ -40,6 +40,6 @@ NV_STATUS GspMsgQueuesInit(OBJGPU *pGpu, MESSAGE_QUEUE_COLLECTION **ppMQCollecti
 void      GspMsgQueuesCleanup(MESSAGE_QUEUE_COLLECTION **ppMQCollection);
 NV_STATUS GspStatusQueueInit(OBJGPU *pGpu, MESSAGE_QUEUE_INFO **ppMQI);
 NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu);
-NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI);
+NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu);
 
 #endif // _MESSAGE_QUEUE_H_

src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h

@@ -42,9 +42,12 @@
 
 typedef struct GSP_MSG_QUEUE_ELEMENT
 {
-    NvU32 checkSum;        // Set to value needed to make checksum always zero.
-    NvU32 seqNum;          // Sequence number maintained by the message queue.
-    rpc_message_header_v  rpc;
+    NvU8  authTagBuffer[16];         // Authentication tag buffer.
+    NvU8  aadBuffer[16];             // AAD buffer.
+    NvU32 checkSum;                  // Set to value needed to make checksum always zero.
+    NvU32 seqNum;                    // Sequence number maintained by the message queue.
+    NvU32 elemCount;                 // Number of message queue elements this message has.
+    NV_DECLARE_ALIGNED(rpc_message_header_v rpc, 8);
 } GSP_MSG_QUEUE_ELEMENT;
 
 typedef struct _message_queue_info

src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils_sizes.h

@@ -24,13 +24,19 @@
 #ifndef _CE_UTILS_SIZES_H
 #define _CE_UTILS_SIZES_H
 
+#define NUM_COPY_BLOCKS                       4096
+#define CHANNEL_HOST_SEMAPHORE_SIZE           4
+#define CHANNEL_ENGINE_SEMAPHORE_SIZE         4
+#define GPFIFO_SIZE                           NV906F_GP_ENTRY__SIZE * NUM_COPY_BLOCKS
+#define CHANNEL_NOTIFIER_SIZE                 (sizeof(NvNotification) *                 \
+                                              NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1)
+
 #define CE_MAX_BYTES_PER_LINE                 0xffffffffULL
-#define CE_NUM_COPY_BLOCKS                    4096
-#define CE_CHANNEL_SEMAPHORE_SIZE             8
-#define CE_GPFIFO_SIZE                        NV906F_GP_ENTRY__SIZE * CE_NUM_COPY_BLOCKS
-#define CE_CHANNEL_NOTIFIER_SIZE              (sizeof(NvNotification) *                     \
-                                               NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1)
 #define CE_METHOD_SIZE_PER_BLOCK              0x64
 #define FAST_SCRUBBER_METHOD_SIZE_PER_BLOCK   0x78
 
+// number of bytes per sec2 method-stream (including host methods)
+#define SEC2_METHOD_SIZE_PER_BLOCK            0x94
+#define SEC2_AUTH_TAG_BUF_SEMAPHORE_SIZE      4
+
 #endif //  _CE_UTILS_SIZES_H

src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h

@@ -49,6 +49,8 @@
 
 #include "class/clc86f.h"   // HOPPER_CHANNEL_GPFIFO_A
 
+#include "gpu/conf_compute/ccsl.h"
+
 #include "nvctassert.h"
 #include "vgpu/vgpu_guest_pma_scrubber.h"
 
@@ -137,13 +139,21 @@ NvU32 channelReadChannelMemdesc(OBJCHANNEL *pChannel, NvU32 offset);
 // Needed for pushbuffer management
 NV_STATUS channelWaitForFreeEntry(OBJCHANNEL *pChannel, NvU32 *pPutIndex);
 NV_STATUS channelFillGpFifo(OBJCHANNEL *pChannel, NvU32 putIndex, NvU32 methodsLength);
-NvU32 channelFillPb(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined,
-                    NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo);
+NvU32 channelFillCePb(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined,
+                      NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo);
 NvU32 channelFillPbFastScrub(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined,
                     NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo);
 
+NV_STATUS channelFillSec2Pb(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bInsertFinishPayload,
+                            CHANNEL_PB_INFO *pChannelPbInfo, CCSL_CONTEXT *pCcslCtx, 
+                            MEMORY_DESCRIPTOR *pScrubMemDesc, MEMORY_DESCRIPTOR *pSemaMemDesc,
+                            NvU64 scrubMthdAuthTagBufGpuVA, NvU32 scrubAuthTagBufIndex,
+                            NvU64 semaMthdAuthTagBufGpuVA, NvU32 semaAuthTagBufIndex, NvU32* methodLength);
+
 // Needed for work tracking
 NV_STATUS channelWaitForFinishPayload(OBJCHANNEL *pChannel, NvU64 targetPayload);
 NvU64 channelGetFinishPayload(OBJCHANNEL *pChannel);
 
+void channelServiceScrubberInterrupts(OBJCHANNEL *pChannel);
+
 #endif // _CHANNEL_UTILS_H_

src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h

@@ -36,6 +36,7 @@
 #include "vgpu/vgpu_guest_pma_scrubber.h"
 #if !defined(SRT_BUILD)
 #include "gpu/mem_mgr/ce_utils.h"
+#include "gpu/mem_mgr/sec2_utils.h"
 #endif
 
 struct OBJGPU;
@@ -88,7 +89,13 @@ typedef struct OBJMEMSCRUB {
 #if !defined(SRT_BUILD)
     // Scrubber uses ceUtils to manage CE channel
     CeUtils                           *pCeUtils;
-#endif
+
+    // Scrubber uses sec2Utils to manage SEC2 channel
+    Sec2Utils                         *pSec2Utils;
+#endif //  !defined(SRT_BUILD)
+    // Engine used for scrubbing 
+    NvU32                              engineType;
+
     struct OBJGPU                     *pGpu;
     VGPU_GUEST_PMA_SCRUB_BUFFER_RING   vgpuScrubBuffRing;
     NvBool                             bVgpuScrubberEnabled;

src/nvidia/inc/kernel/gpu/mem_mgr/sec2_utils.h

@@ -0,0 +1,112 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "g_sec2_utils_nvoc.h"
+
+#ifndef SEC2_UTILS_H
+#define SEC2_UTILS_H
+
+#include "gpu/gpu_resource.h" // GpuResource
+
+#include "kernel/gpu/mem_mgr/channel_utils.h"
+
+#include "kernel/gpu/conf_compute/ccsl_context.h"
+
+#define SEC2_AUTH_TAG_BUF_SIZE_BYTES (16)
+#define SHA_256_HASH_SIZE_BYTES (32)
+
+typedef struct
+{
+    MEMORY_DESCRIPTOR *pMemDesc;
+    NvU64 offset;
+    NvU64 length;
+    NvU64 submittedWorkId; 
+} SEC2UTILS_MEMSET_PARAMS;
+
+typedef struct
+{
+    NvHandle hPhysMem;
+    NvHandle hVirtMem;
+    NvHandle hVASpace;
+    NvU64    gpuVA;
+    NvU64    size;
+    MEMORY_DESCRIPTOR *pMemDesc;
+} SEC2UTILS_BUFFER_INFO;
+
+NVOC_PREFIX(sec2utils) class Sec2Utils : Object
+{
+public:
+    NV_STATUS sec2utilsConstruct(Sec2Utils *psec2utils, OBJGPU *pGpu, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance);
+
+    void sec2utilsDestruct(Sec2Utils *psec2utils);
+
+    NV_STATUS sec2utilsMemset(Sec2Utils *psec2utils, SEC2UTILS_MEMSET_PARAMS *pParams);
+
+    NvU64 sec2utilsUpdateProgress(Sec2Utils *psec2utils);
+    void sec2utilsServiceInterrupts(Sec2Utils *psec2utils);
+
+    //
+    // Internal states
+    //
+
+    NvHandle hClient;
+    NvHandle hDevice;
+    NvHandle hSubdevice;
+
+    OBJCHANNEL *pChannel;
+    OBJGPU *pGpu;
+
+    NvU32 sec2Class;
+    NvU64 lastSubmittedPayload;
+    NvU64 lastCompletedPayload;
+
+    CCSL_CONTEXT *pCcslCtx;
+
+    //
+    // 4K page consisting of 128 auth tag buffers.
+    // One buffer is used per sec2 method stream.
+    // RM scrubber can submit multiple scrub method streams per sec2 operation.
+    //
+    SEC2UTILS_BUFFER_INFO scrubMthdAuthTagBuf;
+
+    //
+    // 4K page consisting of 128 auth tag buffers.
+    // One buffer is used per scrubber operation (not per sec2 scrub method stream).
+    // One scrub op corresponds to one call to sec2UtilsMemSet
+    //
+    SEC2UTILS_BUFFER_INFO semaMthdAuthTagBuf;
+
+    //
+    // Updated by RM to point to current auth tag buffer index (0-127)
+    // so its incremented for every scrub method stream.
+    //
+    NvU32 authTagPutIndex;
+
+    //
+    // Updated by SEC2 engine to point to last used/ last "seen" auth tag buffer index.
+    // This is updated based on completion of every scrub method stream.
+    //
+    NvU32 authTagGetIndex;
+};
+
+#endif // SEC2_UTILS_H